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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 570:d2893980fbf5
prev569:a1c49e1e8776
next571:9bc09948d0f2
author nkeynes
date Sun Jan 06 12:24:18 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Change to generate different code for mmu on/off cases
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    uint32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE_PHYS( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD_PHYS( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG_PHYS( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE_PHYS( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD_PHYS( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG_PHYS( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define MEM_READ_BYTE_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_byte, R_EAX); MEM_RESULT(value_reg)
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#define MEM_READ_WORD_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_word, R_EAX); MEM_RESULT(value_reg)
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#define MEM_READ_LONG_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func1(sh4_read_long, R_EAX); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_byte, R_EAX, value_reg)
nkeynes@570
   323
#define MEM_WRITE_WORD_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_word, R_EAX, value_reg)
nkeynes@570
   324
#define MEM_WRITE_LONG_VMA( addr_reg, value_reg ) call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); call_func2(sh4_write_long, R_EAX, value_reg)
nkeynes@570
   325
nkeynes@570
   326
#define MEM_READ_BYTE( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_BYTE_VMA(addr_reg,value_reg);}else{MEM_READ_BYTE_PHYS(addr_reg, value_reg);}
nkeynes@570
   327
#define MEM_READ_WORD( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_WORD_VMA(addr_reg,value_reg);}else{MEM_READ_WORD_PHYS(addr_reg, value_reg);}
nkeynes@570
   328
#define MEM_READ_LONG( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_READ_LONG_VMA(addr_reg,value_reg);}else{MEM_READ_LONG_PHYS(addr_reg, value_reg);}
nkeynes@570
   329
#define MEM_WRITE_BYTE( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_BYTE_VMA(addr_reg,value_reg);}else{MEM_WRITE_BYTE_PHYS(addr_reg, value_reg);}
nkeynes@570
   330
#define MEM_WRITE_WORD( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_WORD_VMA(addr_reg,value_reg);}else{MEM_WRITE_WORD_PHYS(addr_reg, value_reg);}
nkeynes@570
   331
#define MEM_WRITE_LONG( addr_reg, value_reg ) if(sh4_x86.tlb_on){MEM_WRITE_LONG_VMA(addr_reg,value_reg);}else{MEM_WRITE_LONG_PHYS(addr_reg, value_reg);}
nkeynes@570
   332
nkeynes@570
   333
#define MEM_READ_SIZE_PHYS (CALL_FUNC1_SIZE)
nkeynes@570
   334
#define MEM_WRITE_SIZE_PHYS (CALL_FUNC2_SIZE)
nkeynes@570
   335
#define MEM_READ_SIZE_VMA (CALL_FUNC1_SIZE + CALL_FUNC1_SIZE + 12)
nkeynes@570
   336
#define MEM_WRITE_SIZE_VMA (CALL_FUNC1_SIZE + CALL_FUNC2_SIZE + 12)
nkeynes@570
   337
nkeynes@570
   338
#define MEM_READ_SIZE (sh4_x86.tlb_on?MEM_READ_SIZE_VMA:MEM_READ_SIZE_PHYS)
nkeynes@570
   339
#define MEM_WRITE_SIZE (sh4_x86.tlb_on?MEM_WRITE_SIZE_VMA:MEM_WRITE_SIZE_PHYS)
nkeynes@559
   340
nkeynes@559
   341
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   342
nkeynes@539
   343
/****** Import appropriate calling conventions ******/
nkeynes@539
   344
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   345
#include "sh4/ia64abi.h"
nkeynes@539
   346
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   347
#ifdef APPLE_BUILD
nkeynes@539
   348
#include "sh4/ia32mac.h"
nkeynes@539
   349
#else
nkeynes@539
   350
#include "sh4/ia32abi.h"
nkeynes@539
   351
#endif
nkeynes@539
   352
#endif
nkeynes@539
   353
nkeynes@539
   354
nkeynes@359
   355
/**
nkeynes@359
   356
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   357
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   358
 * 
nkeynes@359
   359
 *
nkeynes@359
   360
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   361
 * (eg a branch or 
nkeynes@359
   362
 */
nkeynes@526
   363
uint32_t sh4_translate_instruction( sh4addr_t pc )
nkeynes@359
   364
{
nkeynes@388
   365
    uint32_t ir;
nkeynes@388
   366
    /* Read instruction */
nkeynes@569
   367
    if( IS_IN_ICACHE(pc) ) {
nkeynes@569
   368
	ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@388
   369
    } else {
nkeynes@569
   370
	ir = sh4_read_word(pc);
nkeynes@388
   371
    }
nkeynes@359
   372
%%
nkeynes@359
   373
/* ALU operations */
nkeynes@359
   374
ADD Rm, Rn {:
nkeynes@359
   375
    load_reg( R_EAX, Rm );
nkeynes@359
   376
    load_reg( R_ECX, Rn );
nkeynes@359
   377
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   378
    store_reg( R_ECX, Rn );
nkeynes@417
   379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   380
:}
nkeynes@359
   381
ADD #imm, Rn {:  
nkeynes@359
   382
    load_reg( R_EAX, Rn );
nkeynes@359
   383
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   384
    store_reg( R_EAX, Rn );
nkeynes@417
   385
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   386
:}
nkeynes@359
   387
ADDC Rm, Rn {:
nkeynes@417
   388
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   389
	LDC_t();
nkeynes@417
   390
    }
nkeynes@359
   391
    load_reg( R_EAX, Rm );
nkeynes@359
   392
    load_reg( R_ECX, Rn );
nkeynes@359
   393
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   394
    store_reg( R_ECX, Rn );
nkeynes@359
   395
    SETC_t();
nkeynes@417
   396
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   397
:}
nkeynes@359
   398
ADDV Rm, Rn {:
nkeynes@359
   399
    load_reg( R_EAX, Rm );
nkeynes@359
   400
    load_reg( R_ECX, Rn );
nkeynes@359
   401
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   402
    store_reg( R_ECX, Rn );
nkeynes@359
   403
    SETO_t();
nkeynes@417
   404
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   405
:}
nkeynes@359
   406
AND Rm, Rn {:
nkeynes@359
   407
    load_reg( R_EAX, Rm );
nkeynes@359
   408
    load_reg( R_ECX, Rn );
nkeynes@359
   409
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   410
    store_reg( R_ECX, Rn );
nkeynes@417
   411
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   412
:}
nkeynes@359
   413
AND #imm, R0 {:  
nkeynes@359
   414
    load_reg( R_EAX, 0 );
nkeynes@359
   415
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   416
    store_reg( R_EAX, 0 );
nkeynes@417
   417
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   418
:}
nkeynes@359
   419
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   420
    load_reg( R_EAX, 0 );
nkeynes@359
   421
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   422
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   423
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   424
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
   425
    POP_realigned_r32(R_ECX);
nkeynes@386
   426
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   427
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   428
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   429
:}
nkeynes@359
   430
CMP/EQ Rm, Rn {:  
nkeynes@359
   431
    load_reg( R_EAX, Rm );
nkeynes@359
   432
    load_reg( R_ECX, Rn );
nkeynes@359
   433
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   434
    SETE_t();
nkeynes@417
   435
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   436
:}
nkeynes@359
   437
CMP/EQ #imm, R0 {:  
nkeynes@359
   438
    load_reg( R_EAX, 0 );
nkeynes@359
   439
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   440
    SETE_t();
nkeynes@417
   441
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   442
:}
nkeynes@359
   443
CMP/GE Rm, Rn {:  
nkeynes@359
   444
    load_reg( R_EAX, Rm );
nkeynes@359
   445
    load_reg( R_ECX, Rn );
nkeynes@359
   446
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   447
    SETGE_t();
nkeynes@417
   448
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   449
:}
nkeynes@359
   450
CMP/GT Rm, Rn {: 
nkeynes@359
   451
    load_reg( R_EAX, Rm );
nkeynes@359
   452
    load_reg( R_ECX, Rn );
nkeynes@359
   453
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   454
    SETG_t();
nkeynes@417
   455
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   456
:}
nkeynes@359
   457
CMP/HI Rm, Rn {:  
nkeynes@359
   458
    load_reg( R_EAX, Rm );
nkeynes@359
   459
    load_reg( R_ECX, Rn );
nkeynes@359
   460
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   461
    SETA_t();
nkeynes@417
   462
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   463
:}
nkeynes@359
   464
CMP/HS Rm, Rn {: 
nkeynes@359
   465
    load_reg( R_EAX, Rm );
nkeynes@359
   466
    load_reg( R_ECX, Rn );
nkeynes@359
   467
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   468
    SETAE_t();
nkeynes@417
   469
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   470
 :}
nkeynes@359
   471
CMP/PL Rn {: 
nkeynes@359
   472
    load_reg( R_EAX, Rn );
nkeynes@359
   473
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   474
    SETG_t();
nkeynes@417
   475
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   476
:}
nkeynes@359
   477
CMP/PZ Rn {:  
nkeynes@359
   478
    load_reg( R_EAX, Rn );
nkeynes@359
   479
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   480
    SETGE_t();
nkeynes@417
   481
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   482
:}
nkeynes@361
   483
CMP/STR Rm, Rn {:  
nkeynes@368
   484
    load_reg( R_EAX, Rm );
nkeynes@368
   485
    load_reg( R_ECX, Rn );
nkeynes@368
   486
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   487
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   488
    JE_rel8(13, target1);
nkeynes@368
   489
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   490
    JE_rel8(9, target2);
nkeynes@368
   491
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   492
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   493
    JE_rel8(2, target3);
nkeynes@368
   494
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   495
    JMP_TARGET(target1);
nkeynes@380
   496
    JMP_TARGET(target2);
nkeynes@380
   497
    JMP_TARGET(target3);
nkeynes@368
   498
    SETE_t();
nkeynes@417
   499
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   500
:}
nkeynes@361
   501
DIV0S Rm, Rn {:
nkeynes@361
   502
    load_reg( R_EAX, Rm );
nkeynes@386
   503
    load_reg( R_ECX, Rn );
nkeynes@361
   504
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   505
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   506
    store_spreg( R_EAX, R_M );
nkeynes@361
   507
    store_spreg( R_ECX, R_Q );
nkeynes@361
   508
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   509
    SETNE_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   511
:}
nkeynes@361
   512
DIV0U {:  
nkeynes@361
   513
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   514
    store_spreg( R_EAX, R_Q );
nkeynes@361
   515
    store_spreg( R_EAX, R_M );
nkeynes@361
   516
    store_spreg( R_EAX, R_T );
nkeynes@417
   517
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   518
:}
nkeynes@386
   519
DIV1 Rm, Rn {:
nkeynes@386
   520
    load_spreg( R_ECX, R_M );
nkeynes@386
   521
    load_reg( R_EAX, Rn );
nkeynes@417
   522
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   523
	LDC_t();
nkeynes@417
   524
    }
nkeynes@386
   525
    RCL1_r32( R_EAX );
nkeynes@386
   526
    SETC_r8( R_DL ); // Q'
nkeynes@386
   527
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   528
    JE_rel8(5, mqequal);
nkeynes@386
   529
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   530
    JMP_rel8(3, end);
nkeynes@380
   531
    JMP_TARGET(mqequal);
nkeynes@386
   532
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   533
    JMP_TARGET(end);
nkeynes@386
   534
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   535
    SETC_r8(R_AL); // tmp1
nkeynes@386
   536
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   537
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   538
    store_spreg( R_ECX, R_Q );
nkeynes@386
   539
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   540
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   541
    store_spreg( R_EAX, R_T );
nkeynes@417
   542
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   543
:}
nkeynes@361
   544
DMULS.L Rm, Rn {:  
nkeynes@361
   545
    load_reg( R_EAX, Rm );
nkeynes@361
   546
    load_reg( R_ECX, Rn );
nkeynes@361
   547
    IMUL_r32(R_ECX);
nkeynes@361
   548
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   549
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   550
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   551
:}
nkeynes@361
   552
DMULU.L Rm, Rn {:  
nkeynes@361
   553
    load_reg( R_EAX, Rm );
nkeynes@361
   554
    load_reg( R_ECX, Rn );
nkeynes@361
   555
    MUL_r32(R_ECX);
nkeynes@361
   556
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   557
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   558
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   559
:}
nkeynes@359
   560
DT Rn {:  
nkeynes@359
   561
    load_reg( R_EAX, Rn );
nkeynes@382
   562
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   563
    store_reg( R_EAX, Rn );
nkeynes@359
   564
    SETE_t();
nkeynes@417
   565
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   566
:}
nkeynes@359
   567
EXTS.B Rm, Rn {:  
nkeynes@359
   568
    load_reg( R_EAX, Rm );
nkeynes@359
   569
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   570
    store_reg( R_EAX, Rn );
nkeynes@359
   571
:}
nkeynes@361
   572
EXTS.W Rm, Rn {:  
nkeynes@361
   573
    load_reg( R_EAX, Rm );
nkeynes@361
   574
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   575
    store_reg( R_EAX, Rn );
nkeynes@361
   576
:}
nkeynes@361
   577
EXTU.B Rm, Rn {:  
nkeynes@361
   578
    load_reg( R_EAX, Rm );
nkeynes@361
   579
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   580
    store_reg( R_EAX, Rn );
nkeynes@361
   581
:}
nkeynes@361
   582
EXTU.W Rm, Rn {:  
nkeynes@361
   583
    load_reg( R_EAX, Rm );
nkeynes@361
   584
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   585
    store_reg( R_EAX, Rn );
nkeynes@361
   586
:}
nkeynes@386
   587
MAC.L @Rm+, @Rn+ {:  
nkeynes@386
   588
    load_reg( R_ECX, Rm );
nkeynes@386
   589
    check_ralign32( R_ECX );
nkeynes@386
   590
    load_reg( R_ECX, Rn );
nkeynes@386
   591
    check_ralign32( R_ECX );
nkeynes@386
   592
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   593
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   594
    PUSH_realigned_r32( R_EAX );
nkeynes@386
   595
    load_reg( R_ECX, Rm );
nkeynes@386
   596
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   597
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   598
    POP_realigned_r32( R_ECX );
nkeynes@386
   599
    IMUL_r32( R_ECX );
nkeynes@386
   600
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   601
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   602
nkeynes@386
   603
    load_spreg( R_ECX, R_S );
nkeynes@386
   604
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   605
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   606
    call_func0( signsat48 );
nkeynes@386
   607
    JMP_TARGET( nosat );
nkeynes@417
   608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   609
:}
nkeynes@386
   610
MAC.W @Rm+, @Rn+ {:  
nkeynes@386
   611
    load_reg( R_ECX, Rm );
nkeynes@386
   612
    check_ralign16( R_ECX );
nkeynes@386
   613
    load_reg( R_ECX, Rn );
nkeynes@386
   614
    check_ralign16( R_ECX );
nkeynes@386
   615
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
   616
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   617
    PUSH_realigned_r32( R_EAX );
nkeynes@386
   618
    load_reg( R_ECX, Rm );
nkeynes@386
   619
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
   620
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   621
    POP_realigned_r32( R_ECX );
nkeynes@386
   622
    IMUL_r32( R_ECX );
nkeynes@386
   623
nkeynes@386
   624
    load_spreg( R_ECX, R_S );
nkeynes@386
   625
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   626
    JE_rel8( 47, nosat );
nkeynes@386
   627
nkeynes@386
   628
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   629
    JNO_rel8( 51, end );            // 2
nkeynes@386
   630
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   631
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   632
    JS_rel8( 13, positive );        // 2
nkeynes@386
   633
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   634
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   635
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   636
nkeynes@386
   637
    JMP_TARGET(positive);
nkeynes@386
   638
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   639
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   640
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   641
nkeynes@386
   642
    JMP_TARGET(nosat);
nkeynes@386
   643
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   644
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   645
    JMP_TARGET(end);
nkeynes@386
   646
    JMP_TARGET(end2);
nkeynes@386
   647
    JMP_TARGET(end3);
nkeynes@417
   648
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   649
:}
nkeynes@359
   650
MOVT Rn {:  
nkeynes@359
   651
    load_spreg( R_EAX, R_T );
nkeynes@359
   652
    store_reg( R_EAX, Rn );
nkeynes@359
   653
:}
nkeynes@361
   654
MUL.L Rm, Rn {:  
nkeynes@361
   655
    load_reg( R_EAX, Rm );
nkeynes@361
   656
    load_reg( R_ECX, Rn );
nkeynes@361
   657
    MUL_r32( R_ECX );
nkeynes@361
   658
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   659
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   660
:}
nkeynes@374
   661
MULS.W Rm, Rn {:
nkeynes@374
   662
    load_reg16s( R_EAX, Rm );
nkeynes@374
   663
    load_reg16s( R_ECX, Rn );
nkeynes@374
   664
    MUL_r32( R_ECX );
nkeynes@374
   665
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   667
:}
nkeynes@374
   668
MULU.W Rm, Rn {:  
nkeynes@374
   669
    load_reg16u( R_EAX, Rm );
nkeynes@374
   670
    load_reg16u( R_ECX, Rn );
nkeynes@374
   671
    MUL_r32( R_ECX );
nkeynes@374
   672
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   673
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   674
:}
nkeynes@359
   675
NEG Rm, Rn {:
nkeynes@359
   676
    load_reg( R_EAX, Rm );
nkeynes@359
   677
    NEG_r32( R_EAX );
nkeynes@359
   678
    store_reg( R_EAX, Rn );
nkeynes@417
   679
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   680
:}
nkeynes@359
   681
NEGC Rm, Rn {:  
nkeynes@359
   682
    load_reg( R_EAX, Rm );
nkeynes@359
   683
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   684
    LDC_t();
nkeynes@359
   685
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   686
    store_reg( R_ECX, Rn );
nkeynes@359
   687
    SETC_t();
nkeynes@417
   688
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   689
:}
nkeynes@359
   690
NOT Rm, Rn {:  
nkeynes@359
   691
    load_reg( R_EAX, Rm );
nkeynes@359
   692
    NOT_r32( R_EAX );
nkeynes@359
   693
    store_reg( R_EAX, Rn );
nkeynes@417
   694
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   695
:}
nkeynes@359
   696
OR Rm, Rn {:  
nkeynes@359
   697
    load_reg( R_EAX, Rm );
nkeynes@359
   698
    load_reg( R_ECX, Rn );
nkeynes@359
   699
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   700
    store_reg( R_ECX, Rn );
nkeynes@417
   701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   702
:}
nkeynes@359
   703
OR #imm, R0 {:
nkeynes@359
   704
    load_reg( R_EAX, 0 );
nkeynes@359
   705
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   706
    store_reg( R_EAX, 0 );
nkeynes@417
   707
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   708
:}
nkeynes@374
   709
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   710
    load_reg( R_EAX, 0 );
nkeynes@374
   711
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   712
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   713
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   714
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@547
   715
    POP_realigned_r32(R_ECX);
nkeynes@386
   716
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   717
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   718
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   719
:}
nkeynes@359
   720
ROTCL Rn {:
nkeynes@359
   721
    load_reg( R_EAX, Rn );
nkeynes@417
   722
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   723
	LDC_t();
nkeynes@417
   724
    }
nkeynes@359
   725
    RCL1_r32( R_EAX );
nkeynes@359
   726
    store_reg( R_EAX, Rn );
nkeynes@359
   727
    SETC_t();
nkeynes@417
   728
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   729
:}
nkeynes@359
   730
ROTCR Rn {:  
nkeynes@359
   731
    load_reg( R_EAX, Rn );
nkeynes@417
   732
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   733
	LDC_t();
nkeynes@417
   734
    }
nkeynes@359
   735
    RCR1_r32( R_EAX );
nkeynes@359
   736
    store_reg( R_EAX, Rn );
nkeynes@359
   737
    SETC_t();
nkeynes@417
   738
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   739
:}
nkeynes@359
   740
ROTL Rn {:  
nkeynes@359
   741
    load_reg( R_EAX, Rn );
nkeynes@359
   742
    ROL1_r32( R_EAX );
nkeynes@359
   743
    store_reg( R_EAX, Rn );
nkeynes@359
   744
    SETC_t();
nkeynes@417
   745
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   746
:}
nkeynes@359
   747
ROTR Rn {:  
nkeynes@359
   748
    load_reg( R_EAX, Rn );
nkeynes@359
   749
    ROR1_r32( R_EAX );
nkeynes@359
   750
    store_reg( R_EAX, Rn );
nkeynes@359
   751
    SETC_t();
nkeynes@417
   752
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   753
:}
nkeynes@359
   754
SHAD Rm, Rn {:
nkeynes@359
   755
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   756
    load_reg( R_EAX, Rn );
nkeynes@361
   757
    load_reg( R_ECX, Rm );
nkeynes@361
   758
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   759
    JGE_rel8(16, doshl);
nkeynes@361
   760
                    
nkeynes@361
   761
    NEG_r32( R_ECX );      // 2
nkeynes@361
   762
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   763
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   764
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   765
    JMP_rel8(10, end);          // 2
nkeynes@386
   766
nkeynes@386
   767
    JMP_TARGET(emptysar);
nkeynes@386
   768
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   769
    JMP_rel8(5, end2);
nkeynes@382
   770
nkeynes@380
   771
    JMP_TARGET(doshl);
nkeynes@361
   772
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   773
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   774
    JMP_TARGET(end);
nkeynes@386
   775
    JMP_TARGET(end2);
nkeynes@361
   776
    store_reg( R_EAX, Rn );
nkeynes@417
   777
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   778
:}
nkeynes@359
   779
SHLD Rm, Rn {:  
nkeynes@368
   780
    load_reg( R_EAX, Rn );
nkeynes@368
   781
    load_reg( R_ECX, Rm );
nkeynes@382
   782
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   783
    JGE_rel8(15, doshl);
nkeynes@368
   784
nkeynes@382
   785
    NEG_r32( R_ECX );      // 2
nkeynes@382
   786
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   787
    JE_rel8( 4, emptyshr );
nkeynes@382
   788
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   789
    JMP_rel8(9, end);          // 2
nkeynes@386
   790
nkeynes@386
   791
    JMP_TARGET(emptyshr);
nkeynes@386
   792
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   793
    JMP_rel8(5, end2);
nkeynes@382
   794
nkeynes@382
   795
    JMP_TARGET(doshl);
nkeynes@382
   796
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   797
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   798
    JMP_TARGET(end);
nkeynes@386
   799
    JMP_TARGET(end2);
nkeynes@368
   800
    store_reg( R_EAX, Rn );
nkeynes@417
   801
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   802
:}
nkeynes@359
   803
SHAL Rn {: 
nkeynes@359
   804
    load_reg( R_EAX, Rn );
nkeynes@359
   805
    SHL1_r32( R_EAX );
nkeynes@397
   806
    SETC_t();
nkeynes@359
   807
    store_reg( R_EAX, Rn );
nkeynes@417
   808
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   809
:}
nkeynes@359
   810
SHAR Rn {:  
nkeynes@359
   811
    load_reg( R_EAX, Rn );
nkeynes@359
   812
    SAR1_r32( R_EAX );
nkeynes@397
   813
    SETC_t();
nkeynes@359
   814
    store_reg( R_EAX, Rn );
nkeynes@417
   815
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   816
:}
nkeynes@359
   817
SHLL Rn {:  
nkeynes@359
   818
    load_reg( R_EAX, Rn );
nkeynes@359
   819
    SHL1_r32( R_EAX );
nkeynes@397
   820
    SETC_t();
nkeynes@359
   821
    store_reg( R_EAX, Rn );
nkeynes@417
   822
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   823
:}
nkeynes@359
   824
SHLL2 Rn {:
nkeynes@359
   825
    load_reg( R_EAX, Rn );
nkeynes@359
   826
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   827
    store_reg( R_EAX, Rn );
nkeynes@417
   828
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   829
:}
nkeynes@359
   830
SHLL8 Rn {:  
nkeynes@359
   831
    load_reg( R_EAX, Rn );
nkeynes@359
   832
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   833
    store_reg( R_EAX, Rn );
nkeynes@417
   834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   835
:}
nkeynes@359
   836
SHLL16 Rn {:  
nkeynes@359
   837
    load_reg( R_EAX, Rn );
nkeynes@359
   838
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   839
    store_reg( R_EAX, Rn );
nkeynes@417
   840
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   841
:}
nkeynes@359
   842
SHLR Rn {:  
nkeynes@359
   843
    load_reg( R_EAX, Rn );
nkeynes@359
   844
    SHR1_r32( R_EAX );
nkeynes@397
   845
    SETC_t();
nkeynes@359
   846
    store_reg( R_EAX, Rn );
nkeynes@417
   847
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   848
:}
nkeynes@359
   849
SHLR2 Rn {:  
nkeynes@359
   850
    load_reg( R_EAX, Rn );
nkeynes@359
   851
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   852
    store_reg( R_EAX, Rn );
nkeynes@417
   853
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   854
:}
nkeynes@359
   855
SHLR8 Rn {:  
nkeynes@359
   856
    load_reg( R_EAX, Rn );
nkeynes@359
   857
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   858
    store_reg( R_EAX, Rn );
nkeynes@417
   859
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   860
:}
nkeynes@359
   861
SHLR16 Rn {:  
nkeynes@359
   862
    load_reg( R_EAX, Rn );
nkeynes@359
   863
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   864
    store_reg( R_EAX, Rn );
nkeynes@417
   865
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   866
:}
nkeynes@359
   867
SUB Rm, Rn {:  
nkeynes@359
   868
    load_reg( R_EAX, Rm );
nkeynes@359
   869
    load_reg( R_ECX, Rn );
nkeynes@359
   870
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   871
    store_reg( R_ECX, Rn );
nkeynes@417
   872
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   873
:}
nkeynes@359
   874
SUBC Rm, Rn {:  
nkeynes@359
   875
    load_reg( R_EAX, Rm );
nkeynes@359
   876
    load_reg( R_ECX, Rn );
nkeynes@417
   877
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   878
	LDC_t();
nkeynes@417
   879
    }
nkeynes@359
   880
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   881
    store_reg( R_ECX, Rn );
nkeynes@394
   882
    SETC_t();
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   884
:}
nkeynes@359
   885
SUBV Rm, Rn {:  
nkeynes@359
   886
    load_reg( R_EAX, Rm );
nkeynes@359
   887
    load_reg( R_ECX, Rn );
nkeynes@359
   888
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   889
    store_reg( R_ECX, Rn );
nkeynes@359
   890
    SETO_t();
nkeynes@417
   891
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   892
:}
nkeynes@359
   893
SWAP.B Rm, Rn {:  
nkeynes@359
   894
    load_reg( R_EAX, Rm );
nkeynes@359
   895
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   896
    store_reg( R_EAX, Rn );
nkeynes@359
   897
:}
nkeynes@359
   898
SWAP.W Rm, Rn {:  
nkeynes@359
   899
    load_reg( R_EAX, Rm );
nkeynes@359
   900
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   901
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   902
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   903
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   904
    store_reg( R_ECX, Rn );
nkeynes@417
   905
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   906
:}
nkeynes@361
   907
TAS.B @Rn {:  
nkeynes@361
   908
    load_reg( R_ECX, Rn );
nkeynes@361
   909
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   910
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   911
    SETE_t();
nkeynes@361
   912
    OR_imm8_r8( 0x80, R_AL );
nkeynes@386
   913
    load_reg( R_ECX, Rn );
nkeynes@361
   914
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   915
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   916
:}
nkeynes@361
   917
TST Rm, Rn {:  
nkeynes@361
   918
    load_reg( R_EAX, Rm );
nkeynes@361
   919
    load_reg( R_ECX, Rn );
nkeynes@361
   920
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   921
    SETE_t();
nkeynes@417
   922
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   923
:}
nkeynes@368
   924
TST #imm, R0 {:  
nkeynes@368
   925
    load_reg( R_EAX, 0 );
nkeynes@368
   926
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   927
    SETE_t();
nkeynes@417
   928
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   929
:}
nkeynes@368
   930
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   931
    load_reg( R_EAX, 0);
nkeynes@368
   932
    load_reg( R_ECX, R_GBR);
nkeynes@368
   933
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   934
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
   935
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
   936
    SETE_t();
nkeynes@417
   937
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
   938
:}
nkeynes@359
   939
XOR Rm, Rn {:  
nkeynes@359
   940
    load_reg( R_EAX, Rm );
nkeynes@359
   941
    load_reg( R_ECX, Rn );
nkeynes@359
   942
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   943
    store_reg( R_ECX, Rn );
nkeynes@417
   944
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   945
:}
nkeynes@359
   946
XOR #imm, R0 {:  
nkeynes@359
   947
    load_reg( R_EAX, 0 );
nkeynes@359
   948
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   949
    store_reg( R_EAX, 0 );
nkeynes@417
   950
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   951
:}
nkeynes@359
   952
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   953
    load_reg( R_EAX, 0 );
nkeynes@359
   954
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   955
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@547
   956
    PUSH_realigned_r32(R_ECX);
nkeynes@527
   957
    MEM_READ_BYTE(R_ECX, R_EAX);
nkeynes@547
   958
    POP_realigned_r32(R_ECX);
nkeynes@359
   959
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   960
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   961
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   962
:}
nkeynes@361
   963
XTRCT Rm, Rn {:
nkeynes@361
   964
    load_reg( R_EAX, Rm );
nkeynes@394
   965
    load_reg( R_ECX, Rn );
nkeynes@394
   966
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
   967
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
   968
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   969
    store_reg( R_ECX, Rn );
nkeynes@417
   970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   971
:}
nkeynes@359
   972
nkeynes@359
   973
/* Data move instructions */
nkeynes@359
   974
MOV Rm, Rn {:  
nkeynes@359
   975
    load_reg( R_EAX, Rm );
nkeynes@359
   976
    store_reg( R_EAX, Rn );
nkeynes@359
   977
:}
nkeynes@359
   978
MOV #imm, Rn {:  
nkeynes@359
   979
    load_imm32( R_EAX, imm );
nkeynes@359
   980
    store_reg( R_EAX, Rn );
nkeynes@359
   981
:}
nkeynes@359
   982
MOV.B Rm, @Rn {:  
nkeynes@359
   983
    load_reg( R_EAX, Rm );
nkeynes@359
   984
    load_reg( R_ECX, Rn );
nkeynes@359
   985
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   986
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   987
:}
nkeynes@359
   988
MOV.B Rm, @-Rn {:  
nkeynes@359
   989
    load_reg( R_EAX, Rm );
nkeynes@359
   990
    load_reg( R_ECX, Rn );
nkeynes@382
   991
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   992
    store_reg( R_ECX, Rn );
nkeynes@359
   993
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   994
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   995
:}
nkeynes@359
   996
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   997
    load_reg( R_EAX, 0 );
nkeynes@359
   998
    load_reg( R_ECX, Rn );
nkeynes@359
   999
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1000
    load_reg( R_EAX, Rm );
nkeynes@359
  1001
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1002
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1003
:}
nkeynes@359
  1004
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
  1005
    load_reg( R_EAX, 0 );
nkeynes@359
  1006
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1007
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1008
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1009
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1010
:}
nkeynes@359
  1011
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
  1012
    load_reg( R_EAX, 0 );
nkeynes@359
  1013
    load_reg( R_ECX, Rn );
nkeynes@359
  1014
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1015
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1016
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1017
:}
nkeynes@359
  1018
MOV.B @Rm, Rn {:  
nkeynes@359
  1019
    load_reg( R_ECX, Rm );
nkeynes@359
  1020
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  1021
    store_reg( R_EAX, Rn );
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1023
:}
nkeynes@359
  1024
MOV.B @Rm+, Rn {:  
nkeynes@359
  1025
    load_reg( R_ECX, Rm );
nkeynes@359
  1026
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1027
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1028
    store_reg( R_EAX, Rm );
nkeynes@359
  1029
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1030
    store_reg( R_EAX, Rn );
nkeynes@417
  1031
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1032
:}
nkeynes@359
  1033
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1034
    load_reg( R_EAX, 0 );
nkeynes@359
  1035
    load_reg( R_ECX, Rm );
nkeynes@359
  1036
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1037
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1038
    store_reg( R_EAX, Rn );
nkeynes@417
  1039
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1040
:}
nkeynes@359
  1041
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
  1042
    load_spreg( R_ECX, R_GBR );
nkeynes@359
  1043
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1044
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1045
    store_reg( R_EAX, 0 );
nkeynes@417
  1046
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1047
:}
nkeynes@359
  1048
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
  1049
    load_reg( R_ECX, Rm );
nkeynes@359
  1050
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1051
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1052
    store_reg( R_EAX, 0 );
nkeynes@417
  1053
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1054
:}
nkeynes@374
  1055
MOV.L Rm, @Rn {:
nkeynes@361
  1056
    load_reg( R_EAX, Rm );
nkeynes@361
  1057
    load_reg( R_ECX, Rn );
nkeynes@374
  1058
    check_walign32(R_ECX);
nkeynes@361
  1059
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1060
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1061
:}
nkeynes@361
  1062
MOV.L Rm, @-Rn {:  
nkeynes@361
  1063
    load_reg( R_EAX, Rm );
nkeynes@361
  1064
    load_reg( R_ECX, Rn );
nkeynes@374
  1065
    check_walign32( R_ECX );
nkeynes@361
  1066
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
  1067
    store_reg( R_ECX, Rn );
nkeynes@361
  1068
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1069
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1070
:}
nkeynes@361
  1071
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1072
    load_reg( R_EAX, 0 );
nkeynes@361
  1073
    load_reg( R_ECX, Rn );
nkeynes@361
  1074
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1075
    check_walign32( R_ECX );
nkeynes@361
  1076
    load_reg( R_EAX, Rm );
nkeynes@361
  1077
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1078
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1079
:}
nkeynes@361
  1080
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
  1081
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1082
    load_reg( R_EAX, 0 );
nkeynes@361
  1083
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1084
    check_walign32( R_ECX );
nkeynes@361
  1085
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1086
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1087
:}
nkeynes@361
  1088
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
  1089
    load_reg( R_ECX, Rn );
nkeynes@361
  1090
    load_reg( R_EAX, Rm );
nkeynes@361
  1091
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1092
    check_walign32( R_ECX );
nkeynes@361
  1093
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1094
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1095
:}
nkeynes@361
  1096
MOV.L @Rm, Rn {:  
nkeynes@361
  1097
    load_reg( R_ECX, Rm );
nkeynes@374
  1098
    check_ralign32( R_ECX );
nkeynes@361
  1099
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1100
    store_reg( R_EAX, Rn );
nkeynes@417
  1101
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1102
:}
nkeynes@361
  1103
MOV.L @Rm+, Rn {:  
nkeynes@361
  1104
    load_reg( R_EAX, Rm );
nkeynes@382
  1105
    check_ralign32( R_EAX );
nkeynes@361
  1106
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1107
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1108
    store_reg( R_EAX, Rm );
nkeynes@361
  1109
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1110
    store_reg( R_EAX, Rn );
nkeynes@417
  1111
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1112
:}
nkeynes@361
  1113
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1114
    load_reg( R_EAX, 0 );
nkeynes@361
  1115
    load_reg( R_ECX, Rm );
nkeynes@361
  1116
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1117
    check_ralign32( R_ECX );
nkeynes@361
  1118
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1119
    store_reg( R_EAX, Rn );
nkeynes@417
  1120
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1121
:}
nkeynes@361
  1122
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1123
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1124
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1125
    check_ralign32( R_ECX );
nkeynes@361
  1126
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1127
    store_reg( R_EAX, 0 );
nkeynes@417
  1128
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1129
:}
nkeynes@361
  1130
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1131
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1132
	SLOTILLEGAL();
nkeynes@374
  1133
    } else {
nkeynes@388
  1134
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569
  1135
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1136
	    // If the target address is in the same page as the code, it's
nkeynes@569
  1137
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569
  1138
	    // memory subsystem. (this is a big performance win)
nkeynes@569
  1139
nkeynes@569
  1140
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569
  1141
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569
  1142
	    // (should generate a TLB miss although need to test SH4 
nkeynes@569
  1143
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569
  1144
	    // behaviour though.
nkeynes@569
  1145
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1146
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1147
	} else {
nkeynes@569
  1148
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569
  1149
	    // different virtual address than the translation was done with,
nkeynes@569
  1150
	    // but we can safely assume that the low bits are the same.
nkeynes@569
  1151
	    load_imm32( R_ECX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  1152
	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@388
  1153
	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@569
  1154
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1155
	}
nkeynes@382
  1156
	store_reg( R_EAX, Rn );
nkeynes@374
  1157
    }
nkeynes@361
  1158
:}
nkeynes@361
  1159
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1160
    load_reg( R_ECX, Rm );
nkeynes@361
  1161
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1162
    check_ralign32( R_ECX );
nkeynes@361
  1163
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1164
    store_reg( R_EAX, Rn );
nkeynes@417
  1165
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1166
:}
nkeynes@361
  1167
MOV.W Rm, @Rn {:  
nkeynes@361
  1168
    load_reg( R_ECX, Rn );
nkeynes@374
  1169
    check_walign16( R_ECX );
nkeynes@382
  1170
    load_reg( R_EAX, Rm );
nkeynes@382
  1171
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1172
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1173
:}
nkeynes@361
  1174
MOV.W Rm, @-Rn {:  
nkeynes@361
  1175
    load_reg( R_ECX, Rn );
nkeynes@374
  1176
    check_walign16( R_ECX );
nkeynes@361
  1177
    load_reg( R_EAX, Rm );
nkeynes@361
  1178
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1179
    store_reg( R_ECX, Rn );
nkeynes@361
  1180
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1181
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1182
:}
nkeynes@361
  1183
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1184
    load_reg( R_EAX, 0 );
nkeynes@361
  1185
    load_reg( R_ECX, Rn );
nkeynes@361
  1186
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1187
    check_walign16( R_ECX );
nkeynes@361
  1188
    load_reg( R_EAX, Rm );
nkeynes@361
  1189
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1191
:}
nkeynes@361
  1192
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1193
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1194
    load_reg( R_EAX, 0 );
nkeynes@361
  1195
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1196
    check_walign16( R_ECX );
nkeynes@361
  1197
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1199
:}
nkeynes@361
  1200
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1201
    load_reg( R_ECX, Rn );
nkeynes@361
  1202
    load_reg( R_EAX, 0 );
nkeynes@361
  1203
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1204
    check_walign16( R_ECX );
nkeynes@361
  1205
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@417
  1206
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1207
:}
nkeynes@361
  1208
MOV.W @Rm, Rn {:  
nkeynes@361
  1209
    load_reg( R_ECX, Rm );
nkeynes@374
  1210
    check_ralign16( R_ECX );
nkeynes@361
  1211
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1212
    store_reg( R_EAX, Rn );
nkeynes@417
  1213
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1214
:}
nkeynes@361
  1215
MOV.W @Rm+, Rn {:  
nkeynes@361
  1216
    load_reg( R_EAX, Rm );
nkeynes@374
  1217
    check_ralign16( R_EAX );
nkeynes@361
  1218
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1219
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1220
    store_reg( R_EAX, Rm );
nkeynes@361
  1221
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1222
    store_reg( R_EAX, Rn );
nkeynes@417
  1223
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1224
:}
nkeynes@361
  1225
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1226
    load_reg( R_EAX, 0 );
nkeynes@361
  1227
    load_reg( R_ECX, Rm );
nkeynes@361
  1228
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1229
    check_ralign16( R_ECX );
nkeynes@361
  1230
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1231
    store_reg( R_EAX, Rn );
nkeynes@417
  1232
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1233
:}
nkeynes@361
  1234
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1235
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1236
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1237
    check_ralign16( R_ECX );
nkeynes@361
  1238
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1239
    store_reg( R_EAX, 0 );
nkeynes@417
  1240
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1241
:}
nkeynes@361
  1242
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1243
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1244
	SLOTILLEGAL();
nkeynes@374
  1245
    } else {
nkeynes@569
  1246
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569
  1247
	uint32_t target = pc + disp + 4;
nkeynes@569
  1248
	if( IS_IN_ICACHE(target) ) {
nkeynes@569
  1249
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@569
  1250
	    MOV_moff32_EAX( ptr );
nkeynes@569
  1251
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@569
  1252
	} else {
nkeynes@569
  1253
	    load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@569
  1254
	    ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@569
  1255
	    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@569
  1256
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569
  1257
	}
nkeynes@374
  1258
	store_reg( R_EAX, Rn );
nkeynes@374
  1259
    }
nkeynes@361
  1260
:}
nkeynes@361
  1261
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1262
    load_reg( R_ECX, Rm );
nkeynes@361
  1263
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1264
    check_ralign16( R_ECX );
nkeynes@361
  1265
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1266
    store_reg( R_EAX, 0 );
nkeynes@417
  1267
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1268
:}
nkeynes@361
  1269
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1270
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1271
	SLOTILLEGAL();
nkeynes@374
  1272
    } else {
nkeynes@569
  1273
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@569
  1274
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1275
	store_reg( R_ECX, 0 );
nkeynes@374
  1276
    }
nkeynes@361
  1277
:}
nkeynes@361
  1278
MOVCA.L R0, @Rn {:  
nkeynes@361
  1279
    load_reg( R_EAX, 0 );
nkeynes@361
  1280
    load_reg( R_ECX, Rn );
nkeynes@374
  1281
    check_walign32( R_ECX );
nkeynes@361
  1282
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1284
:}
nkeynes@359
  1285
nkeynes@359
  1286
/* Control transfer instructions */
nkeynes@374
  1287
BF disp {:
nkeynes@374
  1288
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1289
	SLOTILLEGAL();
nkeynes@374
  1290
    } else {
nkeynes@527
  1291
	JT_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1292
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1293
	JMP_TARGET(nottaken);
nkeynes@408
  1294
	return 2;
nkeynes@374
  1295
    }
nkeynes@374
  1296
:}
nkeynes@374
  1297
BF/S disp {:
nkeynes@374
  1298
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1299
	SLOTILLEGAL();
nkeynes@374
  1300
    } else {
nkeynes@408
  1301
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1302
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1303
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1304
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1305
	}
nkeynes@417
  1306
	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
nkeynes@526
  1307
	sh4_translate_instruction(pc+2);
nkeynes@408
  1308
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1309
	// not taken
nkeynes@408
  1310
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1311
	sh4_translate_instruction(pc+2);
nkeynes@408
  1312
	return 4;
nkeynes@374
  1313
    }
nkeynes@374
  1314
:}
nkeynes@374
  1315
BRA disp {:  
nkeynes@374
  1316
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1317
	SLOTILLEGAL();
nkeynes@374
  1318
    } else {
nkeynes@374
  1319
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1320
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1321
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1322
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1323
	return 4;
nkeynes@374
  1324
    }
nkeynes@374
  1325
:}
nkeynes@374
  1326
BRAF Rn {:  
nkeynes@374
  1327
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1328
	SLOTILLEGAL();
nkeynes@374
  1329
    } else {
nkeynes@408
  1330
	load_reg( R_EAX, Rn );
nkeynes@408
  1331
	ADD_imm32_r32( pc + 4, R_EAX );
nkeynes@408
  1332
	store_spreg( R_EAX, REG_OFFSET(pc) );
nkeynes@374
  1333
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1334
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1335
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1336
	exit_block_pcset(pc+2);
nkeynes@409
  1337
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1338
	return 4;
nkeynes@374
  1339
    }
nkeynes@374
  1340
:}
nkeynes@374
  1341
BSR disp {:  
nkeynes@374
  1342
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1343
	SLOTILLEGAL();
nkeynes@374
  1344
    } else {
nkeynes@374
  1345
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1346
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1347
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1348
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1349
	exit_block( disp + pc + 4, pc+4 );
nkeynes@409
  1350
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1351
	return 4;
nkeynes@374
  1352
    }
nkeynes@374
  1353
:}
nkeynes@374
  1354
BSRF Rn {:  
nkeynes@374
  1355
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1356
	SLOTILLEGAL();
nkeynes@374
  1357
    } else {
nkeynes@408
  1358
	load_imm32( R_ECX, pc + 4 );
nkeynes@408
  1359
	store_spreg( R_ECX, R_PR );
nkeynes@408
  1360
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_ECX );
nkeynes@408
  1361
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1362
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1363
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1364
	sh4_translate_instruction( pc + 2 );
nkeynes@408
  1365
	exit_block_pcset(pc+2);
nkeynes@409
  1366
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1367
	return 4;
nkeynes@374
  1368
    }
nkeynes@374
  1369
:}
nkeynes@374
  1370
BT disp {:
nkeynes@374
  1371
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1372
	SLOTILLEGAL();
nkeynes@374
  1373
    } else {
nkeynes@527
  1374
	JF_rel8( EXIT_BLOCK_SIZE, nottaken );
nkeynes@408
  1375
	exit_block( disp + pc + 4, pc+2 );
nkeynes@380
  1376
	JMP_TARGET(nottaken);
nkeynes@408
  1377
	return 2;
nkeynes@374
  1378
    }
nkeynes@374
  1379
:}
nkeynes@374
  1380
BT/S disp {:
nkeynes@374
  1381
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1382
	SLOTILLEGAL();
nkeynes@374
  1383
    } else {
nkeynes@408
  1384
	sh4_x86.in_delay_slot = TRUE;
nkeynes@417
  1385
	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@417
  1386
	    CMP_imm8s_sh4r( 1, R_T );
nkeynes@417
  1387
	    sh4_x86.tstate = TSTATE_E;
nkeynes@417
  1388
	}
nkeynes@417
  1389
	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
nkeynes@526
  1390
	sh4_translate_instruction(pc+2);
nkeynes@408
  1391
	exit_block( disp + pc + 4, pc+4 );
nkeynes@408
  1392
	// not taken
nkeynes@408
  1393
	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@526
  1394
	sh4_translate_instruction(pc+2);
nkeynes@408
  1395
	return 4;
nkeynes@374
  1396
    }
nkeynes@374
  1397
:}
nkeynes@374
  1398
JMP @Rn {:  
nkeynes@374
  1399
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1400
	SLOTILLEGAL();
nkeynes@374
  1401
    } else {
nkeynes@408
  1402
	load_reg( R_ECX, Rn );
nkeynes@408
  1403
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1404
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1405
	sh4_translate_instruction(pc+2);
nkeynes@408
  1406
	exit_block_pcset(pc+2);
nkeynes@409
  1407
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1408
	return 4;
nkeynes@374
  1409
    }
nkeynes@374
  1410
:}
nkeynes@374
  1411
JSR @Rn {:  
nkeynes@374
  1412
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1413
	SLOTILLEGAL();
nkeynes@374
  1414
    } else {
nkeynes@374
  1415
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1416
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1417
	load_reg( R_ECX, Rn );
nkeynes@408
  1418
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1419
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1420
	sh4_translate_instruction(pc+2);
nkeynes@408
  1421
	exit_block_pcset(pc+2);
nkeynes@409
  1422
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1423
	return 4;
nkeynes@374
  1424
    }
nkeynes@374
  1425
:}
nkeynes@374
  1426
RTE {:  
nkeynes@374
  1427
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1428
	SLOTILLEGAL();
nkeynes@374
  1429
    } else {
nkeynes@408
  1430
	check_priv();
nkeynes@408
  1431
	load_spreg( R_ECX, R_SPC );
nkeynes@408
  1432
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1433
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1434
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1435
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1436
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1437
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1438
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@526
  1439
	sh4_translate_instruction(pc+2);
nkeynes@408
  1440
	exit_block_pcset(pc+2);
nkeynes@409
  1441
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1442
	return 4;
nkeynes@374
  1443
    }
nkeynes@374
  1444
:}
nkeynes@374
  1445
RTS {:  
nkeynes@374
  1446
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1447
	SLOTILLEGAL();
nkeynes@374
  1448
    } else {
nkeynes@408
  1449
	load_spreg( R_ECX, R_PR );
nkeynes@408
  1450
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@374
  1451
	sh4_x86.in_delay_slot = TRUE;
nkeynes@526
  1452
	sh4_translate_instruction(pc+2);
nkeynes@408
  1453
	exit_block_pcset(pc+2);
nkeynes@409
  1454
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1455
	return 4;
nkeynes@374
  1456
    }
nkeynes@374
  1457
:}
nkeynes@374
  1458
TRAPA #imm {:  
nkeynes@374
  1459
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1460
	SLOTILLEGAL();
nkeynes@374
  1461
    } else {
nkeynes@533
  1462
	load_imm32( R_ECX, pc+2 );
nkeynes@533
  1463
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@527
  1464
	load_imm32( R_EAX, imm );
nkeynes@527
  1465
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1466
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1467
	exit_block_pcset(pc);
nkeynes@409
  1468
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1469
	return 2;
nkeynes@374
  1470
    }
nkeynes@374
  1471
:}
nkeynes@374
  1472
UNDEF {:  
nkeynes@374
  1473
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1474
	SLOTILLEGAL();
nkeynes@374
  1475
    } else {
nkeynes@559
  1476
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1477
	return 2;
nkeynes@374
  1478
    }
nkeynes@368
  1479
:}
nkeynes@374
  1480
nkeynes@374
  1481
CLRMAC {:  
nkeynes@374
  1482
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1483
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1484
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1485
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1486
:}
nkeynes@374
  1487
CLRS {:
nkeynes@374
  1488
    CLC();
nkeynes@374
  1489
    SETC_sh4r(R_S);
nkeynes@417
  1490
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1491
:}
nkeynes@374
  1492
CLRT {:  
nkeynes@374
  1493
    CLC();
nkeynes@374
  1494
    SETC_t();
nkeynes@417
  1495
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1496
:}
nkeynes@374
  1497
SETS {:  
nkeynes@374
  1498
    STC();
nkeynes@374
  1499
    SETC_sh4r(R_S);
nkeynes@417
  1500
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1501
:}
nkeynes@374
  1502
SETT {:  
nkeynes@374
  1503
    STC();
nkeynes@374
  1504
    SETC_t();
nkeynes@417
  1505
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1506
:}
nkeynes@359
  1507
nkeynes@375
  1508
/* Floating point moves */
nkeynes@375
  1509
FMOV FRm, FRn {:  
nkeynes@375
  1510
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1511
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1512
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1513
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1514
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1515
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1516
     */
nkeynes@377
  1517
    check_fpuen();
nkeynes@375
  1518
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1519
    load_fr_bank( R_EDX );
nkeynes@375
  1520
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1521
    JNE_rel8(8, doublesize);
nkeynes@375
  1522
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1523
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1524
    if( FRm&1 ) {
nkeynes@386
  1525
	JMP_rel8(24, end);
nkeynes@380
  1526
	JMP_TARGET(doublesize);
nkeynes@375
  1527
	load_xf_bank( R_ECX ); 
nkeynes@375
  1528
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1529
	if( FRn&1 ) {
nkeynes@375
  1530
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1531
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1532
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1533
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1534
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1535
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1536
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1537
	}
nkeynes@380
  1538
	JMP_TARGET(end);
nkeynes@375
  1539
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1540
	if( FRn&1 ) {
nkeynes@386
  1541
	    JMP_rel8(24, end);
nkeynes@375
  1542
	    load_xf_bank( R_ECX );
nkeynes@375
  1543
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1544
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1545
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1546
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1547
	    JMP_TARGET(end);
nkeynes@375
  1548
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1549
	    JMP_rel8(12, end);
nkeynes@375
  1550
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1551
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1552
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1553
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1554
	    JMP_TARGET(end);
nkeynes@375
  1555
	}
nkeynes@375
  1556
    }
nkeynes@417
  1557
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1558
:}
nkeynes@416
  1559
FMOV FRm, @Rn {: 
nkeynes@559
  1560
    check_fpuen();
nkeynes@416
  1561
    load_reg( R_ECX, Rn );
nkeynes@416
  1562
    check_walign32( R_ECX );
nkeynes@416
  1563
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1564
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1565
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1566
    load_fr_bank( R_EDX );
nkeynes@416
  1567
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1568
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@375
  1569
    if( FRm&1 ) {
nkeynes@527
  1570
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1571
	JMP_TARGET(doublesize);
nkeynes@416
  1572
	load_xf_bank( R_EDX );
nkeynes@416
  1573
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1574
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1575
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1576
	JMP_TARGET(end);
nkeynes@375
  1577
    } else {
nkeynes@527
  1578
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1579
	JMP_TARGET(doublesize);
nkeynes@416
  1580
	load_fr_bank( R_EDX );
nkeynes@416
  1581
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1582
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1583
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1584
	JMP_TARGET(end);
nkeynes@375
  1585
    }
nkeynes@417
  1586
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1587
:}
nkeynes@375
  1588
FMOV @Rm, FRn {:  
nkeynes@559
  1589
    check_fpuen();
nkeynes@416
  1590
    load_reg( R_ECX, Rm );
nkeynes@416
  1591
    check_ralign32( R_ECX );
nkeynes@416
  1592
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1593
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1594
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@416
  1595
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1596
    load_fr_bank( R_EDX );
nkeynes@416
  1597
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1598
    if( FRn&1 ) {
nkeynes@527
  1599
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1600
	JMP_TARGET(doublesize);
nkeynes@416
  1601
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1602
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1603
	load_xf_bank( R_EDX );
nkeynes@416
  1604
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1605
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1606
	JMP_TARGET(end);
nkeynes@375
  1607
    } else {
nkeynes@527
  1608
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1609
	JMP_TARGET(doublesize);
nkeynes@416
  1610
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1611
	load_fr_bank( R_EDX );
nkeynes@416
  1612
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1613
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1614
	JMP_TARGET(end);
nkeynes@375
  1615
    }
nkeynes@417
  1616
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1617
:}
nkeynes@377
  1618
FMOV FRm, @-Rn {:  
nkeynes@559
  1619
    check_fpuen();
nkeynes@416
  1620
    load_reg( R_ECX, Rn );
nkeynes@416
  1621
    check_walign32( R_ECX );
nkeynes@416
  1622
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1623
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1624
    JNE_rel8(14 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1625
    load_fr_bank( R_EDX );
nkeynes@416
  1626
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1627
    ADD_imm8s_r32(-4,R_ECX);
nkeynes@416
  1628
    store_reg( R_ECX, Rn );
nkeynes@416
  1629
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1630
    if( FRm&1 ) {
nkeynes@527
  1631
	JMP_rel8( 24 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1632
	JMP_TARGET(doublesize);
nkeynes@416
  1633
	load_xf_bank( R_EDX );
nkeynes@416
  1634
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1635
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1636
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1637
	store_reg( R_ECX, Rn );
nkeynes@416
  1638
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1639
	JMP_TARGET(end);
nkeynes@377
  1640
    } else {
nkeynes@527
  1641
	JMP_rel8( 15 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1642
	JMP_TARGET(doublesize);
nkeynes@416
  1643
	load_fr_bank( R_EDX );
nkeynes@416
  1644
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1645
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1646
	ADD_imm8s_r32(-8,R_ECX);
nkeynes@416
  1647
	store_reg( R_ECX, Rn );
nkeynes@416
  1648
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1649
	JMP_TARGET(end);
nkeynes@377
  1650
    }
nkeynes@417
  1651
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1652
:}
nkeynes@416
  1653
FMOV @Rm+, FRn {:
nkeynes@559
  1654
    check_fpuen();
nkeynes@416
  1655
    load_reg( R_ECX, Rm );
nkeynes@416
  1656
    check_ralign32( R_ECX );
nkeynes@416
  1657
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@416
  1658
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1659
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1660
    JNE_rel8(14 + MEM_READ_SIZE, doublesize);
nkeynes@377
  1661
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1662
    store_reg( R_EAX, Rm );
nkeynes@416
  1663
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1664
    load_fr_bank( R_EDX );
nkeynes@416
  1665
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1666
    if( FRn&1 ) {
nkeynes@527
  1667
	JMP_rel8(27 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1668
	JMP_TARGET(doublesize);
nkeynes@377
  1669
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1670
	store_reg(R_EAX, Rm);
nkeynes@416
  1671
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1672
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1673
	load_xf_bank( R_EDX );
nkeynes@416
  1674
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1675
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1676
	JMP_TARGET(end);
nkeynes@377
  1677
    } else {
nkeynes@527
  1678
	JMP_rel8(15 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@377
  1679
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1680
	store_reg(R_EAX, Rm);
nkeynes@416
  1681
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1682
	load_fr_bank( R_EDX );
nkeynes@416
  1683
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1684
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1685
	JMP_TARGET(end);
nkeynes@377
  1686
    }
nkeynes@417
  1687
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1688
:}
nkeynes@377
  1689
FMOV FRm, @(R0, Rn) {:  
nkeynes@559
  1690
    check_fpuen();
nkeynes@416
  1691
    load_reg( R_ECX, Rn );
nkeynes@416
  1692
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1693
    check_walign32( R_ECX );
nkeynes@416
  1694
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1695
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1696
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1697
    load_fr_bank( R_EDX );
nkeynes@416
  1698
    load_fr( R_EDX, R_EAX, FRm );
nkeynes@416
  1699
    MEM_WRITE_LONG( R_ECX, R_EAX ); // 12
nkeynes@377
  1700
    if( FRm&1 ) {
nkeynes@527
  1701
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1702
	JMP_TARGET(doublesize);
nkeynes@416
  1703
	load_xf_bank( R_EDX );
nkeynes@416
  1704
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1705
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1706
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1707
	JMP_TARGET(end);
nkeynes@377
  1708
    } else {
nkeynes@527
  1709
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1710
	JMP_TARGET(doublesize);
nkeynes@416
  1711
	load_fr_bank( R_EDX );
nkeynes@416
  1712
	load_fr( R_EDX, R_EAX, FRm&0x0E );
nkeynes@416
  1713
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@416
  1714
	MEM_WRITE_DOUBLE( R_ECX, R_EAX, R_EDX );
nkeynes@380
  1715
	JMP_TARGET(end);
nkeynes@377
  1716
    }
nkeynes@417
  1717
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1718
:}
nkeynes@377
  1719
FMOV @(R0, Rm), FRn {:  
nkeynes@559
  1720
    check_fpuen();
nkeynes@416
  1721
    load_reg( R_ECX, Rm );
nkeynes@416
  1722
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_ECX );
nkeynes@416
  1723
    check_ralign32( R_ECX );
nkeynes@416
  1724
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1725
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@559
  1726
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@416
  1727
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@416
  1728
    load_fr_bank( R_EDX );
nkeynes@416
  1729
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1730
    if( FRn&1 ) {
nkeynes@527
  1731
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1732
	JMP_TARGET(doublesize);
nkeynes@416
  1733
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1734
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1735
	load_xf_bank( R_EDX );
nkeynes@416
  1736
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1737
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1738
	JMP_TARGET(end);
nkeynes@377
  1739
    } else {
nkeynes@527
  1740
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1741
	JMP_TARGET(doublesize);
nkeynes@416
  1742
	MEM_READ_DOUBLE( R_ECX, R_EAX, R_ECX );
nkeynes@416
  1743
	load_fr_bank( R_EDX );
nkeynes@416
  1744
	store_fr( R_EDX, R_EAX, FRn&0x0E );
nkeynes@416
  1745
	store_fr( R_EDX, R_ECX, FRn|0x01 );
nkeynes@380
  1746
	JMP_TARGET(end);
nkeynes@377
  1747
    }
nkeynes@417
  1748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1749
:}
nkeynes@377
  1750
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1751
    check_fpuen();
nkeynes@377
  1752
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1753
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1754
    JNE_rel8(8, end);
nkeynes@377
  1755
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1756
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1757
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1758
    JMP_TARGET(end);
nkeynes@417
  1759
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1760
:}
nkeynes@377
  1761
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1762
    check_fpuen();
nkeynes@377
  1763
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1764
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1765
    JNE_rel8(11, end);
nkeynes@377
  1766
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1767
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1768
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1769
    JMP_TARGET(end);
nkeynes@417
  1770
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1771
:}
nkeynes@377
  1772
nkeynes@377
  1773
FLOAT FPUL, FRn {:  
nkeynes@377
  1774
    check_fpuen();
nkeynes@377
  1775
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1776
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1777
    FILD_sh4r(R_FPUL);
nkeynes@377
  1778
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1779
    JNE_rel8(5, doubleprec);
nkeynes@377
  1780
    pop_fr( R_EDX, FRn );
nkeynes@380
  1781
    JMP_rel8(3, end);
nkeynes@380
  1782
    JMP_TARGET(doubleprec);
nkeynes@377
  1783
    pop_dr( R_EDX, FRn );
nkeynes@380
  1784
    JMP_TARGET(end);
nkeynes@417
  1785
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1786
:}
nkeynes@377
  1787
FTRC FRm, FPUL {:  
nkeynes@377
  1788
    check_fpuen();
nkeynes@388
  1789
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  1790
    load_fr_bank( R_EDX );
nkeynes@388
  1791
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  1792
    JNE_rel8(5, doubleprec);
nkeynes@388
  1793
    push_fr( R_EDX, FRm );
nkeynes@388
  1794
    JMP_rel8(3, doop);
nkeynes@388
  1795
    JMP_TARGET(doubleprec);
nkeynes@388
  1796
    push_dr( R_EDX, FRm );
nkeynes@388
  1797
    JMP_TARGET( doop );
nkeynes@388
  1798
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  1799
    FILD_r32ind( R_ECX );
nkeynes@388
  1800
    FCOMIP_st(1);
nkeynes@394
  1801
    JNA_rel8( 32, sat );
nkeynes@388
  1802
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  1803
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1804
    FCOMIP_st(1);                   // 2
nkeynes@394
  1805
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  1806
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  1807
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  1808
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  1809
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1810
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1811
    FLDCW_r32ind( R_EAX );
nkeynes@388
  1812
    JMP_rel8( 9, end );             // 2
nkeynes@388
  1813
nkeynes@388
  1814
    JMP_TARGET(sat);
nkeynes@388
  1815
    JMP_TARGET(sat2);
nkeynes@388
  1816
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1817
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1818
    FPOP_st();
nkeynes@388
  1819
    JMP_TARGET(end);
nkeynes@417
  1820
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1821
:}
nkeynes@377
  1822
FLDS FRm, FPUL {:  
nkeynes@377
  1823
    check_fpuen();
nkeynes@377
  1824
    load_fr_bank( R_ECX );
nkeynes@377
  1825
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1826
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1827
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1828
:}
nkeynes@377
  1829
FSTS FPUL, FRn {:  
nkeynes@377
  1830
    check_fpuen();
nkeynes@377
  1831
    load_fr_bank( R_ECX );
nkeynes@377
  1832
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1833
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  1834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1835
:}
nkeynes@377
  1836
FCNVDS FRm, FPUL {:  
nkeynes@377
  1837
    check_fpuen();
nkeynes@377
  1838
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1839
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1840
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1841
    load_fr_bank( R_ECX );
nkeynes@377
  1842
    push_dr( R_ECX, FRm );
nkeynes@377
  1843
    pop_fpul();
nkeynes@380
  1844
    JMP_TARGET(end);
nkeynes@417
  1845
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1846
:}
nkeynes@377
  1847
FCNVSD FPUL, FRn {:  
nkeynes@377
  1848
    check_fpuen();
nkeynes@377
  1849
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1850
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1851
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1852
    load_fr_bank( R_ECX );
nkeynes@377
  1853
    push_fpul();
nkeynes@377
  1854
    pop_dr( R_ECX, FRn );
nkeynes@380
  1855
    JMP_TARGET(end);
nkeynes@417
  1856
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1857
:}
nkeynes@375
  1858
nkeynes@359
  1859
/* Floating point instructions */
nkeynes@374
  1860
FABS FRn {:  
nkeynes@377
  1861
    check_fpuen();
nkeynes@374
  1862
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1863
    load_fr_bank( R_EDX );
nkeynes@374
  1864
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1865
    JNE_rel8(10, doubleprec);
nkeynes@374
  1866
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1867
    FABS_st0(); // 2
nkeynes@374
  1868
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1869
    JMP_rel8(8,end); // 2
nkeynes@380
  1870
    JMP_TARGET(doubleprec);
nkeynes@374
  1871
    push_dr(R_EDX, FRn);
nkeynes@374
  1872
    FABS_st0();
nkeynes@374
  1873
    pop_dr(R_EDX, FRn);
nkeynes@380
  1874
    JMP_TARGET(end);
nkeynes@417
  1875
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1876
:}
nkeynes@377
  1877
FADD FRm, FRn {:  
nkeynes@377
  1878
    check_fpuen();
nkeynes@375
  1879
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1880
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1881
    load_fr_bank( R_EDX );
nkeynes@380
  1882
    JNE_rel8(13,doubleprec);
nkeynes@377
  1883
    push_fr(R_EDX, FRm);
nkeynes@377
  1884
    push_fr(R_EDX, FRn);
nkeynes@377
  1885
    FADDP_st(1);
nkeynes@377
  1886
    pop_fr(R_EDX, FRn);
nkeynes@380
  1887
    JMP_rel8(11,end);
nkeynes@380
  1888
    JMP_TARGET(doubleprec);
nkeynes@377
  1889
    push_dr(R_EDX, FRm);
nkeynes@377
  1890
    push_dr(R_EDX, FRn);
nkeynes@377
  1891
    FADDP_st(1);
nkeynes@377
  1892
    pop_dr(R_EDX, FRn);
nkeynes@380
  1893
    JMP_TARGET(end);
nkeynes@417
  1894
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1895
:}
nkeynes@377
  1896
FDIV FRm, FRn {:  
nkeynes@377
  1897
    check_fpuen();
nkeynes@375
  1898
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1899
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1900
    load_fr_bank( R_EDX );
nkeynes@380
  1901
    JNE_rel8(13, doubleprec);
nkeynes@377
  1902
    push_fr(R_EDX, FRn);
nkeynes@377
  1903
    push_fr(R_EDX, FRm);
nkeynes@377
  1904
    FDIVP_st(1);
nkeynes@377
  1905
    pop_fr(R_EDX, FRn);
nkeynes@380
  1906
    JMP_rel8(11, end);
nkeynes@380
  1907
    JMP_TARGET(doubleprec);
nkeynes@377
  1908
    push_dr(R_EDX, FRn);
nkeynes@377
  1909
    push_dr(R_EDX, FRm);
nkeynes@377
  1910
    FDIVP_st(1);
nkeynes@377
  1911
    pop_dr(R_EDX, FRn);
nkeynes@380
  1912
    JMP_TARGET(end);
nkeynes@417
  1913
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1914
:}
nkeynes@375
  1915
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1916
    check_fpuen();
nkeynes@375
  1917
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1918
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1919
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1920
    JNE_rel8(18, doubleprec);
nkeynes@375
  1921
    push_fr( R_EDX, 0 );
nkeynes@375
  1922
    push_fr( R_EDX, FRm );
nkeynes@375
  1923
    FMULP_st(1);
nkeynes@375
  1924
    push_fr( R_EDX, FRn );
nkeynes@375
  1925
    FADDP_st(1);
nkeynes@375
  1926
    pop_fr( R_EDX, FRn );
nkeynes@380
  1927
    JMP_rel8(16, end);
nkeynes@380
  1928
    JMP_TARGET(doubleprec);
nkeynes@375
  1929
    push_dr( R_EDX, 0 );
nkeynes@375
  1930
    push_dr( R_EDX, FRm );
nkeynes@375
  1931
    FMULP_st(1);
nkeynes@375
  1932
    push_dr( R_EDX, FRn );
nkeynes@375
  1933
    FADDP_st(1);
nkeynes@375
  1934
    pop_dr( R_EDX, FRn );
nkeynes@380
  1935
    JMP_TARGET(end);
nkeynes@417
  1936
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1937
:}
nkeynes@375
  1938
nkeynes@377
  1939
FMUL FRm, FRn {:  
nkeynes@377
  1940
    check_fpuen();
nkeynes@377
  1941
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1942
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1943
    load_fr_bank( R_EDX );
nkeynes@380
  1944
    JNE_rel8(13, doubleprec);
nkeynes@377
  1945
    push_fr(R_EDX, FRm);
nkeynes@377
  1946
    push_fr(R_EDX, FRn);
nkeynes@377
  1947
    FMULP_st(1);
nkeynes@377
  1948
    pop_fr(R_EDX, FRn);
nkeynes@380
  1949
    JMP_rel8(11, end);
nkeynes@380
  1950
    JMP_TARGET(doubleprec);
nkeynes@377
  1951
    push_dr(R_EDX, FRm);
nkeynes@377
  1952
    push_dr(R_EDX, FRn);
nkeynes@377
  1953
    FMULP_st(1);
nkeynes@377
  1954
    pop_dr(R_EDX, FRn);
nkeynes@380
  1955
    JMP_TARGET(end);
nkeynes@417
  1956
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1957
:}
nkeynes@377
  1958
FNEG FRn {:  
nkeynes@377
  1959
    check_fpuen();
nkeynes@377
  1960
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1961
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1962
    load_fr_bank( R_EDX );
nkeynes@380
  1963
    JNE_rel8(10, doubleprec);
nkeynes@377
  1964
    push_fr(R_EDX, FRn);
nkeynes@377
  1965
    FCHS_st0();
nkeynes@377
  1966
    pop_fr(R_EDX, FRn);
nkeynes@380
  1967
    JMP_rel8(8, end);
nkeynes@380
  1968
    JMP_TARGET(doubleprec);
nkeynes@377
  1969
    push_dr(R_EDX, FRn);
nkeynes@377
  1970
    FCHS_st0();
nkeynes@377
  1971
    pop_dr(R_EDX, FRn);
nkeynes@380
  1972
    JMP_TARGET(end);
nkeynes@417
  1973
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1974
:}
nkeynes@377
  1975
FSRRA FRn {:  
nkeynes@377
  1976
    check_fpuen();
nkeynes@377
  1977
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1978
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1979
    load_fr_bank( R_EDX );
nkeynes@380
  1980
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1981
    FLD1_st0();
nkeynes@377
  1982
    push_fr(R_EDX, FRn);
nkeynes@377
  1983
    FSQRT_st0();
nkeynes@377
  1984
    FDIVP_st(1);
nkeynes@377
  1985
    pop_fr(R_EDX, FRn);
nkeynes@380
  1986
    JMP_TARGET(end);
nkeynes@417
  1987
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1988
:}
nkeynes@377
  1989
FSQRT FRn {:  
nkeynes@377
  1990
    check_fpuen();
nkeynes@377
  1991
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1992
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1993
    load_fr_bank( R_EDX );
nkeynes@380
  1994
    JNE_rel8(10, doubleprec);
nkeynes@377
  1995
    push_fr(R_EDX, FRn);
nkeynes@377
  1996
    FSQRT_st0();
nkeynes@377
  1997
    pop_fr(R_EDX, FRn);
nkeynes@380
  1998
    JMP_rel8(8, end);
nkeynes@380
  1999
    JMP_TARGET(doubleprec);
nkeynes@377
  2000
    push_dr(R_EDX, FRn);
nkeynes@377
  2001
    FSQRT_st0();
nkeynes@377
  2002
    pop_dr(R_EDX, FRn);
nkeynes@380
  2003
    JMP_TARGET(end);
nkeynes@417
  2004
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2005
:}
nkeynes@377
  2006
FSUB FRm, FRn {:  
nkeynes@377
  2007
    check_fpuen();
nkeynes@377
  2008
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2009
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2010
    load_fr_bank( R_EDX );
nkeynes@380
  2011
    JNE_rel8(13, doubleprec);
nkeynes@377
  2012
    push_fr(R_EDX, FRn);
nkeynes@377
  2013
    push_fr(R_EDX, FRm);
nkeynes@388
  2014
    FSUBP_st(1);
nkeynes@377
  2015
    pop_fr(R_EDX, FRn);
nkeynes@380
  2016
    JMP_rel8(11, end);
nkeynes@380
  2017
    JMP_TARGET(doubleprec);
nkeynes@377
  2018
    push_dr(R_EDX, FRn);
nkeynes@377
  2019
    push_dr(R_EDX, FRm);
nkeynes@388
  2020
    FSUBP_st(1);
nkeynes@377
  2021
    pop_dr(R_EDX, FRn);
nkeynes@380
  2022
    JMP_TARGET(end);
nkeynes@417
  2023
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2024
:}
nkeynes@377
  2025
nkeynes@377
  2026
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2027
    check_fpuen();
nkeynes@377
  2028
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2029
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2030
    load_fr_bank( R_EDX );
nkeynes@380
  2031
    JNE_rel8(8, doubleprec);
nkeynes@377
  2032
    push_fr(R_EDX, FRm);
nkeynes@377
  2033
    push_fr(R_EDX, FRn);
nkeynes@380
  2034
    JMP_rel8(6, end);
nkeynes@380
  2035
    JMP_TARGET(doubleprec);
nkeynes@377
  2036
    push_dr(R_EDX, FRm);
nkeynes@377
  2037
    push_dr(R_EDX, FRn);
nkeynes@382
  2038
    JMP_TARGET(end);
nkeynes@377
  2039
    FCOMIP_st(1);
nkeynes@377
  2040
    SETE_t();
nkeynes@377
  2041
    FPOP_st();
nkeynes@417
  2042
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2043
:}
nkeynes@377
  2044
FCMP/GT FRm, FRn {:  
nkeynes@377
  2045
    check_fpuen();
nkeynes@377
  2046
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2047
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2048
    load_fr_bank( R_EDX );
nkeynes@380
  2049
    JNE_rel8(8, doubleprec);
nkeynes@377
  2050
    push_fr(R_EDX, FRm);
nkeynes@377
  2051
    push_fr(R_EDX, FRn);
nkeynes@380
  2052
    JMP_rel8(6, end);
nkeynes@380
  2053
    JMP_TARGET(doubleprec);
nkeynes@377
  2054
    push_dr(R_EDX, FRm);
nkeynes@377
  2055
    push_dr(R_EDX, FRn);
nkeynes@380
  2056
    JMP_TARGET(end);
nkeynes@377
  2057
    FCOMIP_st(1);
nkeynes@377
  2058
    SETA_t();
nkeynes@377
  2059
    FPOP_st();
nkeynes@417
  2060
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2061
:}
nkeynes@377
  2062
nkeynes@377
  2063
FSCA FPUL, FRn {:  
nkeynes@377
  2064
    check_fpuen();
nkeynes@388
  2065
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2066
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2067
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2068
    load_fr_bank( R_ECX );
nkeynes@388
  2069
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2070
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2071
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2072
    JMP_TARGET(doubleprec);
nkeynes@417
  2073
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2074
:}
nkeynes@377
  2075
FIPR FVm, FVn {:  
nkeynes@377
  2076
    check_fpuen();
nkeynes@388
  2077
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2078
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2079
    JNE_rel8(44, doubleprec);
nkeynes@388
  2080
    
nkeynes@388
  2081
    load_fr_bank( R_ECX );
nkeynes@388
  2082
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2083
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2084
    FMULP_st(1);
nkeynes@388
  2085
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2086
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2087
    FMULP_st(1);
nkeynes@388
  2088
    FADDP_st(1);
nkeynes@388
  2089
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2090
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2091
    FMULP_st(1);
nkeynes@388
  2092
    FADDP_st(1);
nkeynes@388
  2093
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2094
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2095
    FMULP_st(1);
nkeynes@388
  2096
    FADDP_st(1);
nkeynes@388
  2097
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2098
    JMP_TARGET(doubleprec);
nkeynes@417
  2099
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2100
:}
nkeynes@377
  2101
FTRV XMTRX, FVn {:  
nkeynes@377
  2102
    check_fpuen();
nkeynes@388
  2103
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2104
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2105
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2106
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2107
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2108
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2109
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2110
    JMP_TARGET(doubleprec);
nkeynes@417
  2111
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2112
:}
nkeynes@377
  2113
nkeynes@377
  2114
FRCHG {:  
nkeynes@377
  2115
    check_fpuen();
nkeynes@377
  2116
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2117
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2118
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2119
    update_fr_bank( R_ECX );
nkeynes@417
  2120
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2121
:}
nkeynes@377
  2122
FSCHG {:  
nkeynes@377
  2123
    check_fpuen();
nkeynes@377
  2124
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2125
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2126
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2127
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2128
:}
nkeynes@359
  2129
nkeynes@359
  2130
/* Processor control instructions */
nkeynes@368
  2131
LDC Rm, SR {:
nkeynes@386
  2132
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2133
	SLOTILLEGAL();
nkeynes@386
  2134
    } else {
nkeynes@386
  2135
	check_priv();
nkeynes@386
  2136
	load_reg( R_EAX, Rm );
nkeynes@386
  2137
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2138
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2139
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2140
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2141
    }
nkeynes@368
  2142
:}
nkeynes@359
  2143
LDC Rm, GBR {: 
nkeynes@359
  2144
    load_reg( R_EAX, Rm );
nkeynes@359
  2145
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2146
:}
nkeynes@359
  2147
LDC Rm, VBR {:  
nkeynes@386
  2148
    check_priv();
nkeynes@359
  2149
    load_reg( R_EAX, Rm );
nkeynes@359
  2150
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2151
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2152
:}
nkeynes@359
  2153
LDC Rm, SSR {:  
nkeynes@386
  2154
    check_priv();
nkeynes@359
  2155
    load_reg( R_EAX, Rm );
nkeynes@359
  2156
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2157
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2158
:}
nkeynes@359
  2159
LDC Rm, SGR {:  
nkeynes@386
  2160
    check_priv();
nkeynes@359
  2161
    load_reg( R_EAX, Rm );
nkeynes@359
  2162
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2164
:}
nkeynes@359
  2165
LDC Rm, SPC {:  
nkeynes@386
  2166
    check_priv();
nkeynes@359
  2167
    load_reg( R_EAX, Rm );
nkeynes@359
  2168
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2169
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2170
:}
nkeynes@359
  2171
LDC Rm, DBR {:  
nkeynes@386
  2172
    check_priv();
nkeynes@359
  2173
    load_reg( R_EAX, Rm );
nkeynes@359
  2174
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2175
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2176
:}
nkeynes@374
  2177
LDC Rm, Rn_BANK {:  
nkeynes@386
  2178
    check_priv();
nkeynes@374
  2179
    load_reg( R_EAX, Rm );
nkeynes@374
  2180
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2181
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2182
:}
nkeynes@359
  2183
LDC.L @Rm+, GBR {:  
nkeynes@359
  2184
    load_reg( R_EAX, Rm );
nkeynes@395
  2185
    check_ralign32( R_EAX );
nkeynes@359
  2186
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2187
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2188
    store_reg( R_EAX, Rm );
nkeynes@359
  2189
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2190
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2191
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2192
:}
nkeynes@368
  2193
LDC.L @Rm+, SR {:
nkeynes@386
  2194
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2195
	SLOTILLEGAL();
nkeynes@386
  2196
    } else {
nkeynes@559
  2197
	check_priv();
nkeynes@386
  2198
	load_reg( R_EAX, Rm );
nkeynes@395
  2199
	check_ralign32( R_EAX );
nkeynes@386
  2200
	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2201
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  2202
	store_reg( R_EAX, Rm );
nkeynes@386
  2203
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  2204
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2205
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2206
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2207
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2208
    }
nkeynes@359
  2209
:}
nkeynes@359
  2210
LDC.L @Rm+, VBR {:  
nkeynes@559
  2211
    check_priv();
nkeynes@359
  2212
    load_reg( R_EAX, Rm );
nkeynes@395
  2213
    check_ralign32( R_EAX );
nkeynes@359
  2214
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2215
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2216
    store_reg( R_EAX, Rm );
nkeynes@359
  2217
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2218
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2219
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2220
:}
nkeynes@359
  2221
LDC.L @Rm+, SSR {:
nkeynes@559
  2222
    check_priv();
nkeynes@359
  2223
    load_reg( R_EAX, Rm );
nkeynes@416
  2224
    check_ralign32( R_EAX );
nkeynes@359
  2225
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2226
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2227
    store_reg( R_EAX, Rm );
nkeynes@359
  2228
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2229
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2230
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2231
:}
nkeynes@359
  2232
LDC.L @Rm+, SGR {:  
nkeynes@559
  2233
    check_priv();
nkeynes@359
  2234
    load_reg( R_EAX, Rm );
nkeynes@395
  2235
    check_ralign32( R_EAX );
nkeynes@359
  2236
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2237
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2238
    store_reg( R_EAX, Rm );
nkeynes@359
  2239
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2240
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2241
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2242
:}
nkeynes@359
  2243
LDC.L @Rm+, SPC {:  
nkeynes@559
  2244
    check_priv();
nkeynes@359
  2245
    load_reg( R_EAX, Rm );
nkeynes@395
  2246
    check_ralign32( R_EAX );
nkeynes@359
  2247
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2248
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2249
    store_reg( R_EAX, Rm );
nkeynes@359
  2250
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2251
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2252
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2253
:}
nkeynes@359
  2254
LDC.L @Rm+, DBR {:  
nkeynes@559
  2255
    check_priv();
nkeynes@359
  2256
    load_reg( R_EAX, Rm );
nkeynes@395
  2257
    check_ralign32( R_EAX );
nkeynes@359
  2258
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2259
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2260
    store_reg( R_EAX, Rm );
nkeynes@359
  2261
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2262
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2263
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2264
:}
nkeynes@359
  2265
LDC.L @Rm+, Rn_BANK {:  
nkeynes@559
  2266
    check_priv();
nkeynes@374
  2267
    load_reg( R_EAX, Rm );
nkeynes@395
  2268
    check_ralign32( R_EAX );
nkeynes@374
  2269
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2270
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  2271
    store_reg( R_EAX, Rm );
nkeynes@374
  2272
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2273
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2274
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2275
:}
nkeynes@359
  2276
LDS Rm, FPSCR {:  
nkeynes@359
  2277
    load_reg( R_EAX, Rm );
nkeynes@359
  2278
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2279
    update_fr_bank( R_EAX );
nkeynes@417
  2280
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2281
:}
nkeynes@359
  2282
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2283
    load_reg( R_EAX, Rm );
nkeynes@395
  2284
    check_ralign32( R_EAX );
nkeynes@359
  2285
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2286
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2287
    store_reg( R_EAX, Rm );
nkeynes@359
  2288
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2289
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2290
    update_fr_bank( R_EAX );
nkeynes@417
  2291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2292
:}
nkeynes@359
  2293
LDS Rm, FPUL {:  
nkeynes@359
  2294
    load_reg( R_EAX, Rm );
nkeynes@359
  2295
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2296
:}
nkeynes@359
  2297
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2298
    load_reg( R_EAX, Rm );
nkeynes@395
  2299
    check_ralign32( R_EAX );
nkeynes@359
  2300
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2301
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2302
    store_reg( R_EAX, Rm );
nkeynes@359
  2303
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2304
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2305
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2306
:}
nkeynes@359
  2307
LDS Rm, MACH {: 
nkeynes@359
  2308
    load_reg( R_EAX, Rm );
nkeynes@359
  2309
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2310
:}
nkeynes@359
  2311
LDS.L @Rm+, MACH {:  
nkeynes@359
  2312
    load_reg( R_EAX, Rm );
nkeynes@395
  2313
    check_ralign32( R_EAX );
nkeynes@359
  2314
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2315
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2316
    store_reg( R_EAX, Rm );
nkeynes@359
  2317
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2318
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2320
:}
nkeynes@359
  2321
LDS Rm, MACL {:  
nkeynes@359
  2322
    load_reg( R_EAX, Rm );
nkeynes@359
  2323
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2324
:}
nkeynes@359
  2325
LDS.L @Rm+, MACL {:  
nkeynes@359
  2326
    load_reg( R_EAX, Rm );
nkeynes@395
  2327
    check_ralign32( R_EAX );
nkeynes@359
  2328
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2329
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2330
    store_reg( R_EAX, Rm );
nkeynes@359
  2331
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2332
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2334
:}
nkeynes@359
  2335
LDS Rm, PR {:  
nkeynes@359
  2336
    load_reg( R_EAX, Rm );
nkeynes@359
  2337
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2338
:}
nkeynes@359
  2339
LDS.L @Rm+, PR {:  
nkeynes@359
  2340
    load_reg( R_EAX, Rm );
nkeynes@395
  2341
    check_ralign32( R_EAX );
nkeynes@359
  2342
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2343
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  2344
    store_reg( R_EAX, Rm );
nkeynes@359
  2345
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2346
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2347
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2348
:}
nkeynes@550
  2349
LDTLB {:  
nkeynes@553
  2350
    call_func0( MMU_ldtlb );
nkeynes@550
  2351
:}
nkeynes@359
  2352
OCBI @Rn {:  :}
nkeynes@359
  2353
OCBP @Rn {:  :}
nkeynes@359
  2354
OCBWB @Rn {:  :}
nkeynes@374
  2355
PREF @Rn {:
nkeynes@374
  2356
    load_reg( R_EAX, Rn );
nkeynes@532
  2357
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2358
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2359
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@532
  2360
    JNE_rel8(CALL_FUNC1_SIZE, end);
nkeynes@532
  2361
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@380
  2362
    JMP_TARGET(end);
nkeynes@417
  2363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2364
:}
nkeynes@388
  2365
SLEEP {: 
nkeynes@388
  2366
    check_priv();
nkeynes@388
  2367
    call_func0( sh4_sleep );
nkeynes@417
  2368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  2369
    sh4_x86.in_delay_slot = FALSE;
nkeynes@408
  2370
    return 2;
nkeynes@388
  2371
:}
nkeynes@386
  2372
STC SR, Rn {:
nkeynes@386
  2373
    check_priv();
nkeynes@386
  2374
    call_func0(sh4_read_sr);
nkeynes@386
  2375
    store_reg( R_EAX, Rn );
nkeynes@417
  2376
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2377
:}
nkeynes@359
  2378
STC GBR, Rn {:  
nkeynes@359
  2379
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2380
    store_reg( R_EAX, Rn );
nkeynes@359
  2381
:}
nkeynes@359
  2382
STC VBR, Rn {:  
nkeynes@386
  2383
    check_priv();
nkeynes@359
  2384
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2385
    store_reg( R_EAX, Rn );
nkeynes@417
  2386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2387
:}
nkeynes@359
  2388
STC SSR, Rn {:  
nkeynes@386
  2389
    check_priv();
nkeynes@359
  2390
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2391
    store_reg( R_EAX, Rn );
nkeynes@417
  2392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2393
:}
nkeynes@359
  2394
STC SPC, Rn {:  
nkeynes@386
  2395
    check_priv();
nkeynes@359
  2396
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2397
    store_reg( R_EAX, Rn );
nkeynes@417
  2398
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2399
:}
nkeynes@359
  2400
STC SGR, Rn {:  
nkeynes@386
  2401
    check_priv();
nkeynes@359
  2402
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2403
    store_reg( R_EAX, Rn );
nkeynes@417
  2404
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2405
:}
nkeynes@359
  2406
STC DBR, Rn {:  
nkeynes@386
  2407
    check_priv();
nkeynes@359
  2408
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2409
    store_reg( R_EAX, Rn );
nkeynes@417
  2410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2411
:}
nkeynes@374
  2412
STC Rm_BANK, Rn {:
nkeynes@386
  2413
    check_priv();
nkeynes@374
  2414
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2415
    store_reg( R_EAX, Rn );
nkeynes@417
  2416
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2417
:}
nkeynes@374
  2418
STC.L SR, @-Rn {:
nkeynes@559
  2419
    check_priv();
nkeynes@395
  2420
    call_func0( sh4_read_sr );
nkeynes@368
  2421
    load_reg( R_ECX, Rn );
nkeynes@395
  2422
    check_walign32( R_ECX );
nkeynes@382
  2423
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2424
    store_reg( R_ECX, Rn );
nkeynes@368
  2425
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2426
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2427
:}
nkeynes@359
  2428
STC.L VBR, @-Rn {:  
nkeynes@559
  2429
    check_priv();
nkeynes@359
  2430
    load_reg( R_ECX, Rn );
nkeynes@395
  2431
    check_walign32( R_ECX );
nkeynes@382
  2432
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2433
    store_reg( R_ECX, Rn );
nkeynes@359
  2434
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2435
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2436
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2437
:}
nkeynes@359
  2438
STC.L SSR, @-Rn {:  
nkeynes@559
  2439
    check_priv();
nkeynes@359
  2440
    load_reg( R_ECX, Rn );
nkeynes@395
  2441
    check_walign32( R_ECX );
nkeynes@382
  2442
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2443
    store_reg( R_ECX, Rn );
nkeynes@359
  2444
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2445
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2446
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2447
:}
nkeynes@416
  2448
STC.L SPC, @-Rn {:
nkeynes@559
  2449
    check_priv();
nkeynes@359
  2450
    load_reg( R_ECX, Rn );
nkeynes@395
  2451
    check_walign32( R_ECX );
nkeynes@382
  2452
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2453
    store_reg( R_ECX, Rn );
nkeynes@359
  2454
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2455
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2456
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2457
:}
nkeynes@359
  2458
STC.L SGR, @-Rn {:  
nkeynes@559
  2459
    check_priv();
nkeynes@359
  2460
    load_reg( R_ECX, Rn );
nkeynes@395
  2461
    check_walign32( R_ECX );
nkeynes@382
  2462
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2463
    store_reg( R_ECX, Rn );
nkeynes@359
  2464
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2465
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2467
:}
nkeynes@359
  2468
STC.L DBR, @-Rn {:  
nkeynes@559
  2469
    check_priv();
nkeynes@359
  2470
    load_reg( R_ECX, Rn );
nkeynes@395
  2471
    check_walign32( R_ECX );
nkeynes@382
  2472
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2473
    store_reg( R_ECX, Rn );
nkeynes@359
  2474
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2475
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2476
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2477
:}
nkeynes@374
  2478
STC.L Rm_BANK, @-Rn {:  
nkeynes@559
  2479
    check_priv();
nkeynes@374
  2480
    load_reg( R_ECX, Rn );
nkeynes@395
  2481
    check_walign32( R_ECX );
nkeynes@382
  2482
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2483
    store_reg( R_ECX, Rn );
nkeynes@374
  2484
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2485
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2486
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2487
:}
nkeynes@359
  2488
STC.L GBR, @-Rn {:  
nkeynes@359
  2489
    load_reg( R_ECX, Rn );
nkeynes@395
  2490
    check_walign32( R_ECX );
nkeynes@382
  2491
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2492
    store_reg( R_ECX, Rn );
nkeynes@359
  2493
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2494
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2496
:}
nkeynes@359
  2497
STS FPSCR, Rn {:  
nkeynes@359
  2498
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2499
    store_reg( R_EAX, Rn );
nkeynes@359
  2500
:}
nkeynes@359
  2501
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2502
    load_reg( R_ECX, Rn );
nkeynes@395
  2503
    check_walign32( R_ECX );
nkeynes@382
  2504
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2505
    store_reg( R_ECX, Rn );
nkeynes@359
  2506
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2507
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2508
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2509
:}
nkeynes@359
  2510
STS FPUL, Rn {:  
nkeynes@359
  2511
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2512
    store_reg( R_EAX, Rn );
nkeynes@359
  2513
:}
nkeynes@359
  2514
STS.L FPUL, @-Rn {:  
nkeynes@359
  2515
    load_reg( R_ECX, Rn );
nkeynes@395
  2516
    check_walign32( R_ECX );
nkeynes@382
  2517
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2518
    store_reg( R_ECX, Rn );
nkeynes@359
  2519
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2520
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2521
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2522
:}
nkeynes@359
  2523
STS MACH, Rn {:  
nkeynes@359
  2524
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2525
    store_reg( R_EAX, Rn );
nkeynes@359
  2526
:}
nkeynes@359
  2527
STS.L MACH, @-Rn {:  
nkeynes@359
  2528
    load_reg( R_ECX, Rn );
nkeynes@395
  2529
    check_walign32( R_ECX );
nkeynes@382
  2530
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2531
    store_reg( R_ECX, Rn );
nkeynes@359
  2532
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2533
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2534
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2535
:}
nkeynes@359
  2536
STS MACL, Rn {:  
nkeynes@359
  2537
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2538
    store_reg( R_EAX, Rn );
nkeynes@359
  2539
:}
nkeynes@359
  2540
STS.L MACL, @-Rn {:  
nkeynes@359
  2541
    load_reg( R_ECX, Rn );
nkeynes@395
  2542
    check_walign32( R_ECX );
nkeynes@382
  2543
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2544
    store_reg( R_ECX, Rn );
nkeynes@359
  2545
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2546
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2547
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2548
:}
nkeynes@359
  2549
STS PR, Rn {:  
nkeynes@359
  2550
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2551
    store_reg( R_EAX, Rn );
nkeynes@359
  2552
:}
nkeynes@359
  2553
STS.L PR, @-Rn {:  
nkeynes@359
  2554
    load_reg( R_ECX, Rn );
nkeynes@395
  2555
    check_walign32( R_ECX );
nkeynes@382
  2556
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2557
    store_reg( R_ECX, Rn );
nkeynes@359
  2558
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2559
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2560
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2561
:}
nkeynes@359
  2562
nkeynes@359
  2563
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2564
%%
nkeynes@416
  2565
    sh4_x86.in_delay_slot = FALSE;
nkeynes@359
  2566
    return 0;
nkeynes@359
  2567
}
.