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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 1067:d3c00ffccfcd
prev1066:ddffe9d2b332
prev934:3acd3b3ee6d1
next1076:18c164e8aec4
author nkeynes
date Sun Jul 05 13:54:48 2009 +1000 (12 years ago)
permissions -rw-r--r--
last change No-op merge lxdream-mem to tip to remove head (Long since merged in
actuality)
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     1
/**
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 * $Id$
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include <assert.h>
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "pvr2/pvr2mmio.h"
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#include "pvr2/scene.h"
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#include "sh4/sh4.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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#define MAX_RENDER_BUFFERS 4
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
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static render_buffer_t pvr2_next_render_buffer( );
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static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
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static int render_colour_formats[8] = {
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        COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
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        COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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        pvr2_run_slice, NULL,
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        pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    int32_t palette_changed; /* TRUE if palette has changed since last render */
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    int32_t interlaced;
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} pvr2_state;
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static gchar *save_next_render_filename;
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static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
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static uint32_t render_buffer_count = 0;
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static render_buffer_t displayed_render_buffer = NULL;
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static uint32_t displayed_border_colour = 0;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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        pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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        while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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            pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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        }
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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                                  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) 
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{
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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        pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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        pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_gunpos_callback( int eventid ) 
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{
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
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    MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
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    asic_event( EVENT_MAPLE_DMA );
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}
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static void pvr2_init( void )
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{
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    int i;
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    save_next_render_filename = NULL;
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    for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
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        render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    displayed_render_buffer = NULL;
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    displayed_border_colour = 0;
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}
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static void pvr2_reset( void )
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{
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    int i;
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    pvr2_state.palette_changed = FALSE;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    pvr2_ta_init();
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    texcache_flush();
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    if( display_driver ) {
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        display_driver->display_blank(0);
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        for( i=0; i<render_buffer_count; i++ ) {
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            display_driver->destroy_render_buffer(render_buffers[i]);
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            render_buffers[i] = NULL;
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        }
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        render_buffer_count = 0;
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    }
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}
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void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
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{
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    struct frame_buffer fbuf;
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    fbuf.width = buffer->width;
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    fbuf.height = buffer->height;
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    fbuf.rowstride = fbuf.width*3;
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    fbuf.colour_format = COLFMT_BGR888;
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    fbuf.inverted = buffer->inverted;
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    fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
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    display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
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    write_png_to_stream( f, &fbuf );
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    g_free( fbuf.data );
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    fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
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    fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
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    fwrite( &buffer->address, sizeof(buffer->address), 1, f );
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    fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
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    int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
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    fwrite( &flushed, sizeof(flushed), 1, f );
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}
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render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
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{
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    frame_buffer_t frame = read_png_from_stream( f );
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    if( frame == NULL ) {
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        *status = FALSE;
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        return NULL;
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    }
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    *status = TRUE;
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    render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
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    if( buffer != NULL ) {
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        int32_t flushed;
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        fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
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        fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
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        fread( &buffer->address, sizeof(buffer->address), 1, f );
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        fread( &buffer->scale, sizeof(buffer->scale), 1, f );
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        fread( &flushed, sizeof(flushed), 1, f );
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        buffer->flushed = (gboolean)flushed;
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    } else {
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        fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
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                sizeof(buffer->address)+sizeof(buffer->scale)+
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                sizeof(int32_t), SEEK_CUR );
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    }
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    return buffer;
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}
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void pvr2_save_render_buffers( FILE *f )
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{
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    int i;
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    uint32_t has_frontbuffer;
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    fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
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    if( displayed_render_buffer != NULL ) {
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        has_frontbuffer = 1;
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        fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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        pvr2_save_render_buffer( f, displayed_render_buffer );
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    } else {
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        has_frontbuffer = 0;
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        fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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    }
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    for( i=0; i<render_buffer_count; i++ ) {
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        if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
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            pvr2_save_render_buffer( f, render_buffers[i] );
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        }
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    }
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}
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gboolean pvr2_load_render_buffers( FILE *f )
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{
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    uint32_t count, has_frontbuffer;
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    gboolean loadok;
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    int i;
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    fread( &count, sizeof(count), 1, f );
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    if( count > MAX_RENDER_BUFFERS ) {
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        return FALSE;
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    }
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    fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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    for( i=0; i<render_buffer_count; i++ ) {
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        display_driver->destroy_render_buffer(render_buffers[i]);
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        render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    if( has_frontbuffer ) {
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        displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
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        if( displayed_render_buffer != NULL )
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            display_driver->display_render_buffer( displayed_render_buffer );
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        else if( !loadok )
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            return FALSE;
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        count--;
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    }
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    for( i=0; i<count; i++ ) {
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        pvr2_load_render_buffer( f, &loadok );
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        if( !loadok )
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        	return FALSE;
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    }
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    return TRUE;
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}
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static void pvr2_save_state( FILE *f )
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{
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    pvr2_save_render_buffers( f );
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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   302
}
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   303
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static int pvr2_load_state( FILE *f )
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   305
{
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    if( !pvr2_load_render_buffers(f) )
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        return 1;
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   308
    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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   309
        return 1;
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   310
    if( pvr2_ta_load_state(f) ) {
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   311
        return 1;
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   312
    }
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    return pvr2_yuv_load_state(f);
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   314
}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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   321
static void pvr2_update_raster_posn( uint32_t nanosecs )
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   322
{
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   323
    uint32_t old_line_count = pvr2_state.line_count;
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   324
    if( pvr2_state.line_time_ns == 0 ) {
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   325
        return; /* do nothing */
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   326
    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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   329
    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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   330
        pvr2_state.line_count ++;
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   331
        pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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nkeynes@265
   334
    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
nkeynes@736
   335
        pvr2_state.line_count -= pvr2_state.total_lines;
nkeynes@736
   336
        if( pvr2_state.interlaced ) {
nkeynes@736
   337
            pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
nkeynes@736
   338
        }
nkeynes@265
   339
    }
nkeynes@265
   340
    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
nkeynes@736
   341
            (old_line_count < pvr2_state.retrace_end_line ||
nkeynes@736
   342
                    old_line_count > pvr2_state.line_count) ) {
nkeynes@736
   343
        pvr2_state.frame_count++;
nkeynes@736
   344
        pvr2_display_frame();
nkeynes@265
   345
    }
nkeynes@265
   346
}
nkeynes@265
   347
nkeynes@133
   348
static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
nkeynes@133
   349
{
nkeynes@265
   350
    pvr2_update_raster_posn( nanosecs );
nkeynes@265
   351
    pvr2_state.cycles_run = 0;
nkeynes@133
   352
    return nanosecs;
nkeynes@133
   353
}
nkeynes@133
   354
nkeynes@133
   355
int pvr2_get_frame_count() 
nkeynes@133
   356
{
nkeynes@133
   357
    return pvr2_state.frame_count;
nkeynes@106
   358
}
nkeynes@106
   359
nkeynes@677
   360
void pvr2_redraw_display()
nkeynes@477
   361
{
nkeynes@677
   362
    if( display_driver != NULL ) {
nkeynes@677
   363
        if( displayed_render_buffer == NULL ) {
nkeynes@677
   364
            display_driver->display_blank(displayed_border_colour);
nkeynes@677
   365
        } else {
nkeynes@677
   366
            display_driver->display_render_buffer(displayed_render_buffer);
nkeynes@677
   367
        }
nkeynes@677
   368
    }
nkeynes@545
   369
}
nkeynes@545
   370
nkeynes@295
   371
gboolean pvr2_save_next_scene( const gchar *filename )
nkeynes@295
   372
{
nkeynes@674
   373
    if( save_next_render_filename != NULL ) {
nkeynes@736
   374
        g_free( save_next_render_filename );
nkeynes@295
   375
    } 
nkeynes@674
   376
    save_next_render_filename = g_strdup(filename);
nkeynes@295
   377
    return TRUE;
nkeynes@295
   378
}
nkeynes@295
   379
nkeynes@295
   380
nkeynes@295
   381
nkeynes@103
   382
/**
nkeynes@1
   383
 * Display the next frame, copying the current contents of video ram to
nkeynes@1
   384
 * the window. If the video configuration has changed, first recompute the
nkeynes@1
   385
 * new frame size/depth.
nkeynes@1
   386
 */
nkeynes@94
   387
void pvr2_display_frame( void )
nkeynes@1
   388
{
nkeynes@197
   389
    int dispmode = MMIO_READ( PVR2, DISP_MODE );
nkeynes@261
   390
    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
nkeynes@335
   391
    gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
nkeynes@352
   392
nkeynes@352
   393
    if( display_driver == NULL ) {
nkeynes@736
   394
        return; /* can't really do anything much */
nkeynes@352
   395
    } else if( !bEnabled ) {
nkeynes@736
   396
        /* Output disabled == black */
nkeynes@736
   397
        displayed_render_buffer = NULL;
nkeynes@736
   398
        displayed_border_colour = 0;
nkeynes@736
   399
        display_driver->display_blank( 0 ); 
nkeynes@352
   400
    } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
nkeynes@736
   401
        /* Enabled but blanked - border colour */
nkeynes@736
   402
        displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
nkeynes@736
   403
        displayed_render_buffer = NULL;
nkeynes@736
   404
        display_driver->display_blank( displayed_border_colour );
nkeynes@352
   405
    } else {
nkeynes@736
   406
        /* Real output - determine dimensions etc */
nkeynes@736
   407
        struct frame_buffer fbuf;
nkeynes@736
   408
        uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
nkeynes@736
   409
        int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
nkeynes@736
   410
        int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
nkeynes@352
   411
nkeynes@736
   412
        fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
nkeynes@916
   413
        fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
nkeynes@736
   414
        fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
nkeynes@916
   415
        fbuf.size = (vid_ppl << 2) * fbuf.height;
nkeynes@736
   416
        fbuf.rowstride = (vid_ppl + vid_stride) << 2;
nkeynes@352
   417
nkeynes@736
   418
        /* Determine the field to display, and deinterlace if possible */
nkeynes@736
   419
        if( pvr2_state.interlaced ) {
nkeynes@736
   420
            if( vid_ppl == vid_stride ) { /* Magic deinterlace */
nkeynes@736
   421
                fbuf.height = fbuf.height << 1;
nkeynes@736
   422
                fbuf.rowstride = vid_ppl << 2;
nkeynes@736
   423
                fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   424
            } else { 
nkeynes@736
   425
                /* Just display the field as is, folks. This is slightly tricky -
nkeynes@736
   426
                 * we pick the field based on which frame is about to come through,
nkeynes@736
   427
                 * which may not be the same as the odd_even_field.
nkeynes@736
   428
                 */
nkeynes@736
   429
                gboolean oddfield = pvr2_state.odd_even_field;
nkeynes@736
   430
                if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
nkeynes@736
   431
                    oddfield = !oddfield;
nkeynes@736
   432
                }
nkeynes@736
   433
                if( oddfield ) {
nkeynes@736
   434
                    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   435
                } else {
nkeynes@736
   436
                    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@736
   437
                }
nkeynes@736
   438
            }
nkeynes@736
   439
        } else {
nkeynes@736
   440
            fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   441
        }
nkeynes@736
   442
        fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@736
   443
        fbuf.inverted = FALSE;
nkeynes@934
   444
        fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
nkeynes@352
   445
nkeynes@736
   446
        render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
nkeynes@736
   447
        if( rbuf == NULL ) {
nkeynes@736
   448
            rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
nkeynes@736
   449
        }
nkeynes@736
   450
        displayed_render_buffer = rbuf;
nkeynes@736
   451
        if( rbuf != NULL ) {
nkeynes@736
   452
            display_driver->display_render_buffer( rbuf );
nkeynes@736
   453
        }
nkeynes@1
   454
    }
nkeynes@1
   455
}
nkeynes@1
   456
nkeynes@197
   457
/**
nkeynes@197
   458
 * This has to handle every single register individually as they all get masked 
nkeynes@197
   459
 * off differently (and its easier to do it at write time)
nkeynes@197
   460
 */
nkeynes@929
   461
MMIO_REGION_WRITE_FN( PVR2, reg, val )
nkeynes@1
   462
{
nkeynes@929
   463
    reg &= 0xFFF;
nkeynes@1
   464
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   465
        MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   466
        return;
nkeynes@1
   467
    }
nkeynes@736
   468
nkeynes@1
   469
    switch(reg) {
nkeynes@189
   470
    case PVRID:
nkeynes@189
   471
    case PVRVER:
nkeynes@261
   472
    case GUNPOS: /* Read only registers */
nkeynes@736
   473
        break;
nkeynes@197
   474
    case PVRRESET:
nkeynes@736
   475
        val &= 0x00000007; /* Do stuff? */
nkeynes@736
   476
        MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   477
        break;
nkeynes@295
   478
    case RENDER_START: /* Don't really care what value */
nkeynes@736
   479
        if( save_next_render_filename != NULL ) {
nkeynes@736
   480
            if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
nkeynes@736
   481
                INFO( "Saved scene to %s", save_next_render_filename);
nkeynes@736
   482
            }
nkeynes@736
   483
            g_free( save_next_render_filename );
nkeynes@736
   484
            save_next_render_filename = NULL;
nkeynes@736
   485
        }
nkeynes@736
   486
        pvr2_scene_read();
nkeynes@736
   487
        render_buffer_t buffer = pvr2_next_render_buffer();
nkeynes@736
   488
        if( buffer != NULL ) {
nkeynes@736
   489
            pvr2_scene_render( buffer );
nkeynes@871
   490
            if( buffer->address < PVR2_RAM_BASE ) {
nkeynes@871
   491
                // Flush immediately - optimize this later. Otherwise this gets
nkeynes@871
   492
                // complicated very quickly trying to second-guess how it's
nkeynes@871
   493
                // going to be used as a texture.
nkeynes@921
   494
                pvr2_finish_render_buffer( buffer );
nkeynes@871
   495
                pvr2_render_buffer_copy_to_sh4( buffer );
nkeynes@871
   496
            }
nkeynes@736
   497
        }
nkeynes@736
   498
        asic_event( EVENT_PVR_RENDER_DONE );
nkeynes@736
   499
        break;
nkeynes@191
   500
    case RENDER_POLYBASE:
nkeynes@736
   501
        MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@736
   502
        break;
nkeynes@191
   503
    case RENDER_TSPCFG:
nkeynes@736
   504
        MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@736
   505
        break;
nkeynes@197
   506
    case DISP_BORDER:
nkeynes@736
   507
        MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@736
   508
        break;
nkeynes@197
   509
    case DISP_MODE:
nkeynes@736
   510
        MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@736
   511
        break;
nkeynes@191
   512
    case RENDER_MODE:
nkeynes@736
   513
        MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@736
   514
        break;
nkeynes@191
   515
    case RENDER_SIZE:
nkeynes@736
   516
        MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@736
   517
        break;
nkeynes@197
   518
    case DISP_ADDR1:
nkeynes@736
   519
        val &= 0x00FFFFFC;
nkeynes@736
   520
        MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   521
        pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   522
        break;
nkeynes@197
   523
    case DISP_ADDR2:
nkeynes@736
   524
        MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@736
   525
        pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   526
        break;
nkeynes@197
   527
    case DISP_SIZE:
nkeynes@736
   528
        MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@736
   529
        break;
nkeynes@191
   530
    case RENDER_ADDR1:
nkeynes@191
   531
    case RENDER_ADDR2:
nkeynes@736
   532
        MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@736
   533
        break;
nkeynes@191
   534
    case RENDER_HCLIP:
nkeynes@736
   535
        MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@736
   536
        break;
nkeynes@191
   537
    case RENDER_VCLIP:
nkeynes@736
   538
        MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@736
   539
        break;
nkeynes@197
   540
    case DISP_HPOSIRQ:
nkeynes@736
   541
        MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@736
   542
        pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@736
   543
        pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@736
   544
        pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@736
   545
        switch( pvr2_state.irq_hpos_mode ) {
nkeynes@736
   546
        case 3: /* Reserved - treat as 0 */
nkeynes@736
   547
        case 0: /* Once per frame at specified line */
nkeynes@736
   548
            pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@736
   549
            break;
nkeynes@736
   550
        case 2: /* Once per line - as per-line-count */
nkeynes@736
   551
            pvr2_state.irq_hpos_line = 1;
nkeynes@736
   552
            pvr2_state.irq_hpos_mode = 1;
nkeynes@736
   553
        case 1: /* Once per N lines */
nkeynes@736
   554
            pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@736
   555
            pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@736
   556
            pvr2_state.irq_hpos_line_count;
nkeynes@736
   557
            while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@736
   558
                pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@736
   559
            }
nkeynes@736
   560
            pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@736
   561
        }
nkeynes@736
   562
        pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@736
   563
                                      pvr2_state.irq_hpos_time_ns );
nkeynes@736
   564
        break;
nkeynes@736
   565
        case DISP_VPOSIRQ:
nkeynes@736
   566
            val = val & 0x03FF03FF;
nkeynes@736
   567
            pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@736
   568
            pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@736
   569
            pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   570
            pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@736
   571
            pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@736
   572
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   573
            break;
nkeynes@736
   574
        case RENDER_NEARCLIP:
nkeynes@736
   575
            MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@736
   576
            break;
nkeynes@736
   577
        case RENDER_SHADOW:
nkeynes@736
   578
            MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@736
   579
            break;
nkeynes@736
   580
        case RENDER_OBJCFG:
nkeynes@736
   581
            MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@736
   582
            break;
nkeynes@736
   583
        case RENDER_TSPCLIP:
nkeynes@736
   584
            MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@736
   585
            break;
nkeynes@736
   586
        case RENDER_FARCLIP:
nkeynes@736
   587
            MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@736
   588
            break;
nkeynes@736
   589
        case RENDER_BGPLANE:
nkeynes@736
   590
            MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@736
   591
            break;
nkeynes@736
   592
        case RENDER_ISPCFG:
nkeynes@736
   593
            MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@736
   594
            break;
nkeynes@736
   595
        case VRAM_CFG1:
nkeynes@736
   596
            MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@736
   597
            break;
nkeynes@736
   598
        case VRAM_CFG2:
nkeynes@736
   599
            MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@736
   600
            break;
nkeynes@736
   601
        case VRAM_CFG3:
nkeynes@736
   602
            MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@736
   603
            break;
nkeynes@736
   604
        case RENDER_FOGTBLCOL:
nkeynes@736
   605
        case RENDER_FOGVRTCOL:
nkeynes@736
   606
            MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@736
   607
            break;
nkeynes@736
   608
        case RENDER_FOGCOEFF:
nkeynes@736
   609
            MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@736
   610
            break;
nkeynes@736
   611
        case RENDER_CLAMPHI:
nkeynes@736
   612
        case RENDER_CLAMPLO:
nkeynes@736
   613
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   614
            break;
nkeynes@736
   615
        case RENDER_TEXSIZE:
nkeynes@736
   616
            MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@736
   617
            break;
nkeynes@736
   618
        case RENDER_PALETTE:
nkeynes@736
   619
            MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@736
   620
            break;
nkeynes@736
   621
        case RENDER_ALPHA_REF:
nkeynes@736
   622
            MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@736
   623
            break;
nkeynes@736
   624
            /********** CRTC registers *************/
nkeynes@736
   625
        case DISP_HBORDER:
nkeynes@736
   626
        case DISP_VBORDER:
nkeynes@736
   627
            MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@736
   628
            break;
nkeynes@736
   629
        case DISP_TOTAL:
nkeynes@736
   630
            val = val & 0x03FF03FF;
nkeynes@736
   631
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   632
            pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   633
            pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@736
   634
            pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@736
   635
            pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@736
   636
            pvr2_state.retrace_end_line = 0x2A;
nkeynes@736
   637
            pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@736
   638
            pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@736
   639
            pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@736
   640
            pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@736
   641
                                          pvr2_state.irq_hpos_time_ns );
nkeynes@736
   642
            break;
nkeynes@736
   643
        case DISP_SYNCCFG:
nkeynes@736
   644
            MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@736
   645
            pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@736
   646
            break;
nkeynes@736
   647
        case DISP_SYNCTIME:
nkeynes@736
   648
            pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@736
   649
            pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@736
   650
            MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@736
   651
            break;
nkeynes@736
   652
        case DISP_CFG2:
nkeynes@736
   653
            MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@736
   654
            break;
nkeynes@736
   655
        case DISP_HPOS:
nkeynes@736
   656
            val = val & 0x03FF;
nkeynes@736
   657
            pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@736
   658
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   659
            break;
nkeynes@736
   660
        case DISP_VPOS:
nkeynes@736
   661
            MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@736
   662
            break;
nkeynes@261
   663
nkeynes@736
   664
            /*********** Tile accelerator registers ***********/
nkeynes@736
   665
        case TA_POLYPOS:
nkeynes@736
   666
        case TA_LISTPOS:
nkeynes@736
   667
            /* Readonly registers */
nkeynes@736
   668
            break;
nkeynes@736
   669
        case TA_TILEBASE:
nkeynes@736
   670
        case TA_LISTEND:
nkeynes@736
   671
        case TA_LISTBASE:
nkeynes@736
   672
            MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@736
   673
            break;
nkeynes@736
   674
        case RENDER_TILEBASE:
nkeynes@736
   675
        case TA_POLYBASE:
nkeynes@736
   676
        case TA_POLYEND:
nkeynes@736
   677
            MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@736
   678
            break;
nkeynes@736
   679
        case TA_TILESIZE:
nkeynes@736
   680
            MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@736
   681
            break;
nkeynes@736
   682
        case TA_TILECFG:
nkeynes@736
   683
            MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@736
   684
            break;
nkeynes@736
   685
        case TA_INIT:
nkeynes@736
   686
            if( val & 0x80000000 )
nkeynes@736
   687
                pvr2_ta_init();
nkeynes@736
   688
            break;
nkeynes@736
   689
        case TA_REINIT:
nkeynes@736
   690
            break;
nkeynes@736
   691
            /**************** Scaler registers? ****************/
nkeynes@736
   692
        case RENDER_SCALER:
nkeynes@736
   693
            MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@736
   694
            break;
nkeynes@261
   695
nkeynes@736
   696
        case YUV_ADDR:
nkeynes@736
   697
            val = val & 0x00FFFFF8;
nkeynes@736
   698
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   699
            pvr2_yuv_init( val );
nkeynes@736
   700
            break;
nkeynes@736
   701
        case YUV_CFG:
nkeynes@736
   702
            MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@736
   703
            pvr2_yuv_set_config(val);
nkeynes@736
   704
            break;
nkeynes@261
   705
nkeynes@736
   706
            /**************** Unknowns ***************/
nkeynes@736
   707
        case PVRUNK1:
nkeynes@736
   708
            MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@736
   709
            break;
nkeynes@736
   710
        case PVRUNK2:
nkeynes@736
   711
            MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@736
   712
            break;
nkeynes@736
   713
        case PVRUNK3:
nkeynes@736
   714
            MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@736
   715
            break;
nkeynes@736
   716
        case PVRUNK5:
nkeynes@736
   717
            MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@736
   718
            break;
nkeynes@736
   719
        case PVRUNK7:
nkeynes@736
   720
            MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@736
   721
            break;
nkeynes@736
   722
        case PVRUNK8:
nkeynes@736
   723
            MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
nkeynes@736
   724
            break;
nkeynes@1
   725
    }
nkeynes@1
   726
}
nkeynes@1
   727
nkeynes@261
   728
/**
nkeynes@261
   729
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   730
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   731
 * The register reads (LSB to MSB) as:
nkeynes@261
   732
 *     0..9  Current scan line
nkeynes@261
   733
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   734
 *     11    Display active (including border and overscan)
nkeynes@261
   735
 *     12    Horizontal sync off
nkeynes@261
   736
 *     13    Vertical sync off
nkeynes@261
   737
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   738
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   739
 */
nkeynes@261
   740
uint32_t pvr2_get_sync_status()
nkeynes@261
   741
{
nkeynes@265
   742
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   743
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   744
nkeynes@265
   745
    if( pvr2_state.odd_even_field ) {
nkeynes@736
   746
        result |= 0x0400;
nkeynes@261
   747
    }
nkeynes@265
   748
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@736
   749
        if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@736
   750
            result |= 0x1000; /* !HSYNC */
nkeynes@736
   751
        }
nkeynes@736
   752
        if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@736
   753
            if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@736
   754
                result |= 0x2800; /* Display active */
nkeynes@736
   755
            } else {
nkeynes@736
   756
                result |= 0x2000; /* Front porch */
nkeynes@736
   757
            }
nkeynes@736
   758
        }
nkeynes@261
   759
    } else {
nkeynes@736
   760
        if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@736
   761
            if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@736
   762
                result |= 0x3800; /* Display active */
nkeynes@736
   763
            } else {
nkeynes@736
   764
                result |= 0x3000;
nkeynes@736
   765
            }
nkeynes@736
   766
        } else {
nkeynes@736
   767
            result |= 0x1000; /* Back porch */
nkeynes@736
   768
        }
nkeynes@261
   769
    }
nkeynes@261
   770
    return result;
nkeynes@261
   771
}
nkeynes@261
   772
nkeynes@265
   773
/**
nkeynes@265
   774
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   775
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   776
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   777
 * The raster position should be updated before calling this
nkeynes@265
   778
 * method.
nkeynes@304
   779
 * @param eventid Event to fire at the specified time
nkeynes@304
   780
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   781
 *  displays). 
nkeynes@304
   782
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   783
 */
nkeynes@304
   784
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   785
{
nkeynes@265
   786
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   787
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@736
   788
        field = !field;
nkeynes@265
   789
    }
nkeynes@304
   790
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@736
   791
        hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   792
    }
nkeynes@265
   793
nkeynes@265
   794
    line <<= 1;
nkeynes@265
   795
    if( field ) {
nkeynes@736
   796
        line += 1;
nkeynes@265
   797
    }
nkeynes@736
   798
nkeynes@274
   799
    if( line < pvr2_state.total_lines ) {
nkeynes@736
   800
        uint32_t lines;
nkeynes@736
   801
        uint32_t time;
nkeynes@736
   802
        if( line <= pvr2_state.line_count ) {
nkeynes@736
   803
            lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@736
   804
        } else {
nkeynes@736
   805
            lines = (line - pvr2_state.line_count);
nkeynes@736
   806
        }
nkeynes@736
   807
        if( lines <= minimum_lines ) {
nkeynes@736
   808
            lines += pvr2_state.total_lines;
nkeynes@736
   809
        }
nkeynes@736
   810
        time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@736
   811
        event_schedule( eventid, time );
nkeynes@274
   812
    } else {
nkeynes@736
   813
        event_cancel( eventid );
nkeynes@274
   814
    }
nkeynes@265
   815
}
nkeynes@265
   816
nkeynes@850
   817
void pvr2_queue_gun_event( int xpos, int ypos )
nkeynes@850
   818
{
nkeynes@850
   819
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@850
   820
    pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,  
nkeynes@850
   821
            (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns ); 
nkeynes@850
   822
}
nkeynes@850
   823
nkeynes@1
   824
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   825
{
nkeynes@929
   826
    reg &= 0xFFF;
nkeynes@1
   827
    switch( reg ) {
nkeynes@736
   828
    case DISP_SYNCSTAT:
nkeynes@736
   829
        return pvr2_get_sync_status();
nkeynes@736
   830
    default:
nkeynes@736
   831
        return MMIO_READ( PVR2, reg );
nkeynes@1
   832
    }
nkeynes@1
   833
}
nkeynes@975
   834
MMIO_REGION_READ_DEFSUBFNS(PVR2)
nkeynes@975
   835
MMIO_REGION_READ_DEFSUBFNS(PVR2PAL)
nkeynes@19
   836
nkeynes@337
   837
MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
nkeynes@337
   838
{
nkeynes@929
   839
    reg &= 0xFFF;
nkeynes@337
   840
    MMIO_WRITE( PVR2PAL, reg, val );
nkeynes@337
   841
    pvr2_state.palette_changed = TRUE;
nkeynes@337
   842
}
nkeynes@337
   843
nkeynes@337
   844
void pvr2_check_palette_changed()
nkeynes@337
   845
{
nkeynes@337
   846
    if( pvr2_state.palette_changed ) {
nkeynes@736
   847
        texcache_invalidate_palette();
nkeynes@736
   848
        pvr2_state.palette_changed = FALSE;
nkeynes@337
   849
    }
nkeynes@337
   850
}
nkeynes@337
   851
nkeynes@337
   852
MMIO_REGION_READ_DEFFN( PVR2PAL );
nkeynes@85
   853
nkeynes@19
   854
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   855
{
nkeynes@197
   856
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   857
}
nkeynes@56
   858
nkeynes@856
   859
render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
nkeynes@856
   860
{
nkeynes@856
   861
    if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
nkeynes@856
   862
        render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
nkeynes@856
   863
        buffer->address = addr;
nkeynes@856
   864
        return buffer;
nkeynes@856
   865
    }
nkeynes@856
   866
    return NULL;
nkeynes@856
   867
}
nkeynes@856
   868
nkeynes@856
   869
void pvr2_destroy_render_buffer( render_buffer_t buffer )
nkeynes@856
   870
{
nkeynes@856
   871
    if( !buffer->flushed )
nkeynes@856
   872
        pvr2_render_buffer_copy_to_sh4( buffer );
nkeynes@856
   873
     display_driver->destroy_render_buffer( buffer );
nkeynes@856
   874
}
nkeynes@856
   875
nkeynes@856
   876
void pvr2_finish_render_buffer( render_buffer_t buffer )
nkeynes@856
   877
{
nkeynes@856
   878
    display_driver->finish_render( buffer );
nkeynes@856
   879
}
nkeynes@856
   880
nkeynes@352
   881
/**
nkeynes@352
   882
 * Find the render buffer corresponding to the requested output frame
nkeynes@352
   883
 * (does not consider texture renders). 
nkeynes@352
   884
 * @return the render_buffer if found, or null if no such buffer.
nkeynes@352
   885
 *
nkeynes@352
   886
 * Note: Currently does not consider "partial matches", ie partial
nkeynes@352
   887
 * frame overlap - it probably needs to do this.
nkeynes@352
   888
 */
nkeynes@352
   889
render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
nkeynes@352
   890
{
nkeynes@352
   891
    int i;
nkeynes@352
   892
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
   893
        if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
nkeynes@736
   894
            return render_buffers[i];
nkeynes@736
   895
        }
nkeynes@352
   896
    }
nkeynes@352
   897
    return NULL;
nkeynes@352
   898
}
nkeynes@352
   899
nkeynes@352
   900
/**
nkeynes@477
   901
 * Allocate a render buffer with the requested parameters.
nkeynes@477
   902
 * The order of preference is:
nkeynes@352
   903
 *   1. An existing buffer with the same address. (not flushed unless the new
nkeynes@352
   904
 * size is smaller than the old one).
nkeynes@352
   905
 *   2. An existing buffer with the same size chosen by LRU order. Old buffer
nkeynes@352
   906
 *       is flushed to vram.
nkeynes@352
   907
 *   3. A new buffer if one can be created.
nkeynes@352
   908
 *   4. The current display buff
nkeynes@352
   909
 * Note: The current display field(s) will never be overwritten except as a last
nkeynes@352
   910
 * resort.
nkeynes@352
   911
 */
nkeynes@477
   912
render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
nkeynes@352
   913
{
nkeynes@477
   914
    int i;
nkeynes@352
   915
    render_buffer_t result = NULL;
nkeynes@352
   916
nkeynes@352
   917
    /* Check existing buffers for an available buffer */
nkeynes@352
   918
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
   919
        if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
nkeynes@736
   920
            /* needs to be the right dimensions */
nkeynes@736
   921
            if( render_buffers[i]->address == render_addr ) {
nkeynes@736
   922
                if( displayed_render_buffer == render_buffers[i] ) {
nkeynes@736
   923
                    /* Same address, but we can't use it because the
nkeynes@736
   924
                     * display has it. Mark it as unaddressed for later.
nkeynes@736
   925
                     */
nkeynes@736
   926
                    render_buffers[i]->address = -1;
nkeynes@736
   927
                } else {
nkeynes@736
   928
                    /* perfect */
nkeynes@736
   929
                    result = render_buffers[i];
nkeynes@736
   930
                    break;
nkeynes@736
   931
                }
nkeynes@736
   932
            } else if( render_buffers[i]->address == -1 && result == NULL && 
nkeynes@736
   933
                    displayed_render_buffer != render_buffers[i] ) {
nkeynes@736
   934
                result = render_buffers[i];
nkeynes@736
   935
            }
nkeynes@736
   936
nkeynes@736
   937
        } else if( render_buffers[i]->address == render_addr ) {
nkeynes@736
   938
            /* right address, wrong size - if it's larger, flush it, otherwise 
nkeynes@736
   939
             * nuke it quietly */
nkeynes@736
   940
            if( render_buffers[i]->width * render_buffers[i]->height >
nkeynes@736
   941
            width*height ) {
nkeynes@736
   942
                pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@736
   943
            }
nkeynes@736
   944
            render_buffers[i]->address = -1;
nkeynes@736
   945
        }
nkeynes@352
   946
    }
nkeynes@352
   947
nkeynes@352
   948
    /* Nothing available - make one */
nkeynes@352
   949
    if( result == NULL ) {
nkeynes@736
   950
        if( render_buffer_count == MAX_RENDER_BUFFERS ) {
nkeynes@736
   951
            /* maximum buffers reached - need to throw one away */
nkeynes@736
   952
            uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   953
            uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@736
   954
            for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
   955
                if( render_buffers[i]->address != field1_addr &&
nkeynes@736
   956
                        render_buffers[i]->address != field2_addr &&
nkeynes@736
   957
                        render_buffers[i] != displayed_render_buffer ) {
nkeynes@736
   958
                    /* Never throw away the current "front buffer(s)" */
nkeynes@736
   959
                    result = render_buffers[i];
nkeynes@871
   960
                    if( !result->flushed && result->address != -1 ) {
nkeynes@736
   961
                        pvr2_render_buffer_copy_to_sh4( result );
nkeynes@736
   962
                    }
nkeynes@736
   963
                    if( result->width != width || result->height != height ) {
nkeynes@736
   964
                        display_driver->destroy_render_buffer(render_buffers[i]);
nkeynes@805
   965
                        result = display_driver->create_render_buffer(width,height,0);
nkeynes@736
   966
                        render_buffers[i] = result;
nkeynes@736
   967
                    }
nkeynes@736
   968
                    break;
nkeynes@736
   969
                }
nkeynes@736
   970
            }
nkeynes@736
   971
        } else {
nkeynes@805
   972
            result = display_driver->create_render_buffer(width,height,0);
nkeynes@736
   973
            if( result != NULL ) { 
nkeynes@736
   974
                render_buffers[render_buffer_count++] = result;
nkeynes@736
   975
            }
nkeynes@736
   976
        }
nkeynes@352
   977
    }
nkeynes@352
   978
nkeynes@477
   979
    if( result != NULL ) {
nkeynes@736
   980
        result->address = render_addr;
nkeynes@477
   981
    }
nkeynes@352
   982
    return result;
nkeynes@352
   983
}
nkeynes@352
   984
nkeynes@352
   985
/**
nkeynes@477
   986
 * Allocate a render buffer based on the current rendering settings
nkeynes@477
   987
 */
nkeynes@477
   988
render_buffer_t pvr2_next_render_buffer()
nkeynes@477
   989
{
nkeynes@477
   990
    render_buffer_t result = NULL;
nkeynes@477
   991
    uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
nkeynes@477
   992
    uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
nkeynes@477
   993
    uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
nkeynes@477
   994
    uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
nkeynes@477
   995
nkeynes@856
   996
    int width = pvr2_scene_buffer_width();
nkeynes@856
   997
    int height = pvr2_scene_buffer_height();
nkeynes@856
   998
    int colour_format = render_colour_formats[render_mode&0x07];
nkeynes@856
   999
nkeynes@477
  1000
    if( render_addr & 0x01000000 ) { /* vram64 */
nkeynes@736
  1001
        render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
nkeynes@477
  1002
    } else { /* vram32 */
nkeynes@736
  1003
        render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@477
  1004
    }
nkeynes@871
  1005
    result = pvr2_alloc_render_buffer( render_addr, width, height );
nkeynes@871
  1006
    
nkeynes@477
  1007
    /* Setup the buffer */
nkeynes@477
  1008
    if( result != NULL ) {
nkeynes@736
  1009
        result->rowstride = render_stride;
nkeynes@736
  1010
        result->colour_format = colour_format;
nkeynes@736
  1011
        result->scale = render_scale;
nkeynes@736
  1012
        result->size = width * height * colour_formats[colour_format].bpp;
nkeynes@736
  1013
        result->flushed = FALSE;
nkeynes@736
  1014
        result->inverted = TRUE; // render buffers are inverted normally
nkeynes@477
  1015
    }
nkeynes@477
  1016
    return result;
nkeynes@477
  1017
}
nkeynes@477
  1018
nkeynes@477
  1019
static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
nkeynes@477
  1020
{
nkeynes@477
  1021
    render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
nkeynes@477
  1022
    if( result != NULL ) {
nkeynes@736
  1023
        int bpp = colour_formats[frame->colour_format].bpp;
nkeynes@736
  1024
        result->rowstride = frame->rowstride;
nkeynes@736
  1025
        result->colour_format = frame->colour_format;
nkeynes@736
  1026
        result->scale = 0x400;
nkeynes@736
  1027
        result->size = frame->width * frame->height * bpp;
nkeynes@736
  1028
        result->flushed = TRUE;
nkeynes@736
  1029
        result->inverted = frame->inverted;
nkeynes@736
  1030
        display_driver->load_frame_buffer( frame, result );
nkeynes@477
  1031
    }
nkeynes@477
  1032
    return result;
nkeynes@477
  1033
}
nkeynes@736
  1034
nkeynes@477
  1035
nkeynes@477
  1036
/**
nkeynes@352
  1037
 * Invalidate any caching on the supplied address. Specifically, if it falls
nkeynes@352
  1038
 * within any of the render buffers, flush the buffer back to PVR2 ram.
nkeynes@352
  1039
 */
nkeynes@352
  1040
gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
nkeynes@352
  1041
{
nkeynes@352
  1042
    int i;
nkeynes@352
  1043
    address = address & 0x1FFFFFFF;
nkeynes@352
  1044
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
  1045
        uint32_t bufaddr = render_buffers[i]->address;
nkeynes@736
  1046
        if( bufaddr != -1 && bufaddr <= address && 
nkeynes@736
  1047
                (bufaddr + render_buffers[i]->size) > address ) {
nkeynes@736
  1048
            if( !render_buffers[i]->flushed ) {
nkeynes@736
  1049
                pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@736
  1050
            }
nkeynes@736
  1051
            if( isWrite ) {
nkeynes@736
  1052
                render_buffers[i]->address = -1; /* Invalid */
nkeynes@736
  1053
            }
nkeynes@736
  1054
            return TRUE; /* should never have overlapping buffers */
nkeynes@736
  1055
        }
nkeynes@352
  1056
    }
nkeynes@352
  1057
    return FALSE;
nkeynes@352
  1058
}
.