filename | src/aica/armcore.h |
changeset | 5:d85c2e81ce2d |
prev | 2:42349f6ea216 |
next | 7:976a16e92aab |
author | nkeynes |
date | Sat Oct 02 05:49:23 2004 +0000 (19 years ago) |
permissions | -rw-r--r-- |
last change | More work on the arm core |
file | annotate | diff | log | raw |
nkeynes@2 | 1 | |
nkeynes@2 | 2 | #ifndef dream_armcore_H |
nkeynes@2 | 3 | #define dream_armcore_H 1 |
nkeynes@2 | 4 | |
nkeynes@2 | 5 | #include "dream.h" |
nkeynes@2 | 6 | #include <stdint.h> |
nkeynes@2 | 7 | |
nkeynes@2 | 8 | |
nkeynes@2 | 9 | |
nkeynes@2 | 10 | struct arm_registers { |
nkeynes@2 | 11 | uint32_t r[16]; /* Current register bank */ |
nkeynes@2 | 12 | |
nkeynes@2 | 13 | uint32_t cpsr; |
nkeynes@2 | 14 | uint32_t spsr; |
nkeynes@2 | 15 | |
nkeynes@2 | 16 | /* Various banked versions of the registers. */ |
nkeynes@2 | 17 | uint32_t fiq_r[7]; /* FIQ bank 8..14 */ |
nkeynes@2 | 18 | uint32_t irq_r[2]; /* IRQ bank 13..14 */ |
nkeynes@2 | 19 | uint32_t und_r[2]; /* UND bank 13..14 */ |
nkeynes@2 | 20 | uint32_t abt_r[2]; /* ABT bank 13..14 */ |
nkeynes@2 | 21 | uint32_t svc_r[2]; /* SVC bank 13..14 */ |
nkeynes@2 | 22 | uint32_t user_r[7]; /* User/System bank 8..14 */ |
nkeynes@2 | 23 | |
nkeynes@5 | 24 | uint32_t c,n,z,v,t; |
nkeynes@5 | 25 | |
nkeynes@5 | 26 | /* "fake" registers */ |
nkeynes@5 | 27 | uint32_t shift_c; /* used for temporary storage of shifter results */ |
nkeynes@2 | 28 | }; |
nkeynes@2 | 29 | |
nkeynes@2 | 30 | #define CPSR_N 0x80000000 /* Negative flag */ |
nkeynes@2 | 31 | #define CPSR_Z 0x40000000 /* Zero flag */ |
nkeynes@2 | 32 | #define CPSR_C 0x20000000 /* Carry flag */ |
nkeynes@2 | 33 | #define CPSR_V 0x10000000 /* Overflow flag */ |
nkeynes@2 | 34 | #define CPSR_I 0x00000080 /* Interrupt disable bit */ |
nkeynes@2 | 35 | #define CPSR_F 0x00000040 /* Fast interrupt disable bit */ |
nkeynes@2 | 36 | #define CPSR_T 0x00000020 /* Thumb mode */ |
nkeynes@2 | 37 | #define CPSR_MODE 0x0000001F /* Current execution mode */ |
nkeynes@2 | 38 | |
nkeynes@2 | 39 | #define MODE_USER 0x00 /* User mode */ |
nkeynes@2 | 40 | #define MODE_FIQ 0x01 /* Fast IRQ mode */ |
nkeynes@2 | 41 | #define MODE_IRQ 0x02 /* IRQ mode */ |
nkeynes@2 | 42 | #define MODE_SV 0x03 /* Supervisor mode */ |
nkeynes@2 | 43 | #define MODE_ABT 0x07 /* Abort mode */ |
nkeynes@2 | 44 | #define MODE_UND 0x0B /* Undefined mode */ |
nkeynes@2 | 45 | #define MODE_SYS 0x0F /* System mode */ |
nkeynes@2 | 46 | |
nkeynes@2 | 47 | extern struct arm_registers armr; |
nkeynes@2 | 48 | |
nkeynes@5 | 49 | #define CARRY_FLAG (armr.cpsr&CPSR_C) |
nkeynes@2 | 50 | |
nkeynes@2 | 51 | #endif /* !dream_armcore_H */ |
.