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lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 54:d8b73031289c
prev35:21a4be098304
next92:108450d84ce8
author nkeynes
date Sun Jan 01 08:08:40 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add (partial) DMAC implementation
file annotate diff log raw
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/**
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 * $Id: sh4mmio.c,v 1.7 2006-01-01 08:08:40 nkeynes Exp $
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 * 
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 * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
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 * responsible for including the IMPL side of the SH4 MMIO pages.
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 * Most of these will eventually be split off into their own files.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include "dream.h"
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#include "mem.h"
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#include "clock.h"
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#include "sh4core.h"
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#include "sh4mmio.h"
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#define MMIO_IMPL
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#include "sh4mmio.h"
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/********************************* MMU *************************************/
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MMIO_REGION_READ_STUBFN( MMU )
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#define OCRAM_START (0x1C000000>>PAGE_BITS)
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#define OCRAM_END   (0x20000000>>PAGE_BITS)
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static char *cache = NULL;
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    switch(reg) {
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        case CCR:
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            mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
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            INFO( "Cache mode set to %08X", val );
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            break;
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        default:
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            break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void mmu_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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        case MEM_OC_INDEX0: /* OIX=0 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
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            break;
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        case MEM_OC_INDEX1: /* OIX=1 */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
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            break;
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        default: /* disabled */
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            for( i=OCRAM_START; i<OCRAM_END; i++ )
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                page_map[i] = NULL;
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            break;
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    }
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}
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/********************************* BSC *************************************/
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uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
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uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
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uint32_t bsc_output = 0, bsc_input = 0x0300;
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void bsc_out( int output, int mask )
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{
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    /* Go figure... The BIOS won't start without this mess though */
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    if( ((output | (~mask)) & 0x03) == 3 ) {
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        bsc_output |= 0x03;
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    } else {
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        bsc_output &= ~0x03;
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    }
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}
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void mmio_region_BSC_write( uint32_t reg, uint32_t val )
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{
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    int i;
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    switch( reg ) {
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        case PCTRA:
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            bsc_input_mask_lo = bsc_output_mask_lo = 0;
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            for( i=0; i<16; i++ ) {
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                int bits = (val >> (i<<1)) & 0x03;
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                if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
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                else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
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            }
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            bsc_output = (bsc_output&0x000F0000) |
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                (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
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            bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
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                     bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
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            break;
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        case PCTRB:
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            bsc_input_mask_hi = bsc_output_mask_hi = 0;
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            for( i=0; i<4; i++ ) {
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                int bits = (val >> (i>>1)) & 0x03;
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                if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
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                else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
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            }
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            bsc_output = (bsc_output&0xFFFF) |
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                ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
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            break;
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        case PDTRA:
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            bsc_output = (bsc_output&0x000F0000) |
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                (val & bsc_output_mask_lo );
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            bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
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                     bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
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            break;
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        case PDTRB:
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            bsc_output = (bsc_output&0xFFFF) |
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                ( (val & bsc_output_mask_hi)<<16 );
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            break;
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    }
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    WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
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          reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
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    MMIO_WRITE( BSC, reg, val );
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}
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int32_t mmio_region_BSC_read( uint32_t reg )
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{
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    int32_t val;
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    switch( reg ) {
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        case PDTRA:
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            val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
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            break;
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        case PDTRB:
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            val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
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            break;
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        default:
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            val = MMIO_READ( BSC, reg );
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    }
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    WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
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          reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
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    return val;
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}
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/********************************* UBC *************************************/
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MMIO_REGION_STUBFNS( UBC )
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/********************************** SCI *************************************/
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MMIO_REGION_STUBFNS( SCI )
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.