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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 601:d8d1af0d133c
prev596:dfc0c93d882e
next604:1024c3a9cb88
author nkeynes
date Tue Jan 22 10:11:45 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Invoke emulator single-step for untranslatable delay slots (and fix a few
related bugs)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   334
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   335
 */
nkeynes@586
   336
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   337
nkeynes@586
   338
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   339
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   340
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   341
nkeynes@590
   342
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   343
nkeynes@539
   344
/****** Import appropriate calling conventions ******/
nkeynes@539
   345
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   346
#include "sh4/ia64abi.h"
nkeynes@539
   347
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   348
#ifdef APPLE_BUILD
nkeynes@539
   349
#include "sh4/ia32mac.h"
nkeynes@539
   350
#else
nkeynes@539
   351
#include "sh4/ia32abi.h"
nkeynes@539
   352
#endif
nkeynes@539
   353
#endif
nkeynes@539
   354
nkeynes@593
   355
uint32_t sh4_translate_end_block_size()
nkeynes@593
   356
{
nkeynes@596
   357
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   358
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   359
    } else {
nkeynes@596
   360
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   361
    }
nkeynes@593
   362
}
nkeynes@593
   363
nkeynes@593
   364
nkeynes@590
   365
/**
nkeynes@590
   366
 * Embed a breakpoint into the generated code
nkeynes@590
   367
 */
nkeynes@586
   368
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   369
{
nkeynes@591
   370
    load_imm32( R_EAX, pc );
nkeynes@591
   371
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   372
}
nkeynes@590
   373
nkeynes@601
   374
nkeynes@601
   375
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   376
nkeynes@590
   377
/**
nkeynes@590
   378
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   379
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   380
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   381
 *
nkeynes@601
   382
 * Performs:
nkeynes@601
   383
 *   Set PC = endpc
nkeynes@601
   384
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   385
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   386
 *   Call sh4_execute_instruction
nkeynes@601
   387
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   388
 */
nkeynes@601
   389
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   390
{
nkeynes@590
   391
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   392
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   393
    
nkeynes@601
   394
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   395
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   396
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   397
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   398
nkeynes@590
   399
    call_func0( sh4_execute_instruction );    
nkeynes@601
   400
    load_spreg( R_EAX, R_PC );
nkeynes@590
   401
    if( sh4_x86.tlb_on ) {
nkeynes@590
   402
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   403
    } else {
nkeynes@590
   404
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   405
    }
nkeynes@601
   406
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   407
    POP_r32(R_EBP);
nkeynes@590
   408
    RET();
nkeynes@590
   409
} 
nkeynes@539
   410
nkeynes@359
   411
/**
nkeynes@359
   412
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   413
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   414
 * 
nkeynes@586
   415
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   416
 *
nkeynes@359
   417
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   418
 * (eg a branch or 
nkeynes@359
   419
 */
nkeynes@590
   420
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   421
{
nkeynes@388
   422
    uint32_t ir;
nkeynes@586
   423
    /* Read instruction from icache */
nkeynes@586
   424
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   425
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   426
    
nkeynes@586
   427
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   428
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   429
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   430
	 * almost certainly in a delay slot.
nkeynes@586
   431
	 *
nkeynes@586
   432
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   433
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   434
	 * small repairs to cope with the different environment).
nkeynes@586
   435
	 */
nkeynes@586
   436
nkeynes@586
   437
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   438
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   439
    }
nkeynes@359
   440
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   441
            case 0x0:
nkeynes@359
   442
                switch( ir&0xF ) {
nkeynes@359
   443
                    case 0x2:
nkeynes@359
   444
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   445
                            case 0x0:
nkeynes@359
   446
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   447
                                    case 0x0:
nkeynes@359
   448
                                        { /* STC SR, Rn */
nkeynes@359
   449
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   450
                                        check_priv();
nkeynes@374
   451
                                        call_func0(sh4_read_sr);
nkeynes@368
   452
                                        store_reg( R_EAX, Rn );
nkeynes@417
   453
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   454
                                        }
nkeynes@359
   455
                                        break;
nkeynes@359
   456
                                    case 0x1:
nkeynes@359
   457
                                        { /* STC GBR, Rn */
nkeynes@359
   458
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   459
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   460
                                        store_reg( R_EAX, Rn );
nkeynes@359
   461
                                        }
nkeynes@359
   462
                                        break;
nkeynes@359
   463
                                    case 0x2:
nkeynes@359
   464
                                        { /* STC VBR, Rn */
nkeynes@359
   465
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   466
                                        check_priv();
nkeynes@359
   467
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   468
                                        store_reg( R_EAX, Rn );
nkeynes@417
   469
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   470
                                        }
nkeynes@359
   471
                                        break;
nkeynes@359
   472
                                    case 0x3:
nkeynes@359
   473
                                        { /* STC SSR, Rn */
nkeynes@359
   474
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   475
                                        check_priv();
nkeynes@359
   476
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   477
                                        store_reg( R_EAX, Rn );
nkeynes@417
   478
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   479
                                        }
nkeynes@359
   480
                                        break;
nkeynes@359
   481
                                    case 0x4:
nkeynes@359
   482
                                        { /* STC SPC, Rn */
nkeynes@359
   483
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   484
                                        check_priv();
nkeynes@359
   485
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   486
                                        store_reg( R_EAX, Rn );
nkeynes@417
   487
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   488
                                        }
nkeynes@359
   489
                                        break;
nkeynes@359
   490
                                    default:
nkeynes@359
   491
                                        UNDEF();
nkeynes@359
   492
                                        break;
nkeynes@359
   493
                                }
nkeynes@359
   494
                                break;
nkeynes@359
   495
                            case 0x1:
nkeynes@359
   496
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   497
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   498
                                check_priv();
nkeynes@374
   499
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   500
                                store_reg( R_EAX, Rn );
nkeynes@417
   501
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   502
                                }
nkeynes@359
   503
                                break;
nkeynes@359
   504
                        }
nkeynes@359
   505
                        break;
nkeynes@359
   506
                    case 0x3:
nkeynes@359
   507
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   508
                            case 0x0:
nkeynes@359
   509
                                { /* BSRF Rn */
nkeynes@359
   510
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   511
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   512
                            	SLOTILLEGAL();
nkeynes@374
   513
                                } else {
nkeynes@590
   514
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   515
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   516
                            	store_spreg( R_EAX, R_PR );
nkeynes@590
   517
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   518
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   519
                            
nkeynes@601
   520
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   521
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   522
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   523
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   524
                            	    exit_block_emu(pc+2);
nkeynes@601
   525
                            	    return 2;
nkeynes@601
   526
                            	} else {
nkeynes@601
   527
                            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
   528
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   529
                            	    return 4;
nkeynes@601
   530
                            	}
nkeynes@374
   531
                                }
nkeynes@359
   532
                                }
nkeynes@359
   533
                                break;
nkeynes@359
   534
                            case 0x2:
nkeynes@359
   535
                                { /* BRAF Rn */
nkeynes@359
   536
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   537
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   538
                            	SLOTILLEGAL();
nkeynes@374
   539
                                } else {
nkeynes@590
   540
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   541
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   542
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   543
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   544
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   545
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   546
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   547
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   548
                            	    exit_block_emu(pc+2);
nkeynes@601
   549
                            	    return 2;
nkeynes@601
   550
                            	} else {
nkeynes@601
   551
                            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
   552
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   553
                            	    return 4;
nkeynes@601
   554
                            	}
nkeynes@374
   555
                                }
nkeynes@359
   556
                                }
nkeynes@359
   557
                                break;
nkeynes@359
   558
                            case 0x8:
nkeynes@359
   559
                                { /* PREF @Rn */
nkeynes@359
   560
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   561
                                load_reg( R_EAX, Rn );
nkeynes@532
   562
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   563
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   564
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
   565
                                JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
   566
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
   567
                                TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
   568
                                JE_exc(-1);
nkeynes@380
   569
                                JMP_TARGET(end);
nkeynes@417
   570
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   571
                                }
nkeynes@359
   572
                                break;
nkeynes@359
   573
                            case 0x9:
nkeynes@359
   574
                                { /* OCBI @Rn */
nkeynes@359
   575
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   576
                                }
nkeynes@359
   577
                                break;
nkeynes@359
   578
                            case 0xA:
nkeynes@359
   579
                                { /* OCBP @Rn */
nkeynes@359
   580
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   581
                                }
nkeynes@359
   582
                                break;
nkeynes@359
   583
                            case 0xB:
nkeynes@359
   584
                                { /* OCBWB @Rn */
nkeynes@359
   585
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   586
                                }
nkeynes@359
   587
                                break;
nkeynes@359
   588
                            case 0xC:
nkeynes@359
   589
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   590
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
   591
                                load_reg( R_EAX, Rn );
nkeynes@586
   592
                                check_walign32( R_EAX );
nkeynes@586
   593
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   594
                                load_reg( R_EDX, 0 );
nkeynes@586
   595
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   596
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   597
                                }
nkeynes@359
   598
                                break;
nkeynes@359
   599
                            default:
nkeynes@359
   600
                                UNDEF();
nkeynes@359
   601
                                break;
nkeynes@359
   602
                        }
nkeynes@359
   603
                        break;
nkeynes@359
   604
                    case 0x4:
nkeynes@359
   605
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   606
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   607
                        load_reg( R_EAX, 0 );
nkeynes@359
   608
                        load_reg( R_ECX, Rn );
nkeynes@586
   609
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   610
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   611
                        load_reg( R_EDX, Rm );
nkeynes@586
   612
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   613
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   614
                        }
nkeynes@359
   615
                        break;
nkeynes@359
   616
                    case 0x5:
nkeynes@359
   617
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   618
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   619
                        load_reg( R_EAX, 0 );
nkeynes@361
   620
                        load_reg( R_ECX, Rn );
nkeynes@586
   621
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   622
                        check_walign16( R_EAX );
nkeynes@586
   623
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   624
                        load_reg( R_EDX, Rm );
nkeynes@586
   625
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   626
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   627
                        }
nkeynes@359
   628
                        break;
nkeynes@359
   629
                    case 0x6:
nkeynes@359
   630
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   631
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   632
                        load_reg( R_EAX, 0 );
nkeynes@361
   633
                        load_reg( R_ECX, Rn );
nkeynes@586
   634
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   635
                        check_walign32( R_EAX );
nkeynes@586
   636
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   637
                        load_reg( R_EDX, Rm );
nkeynes@586
   638
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   639
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   640
                        }
nkeynes@359
   641
                        break;
nkeynes@359
   642
                    case 0x7:
nkeynes@359
   643
                        { /* MUL.L Rm, Rn */
nkeynes@359
   644
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   645
                        load_reg( R_EAX, Rm );
nkeynes@361
   646
                        load_reg( R_ECX, Rn );
nkeynes@361
   647
                        MUL_r32( R_ECX );
nkeynes@361
   648
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   649
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   650
                        }
nkeynes@359
   651
                        break;
nkeynes@359
   652
                    case 0x8:
nkeynes@359
   653
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   654
                            case 0x0:
nkeynes@359
   655
                                { /* CLRT */
nkeynes@374
   656
                                CLC();
nkeynes@374
   657
                                SETC_t();
nkeynes@417
   658
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   659
                                }
nkeynes@359
   660
                                break;
nkeynes@359
   661
                            case 0x1:
nkeynes@359
   662
                                { /* SETT */
nkeynes@374
   663
                                STC();
nkeynes@374
   664
                                SETC_t();
nkeynes@417
   665
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   666
                                }
nkeynes@359
   667
                                break;
nkeynes@359
   668
                            case 0x2:
nkeynes@359
   669
                                { /* CLRMAC */
nkeynes@374
   670
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   671
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   672
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   673
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   674
                                }
nkeynes@359
   675
                                break;
nkeynes@359
   676
                            case 0x3:
nkeynes@359
   677
                                { /* LDTLB */
nkeynes@553
   678
                                call_func0( MMU_ldtlb );
nkeynes@359
   679
                                }
nkeynes@359
   680
                                break;
nkeynes@359
   681
                            case 0x4:
nkeynes@359
   682
                                { /* CLRS */
nkeynes@374
   683
                                CLC();
nkeynes@374
   684
                                SETC_sh4r(R_S);
nkeynes@417
   685
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   686
                                }
nkeynes@359
   687
                                break;
nkeynes@359
   688
                            case 0x5:
nkeynes@359
   689
                                { /* SETS */
nkeynes@374
   690
                                STC();
nkeynes@374
   691
                                SETC_sh4r(R_S);
nkeynes@417
   692
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   693
                                }
nkeynes@359
   694
                                break;
nkeynes@359
   695
                            default:
nkeynes@359
   696
                                UNDEF();
nkeynes@359
   697
                                break;
nkeynes@359
   698
                        }
nkeynes@359
   699
                        break;
nkeynes@359
   700
                    case 0x9:
nkeynes@359
   701
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   702
                            case 0x0:
nkeynes@359
   703
                                { /* NOP */
nkeynes@359
   704
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   705
                                }
nkeynes@359
   706
                                break;
nkeynes@359
   707
                            case 0x1:
nkeynes@359
   708
                                { /* DIV0U */
nkeynes@361
   709
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   710
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   711
                                store_spreg( R_EAX, R_M );
nkeynes@361
   712
                                store_spreg( R_EAX, R_T );
nkeynes@417
   713
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   714
                                }
nkeynes@359
   715
                                break;
nkeynes@359
   716
                            case 0x2:
nkeynes@359
   717
                                { /* MOVT Rn */
nkeynes@359
   718
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   719
                                load_spreg( R_EAX, R_T );
nkeynes@359
   720
                                store_reg( R_EAX, Rn );
nkeynes@359
   721
                                }
nkeynes@359
   722
                                break;
nkeynes@359
   723
                            default:
nkeynes@359
   724
                                UNDEF();
nkeynes@359
   725
                                break;
nkeynes@359
   726
                        }
nkeynes@359
   727
                        break;
nkeynes@359
   728
                    case 0xA:
nkeynes@359
   729
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   730
                            case 0x0:
nkeynes@359
   731
                                { /* STS MACH, Rn */
nkeynes@359
   732
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   733
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   734
                                store_reg( R_EAX, Rn );
nkeynes@359
   735
                                }
nkeynes@359
   736
                                break;
nkeynes@359
   737
                            case 0x1:
nkeynes@359
   738
                                { /* STS MACL, Rn */
nkeynes@359
   739
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   740
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   741
                                store_reg( R_EAX, Rn );
nkeynes@359
   742
                                }
nkeynes@359
   743
                                break;
nkeynes@359
   744
                            case 0x2:
nkeynes@359
   745
                                { /* STS PR, Rn */
nkeynes@359
   746
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   747
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   748
                                store_reg( R_EAX, Rn );
nkeynes@359
   749
                                }
nkeynes@359
   750
                                break;
nkeynes@359
   751
                            case 0x3:
nkeynes@359
   752
                                { /* STC SGR, Rn */
nkeynes@359
   753
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   754
                                check_priv();
nkeynes@359
   755
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   756
                                store_reg( R_EAX, Rn );
nkeynes@417
   757
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   758
                                }
nkeynes@359
   759
                                break;
nkeynes@359
   760
                            case 0x5:
nkeynes@359
   761
                                { /* STS FPUL, Rn */
nkeynes@359
   762
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   763
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   764
                                store_reg( R_EAX, Rn );
nkeynes@359
   765
                                }
nkeynes@359
   766
                                break;
nkeynes@359
   767
                            case 0x6:
nkeynes@359
   768
                                { /* STS FPSCR, Rn */
nkeynes@359
   769
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   770
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   771
                                store_reg( R_EAX, Rn );
nkeynes@359
   772
                                }
nkeynes@359
   773
                                break;
nkeynes@359
   774
                            case 0xF:
nkeynes@359
   775
                                { /* STC DBR, Rn */
nkeynes@359
   776
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   777
                                check_priv();
nkeynes@359
   778
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   779
                                store_reg( R_EAX, Rn );
nkeynes@417
   780
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   781
                                }
nkeynes@359
   782
                                break;
nkeynes@359
   783
                            default:
nkeynes@359
   784
                                UNDEF();
nkeynes@359
   785
                                break;
nkeynes@359
   786
                        }
nkeynes@359
   787
                        break;
nkeynes@359
   788
                    case 0xB:
nkeynes@359
   789
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   790
                            case 0x0:
nkeynes@359
   791
                                { /* RTS */
nkeynes@374
   792
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   793
                            	SLOTILLEGAL();
nkeynes@374
   794
                                } else {
nkeynes@408
   795
                            	load_spreg( R_ECX, R_PR );
nkeynes@590
   796
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
   797
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
   798
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   799
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   800
                            	    exit_block_emu(pc+2);
nkeynes@601
   801
                            	    return 2;
nkeynes@601
   802
                            	} else {
nkeynes@601
   803
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
   804
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   805
                            	    return 4;
nkeynes@601
   806
                            	}
nkeynes@374
   807
                                }
nkeynes@359
   808
                                }
nkeynes@359
   809
                                break;
nkeynes@359
   810
                            case 0x1:
nkeynes@359
   811
                                { /* SLEEP */
nkeynes@388
   812
                                check_priv();
nkeynes@388
   813
                                call_func0( sh4_sleep );
nkeynes@417
   814
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
   815
                                sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
   816
                                return 2;
nkeynes@359
   817
                                }
nkeynes@359
   818
                                break;
nkeynes@359
   819
                            case 0x2:
nkeynes@359
   820
                                { /* RTE */
nkeynes@374
   821
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   822
                            	SLOTILLEGAL();
nkeynes@374
   823
                                } else {
nkeynes@408
   824
                            	check_priv();
nkeynes@408
   825
                            	load_spreg( R_ECX, R_SPC );
nkeynes@590
   826
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
   827
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   828
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
   829
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
   830
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   831
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   832
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   833
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   834
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   835
                            	    exit_block_emu(pc+2);
nkeynes@601
   836
                            	    return 2;
nkeynes@601
   837
                            	} else {
nkeynes@601
   838
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
   839
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   840
                            	    return 4;
nkeynes@601
   841
                            	}
nkeynes@374
   842
                                }
nkeynes@359
   843
                                }
nkeynes@359
   844
                                break;
nkeynes@359
   845
                            default:
nkeynes@359
   846
                                UNDEF();
nkeynes@359
   847
                                break;
nkeynes@359
   848
                        }
nkeynes@359
   849
                        break;
nkeynes@359
   850
                    case 0xC:
nkeynes@359
   851
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   852
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   853
                        load_reg( R_EAX, 0 );
nkeynes@359
   854
                        load_reg( R_ECX, Rm );
nkeynes@586
   855
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   856
                        MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
   857
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
   858
                        store_reg( R_EAX, Rn );
nkeynes@417
   859
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   860
                        }
nkeynes@359
   861
                        break;
nkeynes@359
   862
                    case 0xD:
nkeynes@359
   863
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   864
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   865
                        load_reg( R_EAX, 0 );
nkeynes@361
   866
                        load_reg( R_ECX, Rm );
nkeynes@586
   867
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   868
                        check_ralign16( R_EAX );
nkeynes@586
   869
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   870
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
   871
                        store_reg( R_EAX, Rn );
nkeynes@417
   872
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   873
                        }
nkeynes@359
   874
                        break;
nkeynes@359
   875
                    case 0xE:
nkeynes@359
   876
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   877
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   878
                        load_reg( R_EAX, 0 );
nkeynes@361
   879
                        load_reg( R_ECX, Rm );
nkeynes@586
   880
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   881
                        check_ralign32( R_EAX );
nkeynes@586
   882
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   883
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
   884
                        store_reg( R_EAX, Rn );
nkeynes@417
   885
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   886
                        }
nkeynes@359
   887
                        break;
nkeynes@359
   888
                    case 0xF:
nkeynes@359
   889
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   890
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   891
                        if( Rm == Rn ) {
nkeynes@586
   892
                    	load_reg( R_EAX, Rm );
nkeynes@586
   893
                    	check_ralign32( R_EAX );
nkeynes@586
   894
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   895
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   896
                    	load_reg( R_EAX, Rn );
nkeynes@586
   897
                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   898
                    	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   899
                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   900
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   901
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
   902
                        } else {
nkeynes@586
   903
                    	load_reg( R_EAX, Rm );
nkeynes@586
   904
                    	check_ralign32( R_EAX );
nkeynes@586
   905
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   906
                    	load_reg( R_ECX, Rn );
nkeynes@596
   907
                    	check_ralign32( R_ECX );
nkeynes@586
   908
                    	PUSH_realigned_r32( R_EAX );
nkeynes@596
   909
                    	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   910
                    	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   911
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   912
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   913
                        }
nkeynes@586
   914
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   915
                        POP_r32( R_ECX );
nkeynes@586
   916
                        PUSH_r32( R_EAX );
nkeynes@386
   917
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   918
                        POP_realigned_r32( R_ECX );
nkeynes@586
   919
                    
nkeynes@386
   920
                        IMUL_r32( R_ECX );
nkeynes@386
   921
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   922
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   923
                    
nkeynes@386
   924
                        load_spreg( R_ECX, R_S );
nkeynes@386
   925
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   926
                        JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   927
                        call_func0( signsat48 );
nkeynes@386
   928
                        JMP_TARGET( nosat );
nkeynes@417
   929
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   930
                        }
nkeynes@359
   931
                        break;
nkeynes@359
   932
                    default:
nkeynes@359
   933
                        UNDEF();
nkeynes@359
   934
                        break;
nkeynes@359
   935
                }
nkeynes@359
   936
                break;
nkeynes@359
   937
            case 0x1:
nkeynes@359
   938
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   939
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
   940
                load_reg( R_EAX, Rn );
nkeynes@586
   941
                ADD_imm32_r32( disp, R_EAX );
nkeynes@586
   942
                check_walign32( R_EAX );
nkeynes@586
   943
                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   944
                load_reg( R_EDX, Rm );
nkeynes@586
   945
                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   946
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   947
                }
nkeynes@359
   948
                break;
nkeynes@359
   949
            case 0x2:
nkeynes@359
   950
                switch( ir&0xF ) {
nkeynes@359
   951
                    case 0x0:
nkeynes@359
   952
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   953
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   954
                        load_reg( R_EAX, Rn );
nkeynes@586
   955
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   956
                        load_reg( R_EDX, Rm );
nkeynes@586
   957
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   958
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   959
                        }
nkeynes@359
   960
                        break;
nkeynes@359
   961
                    case 0x1:
nkeynes@359
   962
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   963
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   964
                        load_reg( R_EAX, Rn );
nkeynes@586
   965
                        check_walign16( R_EAX );
nkeynes@586
   966
                        MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
   967
                        load_reg( R_EDX, Rm );
nkeynes@586
   968
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   969
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   970
                        }
nkeynes@359
   971
                        break;
nkeynes@359
   972
                    case 0x2:
nkeynes@359
   973
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   974
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   975
                        load_reg( R_EAX, Rn );
nkeynes@586
   976
                        check_walign32(R_EAX);
nkeynes@586
   977
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   978
                        load_reg( R_EDX, Rm );
nkeynes@586
   979
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   980
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   981
                        }
nkeynes@359
   982
                        break;
nkeynes@359
   983
                    case 0x4:
nkeynes@359
   984
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   985
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   986
                        load_reg( R_EAX, Rn );
nkeynes@586
   987
                        ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
   988
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   989
                        load_reg( R_EDX, Rm );
nkeynes@586
   990
                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
   991
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   992
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   993
                        }
nkeynes@359
   994
                        break;
nkeynes@359
   995
                    case 0x5:
nkeynes@359
   996
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   997
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
   998
                        load_reg( R_EAX, Rn );
nkeynes@586
   999
                        ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1000
                        check_walign16( R_EAX );
nkeynes@586
  1001
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1002
                        load_reg( R_EDX, Rm );
nkeynes@586
  1003
                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1004
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1005
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1006
                        }
nkeynes@359
  1007
                        break;
nkeynes@359
  1008
                    case 0x6:
nkeynes@359
  1009
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
  1010
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  1011
                        load_reg( R_EAX, Rn );
nkeynes@586
  1012
                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1013
                        check_walign32( R_EAX );
nkeynes@586
  1014
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1015
                        load_reg( R_EDX, Rm );
nkeynes@586
  1016
                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1017
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1018
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1019
                        }
nkeynes@359
  1020
                        break;
nkeynes@359
  1021
                    case 0x7:
nkeynes@359
  1022
                        { /* DIV0S Rm, Rn */
nkeynes@359
  1023
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1024
                        load_reg( R_EAX, Rm );
nkeynes@386
  1025
                        load_reg( R_ECX, Rn );
nkeynes@361
  1026
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
  1027
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
  1028
                        store_spreg( R_EAX, R_M );
nkeynes@361
  1029
                        store_spreg( R_ECX, R_Q );
nkeynes@361
  1030
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1031
                        SETNE_t();
nkeynes@417
  1032
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
  1033
                        }
nkeynes@359
  1034
                        break;
nkeynes@359
  1035
                    case 0x8:
nkeynes@359
  1036
                        { /* TST Rm, Rn */
nkeynes@359
  1037
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1038
                        load_reg( R_EAX, Rm );
nkeynes@361
  1039
                        load_reg( R_ECX, Rn );
nkeynes@361
  1040
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1041
                        SETE_t();
nkeynes@417
  1042
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1043
                        }
nkeynes@359
  1044
                        break;
nkeynes@359
  1045
                    case 0x9:
nkeynes@359
  1046
                        { /* AND Rm, Rn */
nkeynes@359
  1047
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1048
                        load_reg( R_EAX, Rm );
nkeynes@359
  1049
                        load_reg( R_ECX, Rn );
nkeynes@359
  1050
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1051
                        store_reg( R_ECX, Rn );
nkeynes@417
  1052
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1053
                        }
nkeynes@359
  1054
                        break;
nkeynes@359
  1055
                    case 0xA:
nkeynes@359
  1056
                        { /* XOR Rm, Rn */
nkeynes@359
  1057
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1058
                        load_reg( R_EAX, Rm );
nkeynes@359
  1059
                        load_reg( R_ECX, Rn );
nkeynes@359
  1060
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1061
                        store_reg( R_ECX, Rn );
nkeynes@417
  1062
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1063
                        }
nkeynes@359
  1064
                        break;
nkeynes@359
  1065
                    case 0xB:
nkeynes@359
  1066
                        { /* OR Rm, Rn */
nkeynes@359
  1067
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1068
                        load_reg( R_EAX, Rm );
nkeynes@359
  1069
                        load_reg( R_ECX, Rn );
nkeynes@359
  1070
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1071
                        store_reg( R_ECX, Rn );
nkeynes@417
  1072
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1073
                        }
nkeynes@359
  1074
                        break;
nkeynes@359
  1075
                    case 0xC:
nkeynes@359
  1076
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1077
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1078
                        load_reg( R_EAX, Rm );
nkeynes@368
  1079
                        load_reg( R_ECX, Rn );
nkeynes@368
  1080
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1081
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
  1082
                        JE_rel8(13, target1);
nkeynes@368
  1083
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1084
                        JE_rel8(9, target2);
nkeynes@368
  1085
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
  1086
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1087
                        JE_rel8(2, target3);
nkeynes@368
  1088
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1089
                        JMP_TARGET(target1);
nkeynes@380
  1090
                        JMP_TARGET(target2);
nkeynes@380
  1091
                        JMP_TARGET(target3);
nkeynes@368
  1092
                        SETE_t();
nkeynes@417
  1093
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1094
                        }
nkeynes@359
  1095
                        break;
nkeynes@359
  1096
                    case 0xD:
nkeynes@359
  1097
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1098
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1099
                        load_reg( R_EAX, Rm );
nkeynes@394
  1100
                        load_reg( R_ECX, Rn );
nkeynes@394
  1101
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1102
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1103
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1104
                        store_reg( R_ECX, Rn );
nkeynes@417
  1105
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1106
                        }
nkeynes@359
  1107
                        break;
nkeynes@359
  1108
                    case 0xE:
nkeynes@359
  1109
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1110
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1111
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1112
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1113
                        MUL_r32( R_ECX );
nkeynes@374
  1114
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1115
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1116
                        }
nkeynes@359
  1117
                        break;
nkeynes@359
  1118
                    case 0xF:
nkeynes@359
  1119
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1120
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1121
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1122
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1123
                        MUL_r32( R_ECX );
nkeynes@374
  1124
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1125
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1126
                        }
nkeynes@359
  1127
                        break;
nkeynes@359
  1128
                    default:
nkeynes@359
  1129
                        UNDEF();
nkeynes@359
  1130
                        break;
nkeynes@359
  1131
                }
nkeynes@359
  1132
                break;
nkeynes@359
  1133
            case 0x3:
nkeynes@359
  1134
                switch( ir&0xF ) {
nkeynes@359
  1135
                    case 0x0:
nkeynes@359
  1136
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1137
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1138
                        load_reg( R_EAX, Rm );
nkeynes@359
  1139
                        load_reg( R_ECX, Rn );
nkeynes@359
  1140
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1141
                        SETE_t();
nkeynes@417
  1142
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1143
                        }
nkeynes@359
  1144
                        break;
nkeynes@359
  1145
                    case 0x2:
nkeynes@359
  1146
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1147
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1148
                        load_reg( R_EAX, Rm );
nkeynes@359
  1149
                        load_reg( R_ECX, Rn );
nkeynes@359
  1150
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1151
                        SETAE_t();
nkeynes@417
  1152
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1153
                        }
nkeynes@359
  1154
                        break;
nkeynes@359
  1155
                    case 0x3:
nkeynes@359
  1156
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1157
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1158
                        load_reg( R_EAX, Rm );
nkeynes@359
  1159
                        load_reg( R_ECX, Rn );
nkeynes@359
  1160
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1161
                        SETGE_t();
nkeynes@417
  1162
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1163
                        }
nkeynes@359
  1164
                        break;
nkeynes@359
  1165
                    case 0x4:
nkeynes@359
  1166
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1167
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1168
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1169
                        load_reg( R_EAX, Rn );
nkeynes@417
  1170
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1171
                    	LDC_t();
nkeynes@417
  1172
                        }
nkeynes@386
  1173
                        RCL1_r32( R_EAX );
nkeynes@386
  1174
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1175
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1176
                        JE_rel8(5, mqequal);
nkeynes@386
  1177
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1178
                        JMP_rel8(3, end);
nkeynes@380
  1179
                        JMP_TARGET(mqequal);
nkeynes@386
  1180
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1181
                        JMP_TARGET(end);
nkeynes@386
  1182
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1183
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1184
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1185
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1186
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1187
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1188
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1189
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1190
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1191
                        }
nkeynes@359
  1192
                        break;
nkeynes@359
  1193
                    case 0x5:
nkeynes@359
  1194
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1195
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1196
                        load_reg( R_EAX, Rm );
nkeynes@361
  1197
                        load_reg( R_ECX, Rn );
nkeynes@361
  1198
                        MUL_r32(R_ECX);
nkeynes@361
  1199
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1200
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1201
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1202
                        }
nkeynes@359
  1203
                        break;
nkeynes@359
  1204
                    case 0x6:
nkeynes@359
  1205
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1206
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1207
                        load_reg( R_EAX, Rm );
nkeynes@359
  1208
                        load_reg( R_ECX, Rn );
nkeynes@359
  1209
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1210
                        SETA_t();
nkeynes@417
  1211
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1212
                        }
nkeynes@359
  1213
                        break;
nkeynes@359
  1214
                    case 0x7:
nkeynes@359
  1215
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1216
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1217
                        load_reg( R_EAX, Rm );
nkeynes@359
  1218
                        load_reg( R_ECX, Rn );
nkeynes@359
  1219
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1220
                        SETG_t();
nkeynes@417
  1221
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1222
                        }
nkeynes@359
  1223
                        break;
nkeynes@359
  1224
                    case 0x8:
nkeynes@359
  1225
                        { /* SUB Rm, Rn */
nkeynes@359
  1226
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1227
                        load_reg( R_EAX, Rm );
nkeynes@359
  1228
                        load_reg( R_ECX, Rn );
nkeynes@359
  1229
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1230
                        store_reg( R_ECX, Rn );
nkeynes@417
  1231
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1232
                        }
nkeynes@359
  1233
                        break;
nkeynes@359
  1234
                    case 0xA:
nkeynes@359
  1235
                        { /* SUBC Rm, Rn */
nkeynes@359
  1236
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1237
                        load_reg( R_EAX, Rm );
nkeynes@359
  1238
                        load_reg( R_ECX, Rn );
nkeynes@417
  1239
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1240
                    	LDC_t();
nkeynes@417
  1241
                        }
nkeynes@359
  1242
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1243
                        store_reg( R_ECX, Rn );
nkeynes@394
  1244
                        SETC_t();
nkeynes@417
  1245
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1246
                        }
nkeynes@359
  1247
                        break;
nkeynes@359
  1248
                    case 0xB:
nkeynes@359
  1249
                        { /* SUBV Rm, Rn */
nkeynes@359
  1250
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1251
                        load_reg( R_EAX, Rm );
nkeynes@359
  1252
                        load_reg( R_ECX, Rn );
nkeynes@359
  1253
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1254
                        store_reg( R_ECX, Rn );
nkeynes@359
  1255
                        SETO_t();
nkeynes@417
  1256
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1257
                        }
nkeynes@359
  1258
                        break;
nkeynes@359
  1259
                    case 0xC:
nkeynes@359
  1260
                        { /* ADD Rm, Rn */
nkeynes@359
  1261
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1262
                        load_reg( R_EAX, Rm );
nkeynes@359
  1263
                        load_reg( R_ECX, Rn );
nkeynes@359
  1264
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1265
                        store_reg( R_ECX, Rn );
nkeynes@417
  1266
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1267
                        }
nkeynes@359
  1268
                        break;
nkeynes@359
  1269
                    case 0xD:
nkeynes@359
  1270
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1271
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1272
                        load_reg( R_EAX, Rm );
nkeynes@361
  1273
                        load_reg( R_ECX, Rn );
nkeynes@361
  1274
                        IMUL_r32(R_ECX);
nkeynes@361
  1275
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1276
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1277
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1278
                        }
nkeynes@359
  1279
                        break;
nkeynes@359
  1280
                    case 0xE:
nkeynes@359
  1281
                        { /* ADDC Rm, Rn */
nkeynes@359
  1282
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@417
  1283
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1284
                    	LDC_t();
nkeynes@417
  1285
                        }
nkeynes@359
  1286
                        load_reg( R_EAX, Rm );
nkeynes@359
  1287
                        load_reg( R_ECX, Rn );
nkeynes@359
  1288
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1289
                        store_reg( R_ECX, Rn );
nkeynes@359
  1290
                        SETC_t();
nkeynes@417
  1291
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1292
                        }
nkeynes@359
  1293
                        break;
nkeynes@359
  1294
                    case 0xF:
nkeynes@359
  1295
                        { /* ADDV Rm, Rn */
nkeynes@359
  1296
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1297
                        load_reg( R_EAX, Rm );
nkeynes@359
  1298
                        load_reg( R_ECX, Rn );
nkeynes@359
  1299
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1300
                        store_reg( R_ECX, Rn );
nkeynes@359
  1301
                        SETO_t();
nkeynes@417
  1302
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1303
                        }
nkeynes@359
  1304
                        break;
nkeynes@359
  1305
                    default:
nkeynes@359
  1306
                        UNDEF();
nkeynes@359
  1307
                        break;
nkeynes@359
  1308
                }
nkeynes@359
  1309
                break;
nkeynes@359
  1310
            case 0x4:
nkeynes@359
  1311
                switch( ir&0xF ) {
nkeynes@359
  1312
                    case 0x0:
nkeynes@359
  1313
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1314
                            case 0x0:
nkeynes@359
  1315
                                { /* SHLL Rn */
nkeynes@359
  1316
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1317
                                load_reg( R_EAX, Rn );
nkeynes@359
  1318
                                SHL1_r32( R_EAX );
nkeynes@397
  1319
                                SETC_t();
nkeynes@359
  1320
                                store_reg( R_EAX, Rn );
nkeynes@417
  1321
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1322
                                }
nkeynes@359
  1323
                                break;
nkeynes@359
  1324
                            case 0x1:
nkeynes@359
  1325
                                { /* DT Rn */
nkeynes@359
  1326
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1327
                                load_reg( R_EAX, Rn );
nkeynes@386
  1328
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1329
                                store_reg( R_EAX, Rn );
nkeynes@359
  1330
                                SETE_t();
nkeynes@417
  1331
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1332
                                }
nkeynes@359
  1333
                                break;
nkeynes@359
  1334
                            case 0x2:
nkeynes@359
  1335
                                { /* SHAL Rn */
nkeynes@359
  1336
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1337
                                load_reg( R_EAX, Rn );
nkeynes@359
  1338
                                SHL1_r32( R_EAX );
nkeynes@397
  1339
                                SETC_t();
nkeynes@359
  1340
                                store_reg( R_EAX, Rn );
nkeynes@417
  1341
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1342
                                }
nkeynes@359
  1343
                                break;
nkeynes@359
  1344
                            default:
nkeynes@359
  1345
                                UNDEF();
nkeynes@359
  1346
                                break;
nkeynes@359
  1347
                        }
nkeynes@359
  1348
                        break;
nkeynes@359
  1349
                    case 0x1:
nkeynes@359
  1350
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1351
                            case 0x0:
nkeynes@359
  1352
                                { /* SHLR Rn */
nkeynes@359
  1353
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1354
                                load_reg( R_EAX, Rn );
nkeynes@359
  1355
                                SHR1_r32( R_EAX );
nkeynes@397
  1356
                                SETC_t();
nkeynes@359
  1357
                                store_reg( R_EAX, Rn );
nkeynes@417
  1358
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1359
                                }
nkeynes@359
  1360
                                break;
nkeynes@359
  1361
                            case 0x1:
nkeynes@359
  1362
                                { /* CMP/PZ Rn */
nkeynes@359
  1363
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1364
                                load_reg( R_EAX, Rn );
nkeynes@359
  1365
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1366
                                SETGE_t();
nkeynes@417
  1367
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1368
                                }
nkeynes@359
  1369
                                break;
nkeynes@359
  1370
                            case 0x2:
nkeynes@359
  1371
                                { /* SHAR Rn */
nkeynes@359
  1372
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1373
                                load_reg( R_EAX, Rn );
nkeynes@359
  1374
                                SAR1_r32( R_EAX );
nkeynes@397
  1375
                                SETC_t();
nkeynes@359
  1376
                                store_reg( R_EAX, Rn );
nkeynes@417
  1377
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1378
                                }
nkeynes@359
  1379
                                break;
nkeynes@359
  1380
                            default:
nkeynes@359
  1381
                                UNDEF();
nkeynes@359
  1382
                                break;
nkeynes@359
  1383
                        }
nkeynes@359
  1384
                        break;
nkeynes@359
  1385
                    case 0x2:
nkeynes@359
  1386
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1387
                            case 0x0:
nkeynes@359
  1388
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1389
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1390
                                load_reg( R_EAX, Rn );
nkeynes@586
  1391
                                check_walign32( R_EAX );
nkeynes@586
  1392
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1393
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1394
                                load_spreg( R_EDX, R_MACH );
nkeynes@586
  1395
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1396
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1397
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1398
                                }
nkeynes@359
  1399
                                break;
nkeynes@359
  1400
                            case 0x1:
nkeynes@359
  1401
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1402
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1403
                                load_reg( R_EAX, Rn );
nkeynes@586
  1404
                                check_walign32( R_EAX );
nkeynes@586
  1405
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1406
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1407
                                load_spreg( R_EDX, R_MACL );
nkeynes@586
  1408
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1409
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1410
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1411
                                }
nkeynes@359
  1412
                                break;
nkeynes@359
  1413
                            case 0x2:
nkeynes@359
  1414
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1415
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1416
                                load_reg( R_EAX, Rn );
nkeynes@586
  1417
                                check_walign32( R_EAX );
nkeynes@586
  1418
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1419
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1420
                                load_spreg( R_EDX, R_PR );
nkeynes@586
  1421
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1422
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1423
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1424
                                }
nkeynes@359
  1425
                                break;
nkeynes@359
  1426
                            case 0x3:
nkeynes@359
  1427
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1428
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1429
                                check_priv();
nkeynes@586
  1430
                                load_reg( R_EAX, Rn );
nkeynes@586
  1431
                                check_walign32( R_EAX );
nkeynes@586
  1432
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1433
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1434
                                load_spreg( R_EDX, R_SGR );
nkeynes@586
  1435
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1436
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1437
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1438
                                }
nkeynes@359
  1439
                                break;
nkeynes@359
  1440
                            case 0x5:
nkeynes@359
  1441
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1442
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1443
                                load_reg( R_EAX, Rn );
nkeynes@586
  1444
                                check_walign32( R_EAX );
nkeynes@586
  1445
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1446
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1447
                                load_spreg( R_EDX, R_FPUL );
nkeynes@586
  1448
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1449
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1450
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1451
                                }
nkeynes@359
  1452
                                break;
nkeynes@359
  1453
                            case 0x6:
nkeynes@359
  1454
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1455
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1456
                                load_reg( R_EAX, Rn );
nkeynes@586
  1457
                                check_walign32( R_EAX );
nkeynes@586
  1458
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1459
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1460
                                load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  1461
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1462
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1463
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1464
                                }
nkeynes@359
  1465
                                break;
nkeynes@359
  1466
                            case 0xF:
nkeynes@359
  1467
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1468
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1469
                                check_priv();
nkeynes@586
  1470
                                load_reg( R_EAX, Rn );
nkeynes@586
  1471
                                check_walign32( R_EAX );
nkeynes@586
  1472
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1473
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1474
                                load_spreg( R_EDX, R_DBR );
nkeynes@586
  1475
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1476
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1477
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1478
                                }
nkeynes@359
  1479
                                break;
nkeynes@359
  1480
                            default:
nkeynes@359
  1481
                                UNDEF();
nkeynes@359
  1482
                                break;
nkeynes@359
  1483
                        }
nkeynes@359
  1484
                        break;
nkeynes@359
  1485
                    case 0x3:
nkeynes@359
  1486
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1487
                            case 0x0:
nkeynes@359
  1488
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1489
                                    case 0x0:
nkeynes@359
  1490
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1491
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1492
                                        check_priv();
nkeynes@586
  1493
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1494
                                        check_walign32( R_EAX );
nkeynes@586
  1495
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1496
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1497
                                        PUSH_realigned_r32( R_EAX );
nkeynes@395
  1498
                                        call_func0( sh4_read_sr );
nkeynes@586
  1499
                                        POP_realigned_r32( R_ECX );
nkeynes@586
  1500
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374
  1501
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1502
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1503
                                        }
nkeynes@359
  1504
                                        break;
nkeynes@359
  1505
                                    case 0x1:
nkeynes@359
  1506
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1507
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1508
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1509
                                        check_walign32( R_EAX );
nkeynes@586
  1510
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1511
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1512
                                        load_spreg( R_EDX, R_GBR );
nkeynes@586
  1513
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1514
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1515
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1516
                                        }
nkeynes@359
  1517
                                        break;
nkeynes@359
  1518
                                    case 0x2:
nkeynes@359
  1519
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1520
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1521
                                        check_priv();
nkeynes@586
  1522
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1523
                                        check_walign32( R_EAX );
nkeynes@586
  1524
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1525
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1526
                                        load_spreg( R_EDX, R_VBR );
nkeynes@586
  1527
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1528
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1529
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1530
                                        }
nkeynes@359
  1531
                                        break;
nkeynes@359
  1532
                                    case 0x3:
nkeynes@359
  1533
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1534
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1535
                                        check_priv();
nkeynes@586
  1536
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1537
                                        check_walign32( R_EAX );
nkeynes@586
  1538
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1539
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1540
                                        load_spreg( R_EDX, R_SSR );
nkeynes@586
  1541
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1542
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1543
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1544
                                        }
nkeynes@359
  1545
                                        break;
nkeynes@359
  1546
                                    case 0x4:
nkeynes@359
  1547
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1548
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1549
                                        check_priv();
nkeynes@586
  1550
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1551
                                        check_walign32( R_EAX );
nkeynes@586
  1552
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1553
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1554
                                        load_spreg( R_EDX, R_SPC );
nkeynes@586
  1555
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1556
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1557
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1558
                                        }
nkeynes@359
  1559
                                        break;
nkeynes@359
  1560
                                    default:
nkeynes@359
  1561
                                        UNDEF();
nkeynes@359
  1562
                                        break;
nkeynes@359
  1563
                                }
nkeynes@359
  1564
                                break;
nkeynes@359
  1565
                            case 0x1:
nkeynes@359
  1566
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1567
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1568
                                check_priv();
nkeynes@586
  1569
                                load_reg( R_EAX, Rn );
nkeynes@586
  1570
                                check_walign32( R_EAX );
nkeynes@586
  1571
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1572
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1573
                                load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  1574
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1575
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1576
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1577
                                }
nkeynes@359
  1578
                                break;
nkeynes@359
  1579
                        }
nkeynes@359
  1580
                        break;
nkeynes@359
  1581
                    case 0x4:
nkeynes@359
  1582
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1583
                            case 0x0:
nkeynes@359
  1584
                                { /* ROTL Rn */
nkeynes@359
  1585
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1586
                                load_reg( R_EAX, Rn );
nkeynes@359
  1587
                                ROL1_r32( R_EAX );
nkeynes@359
  1588
                                store_reg( R_EAX, Rn );
nkeynes@359
  1589
                                SETC_t();
nkeynes@417
  1590
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1591
                                }
nkeynes@359
  1592
                                break;
nkeynes@359
  1593
                            case 0x2:
nkeynes@359
  1594
                                { /* ROTCL Rn */
nkeynes@359
  1595
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1596
                                load_reg( R_EAX, Rn );
nkeynes@417
  1597
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1598
                            	LDC_t();
nkeynes@417
  1599
                                }
nkeynes@359
  1600
                                RCL1_r32( R_EAX );
nkeynes@359
  1601
                                store_reg( R_EAX, Rn );
nkeynes@359
  1602
                                SETC_t();
nkeynes@417
  1603
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1604
                                }
nkeynes@359
  1605
                                break;
nkeynes@359
  1606
                            default:
nkeynes@359
  1607
                                UNDEF();
nkeynes@359
  1608
                                break;
nkeynes@359
  1609
                        }
nkeynes@359
  1610
                        break;
nkeynes@359
  1611
                    case 0x5:
nkeynes@359
  1612
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1613
                            case 0x0:
nkeynes@359
  1614
                                { /* ROTR Rn */
nkeynes@359
  1615
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1616
                                load_reg( R_EAX, Rn );
nkeynes@359
  1617
                                ROR1_r32( R_EAX );
nkeynes@359
  1618
                                store_reg( R_EAX, Rn );
nkeynes@359
  1619
                                SETC_t();
nkeynes@417
  1620
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1621
                                }
nkeynes@359
  1622
                                break;
nkeynes@359
  1623
                            case 0x1:
nkeynes@359
  1624
                                { /* CMP/PL Rn */
nkeynes@359
  1625
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1626
                                load_reg( R_EAX, Rn );
nkeynes@359
  1627
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1628
                                SETG_t();
nkeynes@417
  1629
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1630
                                }
nkeynes@359
  1631
                                break;
nkeynes@359
  1632
                            case 0x2:
nkeynes@359
  1633
                                { /* ROTCR Rn */
nkeynes@359
  1634
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1635
                                load_reg( R_EAX, Rn );
nkeynes@417
  1636
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1637
                            	LDC_t();
nkeynes@417
  1638
                                }
nkeynes@359
  1639
                                RCR1_r32( R_EAX );
nkeynes@359
  1640
                                store_reg( R_EAX, Rn );
nkeynes@359
  1641
                                SETC_t();
nkeynes@417
  1642
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1643
                                }
nkeynes@359
  1644
                                break;
nkeynes@359
  1645
                            default:
nkeynes@359
  1646
                                UNDEF();
nkeynes@359
  1647
                                break;
nkeynes@359
  1648
                        }
nkeynes@359
  1649
                        break;
nkeynes@359
  1650
                    case 0x6:
nkeynes@359
  1651
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1652
                            case 0x0:
nkeynes@359
  1653
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1654
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1655
                                load_reg( R_EAX, Rm );
nkeynes@395
  1656
                                check_ralign32( R_EAX );
nkeynes@586
  1657
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1658
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1659
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1660
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1661
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1662
                                }
nkeynes@359
  1663
                                break;
nkeynes@359
  1664
                            case 0x1:
nkeynes@359
  1665
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1666
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1667
                                load_reg( R_EAX, Rm );
nkeynes@395
  1668
                                check_ralign32( R_EAX );
nkeynes@586
  1669
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1670
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1671
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1672
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1673
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1674
                                }
nkeynes@359
  1675
                                break;
nkeynes@359
  1676
                            case 0x2:
nkeynes@359
  1677
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1678
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1679
                                load_reg( R_EAX, Rm );
nkeynes@395
  1680
                                check_ralign32( R_EAX );
nkeynes@586
  1681
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1682
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1683
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1684
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1685
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1686
                                }
nkeynes@359
  1687
                                break;
nkeynes@359
  1688
                            case 0x3:
nkeynes@359
  1689
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1690
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1691
                                check_priv();
nkeynes@359
  1692
                                load_reg( R_EAX, Rm );
nkeynes@395
  1693
                                check_ralign32( R_EAX );
nkeynes@586
  1694
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1695
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1696
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1697
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1698
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1699
                                }
nkeynes@359
  1700
                                break;
nkeynes@359
  1701
                            case 0x5:
nkeynes@359
  1702
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1703
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1704
                                load_reg( R_EAX, Rm );
nkeynes@395
  1705
                                check_ralign32( R_EAX );
nkeynes@586
  1706
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1707
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1708
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1709
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1710
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1711
                                }
nkeynes@359
  1712
                                break;
nkeynes@359
  1713
                            case 0x6:
nkeynes@359
  1714
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1715
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1716
                                load_reg( R_EAX, Rm );
nkeynes@395
  1717
                                check_ralign32( R_EAX );
nkeynes@586
  1718
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1719
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1720
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1721
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1722
                                update_fr_bank( R_EAX );
nkeynes@417
  1723
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1724
                                }
nkeynes@359
  1725
                                break;
nkeynes@359
  1726
                            case 0xF:
nkeynes@359
  1727
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1728
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1729
                                check_priv();
nkeynes@359
  1730
                                load_reg( R_EAX, Rm );
nkeynes@395
  1731
                                check_ralign32( R_EAX );
nkeynes@586
  1732
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1733
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1734
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1735
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1736
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1737
                                }
nkeynes@359
  1738
                                break;
nkeynes@359
  1739
                            default:
nkeynes@359
  1740
                                UNDEF();
nkeynes@359
  1741
                                break;
nkeynes@359
  1742
                        }
nkeynes@359
  1743
                        break;
nkeynes@359
  1744
                    case 0x7:
nkeynes@359
  1745
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1746
                            case 0x0:
nkeynes@359
  1747
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1748
                                    case 0x0:
nkeynes@359
  1749
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1750
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1751
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1752
                                    	SLOTILLEGAL();
nkeynes@386
  1753
                                        } else {
nkeynes@586
  1754
                                    	check_priv();
nkeynes@386
  1755
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1756
                                    	check_ralign32( R_EAX );
nkeynes@586
  1757
                                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1758
                                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1759
                                    	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  1760
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1761
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1762
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1763
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1764
                                        }
nkeynes@359
  1765
                                        }
nkeynes@359
  1766
                                        break;
nkeynes@359
  1767
                                    case 0x1:
nkeynes@359
  1768
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1769
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1770
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1771
                                        check_ralign32( R_EAX );
nkeynes@586
  1772
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1773
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1774
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1775
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1776
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1777
                                        }
nkeynes@359
  1778
                                        break;
nkeynes@359
  1779
                                    case 0x2:
nkeynes@359
  1780
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1781
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1782
                                        check_priv();
nkeynes@359
  1783
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1784
                                        check_ralign32( R_EAX );
nkeynes@586
  1785
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1786
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1787
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1788
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1789
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1790
                                        }
nkeynes@359
  1791
                                        break;
nkeynes@359
  1792
                                    case 0x3:
nkeynes@359
  1793
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1794
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1795
                                        check_priv();
nkeynes@359
  1796
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1797
                                        check_ralign32( R_EAX );
nkeynes@586
  1798
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1799
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1800
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1801
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1802
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1803
                                        }
nkeynes@359
  1804
                                        break;
nkeynes@359
  1805
                                    case 0x4:
nkeynes@359
  1806
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1807
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@586
  1808
                                        check_priv();
nkeynes@359
  1809
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1810
                                        check_ralign32( R_EAX );
nkeynes@586
  1811
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1812
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1813
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1814
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1815
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1816
                                        }
nkeynes@359
  1817
                                        break;
nkeynes@359
  1818
                                    default:
nkeynes@359
  1819
                                        UNDEF();
nkeynes@359
  1820
                                        break;
nkeynes@359
  1821
                                }
nkeynes@359
  1822
                                break;
nkeynes@359
  1823
                            case 0x1:
nkeynes@359
  1824
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1825
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@586
  1826
                                check_priv();
nkeynes@374
  1827
                                load_reg( R_EAX, Rm );
nkeynes@395
  1828
                                check_ralign32( R_EAX );
nkeynes@586
  1829
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1830
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1831
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  1832
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1833
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1834
                                }
nkeynes@359
  1835
                                break;
nkeynes@359
  1836
                        }
nkeynes@359
  1837
                        break;
nkeynes@359
  1838
                    case 0x8:
nkeynes@359
  1839
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1840
                            case 0x0:
nkeynes@359
  1841
                                { /* SHLL2 Rn */
nkeynes@359
  1842
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1843
                                load_reg( R_EAX, Rn );
nkeynes@359
  1844
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1845
                                store_reg( R_EAX, Rn );
nkeynes@417
  1846
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1847
                                }
nkeynes@359
  1848
                                break;
nkeynes@359
  1849
                            case 0x1:
nkeynes@359
  1850
                                { /* SHLL8 Rn */
nkeynes@359
  1851
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1852
                                load_reg( R_EAX, Rn );
nkeynes@359
  1853
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1854
                                store_reg( R_EAX, Rn );
nkeynes@417
  1855
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1856
                                }
nkeynes@359
  1857
                                break;
nkeynes@359
  1858
                            case 0x2:
nkeynes@359
  1859
                                { /* SHLL16 Rn */
nkeynes@359
  1860
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1861
                                load_reg( R_EAX, Rn );
nkeynes@359
  1862
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1863
                                store_reg( R_EAX, Rn );
nkeynes@417
  1864
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1865
                                }
nkeynes@359
  1866
                                break;
nkeynes@359
  1867
                            default:
nkeynes@359
  1868
                                UNDEF();
nkeynes@359
  1869
                                break;
nkeynes@359
  1870
                        }
nkeynes@359
  1871
                        break;
nkeynes@359
  1872
                    case 0x9:
nkeynes@359
  1873
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1874
                            case 0x0:
nkeynes@359
  1875
                                { /* SHLR2 Rn */
nkeynes@359
  1876
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1877
                                load_reg( R_EAX, Rn );
nkeynes@359
  1878
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1879
                                store_reg( R_EAX, Rn );
nkeynes@417
  1880
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1881
                                }
nkeynes@359
  1882
                                break;
nkeynes@359
  1883
                            case 0x1:
nkeynes@359
  1884
                                { /* SHLR8 Rn */
nkeynes@359
  1885
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1886
                                load_reg( R_EAX, Rn );
nkeynes@359
  1887
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1888
                                store_reg( R_EAX, Rn );
nkeynes@417
  1889
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1890
                                }
nkeynes@359
  1891
                                break;
nkeynes@359
  1892
                            case 0x2:
nkeynes@359
  1893
                                { /* SHLR16 Rn */
nkeynes@359
  1894
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1895
                                load_reg( R_EAX, Rn );
nkeynes@359
  1896
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1897
                                store_reg( R_EAX, Rn );
nkeynes@417
  1898
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1899
                                }
nkeynes@359
  1900
                                break;
nkeynes@359
  1901
                            default:
nkeynes@359
  1902
                                UNDEF();
nkeynes@359
  1903
                                break;
nkeynes@359
  1904
                        }
nkeynes@359
  1905
                        break;
nkeynes@359
  1906
                    case 0xA:
nkeynes@359
  1907
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1908
                            case 0x0:
nkeynes@359
  1909
                                { /* LDS Rm, MACH */
nkeynes@359
  1910
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1911
                                load_reg( R_EAX, Rm );
nkeynes@359
  1912
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1913
                                }
nkeynes@359
  1914
                                break;
nkeynes@359
  1915
                            case 0x1:
nkeynes@359
  1916
                                { /* LDS Rm, MACL */
nkeynes@359
  1917
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1918
                                load_reg( R_EAX, Rm );
nkeynes@359
  1919
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1920
                                }
nkeynes@359
  1921
                                break;
nkeynes@359
  1922
                            case 0x2:
nkeynes@359
  1923
                                { /* LDS Rm, PR */
nkeynes@359
  1924
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1925
                                load_reg( R_EAX, Rm );
nkeynes@359
  1926
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1927
                                }
nkeynes@359
  1928
                                break;
nkeynes@359
  1929
                            case 0x3:
nkeynes@359
  1930
                                { /* LDC Rm, SGR */
nkeynes@359
  1931
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1932
                                check_priv();
nkeynes@359
  1933
                                load_reg( R_EAX, Rm );
nkeynes@359
  1934
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1935
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1936
                                }
nkeynes@359
  1937
                                break;
nkeynes@359
  1938
                            case 0x5:
nkeynes@359
  1939
                                { /* LDS Rm, FPUL */
nkeynes@359
  1940
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1941
                                load_reg( R_EAX, Rm );
nkeynes@359
  1942
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1943
                                }
nkeynes@359
  1944
                                break;
nkeynes@359
  1945
                            case 0x6:
nkeynes@359
  1946
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1947
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1948
                                load_reg( R_EAX, Rm );
nkeynes@359
  1949
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1950
                                update_fr_bank( R_EAX );
nkeynes@417
  1951
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1952
                                }
nkeynes@359
  1953
                                break;
nkeynes@359
  1954
                            case 0xF:
nkeynes@359
  1955
                                { /* LDC Rm, DBR */
nkeynes@359
  1956
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1957
                                check_priv();
nkeynes@359
  1958
                                load_reg( R_EAX, Rm );
nkeynes@359
  1959
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1960
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1961
                                }
nkeynes@359
  1962
                                break;
nkeynes@359
  1963
                            default:
nkeynes@359
  1964
                                UNDEF();
nkeynes@359
  1965
                                break;
nkeynes@359
  1966
                        }
nkeynes@359
  1967
                        break;
nkeynes@359
  1968
                    case 0xB:
nkeynes@359
  1969
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1970
                            case 0x0:
nkeynes@359
  1971
                                { /* JSR @Rn */
nkeynes@359
  1972
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1973
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1974
                            	SLOTILLEGAL();
nkeynes@374
  1975
                                } else {
nkeynes@590
  1976
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
  1977
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1978
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  1979
                            	load_reg( R_ECX, Rn );
nkeynes@590
  1980
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1981
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1982
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1983
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1984
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1985
                            	    exit_block_emu(pc+2);
nkeynes@601
  1986
                            	    return 2;
nkeynes@601
  1987
                            	} else {
nkeynes@601
  1988
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
  1989
                            	    exit_block_newpcset(pc+2);
nkeynes@601
  1990
                            	    return 4;
nkeynes@601
  1991
                            	}
nkeynes@374
  1992
                                }
nkeynes@359
  1993
                                }
nkeynes@359
  1994
                                break;
nkeynes@359
  1995
                            case 0x1:
nkeynes@359
  1996
                                { /* TAS.B @Rn */
nkeynes@359
  1997
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@586
  1998
                                load_reg( R_EAX, Rn );
nkeynes@586
  1999
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2000
                                PUSH_realigned_r32( R_EAX );
nkeynes@586
  2001
                                MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  2002
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  2003
                                SETE_t();
nkeynes@361
  2004
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  2005
                                POP_realigned_r32( R_ECX );
nkeynes@361
  2006
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2007
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2008
                                }
nkeynes@359
  2009
                                break;
nkeynes@359
  2010
                            case 0x2:
nkeynes@359
  2011
                                { /* JMP @Rn */
nkeynes@359
  2012
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  2013
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2014
                            	SLOTILLEGAL();
nkeynes@374
  2015
                                } else {
nkeynes@408
  2016
                            	load_reg( R_ECX, Rn );
nkeynes@590
  2017
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  2018
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2019
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2020
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2021
                            	    exit_block_emu(pc+2);
nkeynes@601
  2022
                            	    return 2;
nkeynes@601
  2023
                            	} else {
nkeynes@601
  2024
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
  2025
                            	    exit_block_newpcset(pc+2);
nkeynes@601
  2026
                            	    return 4;
nkeynes@601
  2027
                            	}
nkeynes@374
  2028
                                }
nkeynes@359
  2029
                                }
nkeynes@359
  2030
                                break;
nkeynes@359
  2031
                            default:
nkeynes@359
  2032
                                UNDEF();
nkeynes@359
  2033
                                break;
nkeynes@359
  2034
                        }
nkeynes@359
  2035
                        break;
nkeynes@359
  2036
                    case 0xC:
nkeynes@359
  2037
                        { /* SHAD Rm, Rn */
nkeynes@359
  2038
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2039
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  2040
                        load_reg( R_EAX, Rn );
nkeynes@361
  2041
                        load_reg( R_ECX, Rm );
nkeynes@361
  2042
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2043
                        JGE_rel8(16, doshl);
nkeynes@361
  2044
                                        
nkeynes@361
  2045
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  2046
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2047
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  2048
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  2049
                        JMP_rel8(10, end);          // 2
nkeynes@386
  2050
                    
nkeynes@386
  2051
                        JMP_TARGET(emptysar);
nkeynes@386
  2052
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  2053
                        JMP_rel8(5, end2);
nkeynes@386
  2054
                    
nkeynes@380
  2055
                        JMP_TARGET(doshl);
nkeynes@361
  2056
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2057
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2058
                        JMP_TARGET(end);
nkeynes@386
  2059
                        JMP_TARGET(end2);
nkeynes@361
  2060
                        store_reg( R_EAX, Rn );
nkeynes@417
  2061
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2062
                        }
nkeynes@359
  2063
                        break;
nkeynes@359
  2064
                    case 0xD:
nkeynes@359
  2065
                        { /* SHLD Rm, Rn */
nkeynes@359
  2066
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  2067
                        load_reg( R_EAX, Rn );
nkeynes@368
  2068
                        load_reg( R_ECX, Rm );
nkeynes@386
  2069
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  2070
                        JGE_rel8(15, doshl);
nkeynes@368
  2071
                    
nkeynes@386
  2072
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2073
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2074
                        JE_rel8( 4, emptyshr );
nkeynes@386
  2075
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  2076
                        JMP_rel8(9, end);          // 2
nkeynes@386
  2077
                    
nkeynes@386
  2078
                        JMP_TARGET(emptyshr);
nkeynes@386
  2079
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  2080
                        JMP_rel8(5, end2);
nkeynes@386
  2081
                    
nkeynes@386
  2082
                        JMP_TARGET(doshl);
nkeynes@386
  2083
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2084
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2085
                        JMP_TARGET(end);
nkeynes@386
  2086
                        JMP_TARGET(end2);
nkeynes@368
  2087
                        store_reg( R_EAX, Rn );
nkeynes@417
  2088
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2089
                        }
nkeynes@359
  2090
                        break;
nkeynes@359
  2091
                    case 0xE:
nkeynes@359
  2092
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2093
                            case 0x0:
nkeynes@359
  2094
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2095
                                    case 0x0:
nkeynes@359
  2096
                                        { /* LDC Rm, SR */
nkeynes@359
  2097
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2098
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2099
                                    	SLOTILLEGAL();
nkeynes@386
  2100
                                        } else {
nkeynes@386
  2101
                                    	check_priv();
nkeynes@386
  2102
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2103
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2104
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2105
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2106
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2107
                                        }
nkeynes@359
  2108
                                        }
nkeynes@359
  2109
                                        break;
nkeynes@359
  2110
                                    case 0x1:
nkeynes@359
  2111
                                        { /* LDC Rm, GBR */
nkeynes@359
  2112
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  2113
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2114
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2115
                                        }
nkeynes@359
  2116
                                        break;
nkeynes@359
  2117
                                    case 0x2:
nkeynes@359
  2118
                                        { /* LDC Rm, VBR */
nkeynes@359
  2119
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2120
                                        check_priv();
nkeynes@359
  2121
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2122
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2123
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2124
                                        }
nkeynes@359
  2125
                                        break;
nkeynes@359
  2126
                                    case 0x3:
nkeynes@359
  2127
                                        { /* LDC Rm, SSR */
nkeynes@359
  2128
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2129
                                        check_priv();
nkeynes@359
  2130
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2131
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2132
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2133
                                        }
nkeynes@359
  2134
                                        break;
nkeynes@359
  2135
                                    case 0x4:
nkeynes@359
  2136
                                        { /* LDC Rm, SPC */
nkeynes@359
  2137
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  2138
                                        check_priv();
nkeynes@359
  2139
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2140
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2141
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2142
                                        }
nkeynes@359
  2143
                                        break;
nkeynes@359
  2144
                                    default:
nkeynes@359
  2145
                                        UNDEF();
nkeynes@359
  2146
                                        break;
nkeynes@359
  2147
                                }
nkeynes@359
  2148
                                break;
nkeynes@359
  2149
                            case 0x1:
nkeynes@359
  2150
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2151
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  2152
                                check_priv();
nkeynes@374
  2153
                                load_reg( R_EAX, Rm );
nkeynes@374
  2154
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2155
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2156
                                }
nkeynes@359
  2157
                                break;
nkeynes@359
  2158
                        }
nkeynes@359
  2159
                        break;
nkeynes@359
  2160
                    case 0xF:
nkeynes@359
  2161
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2162
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2163
                        if( Rm == Rn ) {
nkeynes@586
  2164
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2165
                    	check_ralign16( R_EAX );
nkeynes@586
  2166
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2167
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2168
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2169
                    	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
  2170
                    	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
  2171
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2172
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  2173
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
  2174
                        } else {
nkeynes@586
  2175
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2176
                    	check_ralign16( R_EAX );
nkeynes@586
  2177
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
  2178
                    	load_reg( R_ECX, Rn );
nkeynes@596
  2179
                    	check_ralign16( R_ECX );
nkeynes@586
  2180
                    	PUSH_realigned_r32( R_EAX );
nkeynes@596
  2181
                    	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
  2182
                    	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2183
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
  2184
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2185
                        }
nkeynes@586
  2186
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2187
                        POP_r32( R_ECX );
nkeynes@586
  2188
                        PUSH_r32( R_EAX );
nkeynes@386
  2189
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2190
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2191
                        IMUL_r32( R_ECX );
nkeynes@386
  2192
                    
nkeynes@386
  2193
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2194
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2195
                        JE_rel8( 47, nosat );
nkeynes@386
  2196
                    
nkeynes@386
  2197
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2198
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2199
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2200
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2201
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2202
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2203
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2204
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2205
                    
nkeynes@386
  2206
                        JMP_TARGET(positive);
nkeynes@386
  2207
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2208
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2209
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2210
                    
nkeynes@386
  2211
                        JMP_TARGET(nosat);
nkeynes@386
  2212
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2213
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2214
                        JMP_TARGET(end);
nkeynes@386
  2215
                        JMP_TARGET(end2);
nkeynes@386
  2216
                        JMP_TARGET(end3);
nkeynes@417
  2217
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2218
                        }
nkeynes@359
  2219
                        break;
nkeynes@359
  2220
                }
nkeynes@359
  2221
                break;
nkeynes@359
  2222
            case 0x5:
nkeynes@359
  2223
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2224
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@586
  2225
                load_reg( R_EAX, Rm );
nkeynes@586
  2226
                ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  2227
                check_ralign32( R_EAX );
nkeynes@586
  2228
                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2229
                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2230
                store_reg( R_EAX, Rn );
nkeynes@417
  2231
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2232
                }
nkeynes@359
  2233
                break;
nkeynes@359
  2234
            case 0x6:
nkeynes@359
  2235
                switch( ir&0xF ) {
nkeynes@359
  2236
                    case 0x0:
nkeynes@359
  2237
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2238
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2239
                        load_reg( R_EAX, Rm );
nkeynes@586
  2240
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2241
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  2242
                        store_reg( R_EAX, Rn );
nkeynes@417
  2243
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2244
                        }
nkeynes@359
  2245
                        break;
nkeynes@359
  2246
                    case 0x1:
nkeynes@359
  2247
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2248
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2249
                        load_reg( R_EAX, Rm );
nkeynes@586
  2250
                        check_ralign16( R_EAX );
nkeynes@586
  2251
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2252
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2253
                        store_reg( R_EAX, Rn );
nkeynes@417
  2254
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2255
                        }
nkeynes@359
  2256
                        break;
nkeynes@359
  2257
                    case 0x2:
nkeynes@359
  2258
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2259
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2260
                        load_reg( R_EAX, Rm );
nkeynes@586
  2261
                        check_ralign32( R_EAX );
nkeynes@586
  2262
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2263
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2264
                        store_reg( R_EAX, Rn );
nkeynes@417
  2265
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2266
                        }
nkeynes@359
  2267
                        break;
nkeynes@359
  2268
                    case 0x3:
nkeynes@359
  2269
                        { /* MOV Rm, Rn */
nkeynes@359
  2270
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2271
                        load_reg( R_EAX, Rm );
nkeynes@359
  2272
                        store_reg( R_EAX, Rn );
nkeynes@359
  2273
                        }
nkeynes@359
  2274
                        break;
nkeynes@359
  2275
                    case 0x4:
nkeynes@359
  2276
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2277
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@586
  2278
                        load_reg( R_EAX, Rm );
nkeynes@586
  2279
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2280
                        ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  2281
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2282
                        store_reg( R_EAX, Rn );
nkeynes@417
  2283
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2284
                        }
nkeynes@359
  2285
                        break;
nkeynes@359
  2286
                    case 0x5:
nkeynes@359
  2287
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2288
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2289
                        load_reg( R_EAX, Rm );
nkeynes@374
  2290
                        check_ralign16( R_EAX );
nkeynes@586
  2291
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2292
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2293
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2294
                        store_reg( R_EAX, Rn );
nkeynes@417
  2295
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2296
                        }
nkeynes@359
  2297
                        break;
nkeynes@359
  2298
                    case 0x6:
nkeynes@359
  2299
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2300
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2301
                        load_reg( R_EAX, Rm );
nkeynes@386
  2302
                        check_ralign32( R_EAX );
nkeynes@586
  2303
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2304
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2305
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2306
                        store_reg( R_EAX, Rn );
nkeynes@417
  2307
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2308
                        }
nkeynes@359
  2309
                        break;
nkeynes@359
  2310
                    case 0x7:
nkeynes@359
  2311
                        { /* NOT Rm, Rn */
nkeynes@359
  2312
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2313
                        load_reg( R_EAX, Rm );
nkeynes@359
  2314
                        NOT_r32( R_EAX );
nkeynes@359
  2315
                        store_reg( R_EAX, Rn );
nkeynes@417
  2316
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2317
                        }
nkeynes@359
  2318
                        break;
nkeynes@359
  2319
                    case 0x8:
nkeynes@359
  2320
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2321
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2322
                        load_reg( R_EAX, Rm );
nkeynes@601
  2323
                        XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  2324
                        store_reg( R_EAX, Rn );
nkeynes@359
  2325
                        }
nkeynes@359
  2326
                        break;
nkeynes@359
  2327
                    case 0x9:
nkeynes@359
  2328
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2329
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2330
                        load_reg( R_EAX, Rm );
nkeynes@359
  2331
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2332
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2333
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2334
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2335
                        store_reg( R_ECX, Rn );
nkeynes@417
  2336
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2337
                        }
nkeynes@359
  2338
                        break;
nkeynes@359
  2339
                    case 0xA:
nkeynes@359
  2340
                        { /* NEGC Rm, Rn */
nkeynes@359
  2341
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2342
                        load_reg( R_EAX, Rm );
nkeynes@359
  2343
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2344
                        LDC_t();
nkeynes@359
  2345
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2346
                        store_reg( R_ECX, Rn );
nkeynes@359
  2347
                        SETC_t();
nkeynes@417
  2348
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2349
                        }
nkeynes@359
  2350
                        break;
nkeynes@359
  2351
                    case 0xB:
nkeynes@359
  2352
                        { /* NEG Rm, Rn */
nkeynes@359
  2353
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2354
                        load_reg( R_EAX, Rm );
nkeynes@359
  2355
                        NEG_r32( R_EAX );
nkeynes@359
  2356
                        store_reg( R_EAX, Rn );
nkeynes@417
  2357
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2358
                        }
nkeynes@359
  2359
                        break;
nkeynes@359
  2360
                    case 0xC:
nkeynes@359
  2361
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2362
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2363
                        load_reg( R_EAX, Rm );
nkeynes@361
  2364
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2365
                        store_reg( R_EAX, Rn );
nkeynes@359
  2366
                        }
nkeynes@359
  2367
                        break;
nkeynes@359
  2368
                    case 0xD:
nkeynes@359
  2369
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2370
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2371
                        load_reg( R_EAX, Rm );
nkeynes@361
  2372
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2373
                        store_reg( R_EAX, Rn );
nkeynes@359
  2374
                        }
nkeynes@359
  2375
                        break;
nkeynes@359
  2376
                    case 0xE:
nkeynes@359
  2377
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2378
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2379
                        load_reg( R_EAX, Rm );
nkeynes@359
  2380
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2381
                        store_reg( R_EAX, Rn );
nkeynes@359
  2382
                        }
nkeynes@359
  2383
                        break;
nkeynes@359
  2384
                    case 0xF:
nkeynes@359
  2385
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2386
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2387
                        load_reg( R_EAX, Rm );
nkeynes@361
  2388
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2389
                        store_reg( R_EAX, Rn );
nkeynes@359
  2390
                        }
nkeynes@359
  2391
                        break;
nkeynes@359
  2392
                }
nkeynes@359
  2393
                break;
nkeynes@359
  2394
            case 0x7:
nkeynes@359
  2395
                { /* ADD #imm, Rn */
nkeynes@359
  2396
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2397
                load_reg( R_EAX, Rn );
nkeynes@359
  2398
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2399
                store_reg( R_EAX, Rn );
nkeynes@417
  2400
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2401
                }
nkeynes@359
  2402
                break;
nkeynes@359
  2403
            case 0x8:
nkeynes@359
  2404
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2405
                    case 0x0:
nkeynes@359
  2406
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2407
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2408
                        load_reg( R_EAX, Rn );
nkeynes@586
  2409
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2410
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2411
                        load_reg( R_EDX, 0 );
nkeynes@586
  2412
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2413
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2414
                        }
nkeynes@359
  2415
                        break;
nkeynes@359
  2416
                    case 0x1:
nkeynes@359
  2417
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2418
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2419
                        load_reg( R_EAX, Rn );
nkeynes@586
  2420
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2421
                        check_walign16( R_EAX );
nkeynes@586
  2422
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2423
                        load_reg( R_EDX, 0 );
nkeynes@586
  2424
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2425
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2426
                        }
nkeynes@359
  2427
                        break;
nkeynes@359
  2428
                    case 0x4:
nkeynes@359
  2429
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2430
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@586
  2431
                        load_reg( R_EAX, Rm );
nkeynes@586
  2432
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2433
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2434
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2435
                        store_reg( R_EAX, 0 );
nkeynes@417
  2436
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2437
                        }
nkeynes@359
  2438
                        break;
nkeynes@359
  2439
                    case 0x5:
nkeynes@359
  2440
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2441
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@586
  2442
                        load_reg( R_EAX, Rm );
nkeynes@586
  2443
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2444
                        check_ralign16( R_EAX );
nkeynes@586
  2445
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2446
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2447
                        store_reg( R_EAX, 0 );
nkeynes@417
  2448
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2449
                        }
nkeynes@359
  2450
                        break;
nkeynes@359
  2451
                    case 0x8:
nkeynes@359
  2452
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2453
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2454
                        load_reg( R_EAX, 0 );
nkeynes@359
  2455
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2456
                        SETE_t();
nkeynes@417
  2457
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2458
                        }
nkeynes@359
  2459
                        break;
nkeynes@359
  2460
                    case 0x9:
nkeynes@359
  2461
                        { /* BT disp */
nkeynes@359
  2462
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2463
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2464
                    	SLOTILLEGAL();
nkeynes@374
  2465
                        } else {
nkeynes@586
  2466
                    	sh4vma_t target = disp + pc + 4;
nkeynes@586
  2467
                    	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  2468
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2469
                    	JMP_TARGET(nottaken);
nkeynes@408
  2470
                    	return 2;
nkeynes@374
  2471
                        }
nkeynes@359
  2472
                        }
nkeynes@359
  2473
                        break;
nkeynes@359
  2474
                    case 0xB:
nkeynes@359
  2475
                        { /* BF disp */
nkeynes@359
  2476
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2477
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2478
                    	SLOTILLEGAL();
nkeynes@374
  2479
                        } else {
nkeynes@586
  2480
                    	sh4vma_t target = disp + pc + 4;
nkeynes@586
  2481
                    	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  2482
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2483
                    	JMP_TARGET(nottaken);
nkeynes@408
  2484
                    	return 2;
nkeynes@374
  2485
                        }
nkeynes@359
  2486
                        }
nkeynes@359
  2487
                        break;
nkeynes@359
  2488
                    case 0xD:
nkeynes@359
  2489
                        { /* BT/S disp */
nkeynes@359
  2490
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2491
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2492
                    	SLOTILLEGAL();
nkeynes@374
  2493
                        } else {
nkeynes@590
  2494
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2495
                    	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2496
                    	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601
  2497
                    	    JF_rel8(6,nottaken);
nkeynes@601
  2498
                    	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2499
                    	    JMP_TARGET(nottaken);
nkeynes@601
  2500
                    	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  2501
                    	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2502
                    	    exit_block_emu(pc+2);
nkeynes@601
  2503
                    	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2504
                    	    return 2;
nkeynes@601
  2505
                    	} else {
nkeynes@601
  2506
                    	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  2507
                    		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  2508
                    		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2509
                    	    }
nkeynes@601
  2510
                    	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  2511
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2512
                    	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2513
                    	    // not taken
nkeynes@601
  2514
                    	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  2515
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2516
                    	    return 4;
nkeynes@417
  2517
                    	}
nkeynes@374
  2518
                        }
nkeynes@359
  2519
                        }
nkeynes@359
  2520
                        break;
nkeynes@359
  2521
                    case 0xF:
nkeynes@359
  2522
                        { /* BF/S disp */
nkeynes@359
  2523
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2524
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2525
                    	SLOTILLEGAL();
nkeynes@374
  2526
                        } else {
nkeynes@590
  2527
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2528
                    	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2529
                    	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601
  2530
                    	    JT_rel8(6,nottaken);
nkeynes@601
  2531
                    	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2532
                    	    JMP_TARGET(nottaken);
nkeynes@601
  2533
                    	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  2534
                    	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2535
                    	    exit_block_emu(pc+2);
nkeynes@601
  2536
                    	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2537
                    	    return 2;
nkeynes@601
  2538
                    	} else {
nkeynes@601
  2539
                    	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  2540
                    		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  2541
                    		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2542
                    	    }
nkeynes@601
  2543
                    	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  2544
                    	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  2545
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2546
                    	    exit_block_rel( target, pc+4 );
nkeynes@601
  2547
                    	    
nkeynes@601
  2548
                    	    // not taken
nkeynes@601
  2549
                    	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  2550
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2551
                    	    return 4;
nkeynes@417
  2552
                    	}
nkeynes@374
  2553
                        }
nkeynes@359
  2554
                        }
nkeynes@359
  2555
                        break;
nkeynes@359
  2556
                    default:
nkeynes@359
  2557
                        UNDEF();
nkeynes@359
  2558
                        break;
nkeynes@359
  2559
                }
nkeynes@359
  2560
                break;
nkeynes@359
  2561
            case 0x9:
nkeynes@359
  2562
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2563
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2564
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2565
            	SLOTILLEGAL();
nkeynes@374
  2566
                } else {
nkeynes@586
  2567
            	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  2568
            	uint32_t target = pc + disp + 4;
nkeynes@586
  2569
            	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  2570
            	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  2571
            	    MOV_moff32_EAX( ptr );
nkeynes@586
  2572
            	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  2573
            	} else {
nkeynes@586
  2574
            	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  2575
            	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  2576
            	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2577
            	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2578
            	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  2579
            	}
nkeynes@374
  2580
            	store_reg( R_EAX, Rn );
nkeynes@374
  2581
                }
nkeynes@359
  2582
                }
nkeynes@359
  2583
                break;
nkeynes@359
  2584
            case 0xA:
nkeynes@359
  2585
                { /* BRA disp */
nkeynes@359
  2586
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2587
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2588
            	SLOTILLEGAL();
nkeynes@374
  2589
                } else {
nkeynes@590
  2590
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2591
            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2592
            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2593
            	    load_spreg( R_EAX, R_PC );
nkeynes@601
  2594
            	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  2595
            	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2596
            	    exit_block_emu(pc+2);
nkeynes@601
  2597
            	    return 2;
nkeynes@601
  2598
            	} else {
nkeynes@601
  2599
            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2600
            	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2601
            	    return 4;
nkeynes@601
  2602
            	}
nkeynes@374
  2603
                }
nkeynes@359
  2604
                }
nkeynes@359
  2605
                break;
nkeynes@359
  2606
            case 0xB:
nkeynes@359
  2607
                { /* BSR disp */
nkeynes@359
  2608
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2609
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2610
            	SLOTILLEGAL();
nkeynes@374
  2611
                } else {
nkeynes@590
  2612
            	load_spreg( R_EAX, R_PC );
nkeynes@590
  2613
            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  2614
            	store_spreg( R_EAX, R_PR );
nkeynes@590
  2615
            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2616
            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2617
            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2618
            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2619
            	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2620
            	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2621
            	    exit_block_emu(pc+2);
nkeynes@601
  2622
            	    return 2;
nkeynes@601
  2623
            	} else {
nkeynes@601
  2624
            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2625
            	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2626
            	    return 4;
nkeynes@601
  2627
            	}
nkeynes@374
  2628
                }
nkeynes@359
  2629
                }
nkeynes@359
  2630
                break;
nkeynes@359
  2631
            case 0xC:
nkeynes@359
  2632
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2633
                    case 0x0:
nkeynes@359
  2634
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2635
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2636
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2637
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2638
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2639
                        load_reg( R_EDX, 0 );
nkeynes@586
  2640
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2641
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2642
                        }
nkeynes@359
  2643
                        break;
nkeynes@359
  2644
                    case 0x1:
nkeynes@359
  2645
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2646
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2647
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2648
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2649
                        check_walign16( R_EAX );
nkeynes@586
  2650
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2651
                        load_reg( R_EDX, 0 );
nkeynes@586
  2652
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2653
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2654
                        }
nkeynes@359
  2655
                        break;
nkeynes@359
  2656
                    case 0x2:
nkeynes@359
  2657
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2658
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586
  2659
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2660
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2661
                        check_walign32( R_EAX );
nkeynes@586
  2662
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2663
                        load_reg( R_EDX, 0 );
nkeynes@586
  2664
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2665
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2666
                        }
nkeynes@359
  2667
                        break;
nkeynes@359
  2668
                    case 0x3:
nkeynes@359
  2669
                        { /* TRAPA #imm */
nkeynes@359
  2670
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2671
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2672
                    	SLOTILLEGAL();
nkeynes@374
  2673
                        } else {
nkeynes@590
  2674
                    	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  2675
                    	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  2676
                    	load_imm32( R_EAX, imm );
nkeynes@527
  2677
                    	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  2678
                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  2679
                    	exit_block_pcset(pc);
nkeynes@409
  2680
                    	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2681
                    	return 2;
nkeynes@374
  2682
                        }
nkeynes@359
  2683
                        }
nkeynes@359
  2684
                        break;
nkeynes@359
  2685
                    case 0x4:
nkeynes@359
  2686
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2687
                        uint32_t disp = (ir&0xFF); 
nkeynes@586
  2688
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2689
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2690
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2691
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2692
                        store_reg( R_EAX, 0 );
nkeynes@417
  2693
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2694
                        }
nkeynes@359
  2695
                        break;
nkeynes@359
  2696
                    case 0x5:
nkeynes@359
  2697
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2698
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@586
  2699
                        load_spreg( R_EAX, R_GBR );
nkeynes@586
  2700
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2701
                        check_ralign16( R_EAX );
nkeynes@586
  2702
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2703
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2704
                        store_reg( R_EAX, 0 );
nkeynes@417
  2705
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2706
                        }
nkeynes@359
  2707
                        break;
nkeynes@359
  2708
                    case 0x6:
nkeynes@359
  2709
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2710
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@586