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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 601:d8d1af0d133c
prev596:dfc0c93d882e
next604:1024c3a9cb88
author nkeynes
date Tue Jan 22 10:11:45 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Invoke emulator single-step for untranslatable delay slots (and fix a few
related bugs)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t *fixup_addr;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); OP(rel8); \
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    MARK_JMP(rel8,label)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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    MARK_JMP(rel8, label)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
nkeynes@586
   334
 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
nkeynes@586
   335
 */
nkeynes@586
   336
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@368
   337
nkeynes@586
   338
#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
nkeynes@586
   339
#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
nkeynes@586
   340
#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
nkeynes@586
   341
nkeynes@590
   342
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   343
nkeynes@539
   344
/****** Import appropriate calling conventions ******/
nkeynes@539
   345
#if SH4_TRANSLATOR == TARGET_X86_64
nkeynes@539
   346
#include "sh4/ia64abi.h"
nkeynes@539
   347
#else /* SH4_TRANSLATOR == TARGET_X86 */
nkeynes@539
   348
#ifdef APPLE_BUILD
nkeynes@539
   349
#include "sh4/ia32mac.h"
nkeynes@539
   350
#else
nkeynes@539
   351
#include "sh4/ia32abi.h"
nkeynes@539
   352
#endif
nkeynes@539
   353
#endif
nkeynes@539
   354
nkeynes@593
   355
uint32_t sh4_translate_end_block_size()
nkeynes@593
   356
{
nkeynes@596
   357
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   358
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   359
    } else {
nkeynes@596
   360
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   361
    }
nkeynes@593
   362
}
nkeynes@593
   363
nkeynes@593
   364
nkeynes@590
   365
/**
nkeynes@590
   366
 * Embed a breakpoint into the generated code
nkeynes@590
   367
 */
nkeynes@586
   368
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   369
{
nkeynes@591
   370
    load_imm32( R_EAX, pc );
nkeynes@591
   371
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   372
}
nkeynes@590
   373
nkeynes@601
   374
nkeynes@601
   375
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   376
nkeynes@590
   377
/**
nkeynes@590
   378
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   379
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   380
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   381
 *
nkeynes@601
   382
 * Performs:
nkeynes@601
   383
 *   Set PC = endpc
nkeynes@601
   384
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   385
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   386
 *   Call sh4_execute_instruction
nkeynes@601
   387
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   388
 */
nkeynes@601
   389
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   390
{
nkeynes@590
   391
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   392
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   393
    
nkeynes@601
   394
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   395
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   396
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   397
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   398
nkeynes@590
   399
    call_func0( sh4_execute_instruction );    
nkeynes@601
   400
    load_spreg( R_EAX, R_PC );
nkeynes@590
   401
    if( sh4_x86.tlb_on ) {
nkeynes@590
   402
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   403
    } else {
nkeynes@590
   404
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   405
    }
nkeynes@601
   406
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   407
    POP_r32(R_EBP);
nkeynes@590
   408
    RET();
nkeynes@590
   409
} 
nkeynes@539
   410
nkeynes@359
   411
/**
nkeynes@359
   412
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   413
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   414
 * 
nkeynes@586
   415
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   416
 *
nkeynes@359
   417
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   418
 * (eg a branch or 
nkeynes@359
   419
 */
nkeynes@590
   420
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   421
{
nkeynes@388
   422
    uint32_t ir;
nkeynes@586
   423
    /* Read instruction from icache */
nkeynes@586
   424
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   425
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   426
    
nkeynes@586
   427
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   428
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   429
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   430
	 * almost certainly in a delay slot.
nkeynes@586
   431
	 *
nkeynes@586
   432
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   433
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   434
	 * small repairs to cope with the different environment).
nkeynes@586
   435
	 */
nkeynes@586
   436
nkeynes@586
   437
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   438
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   439
    }
nkeynes@359
   440
%%
nkeynes@359
   441
/* ALU operations */
nkeynes@359
   442
ADD Rm, Rn {:
nkeynes@359
   443
    load_reg( R_EAX, Rm );
nkeynes@359
   444
    load_reg( R_ECX, Rn );
nkeynes@359
   445
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   446
    store_reg( R_ECX, Rn );
nkeynes@417
   447
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   448
:}
nkeynes@359
   449
ADD #imm, Rn {:  
nkeynes@359
   450
    load_reg( R_EAX, Rn );
nkeynes@359
   451
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   452
    store_reg( R_EAX, Rn );
nkeynes@417
   453
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   454
:}
nkeynes@359
   455
ADDC Rm, Rn {:
nkeynes@417
   456
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   457
	LDC_t();
nkeynes@417
   458
    }
nkeynes@359
   459
    load_reg( R_EAX, Rm );
nkeynes@359
   460
    load_reg( R_ECX, Rn );
nkeynes@359
   461
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   462
    store_reg( R_ECX, Rn );
nkeynes@359
   463
    SETC_t();
nkeynes@417
   464
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   465
:}
nkeynes@359
   466
ADDV Rm, Rn {:
nkeynes@359
   467
    load_reg( R_EAX, Rm );
nkeynes@359
   468
    load_reg( R_ECX, Rn );
nkeynes@359
   469
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   470
    store_reg( R_ECX, Rn );
nkeynes@359
   471
    SETO_t();
nkeynes@417
   472
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   473
:}
nkeynes@359
   474
AND Rm, Rn {:
nkeynes@359
   475
    load_reg( R_EAX, Rm );
nkeynes@359
   476
    load_reg( R_ECX, Rn );
nkeynes@359
   477
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   478
    store_reg( R_ECX, Rn );
nkeynes@417
   479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   480
:}
nkeynes@359
   481
AND #imm, R0 {:  
nkeynes@359
   482
    load_reg( R_EAX, 0 );
nkeynes@359
   483
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   484
    store_reg( R_EAX, 0 );
nkeynes@417
   485
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   486
:}
nkeynes@359
   487
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   488
    load_reg( R_EAX, 0 );
nkeynes@359
   489
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   490
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   491
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   492
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   493
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   494
    POP_realigned_r32(R_ECX);
nkeynes@386
   495
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   496
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   497
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   498
:}
nkeynes@359
   499
CMP/EQ Rm, Rn {:  
nkeynes@359
   500
    load_reg( R_EAX, Rm );
nkeynes@359
   501
    load_reg( R_ECX, Rn );
nkeynes@359
   502
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   503
    SETE_t();
nkeynes@417
   504
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   505
:}
nkeynes@359
   506
CMP/EQ #imm, R0 {:  
nkeynes@359
   507
    load_reg( R_EAX, 0 );
nkeynes@359
   508
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   509
    SETE_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/GE Rm, Rn {:  
nkeynes@359
   513
    load_reg( R_EAX, Rm );
nkeynes@359
   514
    load_reg( R_ECX, Rn );
nkeynes@359
   515
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   516
    SETGE_t();
nkeynes@417
   517
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   518
:}
nkeynes@359
   519
CMP/GT Rm, Rn {: 
nkeynes@359
   520
    load_reg( R_EAX, Rm );
nkeynes@359
   521
    load_reg( R_ECX, Rn );
nkeynes@359
   522
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   523
    SETG_t();
nkeynes@417
   524
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   525
:}
nkeynes@359
   526
CMP/HI Rm, Rn {:  
nkeynes@359
   527
    load_reg( R_EAX, Rm );
nkeynes@359
   528
    load_reg( R_ECX, Rn );
nkeynes@359
   529
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   530
    SETA_t();
nkeynes@417
   531
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   532
:}
nkeynes@359
   533
CMP/HS Rm, Rn {: 
nkeynes@359
   534
    load_reg( R_EAX, Rm );
nkeynes@359
   535
    load_reg( R_ECX, Rn );
nkeynes@359
   536
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   537
    SETAE_t();
nkeynes@417
   538
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   539
 :}
nkeynes@359
   540
CMP/PL Rn {: 
nkeynes@359
   541
    load_reg( R_EAX, Rn );
nkeynes@359
   542
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   543
    SETG_t();
nkeynes@417
   544
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   545
:}
nkeynes@359
   546
CMP/PZ Rn {:  
nkeynes@359
   547
    load_reg( R_EAX, Rn );
nkeynes@359
   548
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   549
    SETGE_t();
nkeynes@417
   550
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   551
:}
nkeynes@361
   552
CMP/STR Rm, Rn {:  
nkeynes@368
   553
    load_reg( R_EAX, Rm );
nkeynes@368
   554
    load_reg( R_ECX, Rn );
nkeynes@368
   555
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   556
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   557
    JE_rel8(13, target1);
nkeynes@368
   558
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   559
    JE_rel8(9, target2);
nkeynes@368
   560
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   561
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   562
    JE_rel8(2, target3);
nkeynes@368
   563
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   564
    JMP_TARGET(target1);
nkeynes@380
   565
    JMP_TARGET(target2);
nkeynes@380
   566
    JMP_TARGET(target3);
nkeynes@368
   567
    SETE_t();
nkeynes@417
   568
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   569
:}
nkeynes@361
   570
DIV0S Rm, Rn {:
nkeynes@361
   571
    load_reg( R_EAX, Rm );
nkeynes@386
   572
    load_reg( R_ECX, Rn );
nkeynes@361
   573
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   574
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   575
    store_spreg( R_EAX, R_M );
nkeynes@361
   576
    store_spreg( R_ECX, R_Q );
nkeynes@361
   577
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   578
    SETNE_t();
nkeynes@417
   579
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   580
:}
nkeynes@361
   581
DIV0U {:  
nkeynes@361
   582
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   583
    store_spreg( R_EAX, R_Q );
nkeynes@361
   584
    store_spreg( R_EAX, R_M );
nkeynes@361
   585
    store_spreg( R_EAX, R_T );
nkeynes@417
   586
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   587
:}
nkeynes@386
   588
DIV1 Rm, Rn {:
nkeynes@386
   589
    load_spreg( R_ECX, R_M );
nkeynes@386
   590
    load_reg( R_EAX, Rn );
nkeynes@417
   591
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   592
	LDC_t();
nkeynes@417
   593
    }
nkeynes@386
   594
    RCL1_r32( R_EAX );
nkeynes@386
   595
    SETC_r8( R_DL ); // Q'
nkeynes@386
   596
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
   597
    JE_rel8(5, mqequal);
nkeynes@386
   598
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   599
    JMP_rel8(3, end);
nkeynes@380
   600
    JMP_TARGET(mqequal);
nkeynes@386
   601
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   602
    JMP_TARGET(end);
nkeynes@386
   603
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   604
    SETC_r8(R_AL); // tmp1
nkeynes@386
   605
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   606
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   607
    store_spreg( R_ECX, R_Q );
nkeynes@386
   608
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   609
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   610
    store_spreg( R_EAX, R_T );
nkeynes@417
   611
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   612
:}
nkeynes@361
   613
DMULS.L Rm, Rn {:  
nkeynes@361
   614
    load_reg( R_EAX, Rm );
nkeynes@361
   615
    load_reg( R_ECX, Rn );
nkeynes@361
   616
    IMUL_r32(R_ECX);
nkeynes@361
   617
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   618
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   620
:}
nkeynes@361
   621
DMULU.L Rm, Rn {:  
nkeynes@361
   622
    load_reg( R_EAX, Rm );
nkeynes@361
   623
    load_reg( R_ECX, Rn );
nkeynes@361
   624
    MUL_r32(R_ECX);
nkeynes@361
   625
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   626
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   627
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   628
:}
nkeynes@359
   629
DT Rn {:  
nkeynes@359
   630
    load_reg( R_EAX, Rn );
nkeynes@382
   631
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   632
    store_reg( R_EAX, Rn );
nkeynes@359
   633
    SETE_t();
nkeynes@417
   634
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   635
:}
nkeynes@359
   636
EXTS.B Rm, Rn {:  
nkeynes@359
   637
    load_reg( R_EAX, Rm );
nkeynes@359
   638
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   639
    store_reg( R_EAX, Rn );
nkeynes@359
   640
:}
nkeynes@361
   641
EXTS.W Rm, Rn {:  
nkeynes@361
   642
    load_reg( R_EAX, Rm );
nkeynes@361
   643
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   644
    store_reg( R_EAX, Rn );
nkeynes@361
   645
:}
nkeynes@361
   646
EXTU.B Rm, Rn {:  
nkeynes@361
   647
    load_reg( R_EAX, Rm );
nkeynes@361
   648
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   649
    store_reg( R_EAX, Rn );
nkeynes@361
   650
:}
nkeynes@361
   651
EXTU.W Rm, Rn {:  
nkeynes@361
   652
    load_reg( R_EAX, Rm );
nkeynes@361
   653
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   654
    store_reg( R_EAX, Rn );
nkeynes@361
   655
:}
nkeynes@586
   656
MAC.L @Rm+, @Rn+ {:
nkeynes@586
   657
    if( Rm == Rn ) {
nkeynes@586
   658
	load_reg( R_EAX, Rm );
nkeynes@586
   659
	check_ralign32( R_EAX );
nkeynes@586
   660
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   661
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   662
	load_reg( R_EAX, Rn );
nkeynes@586
   663
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   664
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   665
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   666
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   667
	// adding a page-boundary check to skip the second translation
nkeynes@586
   668
    } else {
nkeynes@586
   669
	load_reg( R_EAX, Rm );
nkeynes@586
   670
	check_ralign32( R_EAX );
nkeynes@586
   671
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   672
	load_reg( R_ECX, Rn );
nkeynes@596
   673
	check_ralign32( R_ECX );
nkeynes@586
   674
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   675
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   676
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   677
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   678
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   679
    }
nkeynes@586
   680
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   681
    POP_r32( R_ECX );
nkeynes@586
   682
    PUSH_r32( R_EAX );
nkeynes@386
   683
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   684
    POP_realigned_r32( R_ECX );
nkeynes@586
   685
nkeynes@386
   686
    IMUL_r32( R_ECX );
nkeynes@386
   687
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   688
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   689
nkeynes@386
   690
    load_spreg( R_ECX, R_S );
nkeynes@386
   691
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@527
   692
    JE_rel8( CALL_FUNC0_SIZE, nosat );
nkeynes@386
   693
    call_func0( signsat48 );
nkeynes@386
   694
    JMP_TARGET( nosat );
nkeynes@417
   695
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   696
:}
nkeynes@386
   697
MAC.W @Rm+, @Rn+ {:  
nkeynes@586
   698
    if( Rm == Rn ) {
nkeynes@586
   699
	load_reg( R_EAX, Rm );
nkeynes@586
   700
	check_ralign16( R_EAX );
nkeynes@586
   701
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   702
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   703
	load_reg( R_EAX, Rn );
nkeynes@586
   704
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   705
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   706
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   707
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   708
	// adding a page-boundary check to skip the second translation
nkeynes@586
   709
    } else {
nkeynes@586
   710
	load_reg( R_EAX, Rm );
nkeynes@586
   711
	check_ralign16( R_EAX );
nkeynes@586
   712
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   713
	load_reg( R_ECX, Rn );
nkeynes@596
   714
	check_ralign16( R_ECX );
nkeynes@586
   715
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   716
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   717
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   718
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   719
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   720
    }
nkeynes@586
   721
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   722
    POP_r32( R_ECX );
nkeynes@586
   723
    PUSH_r32( R_EAX );
nkeynes@386
   724
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   725
    POP_realigned_r32( R_ECX );
nkeynes@386
   726
    IMUL_r32( R_ECX );
nkeynes@386
   727
nkeynes@386
   728
    load_spreg( R_ECX, R_S );
nkeynes@386
   729
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
   730
    JE_rel8( 47, nosat );
nkeynes@386
   731
nkeynes@386
   732
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   733
    JNO_rel8( 51, end );            // 2
nkeynes@386
   734
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   735
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
   736
    JS_rel8( 13, positive );        // 2
nkeynes@386
   737
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   738
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   739
    JMP_rel8( 25, end2 );           // 2
nkeynes@386
   740
nkeynes@386
   741
    JMP_TARGET(positive);
nkeynes@386
   742
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   743
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
   744
    JMP_rel8( 12, end3);            // 2
nkeynes@386
   745
nkeynes@386
   746
    JMP_TARGET(nosat);
nkeynes@386
   747
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   748
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   749
    JMP_TARGET(end);
nkeynes@386
   750
    JMP_TARGET(end2);
nkeynes@386
   751
    JMP_TARGET(end3);
nkeynes@417
   752
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   753
:}
nkeynes@359
   754
MOVT Rn {:  
nkeynes@359
   755
    load_spreg( R_EAX, R_T );
nkeynes@359
   756
    store_reg( R_EAX, Rn );
nkeynes@359
   757
:}
nkeynes@361
   758
MUL.L Rm, Rn {:  
nkeynes@361
   759
    load_reg( R_EAX, Rm );
nkeynes@361
   760
    load_reg( R_ECX, Rn );
nkeynes@361
   761
    MUL_r32( R_ECX );
nkeynes@361
   762
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   763
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   764
:}
nkeynes@374
   765
MULS.W Rm, Rn {:
nkeynes@374
   766
    load_reg16s( R_EAX, Rm );
nkeynes@374
   767
    load_reg16s( R_ECX, Rn );
nkeynes@374
   768
    MUL_r32( R_ECX );
nkeynes@374
   769
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   770
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   771
:}
nkeynes@374
   772
MULU.W Rm, Rn {:  
nkeynes@374
   773
    load_reg16u( R_EAX, Rm );
nkeynes@374
   774
    load_reg16u( R_ECX, Rn );
nkeynes@374
   775
    MUL_r32( R_ECX );
nkeynes@374
   776
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   777
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   778
:}
nkeynes@359
   779
NEG Rm, Rn {:
nkeynes@359
   780
    load_reg( R_EAX, Rm );
nkeynes@359
   781
    NEG_r32( R_EAX );
nkeynes@359
   782
    store_reg( R_EAX, Rn );
nkeynes@417
   783
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   784
:}
nkeynes@359
   785
NEGC Rm, Rn {:  
nkeynes@359
   786
    load_reg( R_EAX, Rm );
nkeynes@359
   787
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   788
    LDC_t();
nkeynes@359
   789
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   790
    store_reg( R_ECX, Rn );
nkeynes@359
   791
    SETC_t();
nkeynes@417
   792
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   793
:}
nkeynes@359
   794
NOT Rm, Rn {:  
nkeynes@359
   795
    load_reg( R_EAX, Rm );
nkeynes@359
   796
    NOT_r32( R_EAX );
nkeynes@359
   797
    store_reg( R_EAX, Rn );
nkeynes@417
   798
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   799
:}
nkeynes@359
   800
OR Rm, Rn {:  
nkeynes@359
   801
    load_reg( R_EAX, Rm );
nkeynes@359
   802
    load_reg( R_ECX, Rn );
nkeynes@359
   803
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   804
    store_reg( R_ECX, Rn );
nkeynes@417
   805
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   806
:}
nkeynes@359
   807
OR #imm, R0 {:
nkeynes@359
   808
    load_reg( R_EAX, 0 );
nkeynes@359
   809
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   810
    store_reg( R_EAX, 0 );
nkeynes@417
   811
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   812
:}
nkeynes@374
   813
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   814
    load_reg( R_EAX, 0 );
nkeynes@374
   815
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   816
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   817
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   818
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   819
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   820
    POP_realigned_r32(R_ECX);
nkeynes@386
   821
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   822
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   823
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   824
:}
nkeynes@359
   825
ROTCL Rn {:
nkeynes@359
   826
    load_reg( R_EAX, Rn );
nkeynes@417
   827
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   828
	LDC_t();
nkeynes@417
   829
    }
nkeynes@359
   830
    RCL1_r32( R_EAX );
nkeynes@359
   831
    store_reg( R_EAX, Rn );
nkeynes@359
   832
    SETC_t();
nkeynes@417
   833
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   834
:}
nkeynes@359
   835
ROTCR Rn {:  
nkeynes@359
   836
    load_reg( R_EAX, Rn );
nkeynes@417
   837
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   838
	LDC_t();
nkeynes@417
   839
    }
nkeynes@359
   840
    RCR1_r32( R_EAX );
nkeynes@359
   841
    store_reg( R_EAX, Rn );
nkeynes@359
   842
    SETC_t();
nkeynes@417
   843
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   844
:}
nkeynes@359
   845
ROTL Rn {:  
nkeynes@359
   846
    load_reg( R_EAX, Rn );
nkeynes@359
   847
    ROL1_r32( R_EAX );
nkeynes@359
   848
    store_reg( R_EAX, Rn );
nkeynes@359
   849
    SETC_t();
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   851
:}
nkeynes@359
   852
ROTR Rn {:  
nkeynes@359
   853
    load_reg( R_EAX, Rn );
nkeynes@359
   854
    ROR1_r32( R_EAX );
nkeynes@359
   855
    store_reg( R_EAX, Rn );
nkeynes@359
   856
    SETC_t();
nkeynes@417
   857
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   858
:}
nkeynes@359
   859
SHAD Rm, Rn {:
nkeynes@359
   860
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   861
    load_reg( R_EAX, Rn );
nkeynes@361
   862
    load_reg( R_ECX, Rm );
nkeynes@361
   863
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   864
    JGE_rel8(16, doshl);
nkeynes@361
   865
                    
nkeynes@361
   866
    NEG_r32( R_ECX );      // 2
nkeynes@361
   867
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   868
    JE_rel8( 4, emptysar);     // 2
nkeynes@361
   869
    SAR_r32_CL( R_EAX );       // 2
nkeynes@386
   870
    JMP_rel8(10, end);          // 2
nkeynes@386
   871
nkeynes@386
   872
    JMP_TARGET(emptysar);
nkeynes@386
   873
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
   874
    JMP_rel8(5, end2);
nkeynes@382
   875
nkeynes@380
   876
    JMP_TARGET(doshl);
nkeynes@361
   877
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   878
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   879
    JMP_TARGET(end);
nkeynes@386
   880
    JMP_TARGET(end2);
nkeynes@361
   881
    store_reg( R_EAX, Rn );
nkeynes@417
   882
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   883
:}
nkeynes@359
   884
SHLD Rm, Rn {:  
nkeynes@368
   885
    load_reg( R_EAX, Rn );
nkeynes@368
   886
    load_reg( R_ECX, Rm );
nkeynes@382
   887
    CMP_imm32_r32( 0, R_ECX );
nkeynes@386
   888
    JGE_rel8(15, doshl);
nkeynes@368
   889
nkeynes@382
   890
    NEG_r32( R_ECX );      // 2
nkeynes@382
   891
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
   892
    JE_rel8( 4, emptyshr );
nkeynes@382
   893
    SHR_r32_CL( R_EAX );       // 2
nkeynes@386
   894
    JMP_rel8(9, end);          // 2
nkeynes@386
   895
nkeynes@386
   896
    JMP_TARGET(emptyshr);
nkeynes@386
   897
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
   898
    JMP_rel8(5, end2);
nkeynes@382
   899
nkeynes@382
   900
    JMP_TARGET(doshl);
nkeynes@382
   901
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   902
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   903
    JMP_TARGET(end);
nkeynes@386
   904
    JMP_TARGET(end2);
nkeynes@368
   905
    store_reg( R_EAX, Rn );
nkeynes@417
   906
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   907
:}
nkeynes@359
   908
SHAL Rn {: 
nkeynes@359
   909
    load_reg( R_EAX, Rn );
nkeynes@359
   910
    SHL1_r32( R_EAX );
nkeynes@397
   911
    SETC_t();
nkeynes@359
   912
    store_reg( R_EAX, Rn );
nkeynes@417
   913
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   914
:}
nkeynes@359
   915
SHAR Rn {:  
nkeynes@359
   916
    load_reg( R_EAX, Rn );
nkeynes@359
   917
    SAR1_r32( R_EAX );
nkeynes@397
   918
    SETC_t();
nkeynes@359
   919
    store_reg( R_EAX, Rn );
nkeynes@417
   920
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   921
:}
nkeynes@359
   922
SHLL Rn {:  
nkeynes@359
   923
    load_reg( R_EAX, Rn );
nkeynes@359
   924
    SHL1_r32( R_EAX );
nkeynes@397
   925
    SETC_t();
nkeynes@359
   926
    store_reg( R_EAX, Rn );
nkeynes@417
   927
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   928
:}
nkeynes@359
   929
SHLL2 Rn {:
nkeynes@359
   930
    load_reg( R_EAX, Rn );
nkeynes@359
   931
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   932
    store_reg( R_EAX, Rn );
nkeynes@417
   933
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   934
:}
nkeynes@359
   935
SHLL8 Rn {:  
nkeynes@359
   936
    load_reg( R_EAX, Rn );
nkeynes@359
   937
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   938
    store_reg( R_EAX, Rn );
nkeynes@417
   939
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   940
:}
nkeynes@359
   941
SHLL16 Rn {:  
nkeynes@359
   942
    load_reg( R_EAX, Rn );
nkeynes@359
   943
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   944
    store_reg( R_EAX, Rn );
nkeynes@417
   945
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   946
:}
nkeynes@359
   947
SHLR Rn {:  
nkeynes@359
   948
    load_reg( R_EAX, Rn );
nkeynes@359
   949
    SHR1_r32( R_EAX );
nkeynes@397
   950
    SETC_t();
nkeynes@359
   951
    store_reg( R_EAX, Rn );
nkeynes@417
   952
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   953
:}
nkeynes@359
   954
SHLR2 Rn {:  
nkeynes@359
   955
    load_reg( R_EAX, Rn );
nkeynes@359
   956
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   957
    store_reg( R_EAX, Rn );
nkeynes@417
   958
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   959
:}
nkeynes@359
   960
SHLR8 Rn {:  
nkeynes@359
   961
    load_reg( R_EAX, Rn );
nkeynes@359
   962
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   963
    store_reg( R_EAX, Rn );
nkeynes@417
   964
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   965
:}
nkeynes@359
   966
SHLR16 Rn {:  
nkeynes@359
   967
    load_reg( R_EAX, Rn );
nkeynes@359
   968
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   969
    store_reg( R_EAX, Rn );
nkeynes@417
   970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   971
:}
nkeynes@359
   972
SUB Rm, Rn {:  
nkeynes@359
   973
    load_reg( R_EAX, Rm );
nkeynes@359
   974
    load_reg( R_ECX, Rn );
nkeynes@359
   975
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   976
    store_reg( R_ECX, Rn );
nkeynes@417
   977
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   978
:}
nkeynes@359
   979
SUBC Rm, Rn {:  
nkeynes@359
   980
    load_reg( R_EAX, Rm );
nkeynes@359
   981
    load_reg( R_ECX, Rn );
nkeynes@417
   982
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   983
	LDC_t();
nkeynes@417
   984
    }
nkeynes@359
   985
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   986
    store_reg( R_ECX, Rn );
nkeynes@394
   987
    SETC_t();
nkeynes@417
   988
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   989
:}
nkeynes@359
   990
SUBV Rm, Rn {:  
nkeynes@359
   991
    load_reg( R_EAX, Rm );
nkeynes@359
   992
    load_reg( R_ECX, Rn );
nkeynes@359
   993
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   994
    store_reg( R_ECX, Rn );
nkeynes@359
   995
    SETO_t();
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   997
:}
nkeynes@359
   998
SWAP.B Rm, Rn {:  
nkeynes@359
   999
    load_reg( R_EAX, Rm );
nkeynes@601
  1000
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1001
    store_reg( R_EAX, Rn );
nkeynes@359
  1002
:}
nkeynes@359
  1003
SWAP.W Rm, Rn {:  
nkeynes@359
  1004
    load_reg( R_EAX, Rm );
nkeynes@359
  1005
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1006
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1007
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1008
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1009
    store_reg( R_ECX, Rn );
nkeynes@417
  1010
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1011
:}
nkeynes@361
  1012
TAS.B @Rn {:  
nkeynes@586
  1013
    load_reg( R_EAX, Rn );
nkeynes@586
  1014
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1015
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1016
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1017
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1018
    SETE_t();
nkeynes@361
  1019
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1020
    POP_realigned_r32( R_ECX );
nkeynes@361
  1021
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1023
:}
nkeynes@361
  1024
TST Rm, Rn {:  
nkeynes@361
  1025
    load_reg( R_EAX, Rm );
nkeynes@361
  1026
    load_reg( R_ECX, Rn );
nkeynes@361
  1027
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1028
    SETE_t();
nkeynes@417
  1029
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1030
:}
nkeynes@368
  1031
TST #imm, R0 {:  
nkeynes@368
  1032
    load_reg( R_EAX, 0 );
nkeynes@368
  1033
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1034
    SETE_t();
nkeynes@417
  1035
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1036
:}
nkeynes@368
  1037
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
  1038
    load_reg( R_EAX, 0);
nkeynes@368
  1039
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1040
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1041
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1042
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1043
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1044
    SETE_t();
nkeynes@417
  1045
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1046
:}
nkeynes@359
  1047
XOR Rm, Rn {:  
nkeynes@359
  1048
    load_reg( R_EAX, Rm );
nkeynes@359
  1049
    load_reg( R_ECX, Rn );
nkeynes@359
  1050
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1051
    store_reg( R_ECX, Rn );
nkeynes@417
  1052
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1053
:}
nkeynes@359
  1054
XOR #imm, R0 {:  
nkeynes@359
  1055
    load_reg( R_EAX, 0 );
nkeynes@359
  1056
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1057
    store_reg( R_EAX, 0 );
nkeynes@417
  1058
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1059
:}
nkeynes@359
  1060
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
  1061
    load_reg( R_EAX, 0 );
nkeynes@359
  1062
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1063
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1064
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1065
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1066
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1067
    POP_realigned_r32(R_ECX);
nkeynes@359
  1068
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1069
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1071
:}
nkeynes@361
  1072
XTRCT Rm, Rn {:
nkeynes@361
  1073
    load_reg( R_EAX, Rm );
nkeynes@394
  1074
    load_reg( R_ECX, Rn );
nkeynes@394
  1075
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1076
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1077
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1078
    store_reg( R_ECX, Rn );
nkeynes@417
  1079
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1080
:}
nkeynes@359
  1081
nkeynes@359
  1082
/* Data move instructions */
nkeynes@359
  1083
MOV Rm, Rn {:  
nkeynes@359
  1084
    load_reg( R_EAX, Rm );
nkeynes@359
  1085
    store_reg( R_EAX, Rn );
nkeynes@359
  1086
:}
nkeynes@359
  1087
MOV #imm, Rn {:  
nkeynes@359
  1088
    load_imm32( R_EAX, imm );
nkeynes@359
  1089
    store_reg( R_EAX, Rn );
nkeynes@359
  1090
:}
nkeynes@359
  1091
MOV.B Rm, @Rn {:  
nkeynes@586
  1092
    load_reg( R_EAX, Rn );
nkeynes@586
  1093
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1094
    load_reg( R_EDX, Rm );
nkeynes@586
  1095
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1097
:}
nkeynes@359
  1098
MOV.B Rm, @-Rn {:  
nkeynes@586
  1099
    load_reg( R_EAX, Rn );
nkeynes@586
  1100
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1101
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1102
    load_reg( R_EDX, Rm );
nkeynes@586
  1103
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1104
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1106
:}
nkeynes@359
  1107
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
  1108
    load_reg( R_EAX, 0 );
nkeynes@359
  1109
    load_reg( R_ECX, Rn );
nkeynes@586
  1110
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1111
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1112
    load_reg( R_EDX, Rm );
nkeynes@586
  1113
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1114
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1115
:}
nkeynes@359
  1116
MOV.B R0, @(disp, GBR) {:  
nkeynes@586
  1117
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1118
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1119
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1120
    load_reg( R_EDX, 0 );
nkeynes@586
  1121
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1123
:}
nkeynes@359
  1124
MOV.B R0, @(disp, Rn) {:  
nkeynes@586
  1125
    load_reg( R_EAX, Rn );
nkeynes@586
  1126
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1127
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1128
    load_reg( R_EDX, 0 );
nkeynes@586
  1129
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1130
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1131
:}
nkeynes@359
  1132
MOV.B @Rm, Rn {:  
nkeynes@586
  1133
    load_reg( R_EAX, Rm );
nkeynes@586
  1134
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1135
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1136
    store_reg( R_EAX, Rn );
nkeynes@417
  1137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1138
:}
nkeynes@359
  1139
MOV.B @Rm+, Rn {:  
nkeynes@586
  1140
    load_reg( R_EAX, Rm );
nkeynes@586
  1141
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1142
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1143
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1144
    store_reg( R_EAX, Rn );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1146
:}
nkeynes@359
  1147
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
  1148
    load_reg( R_EAX, 0 );
nkeynes@359
  1149
    load_reg( R_ECX, Rm );
nkeynes@586
  1150
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1151
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1152
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1153
    store_reg( R_EAX, Rn );
nkeynes@417
  1154
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1155
:}
nkeynes@359
  1156
MOV.B @(disp, GBR), R0 {:  
nkeynes@586
  1157
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1158
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1159
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1160
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1161
    store_reg( R_EAX, 0 );
nkeynes@417
  1162
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1163
:}
nkeynes@359
  1164
MOV.B @(disp, Rm), R0 {:  
nkeynes@586
  1165
    load_reg( R_EAX, Rm );
nkeynes@586
  1166
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1167
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1168
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1169
    store_reg( R_EAX, 0 );
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1171
:}
nkeynes@374
  1172
MOV.L Rm, @Rn {:
nkeynes@586
  1173
    load_reg( R_EAX, Rn );
nkeynes@586
  1174
    check_walign32(R_EAX);
nkeynes@586
  1175
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1176
    load_reg( R_EDX, Rm );
nkeynes@586
  1177
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1178
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1179
:}
nkeynes@361
  1180
MOV.L Rm, @-Rn {:  
nkeynes@586
  1181
    load_reg( R_EAX, Rn );
nkeynes@586
  1182
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1183
    check_walign32( R_EAX );
nkeynes@586
  1184
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1185
    load_reg( R_EDX, Rm );
nkeynes@586
  1186
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1187
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1188
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1189
:}
nkeynes@361
  1190
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
  1191
    load_reg( R_EAX, 0 );
nkeynes@361
  1192
    load_reg( R_ECX, Rn );
nkeynes@586
  1193
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1194
    check_walign32( R_EAX );
nkeynes@586
  1195
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1196
    load_reg( R_EDX, Rm );
nkeynes@586
  1197
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1198
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1199
:}
nkeynes@361
  1200
MOV.L R0, @(disp, GBR) {:  
nkeynes@586
  1201
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1202
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1203
    check_walign32( R_EAX );
nkeynes@586
  1204
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1205
    load_reg( R_EDX, 0 );
nkeynes@586
  1206
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1207
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1208
:}
nkeynes@361
  1209
MOV.L Rm, @(disp, Rn) {:  
nkeynes@586
  1210
    load_reg( R_EAX, Rn );
nkeynes@586
  1211
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1212
    check_walign32( R_EAX );
nkeynes@586
  1213
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1214
    load_reg( R_EDX, Rm );
nkeynes@586
  1215
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1216
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1217
:}
nkeynes@361
  1218
MOV.L @Rm, Rn {:  
nkeynes@586
  1219
    load_reg( R_EAX, Rm );
nkeynes@586
  1220
    check_ralign32( R_EAX );
nkeynes@586
  1221
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1222
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1223
    store_reg( R_EAX, Rn );
nkeynes@417
  1224
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1225
:}
nkeynes@361
  1226
MOV.L @Rm+, Rn {:  
nkeynes@361
  1227
    load_reg( R_EAX, Rm );
nkeynes@382
  1228
    check_ralign32( R_EAX );
nkeynes@586
  1229
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1230
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1231
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1232
    store_reg( R_EAX, Rn );
nkeynes@417
  1233
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1234
:}
nkeynes@361
  1235
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1236
    load_reg( R_EAX, 0 );
nkeynes@361
  1237
    load_reg( R_ECX, Rm );
nkeynes@586
  1238
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1239
    check_ralign32( R_EAX );
nkeynes@586
  1240
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1241
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1242
    store_reg( R_EAX, Rn );
nkeynes@417
  1243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1244
:}
nkeynes@361
  1245
MOV.L @(disp, GBR), R0 {:
nkeynes@586
  1246
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1247
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1248
    check_ralign32( R_EAX );
nkeynes@586
  1249
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1250
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1251
    store_reg( R_EAX, 0 );
nkeynes@417
  1252
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1253
:}
nkeynes@361
  1254
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1255
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1256
	SLOTILLEGAL();
nkeynes@374
  1257
    } else {
nkeynes@388
  1258
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1259
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1260
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1261
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1262
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1263
nkeynes@586
  1264
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1265
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1266
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1267
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1268
	    // behaviour though.
nkeynes@586
  1269
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1270
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1271
	} else {
nkeynes@586
  1272
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1273
	    // different virtual address than the translation was done with,
nkeynes@586
  1274
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1275
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1276
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1277
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1278
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1279
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1280
	}
nkeynes@382
  1281
	store_reg( R_EAX, Rn );
nkeynes@374
  1282
    }
nkeynes@361
  1283
:}
nkeynes@361
  1284
MOV.L @(disp, Rm), Rn {:  
nkeynes@586
  1285
    load_reg( R_EAX, Rm );
nkeynes@586
  1286
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1287
    check_ralign32( R_EAX );
nkeynes@586
  1288
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1289
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1290
    store_reg( R_EAX, Rn );
nkeynes@417
  1291
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1292
:}
nkeynes@361
  1293
MOV.W Rm, @Rn {:  
nkeynes@586
  1294
    load_reg( R_EAX, Rn );
nkeynes@586
  1295
    check_walign16( R_EAX );
nkeynes@586
  1296
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1297
    load_reg( R_EDX, Rm );
nkeynes@586
  1298
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1299
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1300
:}
nkeynes@361
  1301
MOV.W Rm, @-Rn {:  
nkeynes@586
  1302
    load_reg( R_EAX, Rn );
nkeynes@586
  1303
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1304
    check_walign16( R_EAX );
nkeynes@586
  1305
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1306
    load_reg( R_EDX, Rm );
nkeynes@586
  1307
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1308
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1309
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1310
:}
nkeynes@361
  1311
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1312
    load_reg( R_EAX, 0 );
nkeynes@361
  1313
    load_reg( R_ECX, Rn );
nkeynes@586
  1314
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1315
    check_walign16( R_EAX );
nkeynes@586
  1316
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1317
    load_reg( R_EDX, Rm );
nkeynes@586
  1318
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1319
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1320
:}
nkeynes@361
  1321
MOV.W R0, @(disp, GBR) {:  
nkeynes@586
  1322
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1323
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1324
    check_walign16( R_EAX );
nkeynes@586
  1325
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1326
    load_reg( R_EDX, 0 );
nkeynes@586
  1327
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1328
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1329
:}
nkeynes@361
  1330
MOV.W R0, @(disp, Rn) {:  
nkeynes@586
  1331
    load_reg( R_EAX, Rn );
nkeynes@586
  1332
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1333
    check_walign16( R_EAX );
nkeynes@586
  1334
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1335
    load_reg( R_EDX, 0 );
nkeynes@586
  1336
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1337
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1338
:}
nkeynes@361
  1339
MOV.W @Rm, Rn {:  
nkeynes@586
  1340
    load_reg( R_EAX, Rm );
nkeynes@586
  1341
    check_ralign16( R_EAX );
nkeynes@586
  1342
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1343
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1344
    store_reg( R_EAX, Rn );
nkeynes@417
  1345
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1346
:}
nkeynes@361
  1347
MOV.W @Rm+, Rn {:  
nkeynes@361
  1348
    load_reg( R_EAX, Rm );
nkeynes@374
  1349
    check_ralign16( R_EAX );
nkeynes@586
  1350
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1351
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1352
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1353
    store_reg( R_EAX, Rn );
nkeynes@417
  1354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1355
:}
nkeynes@361
  1356
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1357
    load_reg( R_EAX, 0 );
nkeynes@361
  1358
    load_reg( R_ECX, Rm );
nkeynes@586
  1359
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1360
    check_ralign16( R_EAX );
nkeynes@586
  1361
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1362
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1363
    store_reg( R_EAX, Rn );
nkeynes@417
  1364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1365
:}
nkeynes@361
  1366
MOV.W @(disp, GBR), R0 {:  
nkeynes@586
  1367
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1368
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1369
    check_ralign16( R_EAX );
nkeynes@586
  1370
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1371
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1372
    store_reg( R_EAX, 0 );
nkeynes@417
  1373
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1374
:}
nkeynes@361
  1375
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1376
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1377
	SLOTILLEGAL();
nkeynes@374
  1378
    } else {
nkeynes@586
  1379
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1380
	uint32_t target = pc + disp + 4;
nkeynes@586
  1381
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1382
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1383
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1384
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1385
	} else {
nkeynes@586
  1386
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1387
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1388
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1389
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1390
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1391
	}
nkeynes@374
  1392
	store_reg( R_EAX, Rn );
nkeynes@374
  1393
    }
nkeynes@361
  1394
:}
nkeynes@361
  1395
MOV.W @(disp, Rm), R0 {:  
nkeynes@586
  1396
    load_reg( R_EAX, Rm );
nkeynes@586
  1397
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1398
    check_ralign16( R_EAX );
nkeynes@586
  1399
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1400
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1401
    store_reg( R_EAX, 0 );
nkeynes@417
  1402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1403
:}
nkeynes@361
  1404
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1405
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1406
	SLOTILLEGAL();
nkeynes@374
  1407
    } else {
nkeynes@586
  1408
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1409
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1410
	store_reg( R_ECX, 0 );
nkeynes@586
  1411
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1412
    }
nkeynes@361
  1413
:}
nkeynes@361
  1414
MOVCA.L R0, @Rn {:  
nkeynes@586
  1415
    load_reg( R_EAX, Rn );
nkeynes@586
  1416
    check_walign32( R_EAX );
nkeynes@586
  1417
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1418
    load_reg( R_EDX, 0 );
nkeynes@586
  1419
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1420
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1421
:}
nkeynes@359
  1422
nkeynes@359
  1423
/* Control transfer instructions */
nkeynes@374
  1424
BF disp {:
nkeynes@374
  1425
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1426
	SLOTILLEGAL();
nkeynes@374
  1427
    } else {
nkeynes@586
  1428
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1429
	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1430
	exit_block_rel(target, pc+2 );
nkeynes@380
  1431
	JMP_TARGET(nottaken);
nkeynes@408
  1432
	return 2;
nkeynes@374
  1433
    }
nkeynes@374
  1434
:}
nkeynes@374
  1435
BF/S disp {:
nkeynes@374
  1436
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1437
	SLOTILLEGAL();
nkeynes@374
  1438
    } else {
nkeynes@590
  1439
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1440
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1441
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601
  1442
	    JT_rel8(6,nottaken);
nkeynes@601
  1443
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1444
	    JMP_TARGET(nottaken);
nkeynes@601
  1445
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1446
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1447
	    exit_block_emu(pc+2);
nkeynes@601
  1448
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1449
	    return 2;
nkeynes@601
  1450
	} else {
nkeynes@601
  1451
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1452
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1453
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1454
	    }
nkeynes@601
  1455
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1456
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  1457
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1458
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1459
	    
nkeynes@601
  1460
	    // not taken
nkeynes@601
  1461
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1462
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1463
	    return 4;
nkeynes@417
  1464
	}
nkeynes@374
  1465
    }
nkeynes@374
  1466
:}
nkeynes@374
  1467
BRA disp {:  
nkeynes@374
  1468
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1469
	SLOTILLEGAL();
nkeynes@374
  1470
    } else {
nkeynes@590
  1471
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1472
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1473
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1474
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1475
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1476
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1477
	    exit_block_emu(pc+2);
nkeynes@601
  1478
	    return 2;
nkeynes@601
  1479
	} else {
nkeynes@601
  1480
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1481
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1482
	    return 4;
nkeynes@601
  1483
	}
nkeynes@374
  1484
    }
nkeynes@374
  1485
:}
nkeynes@374
  1486
BRAF Rn {:  
nkeynes@374
  1487
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1488
	SLOTILLEGAL();
nkeynes@374
  1489
    } else {
nkeynes@590
  1490
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1491
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1492
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1493
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1494
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1495
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1496
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1497
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1498
	    exit_block_emu(pc+2);
nkeynes@601
  1499
	    return 2;
nkeynes@601
  1500
	} else {
nkeynes@601
  1501
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1502
	    exit_block_newpcset(pc+2);
nkeynes@601
  1503
	    return 4;
nkeynes@601
  1504
	}
nkeynes@374
  1505
    }
nkeynes@374
  1506
:}
nkeynes@374
  1507
BSR disp {:  
nkeynes@374
  1508
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1509
	SLOTILLEGAL();
nkeynes@374
  1510
    } else {
nkeynes@590
  1511
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1512
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1513
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1514
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1515
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1516
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1517
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1518
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1519
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1520
	    exit_block_emu(pc+2);
nkeynes@601
  1521
	    return 2;
nkeynes@601
  1522
	} else {
nkeynes@601
  1523
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1524
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1525
	    return 4;
nkeynes@601
  1526
	}
nkeynes@374
  1527
    }
nkeynes@374
  1528
:}
nkeynes@374
  1529
BSRF Rn {:  
nkeynes@374
  1530
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1531
	SLOTILLEGAL();
nkeynes@374
  1532
    } else {
nkeynes@590
  1533
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1534
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1535
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1536
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1537
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1538
nkeynes@601
  1539
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1540
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1541
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1542
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1543
	    exit_block_emu(pc+2);
nkeynes@601
  1544
	    return 2;
nkeynes@601
  1545
	} else {
nkeynes@601
  1546
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1547
	    exit_block_newpcset(pc+2);
nkeynes@601
  1548
	    return 4;
nkeynes@601
  1549
	}
nkeynes@374
  1550
    }
nkeynes@374
  1551
:}
nkeynes@374
  1552
BT disp {:
nkeynes@374
  1553
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1554
	SLOTILLEGAL();
nkeynes@374
  1555
    } else {
nkeynes@586
  1556
	sh4vma_t target = disp + pc + 4;
nkeynes@586
  1557
	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
nkeynes@586
  1558
	exit_block_rel(target, pc+2 );
nkeynes@380
  1559
	JMP_TARGET(nottaken);
nkeynes@408
  1560
	return 2;
nkeynes@374
  1561
    }
nkeynes@374
  1562
:}
nkeynes@374
  1563
BT/S disp {:
nkeynes@374
  1564
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1565
	SLOTILLEGAL();
nkeynes@374
  1566
    } else {
nkeynes@590
  1567
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1568
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1569
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@601
  1570
	    JF_rel8(6,nottaken);
nkeynes@601
  1571
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1572
	    JMP_TARGET(nottaken);
nkeynes@601
  1573
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1574
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1575
	    exit_block_emu(pc+2);
nkeynes@601
  1576
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1577
	    return 2;
nkeynes@601
  1578
	} else {
nkeynes@601
  1579
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1580
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1581
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1582
	    }
nkeynes@601
  1583
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  1584
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1585
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1586
	    // not taken
nkeynes@601
  1587
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1588
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1589
	    return 4;
nkeynes@417
  1590
	}
nkeynes@374
  1591
    }
nkeynes@374
  1592
:}
nkeynes@374
  1593
JMP @Rn {:  
nkeynes@374
  1594
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1595
	SLOTILLEGAL();
nkeynes@374
  1596
    } else {
nkeynes@408
  1597
	load_reg( R_ECX, Rn );
nkeynes@590
  1598
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1599
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1600
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1601
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1602
	    exit_block_emu(pc+2);
nkeynes@601
  1603
	    return 2;
nkeynes@601
  1604
	} else {
nkeynes@601
  1605
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1606
	    exit_block_newpcset(pc+2);
nkeynes@601
  1607
	    return 4;
nkeynes@601
  1608
	}
nkeynes@374
  1609
    }
nkeynes@374
  1610
:}
nkeynes@374
  1611
JSR @Rn {:  
nkeynes@374
  1612
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1613
	SLOTILLEGAL();
nkeynes@374
  1614
    } else {
nkeynes@590
  1615
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1616
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1617
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1618
	load_reg( R_ECX, Rn );
nkeynes@590
  1619
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1620
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1621
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1622
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1623
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1624
	    exit_block_emu(pc+2);
nkeynes@601
  1625
	    return 2;
nkeynes@601
  1626
	} else {
nkeynes@601
  1627
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1628
	    exit_block_newpcset(pc+2);
nkeynes@601
  1629
	    return 4;
nkeynes@601
  1630
	}
nkeynes@374
  1631
    }
nkeynes@374
  1632
:}
nkeynes@374
  1633
RTE {:  
nkeynes@374
  1634
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1635
	SLOTILLEGAL();
nkeynes@374
  1636
    } else {
nkeynes@408
  1637
	check_priv();
nkeynes@408
  1638
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1639
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1640
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1641
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1642
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1643
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1644
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1645
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1646
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1647
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1648
	    exit_block_emu(pc+2);
nkeynes@601
  1649
	    return 2;
nkeynes@601
  1650
	} else {
nkeynes@601
  1651
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1652
	    exit_block_newpcset(pc+2);
nkeynes@601
  1653
	    return 4;
nkeynes@601
  1654
	}
nkeynes@374
  1655
    }
nkeynes@374
  1656
:}
nkeynes@374
  1657
RTS {:  
nkeynes@374
  1658
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1659
	SLOTILLEGAL();
nkeynes@374
  1660
    } else {
nkeynes@408
  1661
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1662
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1663
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1664
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1665
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1666
	    exit_block_emu(pc+2);
nkeynes@601
  1667
	    return 2;
nkeynes@601
  1668
	} else {
nkeynes@601
  1669
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1670
	    exit_block_newpcset(pc+2);
nkeynes@601
  1671
	    return 4;
nkeynes@601
  1672
	}
nkeynes@374
  1673
    }
nkeynes@374
  1674
:}
nkeynes@374
  1675
TRAPA #imm {:  
nkeynes@374
  1676
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1677
	SLOTILLEGAL();
nkeynes@374
  1678
    } else {
nkeynes@590
  1679
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1680
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1681
	load_imm32( R_EAX, imm );
nkeynes@527
  1682
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1683
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1684
	exit_block_pcset(pc);
nkeynes@409
  1685
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1686
	return 2;
nkeynes@374
  1687
    }
nkeynes@374
  1688
:}
nkeynes@374
  1689
UNDEF {:  
nkeynes@374
  1690
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1691
	SLOTILLEGAL();
nkeynes@374
  1692
    } else {
nkeynes@586
  1693
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1694
	return 2;
nkeynes@374
  1695
    }
nkeynes@368
  1696
:}
nkeynes@374
  1697
nkeynes@374
  1698
CLRMAC {:  
nkeynes@374
  1699
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1700
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1701
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1702
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1703
:}
nkeynes@374
  1704
CLRS {:
nkeynes@374
  1705
    CLC();
nkeynes@374
  1706
    SETC_sh4r(R_S);
nkeynes@417
  1707
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1708
:}
nkeynes@374
  1709
CLRT {:  
nkeynes@374
  1710
    CLC();
nkeynes@374
  1711
    SETC_t();
nkeynes@417
  1712
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1713
:}
nkeynes@374
  1714
SETS {:  
nkeynes@374
  1715
    STC();
nkeynes@374
  1716
    SETC_sh4r(R_S);
nkeynes@417
  1717
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1718
:}
nkeynes@374
  1719
SETT {:  
nkeynes@374
  1720
    STC();
nkeynes@374
  1721
    SETC_t();
nkeynes@417
  1722
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1723
:}
nkeynes@359
  1724
nkeynes@375
  1725
/* Floating point moves */
nkeynes@375
  1726
FMOV FRm, FRn {:  
nkeynes@375
  1727
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1728
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1729
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1730
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1731
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1732
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1733
     */
nkeynes@377
  1734
    check_fpuen();
nkeynes@375
  1735
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1736
    load_fr_bank( R_EDX );
nkeynes@375
  1737
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1738
    JNE_rel8(8, doublesize);
nkeynes@375
  1739
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1740
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1741
    if( FRm&1 ) {
nkeynes@386
  1742
	JMP_rel8(24, end);
nkeynes@380
  1743
	JMP_TARGET(doublesize);
nkeynes@375
  1744
	load_xf_bank( R_ECX ); 
nkeynes@375
  1745
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1746
	if( FRn&1 ) {
nkeynes@375
  1747
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1748
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1749
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1750
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1751
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@388
  1752
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@388
  1753
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1754
	}
nkeynes@380
  1755
	JMP_TARGET(end);
nkeynes@375
  1756
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1757
	if( FRn&1 ) {
nkeynes@386
  1758
	    JMP_rel8(24, end);
nkeynes@375
  1759
	    load_xf_bank( R_ECX );
nkeynes@375
  1760
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1761
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1762
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1763
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1764
	    JMP_TARGET(end);
nkeynes@375
  1765
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1766
	    JMP_rel8(12, end);
nkeynes@375
  1767
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1768
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1769
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1770
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1771
	    JMP_TARGET(end);
nkeynes@375
  1772
	}
nkeynes@375
  1773
    }
nkeynes@417
  1774
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1775
:}
nkeynes@416
  1776
FMOV FRm, @Rn {: 
nkeynes@586
  1777
    check_fpuen();
nkeynes@586
  1778
    load_reg( R_EAX, Rn );
nkeynes@586
  1779
    check_walign32( R_EAX );
nkeynes@586
  1780
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1781
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1782
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1783
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1784
    load_fr_bank( R_EDX );
nkeynes@586
  1785
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1786
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@375
  1787
    if( FRm&1 ) {
nkeynes@527
  1788
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1789
	JMP_TARGET(doublesize);
nkeynes@416
  1790
	load_xf_bank( R_EDX );
nkeynes@586
  1791
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1792
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1793
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1794
	JMP_TARGET(end);
nkeynes@375
  1795
    } else {
nkeynes@527
  1796
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1797
	JMP_TARGET(doublesize);
nkeynes@416
  1798
	load_fr_bank( R_EDX );
nkeynes@586
  1799
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1800
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1801
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1802
	JMP_TARGET(end);
nkeynes@375
  1803
    }
nkeynes@417
  1804
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1805
:}
nkeynes@375
  1806
FMOV @Rm, FRn {:  
nkeynes@586
  1807
    check_fpuen();
nkeynes@586
  1808
    load_reg( R_EAX, Rm );
nkeynes@586
  1809
    check_ralign32( R_EAX );
nkeynes@586
  1810
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1811
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1812
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1813
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1814
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1815
    load_fr_bank( R_EDX );
nkeynes@416
  1816
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1817
    if( FRn&1 ) {
nkeynes@527
  1818
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1819
	JMP_TARGET(doublesize);
nkeynes@586
  1820
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1821
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1822
	load_xf_bank( R_EDX );
nkeynes@586
  1823
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1824
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1825
	JMP_TARGET(end);
nkeynes@375
  1826
    } else {
nkeynes@527
  1827
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1828
	JMP_TARGET(doublesize);
nkeynes@586
  1829
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1830
	load_fr_bank( R_EDX );
nkeynes@586
  1831
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1832
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1833
	JMP_TARGET(end);
nkeynes@375
  1834
    }
nkeynes@417
  1835
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1836
:}
nkeynes@377
  1837
FMOV FRm, @-Rn {:  
nkeynes@586
  1838
    check_fpuen();
nkeynes@586
  1839
    load_reg( R_EAX, Rn );
nkeynes@586
  1840
    check_walign32( R_EAX );
nkeynes@416
  1841
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1842
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1843
    JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
nkeynes@586
  1844
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1845
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1846
    load_fr_bank( R_EDX );
nkeynes@586
  1847
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1848
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@586
  1849
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1850
    if( FRm&1 ) {
nkeynes@586
  1851
	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1852
	JMP_TARGET(doublesize);
nkeynes@586
  1853
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1854
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1855
	load_xf_bank( R_EDX );
nkeynes@586
  1856
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1857
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1858
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1859
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1860
	JMP_TARGET(end);
nkeynes@377
  1861
    } else {
nkeynes@586
  1862
	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
nkeynes@380
  1863
	JMP_TARGET(doublesize);
nkeynes@586
  1864
	ADD_imm8s_r32(-8,R_EAX);
nkeynes@586
  1865
	MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1866
	load_fr_bank( R_EDX );
nkeynes@586
  1867
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1868
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1869
	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@586
  1870
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1871
	JMP_TARGET(end);
nkeynes@377
  1872
    }
nkeynes@417
  1873
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1874
:}
nkeynes@416
  1875
FMOV @Rm+, FRn {:
nkeynes@586
  1876
    check_fpuen();
nkeynes@586
  1877
    load_reg( R_EAX, Rm );
nkeynes@586
  1878
    check_ralign32( R_EAX );
nkeynes@586
  1879
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1880
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1881
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1882
    JNE_rel8(12 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1883
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1884
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1885
    load_fr_bank( R_EDX );
nkeynes@416
  1886
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1887
    if( FRn&1 ) {
nkeynes@586
  1888
	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1889
	JMP_TARGET(doublesize);
nkeynes@586
  1890
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1891
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1892
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1893
	load_xf_bank( R_EDX );
nkeynes@586
  1894
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1895
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1896
	JMP_TARGET(end);
nkeynes@377
  1897
    } else {
nkeynes@586
  1898
	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@586
  1899
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@586
  1900
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1901
	load_fr_bank( R_EDX );
nkeynes@586
  1902
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1903
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1904
	JMP_TARGET(end);
nkeynes@377
  1905
    }
nkeynes@417
  1906
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1907
:}
nkeynes@377
  1908
FMOV FRm, @(R0, Rn) {:  
nkeynes@586
  1909
    check_fpuen();
nkeynes@586
  1910
    load_reg( R_EAX, Rn );
nkeynes@586
  1911
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1912
    check_walign32( R_EAX );
nkeynes@586
  1913
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@416
  1914
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1915
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1916
    JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
nkeynes@416
  1917
    load_fr_bank( R_EDX );
nkeynes@586
  1918
    load_fr( R_EDX, R_ECX, FRm );
nkeynes@586
  1919
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@377
  1920
    if( FRm&1 ) {
nkeynes@527
  1921
	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1922
	JMP_TARGET(doublesize);
nkeynes@416
  1923
	load_xf_bank( R_EDX );
nkeynes@586
  1924
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1925
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1926
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1927
	JMP_TARGET(end);
nkeynes@377
  1928
    } else {
nkeynes@527
  1929
	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
nkeynes@380
  1930
	JMP_TARGET(doublesize);
nkeynes@416
  1931
	load_fr_bank( R_EDX );
nkeynes@586
  1932
	load_fr( R_EDX, R_ECX, FRm&0x0E );
nkeynes@416
  1933
	load_fr( R_EDX, R_EDX, FRm|0x01 );
nkeynes@586
  1934
	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@380
  1935
	JMP_TARGET(end);
nkeynes@377
  1936
    }
nkeynes@417
  1937
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1938
:}
nkeynes@377
  1939
FMOV @(R0, Rm), FRn {:  
nkeynes@586
  1940
    check_fpuen();
nkeynes@586
  1941
    load_reg( R_EAX, Rm );
nkeynes@586
  1942
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@586
  1943
    check_ralign32( R_EAX );
nkeynes@586
  1944
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@416
  1945
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1946
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@586
  1947
    JNE_rel8(8 + MEM_READ_SIZE, doublesize);
nkeynes@586
  1948
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@416
  1949
    load_fr_bank( R_EDX );
nkeynes@416
  1950
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@377
  1951
    if( FRn&1 ) {
nkeynes@527
  1952
	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1953
	JMP_TARGET(doublesize);
nkeynes@586
  1954
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1955
	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
nkeynes@416
  1956
	load_xf_bank( R_EDX );
nkeynes@586
  1957
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1958
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1959
	JMP_TARGET(end);
nkeynes@377
  1960
    } else {
nkeynes@527
  1961
	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
nkeynes@380
  1962
	JMP_TARGET(doublesize);
nkeynes@586
  1963
	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@416
  1964
	load_fr_bank( R_EDX );
nkeynes@586
  1965
	store_fr( R_EDX, R_ECX, FRn&0x0E );
nkeynes@586
  1966
	store_fr( R_EDX, R_EAX, FRn|0x01 );
nkeynes@380
  1967
	JMP_TARGET(end);
nkeynes@377
  1968
    }
nkeynes@417
  1969
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1970
:}
nkeynes@377
  1971
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1972
    check_fpuen();
nkeynes@377
  1973
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1974
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1975
    JNE_rel8(8, end);
nkeynes@377
  1976
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1977
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1978
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1979
    JMP_TARGET(end);
nkeynes@417
  1980
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1981
:}
nkeynes@377
  1982
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1983
    check_fpuen();
nkeynes@377
  1984
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1985
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1986
    JNE_rel8(11, end);
nkeynes@377
  1987
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1988
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1989
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1990
    JMP_TARGET(end);
nkeynes@417
  1991
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1992
:}
nkeynes@377
  1993
nkeynes@377
  1994
FLOAT FPUL, FRn {:  
nkeynes@377
  1995
    check_fpuen();
nkeynes@377
  1996
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1997
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1998
    FILD_sh4r(R_FPUL);
nkeynes@377
  1999
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2000
    JNE_rel8(5, doubleprec);
nkeynes@377
  2001
    pop_fr( R_EDX, FRn );
nkeynes@380
  2002
    JMP_rel8(3, end);
nkeynes@380
  2003
    JMP_TARGET(doubleprec);
nkeynes@377
  2004
    pop_dr( R_EDX, FRn );
nkeynes@380
  2005
    JMP_TARGET(end);
nkeynes@417
  2006
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2007
:}
nkeynes@377
  2008
FTRC FRm, FPUL {:  
nkeynes@377
  2009
    check_fpuen();
nkeynes@388
  2010
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2011
    load_fr_bank( R_EDX );
nkeynes@388
  2012
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2013
    JNE_rel8(5, doubleprec);
nkeynes@388
  2014
    push_fr( R_EDX, FRm );
nkeynes@388
  2015
    JMP_rel8(3, doop);
nkeynes@388
  2016
    JMP_TARGET(doubleprec);
nkeynes@388
  2017
    push_dr( R_EDX, FRm );
nkeynes@388
  2018
    JMP_TARGET( doop );
nkeynes@388
  2019
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  2020
    FILD_r32ind( R_ECX );
nkeynes@388
  2021
    FCOMIP_st(1);
nkeynes@394
  2022
    JNA_rel8( 32, sat );
nkeynes@388
  2023
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  2024
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2025
    FCOMIP_st(1);                   // 2
nkeynes@394
  2026
    JAE_rel8( 21, sat2 );            // 2
nkeynes@394
  2027
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  2028
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  2029
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  2030
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2031
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2032
    FLDCW_r32ind( R_EAX );
nkeynes@388
  2033
    JMP_rel8( 9, end );             // 2
nkeynes@388
  2034
nkeynes@388
  2035
    JMP_TARGET(sat);
nkeynes@388
  2036
    JMP_TARGET(sat2);
nkeynes@388
  2037
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2038
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2039
    FPOP_st();
nkeynes@388
  2040
    JMP_TARGET(end);
nkeynes@417
  2041
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2042
:}
nkeynes@377
  2043
FLDS FRm, FPUL {:  
nkeynes@377
  2044
    check_fpuen();
nkeynes@377
  2045
    load_fr_bank( R_ECX );
nkeynes@377
  2046
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2047
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2048
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2049
:}
nkeynes@377
  2050
FSTS FPUL, FRn {:  
nkeynes@377
  2051
    check_fpuen();
nkeynes@377
  2052
    load_fr_bank( R_ECX );
nkeynes@377
  2053
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  2054
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@417
  2055
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2056
:}
nkeynes@377
  2057
FCNVDS FRm, FPUL {:  
nkeynes@377
  2058
    check_fpuen();
nkeynes@377
  2059
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2060
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2061
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2062
    load_fr_bank( R_ECX );
nkeynes@377
  2063
    push_dr( R_ECX, FRm );
nkeynes@377
  2064
    pop_fpul();
nkeynes@380
  2065
    JMP_TARGET(end);
nkeynes@417
  2066
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2067
:}
nkeynes@377
  2068
FCNVSD FPUL, FRn {:  
nkeynes@377
  2069
    check_fpuen();
nkeynes@377
  2070
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2071
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2072
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  2073
    load_fr_bank( R_ECX );
nkeynes@377
  2074
    push_fpul();
nkeynes@377
  2075
    pop_dr( R_ECX, FRn );
nkeynes@380
  2076
    JMP_TARGET(end);
nkeynes@417
  2077
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2078
:}
nkeynes@375
  2079
nkeynes@359
  2080
/* Floating point instructions */
nkeynes@374
  2081
FABS FRn {:  
nkeynes@377
  2082
    check_fpuen();
nkeynes@374
  2083
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2084
    load_fr_bank( R_EDX );
nkeynes@374
  2085
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2086
    JNE_rel8(10, doubleprec);
nkeynes@374
  2087
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  2088
    FABS_st0(); // 2
nkeynes@374
  2089
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  2090
    JMP_rel8(8,end); // 2
nkeynes@380
  2091
    JMP_TARGET(doubleprec);
nkeynes@374
  2092
    push_dr(R_EDX, FRn);
nkeynes@374
  2093
    FABS_st0();
nkeynes@374
  2094
    pop_dr(R_EDX, FRn);
nkeynes@380
  2095
    JMP_TARGET(end);
nkeynes@417
  2096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2097
:}
nkeynes@377
  2098
FADD FRm, FRn {:  
nkeynes@377
  2099
    check_fpuen();
nkeynes@375
  2100
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2101
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2102
    load_fr_bank( R_EDX );
nkeynes@380
  2103
    JNE_rel8(13,doubleprec);
nkeynes@377
  2104
    push_fr(R_EDX, FRm);
nkeynes@377
  2105
    push_fr(R_EDX, FRn);
nkeynes@377
  2106
    FADDP_st(1);
nkeynes@377
  2107
    pop_fr(R_EDX, FRn);
nkeynes@380
  2108
    JMP_rel8(11,end);
nkeynes@380
  2109
    JMP_TARGET(doubleprec);
nkeynes@377
  2110
    push_dr(R_EDX, FRm);
nkeynes@377
  2111
    push_dr(R_EDX, FRn);
nkeynes@377
  2112
    FADDP_st(1);
nkeynes@377
  2113
    pop_dr(R_EDX, FRn);
nkeynes@380
  2114
    JMP_TARGET(end);
nkeynes@417
  2115
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2116
:}
nkeynes@377
  2117
FDIV FRm, FRn {:  
nkeynes@377
  2118
    check_fpuen();
nkeynes@375
  2119
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2120
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2121
    load_fr_bank( R_EDX );
nkeynes@380
  2122
    JNE_rel8(13, doubleprec);
nkeynes@377
  2123
    push_fr(R_EDX, FRn);
nkeynes@377
  2124
    push_fr(R_EDX, FRm);
nkeynes@377
  2125
    FDIVP_st(1);
nkeynes@377
  2126
    pop_fr(R_EDX, FRn);
nkeynes@380
  2127
    JMP_rel8(11, end);
nkeynes@380
  2128
    JMP_TARGET(doubleprec);
nkeynes@377
  2129
    push_dr(R_EDX, FRn);
nkeynes@377
  2130
    push_dr(R_EDX, FRm);
nkeynes@377
  2131
    FDIVP_st(1);
nkeynes@377
  2132
    pop_dr(R_EDX, FRn);
nkeynes@380
  2133
    JMP_TARGET(end);
nkeynes@417
  2134
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2135
:}
nkeynes@375
  2136
FMAC FR0, FRm, FRn {:  
nkeynes@377
  2137
    check_fpuen();
nkeynes@375
  2138
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2139
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  2140
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  2141
    JNE_rel8(18, doubleprec);
nkeynes@375
  2142
    push_fr( R_EDX, 0 );
nkeynes@375
  2143
    push_fr( R_EDX, FRm );
nkeynes@375
  2144
    FMULP_st(1);
nkeynes@375
  2145
    push_fr( R_EDX, FRn );
nkeynes@375
  2146
    FADDP_st(1);
nkeynes@375
  2147
    pop_fr( R_EDX, FRn );
nkeynes@380
  2148
    JMP_rel8(16, end);
nkeynes@380
  2149
    JMP_TARGET(doubleprec);
nkeynes@375
  2150
    push_dr( R_EDX, 0 );
nkeynes@375
  2151
    push_dr( R_EDX, FRm );
nkeynes@375
  2152
    FMULP_st(1);
nkeynes@375
  2153
    push_dr( R_EDX, FRn );
nkeynes@375
  2154
    FADDP_st(1);
nkeynes@375
  2155
    pop_dr( R_EDX, FRn );
nkeynes@380
  2156
    JMP_TARGET(end);
nkeynes@417
  2157
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2158
:}
nkeynes@375
  2159
nkeynes@377
  2160
FMUL FRm, FRn {:  
nkeynes@377
  2161
    check_fpuen();
nkeynes@377
  2162
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2163
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2164
    load_fr_bank( R_EDX );
nkeynes@380
  2165
    JNE_rel8(13, doubleprec);
nkeynes@377
  2166
    push_fr(R_EDX, FRm);
nkeynes@377
  2167
    push_fr(R_EDX, FRn);
nkeynes@377
  2168
    FMULP_st(1);
nkeynes@377
  2169
    pop_fr(R_EDX, FRn);
nkeynes@380
  2170
    JMP_rel8(11, end);
nkeynes@380
  2171
    JMP_TARGET(doubleprec);
nkeynes@377
  2172
    push_dr(R_EDX, FRm);
nkeynes@377
  2173
    push_dr(R_EDX, FRn);
nkeynes@377
  2174
    FMULP_st(1);
nkeynes@377
  2175
    pop_dr(R_EDX, FRn);
nkeynes@380
  2176
    JMP_TARGET(end);
nkeynes@417
  2177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2178
:}
nkeynes@377
  2179
FNEG FRn {:  
nkeynes@377
  2180
    check_fpuen();
nkeynes@377
  2181
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2182
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2183
    load_fr_bank( R_EDX );
nkeynes@380
  2184
    JNE_rel8(10, doubleprec);
nkeynes@377
  2185
    push_fr(R_EDX, FRn);
nkeynes@377
  2186
    FCHS_st0();
nkeynes@377
  2187
    pop_fr(R_EDX, FRn);
nkeynes@380
  2188
    JMP_rel8(8, end);
nkeynes@380
  2189
    JMP_TARGET(doubleprec);
nkeynes@377
  2190
    push_dr(R_EDX, FRn);
nkeynes@377
  2191
    FCHS_st0();
nkeynes@377
  2192
    pop_dr(R_EDX, FRn);
nkeynes@380
  2193
    JMP_TARGET(end);
nkeynes@417
  2194
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2195
:}
nkeynes@377
  2196
FSRRA FRn {:  
nkeynes@377
  2197
    check_fpuen();
nkeynes@377
  2198
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2199
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2200
    load_fr_bank( R_EDX );
nkeynes@380
  2201
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  2202
    FLD1_st0();
nkeynes@377
  2203
    push_fr(R_EDX, FRn);
nkeynes@377
  2204
    FSQRT_st0();
nkeynes@377
  2205
    FDIVP_st(1);
nkeynes@377
  2206
    pop_fr(R_EDX, FRn);
nkeynes@380
  2207
    JMP_TARGET(end);
nkeynes@417
  2208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2209
:}
nkeynes@377
  2210
FSQRT FRn {:  
nkeynes@377
  2211
    check_fpuen();
nkeynes@377
  2212
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2213
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2214
    load_fr_bank( R_EDX );
nkeynes@380
  2215
    JNE_rel8(10, doubleprec);
nkeynes@377
  2216
    push_fr(R_EDX, FRn);
nkeynes@377
  2217
    FSQRT_st0();
nkeynes@377
  2218
    pop_fr(R_EDX, FRn);
nkeynes@380
  2219
    JMP_rel8(8, end);
nkeynes@380
  2220
    JMP_TARGET(doubleprec);
nkeynes@377
  2221
    push_dr(R_EDX, FRn);
nkeynes@377
  2222
    FSQRT_st0();
nkeynes@377
  2223
    pop_dr(R_EDX, FRn);
nkeynes@380
  2224
    JMP_TARGET(end);
nkeynes@417
  2225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2226
:}
nkeynes@377
  2227
FSUB FRm, FRn {:  
nkeynes@377
  2228
    check_fpuen();
nkeynes@377
  2229
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2230
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2231
    load_fr_bank( R_EDX );
nkeynes@380
  2232
    JNE_rel8(13, doubleprec);
nkeynes@377
  2233
    push_fr(R_EDX, FRn);
nkeynes@377
  2234
    push_fr(R_EDX, FRm);
nkeynes@388
  2235
    FSUBP_st(1);
nkeynes@377
  2236
    pop_fr(R_EDX, FRn);
nkeynes@380
  2237
    JMP_rel8(11, end);
nkeynes@380
  2238
    JMP_TARGET(doubleprec);
nkeynes@377
  2239
    push_dr(R_EDX, FRn);
nkeynes@377
  2240
    push_dr(R_EDX, FRm);
nkeynes@388
  2241
    FSUBP_st(1);
nkeynes@377
  2242
    pop_dr(R_EDX, FRn);
nkeynes@380
  2243
    JMP_TARGET(end);
nkeynes@417
  2244
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2245
:}
nkeynes@377
  2246
nkeynes@377
  2247
FCMP/EQ FRm, FRn {:  
nkeynes@377
  2248
    check_fpuen();
nkeynes@377
  2249
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2250
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2251
    load_fr_bank( R_EDX );
nkeynes@380
  2252
    JNE_rel8(8, doubleprec);
nkeynes@377
  2253
    push_fr(R_EDX, FRm);
nkeynes@377
  2254
    push_fr(R_EDX, FRn);
nkeynes@380
  2255
    JMP_rel8(6, end);
nkeynes@380
  2256
    JMP_TARGET(doubleprec);
nkeynes@377
  2257
    push_dr(R_EDX, FRm);
nkeynes@377
  2258
    push_dr(R_EDX, FRn);
nkeynes@382
  2259
    JMP_TARGET(end);
nkeynes@377
  2260
    FCOMIP_st(1);
nkeynes@377
  2261
    SETE_t();
nkeynes@377
  2262
    FPOP_st();
nkeynes@417
  2263
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2264
:}
nkeynes@377
  2265
FCMP/GT FRm, FRn {:  
nkeynes@377
  2266
    check_fpuen();
nkeynes@377
  2267
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2268
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2269
    load_fr_bank( R_EDX );
nkeynes@380
  2270
    JNE_rel8(8, doubleprec);
nkeynes@377
  2271
    push_fr(R_EDX, FRm);
nkeynes@377
  2272
    push_fr(R_EDX, FRn);
nkeynes@380
  2273
    JMP_rel8(6, end);
nkeynes@380
  2274
    JMP_TARGET(doubleprec);
nkeynes@377
  2275
    push_dr(R_EDX, FRm);
nkeynes@377
  2276
    push_dr(R_EDX, FRn);
nkeynes@380
  2277
    JMP_TARGET(end);
nkeynes@377
  2278
    FCOMIP_st(1);
nkeynes@377
  2279
    SETA_t();
nkeynes@377
  2280
    FPOP_st();
nkeynes@417
  2281
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2282
:}
nkeynes@377
  2283
nkeynes@377
  2284
FSCA FPUL, FRn {:  
nkeynes@377
  2285
    check_fpuen();
nkeynes@388
  2286
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2287
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2288
    JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
nkeynes@388
  2289
    load_fr_bank( R_ECX );
nkeynes@388
  2290
    ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388
  2291
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2292
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2293
    JMP_TARGET(doubleprec);
nkeynes@417
  2294
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2295
:}
nkeynes@377
  2296
FIPR FVm, FVn {:  
nkeynes@377
  2297
    check_fpuen();
nkeynes@388
  2298
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2299
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388
  2300
    JNE_rel8(44, doubleprec);
nkeynes@388
  2301
    
nkeynes@388
  2302
    load_fr_bank( R_ECX );
nkeynes@388
  2303
    push_fr( R_ECX, FVm<<2 );
nkeynes@388
  2304
    push_fr( R_ECX, FVn<<2 );
nkeynes@388
  2305
    FMULP_st(1);
nkeynes@388
  2306
    push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388
  2307
    push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388
  2308
    FMULP_st(1);
nkeynes@388
  2309
    FADDP_st(1);
nkeynes@388
  2310
    push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388
  2311
    push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388
  2312
    FMULP_st(1);
nkeynes@388
  2313
    FADDP_st(1);
nkeynes@388
  2314
    push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388
  2315
    push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2316
    FMULP_st(1);
nkeynes@388
  2317
    FADDP_st(1);
nkeynes@388
  2318
    pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388
  2319
    JMP_TARGET(doubleprec);
nkeynes@417
  2320
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2321
:}
nkeynes@377
  2322
FTRV XMTRX, FVn {:  
nkeynes@377
  2323
    check_fpuen();
nkeynes@388
  2324
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2325
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@527
  2326
    JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
nkeynes@388
  2327
    load_fr_bank( R_EDX );                 // 3
nkeynes@388
  2328
    ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
nkeynes@388
  2329
    load_xf_bank( R_ECX );                 // 12
nkeynes@388
  2330
    call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
nkeynes@388
  2331
    JMP_TARGET(doubleprec);
nkeynes@417
  2332
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2333
:}
nkeynes@377
  2334
nkeynes@377
  2335
FRCHG {:  
nkeynes@377
  2336
    check_fpuen();
nkeynes@377
  2337
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2338
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2339
    store_spreg( R_ECX, R_FPSCR );
nkeynes@386
  2340
    update_fr_bank( R_ECX );
nkeynes@417
  2341
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2342
:}
nkeynes@377
  2343
FSCHG {:  
nkeynes@377
  2344
    check_fpuen();
nkeynes@377
  2345
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2346
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2347
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2348
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2349
:}
nkeynes@359
  2350
nkeynes@359
  2351
/* Processor control instructions */
nkeynes@368
  2352
LDC Rm, SR {:
nkeynes@386
  2353
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2354
	SLOTILLEGAL();
nkeynes@386
  2355
    } else {
nkeynes@386
  2356
	check_priv();
nkeynes@386
  2357
	load_reg( R_EAX, Rm );
nkeynes@386
  2358
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2359
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2360
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2361
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2362
    }
nkeynes@368
  2363
:}
nkeynes@359
  2364
LDC Rm, GBR {: 
nkeynes@359
  2365
    load_reg( R_EAX, Rm );
nkeynes@359
  2366
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2367
:}
nkeynes@359
  2368
LDC Rm, VBR {:  
nkeynes@386
  2369
    check_priv();
nkeynes@359
  2370
    load_reg( R_EAX, Rm );
nkeynes@359
  2371
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2372
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2373
:}
nkeynes@359
  2374
LDC Rm, SSR {:  
nkeynes@386
  2375
    check_priv();
nkeynes@359
  2376
    load_reg( R_EAX, Rm );
nkeynes@359
  2377
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2378
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2379
:}
nkeynes@359
  2380
LDC Rm, SGR {:  
nkeynes@386
  2381
    check_priv();
nkeynes@359
  2382
    load_reg( R_EAX, Rm );
nkeynes@359
  2383
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2384
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2385
:}
nkeynes@359
  2386
LDC Rm, SPC {:  
nkeynes@386
  2387
    check_priv();
nkeynes@359
  2388
    load_reg( R_EAX, Rm );
nkeynes@359
  2389
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2390
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2391
:}
nkeynes@359
  2392
LDC Rm, DBR {:  
nkeynes@386
  2393
    check_priv();
nkeynes@359
  2394
    load_reg( R_EAX, Rm );
nkeynes@359
  2395
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2396
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2397
:}
nkeynes@374
  2398
LDC Rm, Rn_BANK {:  
nkeynes@386
  2399
    check_priv();
nkeynes@374
  2400
    load_reg( R_EAX, Rm );
nkeynes@374
  2401
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2403
:}
nkeynes@359
  2404
LDC.L @Rm+, GBR {:  
nkeynes@359
  2405
    load_reg( R_EAX, Rm );
nkeynes@395
  2406
    check_ralign32( R_EAX );
nkeynes@586
  2407
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2408
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2409
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2410
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2411
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2412
:}
nkeynes@368
  2413
LDC.L @Rm+, SR {:
nkeynes@386
  2414
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2415
	SLOTILLEGAL();
nkeynes@386
  2416
    } else {
nkeynes@586
  2417
	check_priv();
nkeynes@386
  2418
	load_reg( R_EAX, Rm );
nkeynes@395
  2419
	check_ralign32( R_EAX );
nkeynes@586
  2420
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2421
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2422
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2423
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2424
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2425
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2426
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2427
    }
nkeynes@359
  2428
:}
nkeynes@359
  2429
LDC.L @Rm+, VBR {:  
nkeynes@586
  2430
    check_priv();
nkeynes@359
  2431
    load_reg( R_EAX, Rm );
nkeynes@395
  2432
    check_ralign32( R_EAX );
nkeynes@586
  2433
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2434
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2435
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2436
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2437
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2438
:}
nkeynes@359
  2439
LDC.L @Rm+, SSR {:
nkeynes@586
  2440
    check_priv();
nkeynes@359
  2441
    load_reg( R_EAX, Rm );
nkeynes@416
  2442
    check_ralign32( R_EAX );
nkeynes@586
  2443
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2444
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2445
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2446
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2447
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2448
:}
nkeynes@359
  2449
LDC.L @Rm+, SGR {:  
nkeynes@586
  2450
    check_priv();
nkeynes@359
  2451
    load_reg( R_EAX, Rm );
nkeynes@395
  2452
    check_ralign32( R_EAX );
nkeynes@586
  2453
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2454
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2455
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2456
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2457
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2458
:}
nkeynes@359
  2459
LDC.L @Rm+, SPC {:  
nkeynes@586
  2460
    check_priv();
nkeynes@359
  2461
    load_reg( R_EAX, Rm );
nkeynes@395
  2462
    check_ralign32( R_EAX );
nkeynes@586
  2463
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2464
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2465
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2466
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2467
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2468
:}
nkeynes@359
  2469
LDC.L @Rm+, DBR {:  
nkeynes@586
  2470
    check_priv();
nkeynes@359
  2471
    load_reg( R_EAX, Rm );
nkeynes@395
  2472
    check_ralign32( R_EAX );
nkeynes@586
  2473
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2474
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2475
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2476
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2477
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2478
:}
nkeynes@359
  2479
LDC.L @Rm+, Rn_BANK {:  
nkeynes@586
  2480
    check_priv();
nkeynes@374
  2481
    load_reg( R_EAX, Rm );
nkeynes@395
  2482
    check_ralign32( R_EAX );
nkeynes@586
  2483
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2484
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2485
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2486
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2487
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2488
:}
nkeynes@359
  2489
LDS Rm, FPSCR {:  
nkeynes@359
  2490
    load_reg( R_EAX, Rm );
nkeynes@359
  2491
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2492
    update_fr_bank( R_EAX );
nkeynes@417
  2493
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2494
:}
nkeynes@359
  2495
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  2496
    load_reg( R_EAX, Rm );
nkeynes@395
  2497
    check_ralign32( R_EAX );
nkeynes@586
  2498
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2499
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2500
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2501
    store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  2502
    update_fr_bank( R_EAX );
nkeynes@417
  2503
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2504
:}
nkeynes@359
  2505
LDS Rm, FPUL {:  
nkeynes@359
  2506
    load_reg( R_EAX, Rm );
nkeynes@359
  2507
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2508
:}
nkeynes@359
  2509
LDS.L @Rm+, FPUL {:  
nkeynes@359
  2510
    load_reg( R_EAX, Rm );
nkeynes@395
  2511
    check_ralign32( R_EAX );
nkeynes@586
  2512
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2513
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2514
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2515
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2516
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2517
:}
nkeynes@359
  2518
LDS Rm, MACH {: 
nkeynes@359
  2519
    load_reg( R_EAX, Rm );
nkeynes@359
  2520
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2521
:}
nkeynes@359
  2522
LDS.L @Rm+, MACH {:  
nkeynes@359
  2523
    load_reg( R_EAX, Rm );
nkeynes@395
  2524
    check_ralign32( R_EAX );
nkeynes@586
  2525
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2526
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2527
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2528
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2529
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2530
:}
nkeynes@359
  2531
LDS Rm, MACL {:  
nkeynes@359
  2532
    load_reg( R_EAX, Rm );
nkeynes@359
  2533
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2534
:}
nkeynes@359
  2535
LDS.L @Rm+, MACL {:  
nkeynes@359
  2536
    load_reg( R_EAX, Rm );
nkeynes@395
  2537
    check_ralign32( R_EAX );
nkeynes@586
  2538
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2539
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2540
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2541
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2542
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2543
:}
nkeynes@359
  2544
LDS Rm, PR {:  
nkeynes@359
  2545
    load_reg( R_EAX, Rm );
nkeynes@359
  2546
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2547
:}
nkeynes@359
  2548
LDS.L @Rm+, PR {:  
nkeynes@359
  2549
    load_reg( R_EAX, Rm );
nkeynes@395
  2550
    check_ralign32( R_EAX );
nkeynes@586
  2551
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2552
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2553
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2554
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2556
:}
nkeynes@550
  2557
LDTLB {:  
nkeynes@553
  2558
    call_func0( MMU_ldtlb );
nkeynes@550
  2559
:}
nkeynes@359
  2560
OCBI @Rn {:  :}
nkeynes@359
  2561
OCBP @Rn {:  :}
nkeynes@359
  2562
OCBWB @Rn {:  :}
nkeynes@374
  2563
PREF @Rn {:
nkeynes@374
  2564
    load_reg( R_EAX, Rn );
nkeynes@532
  2565
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2566
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2567
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@586
  2568
    JNE_rel8(8+CALL_FUNC1_SIZE, end);
nkeynes@532
  2569
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2570
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2571
    JE_exc(-1);
nkeynes@380
  2572
    JMP_TARGET(end);
nkeynes@417
  2573
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2574
:}
nkeynes@388
  2575
SLEEP {: 
nkeynes@388
  2576
    check_priv();
nkeynes@388
  2577
    call_func0( sh4_sleep );
nkeynes@417
  2578
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2579
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2580
    return 2;
nkeynes@388
  2581
:}
nkeynes@386
  2582
STC SR, Rn {:
nkeynes@386
  2583
    check_priv();
nkeynes@386
  2584
    call_func0(sh4_read_sr);
nkeynes@386
  2585
    store_reg( R_EAX, Rn );
nkeynes@417
  2586
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2587
:}
nkeynes@359
  2588
STC GBR, Rn {:  
nkeynes@359
  2589
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2590
    store_reg( R_EAX, Rn );
nkeynes@359
  2591
:}
nkeynes@359
  2592
STC VBR, Rn {:  
nkeynes@386
  2593
    check_priv();
nkeynes@359
  2594
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2595
    store_reg( R_EAX, Rn );
nkeynes@417
  2596
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2597
:}
nkeynes@359
  2598
STC SSR, Rn {:  
nkeynes@386
  2599
    check_priv();
nkeynes@359
  2600
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2601
    store_reg( R_EAX, Rn );
nkeynes@417
  2602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2603
:}
nkeynes@359
  2604
STC SPC, Rn {:  
nkeynes@386
  2605
    check_priv();
nkeynes@359
  2606
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2607
    store_reg( R_EAX, Rn );
nkeynes@417
  2608
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2609
:}
nkeynes@359
  2610
STC SGR, Rn {:  
nkeynes@386
  2611
    check_priv();
nkeynes@359
  2612
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2613
    store_reg( R_EAX, Rn );
nkeynes@417
  2614
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2615
:}
nkeynes@359
  2616
STC DBR, Rn {:  
nkeynes@386
  2617
    check_priv();
nkeynes@359
  2618
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2619
    store_reg( R_EAX, Rn );
nkeynes@417
  2620
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2621
:}
nkeynes@374
  2622
STC Rm_BANK, Rn {:
nkeynes@386
  2623
    check_priv();
nkeynes@374
  2624
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2625
    store_reg( R_EAX, Rn );
nkeynes@417
  2626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2627
:}
nkeynes@374
  2628
STC.L SR, @-Rn {:
nkeynes@586
  2629
    check_priv();
nkeynes@586
  2630
    load_reg( R_EAX, Rn );
nkeynes@586
  2631
    check_walign32( R_EAX );
nkeynes@586
  2632
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2633
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2634
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2635
    call_func0( sh4_read_sr );
nkeynes@586
  2636
    POP_realigned_r32( R_ECX );
nkeynes@586
  2637
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2638
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2639
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2640
:}
nkeynes@359
  2641
STC.L VBR, @-Rn {:  
nkeynes@586
  2642
    check_priv();
nkeynes@586
  2643
    load_reg( R_EAX, Rn );
nkeynes@586
  2644
    check_walign32( R_EAX );
nkeynes@586
  2645
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2646
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2647
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2648
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2649
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2650
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2651
:}
nkeynes@359
  2652
STC.L SSR, @-Rn {:  
nkeynes@586
  2653
    check_priv();
nkeynes@586
  2654
    load_reg( R_EAX, Rn );
nkeynes@586
  2655
    check_walign32( R_EAX );
nkeynes@586
  2656
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2657
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2658
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2659
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2660
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2661
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2662
:}
nkeynes@416
  2663
STC.L SPC, @-Rn {:
nkeynes@586
  2664
    check_priv();
nkeynes@586
  2665
    load_reg( R_EAX, Rn );
nkeynes@586
  2666
    check_walign32( R_EAX );
nkeynes@586
  2667
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2668
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2669
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2670
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2671
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2672
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2673
:}
nkeynes@359
  2674
STC.L SGR, @-Rn {:  
nkeynes@586
  2675
    check_priv();
nkeynes@586
  2676
    load_reg( R_EAX, Rn );
nkeynes@586
  2677
    check_walign32( R_EAX );
nkeynes@586
  2678
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2679
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2680
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2681
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2682
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2683
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2684
:}
nkeynes@359
  2685
STC.L DBR, @-Rn {:  
nkeynes@586
  2686
    check_priv();
nkeynes@586
  2687
    load_reg( R_EAX, Rn );
nkeynes@586
  2688
    check_walign32( R_EAX );
nkeynes@586
  2689
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2690
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2691
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2692
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2693
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2694
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2695
:}
nkeynes@374
  2696
STC.L Rm_BANK, @-Rn {:  
nkeynes@586
  2697
    check_priv();
nkeynes@586
  2698
    load_reg( R_EAX, Rn );
nkeynes@586
  2699
    check_walign32( R_EAX );
nkeynes@586
  2700
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2701
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2702
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2703
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2704
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2705
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2706
:}
nkeynes@359
  2707
STC.L GBR, @-Rn {:  
nkeynes@586
  2708
    load_reg( R_EAX, Rn );
nkeynes@586
  2709
    check_walign32( R_EAX );
nkeynes@586
  2710
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2711
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2712
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2713
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2714
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2715
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2716
:}
nkeynes@359
  2717
STS FPSCR, Rn {:  
nkeynes@359
  2718
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2719
    store_reg( R_EAX, Rn );
nkeynes@359
  2720
:}
nkeynes@359
  2721
STS.L FPSCR, @-Rn {:  
nkeynes@586
  2722
    load_reg( R_EAX, Rn );
nkeynes@586
  2723
    check_walign32( R_EAX );
nkeynes@586
  2724
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2725
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2726
    load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  2727
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2728
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2729
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2730
:}
nkeynes@359
  2731
STS FPUL, Rn {:  
nkeynes@359
  2732
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2733
    store_reg( R_EAX, Rn );
nkeynes@359
  2734
:}
nkeynes@359
  2735
STS.L FPUL, @-Rn {:  
nkeynes@586
  2736
    load_reg( R_EAX, Rn );
nkeynes@586
  2737
    check_walign32( R_EAX );
nkeynes@586
  2738
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2739
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2740
    load_spreg( R_EDX, R_FPUL );
nkeynes@586
  2741
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2742
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2743
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2744
:}
nkeynes@359
  2745
STS MACH, Rn {:  
nkeynes@359
  2746
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2747
    store_reg( R_EAX, Rn );
nkeynes@359
  2748
:}
nkeynes@359
  2749
STS.L MACH, @-Rn {:  
nkeynes@586
  2750
    load_reg( R_EAX, Rn );
nkeynes@586
  2751
    check_walign32( R_EAX );
nkeynes@586
  2752
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2753
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2754
    load_spreg( R_EDX, R_MACH );
nkeynes@586
  2755
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2756
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2757
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2758
:}
nkeynes@359
  2759
STS MACL, Rn {:  
nkeynes@359
  2760
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2761
    store_reg( R_EAX, Rn );
nkeynes@359
  2762
:}
nkeynes@359
  2763
STS.L MACL, @-Rn {:  
nkeynes@586
  2764
    load_reg( R_EAX, Rn );
nkeynes@586
  2765
    check_walign32( R_EAX );
nkeynes@586
  2766
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2767
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2768
    load_spreg( R_EDX, R_MACL );
nkeynes@586
  2769
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2770
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2771
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2772
:}
nkeynes@359
  2773
STS PR, Rn {:  
nkeynes@359
  2774
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2775
    store_reg( R_EAX, Rn );
nkeynes@359
  2776
:}
nkeynes@359
  2777
STS.L PR, @-Rn {:  
nkeynes@586
  2778
    load_reg( R_EAX, Rn );
nkeynes@586
  2779
    check_walign32( R_EAX );
nkeynes@586
  2780
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2781
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2782
    load_spreg( R_EDX, R_PR );
nkeynes@586
  2783
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2784
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2785
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2786
:}
nkeynes@359