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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 191:df4441cf3128
prev189:615b70cfd729
next193:31151fcc3cb7
author nkeynes
date Wed Aug 02 06:24:08 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add more register masks (in line with test case)
Rename renderer registers for consistency
file annotate diff log raw
nkeynes@31
     1
/**
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 * $Id: pvr2.c,v 1.29 2006-08-02 06:24:08 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    50
    int total_lines;
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    51
    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 32000 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    gboolean retrace;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.retrace = FALSE;
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    pvr2_state.timing = ntsc_timing;
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    return 0;
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_state.line_remainder += nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
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	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
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	pvr2_state.line_count++;
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	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
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	    asic_event( EVENT_RETRACE );
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	    pvr2_state.line_count = 0;
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	    pvr2_state.retrace = TRUE;
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	}
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   120
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	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
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	    asic_event( EVENT_SCANLINE1 );
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	} 
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	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
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	    asic_event( EVENT_SCANLINE2 );
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	}
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	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
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	    if( pvr2_state.retrace ) {
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		pvr2_display_frame();
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		pvr2_state.retrace = FALSE;
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	    }
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	}
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    }
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
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   151
    
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    int dispsize = MMIO_READ( PVR2, DISPSIZE );
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    int dispmode = MMIO_READ( PVR2, DISPMODE );
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    int vidcfg = MMIO_READ( PVR2, DISPCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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	break;
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    case 3: 
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	buffer->colour_format = COLFMT_ARGB8888;
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	buffer->hres = vid_ppl; 
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	break;
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    }
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    if( buffer->hres <=8 )
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	buffer->hres = 640;
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    if( buffer->vres <=8 )
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	buffer->vres = 480;
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    if( display_driver != NULL ) {
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	if( buffer->hres != last->hres ||
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	    buffer->vres != last->vres ||
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	    buffer->colour_format != last->colour_format) {
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	    display_driver->set_display_format( buffer->hres, buffer->vres,
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						buffer->colour_format );
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	}
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	if( !bEnabled ) {
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	    display_driver->display_blank_frame( 0 );
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	} else if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
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	    uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
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	    display_driver->display_blank_frame( colour );
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	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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	    display_driver->display_frame( buffer );
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	}
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    }
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    pvr2_state.frame_count++;
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}
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        /* I don't want to hear about these */
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        return;
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    }
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    switch(reg) {
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    case PVRID:
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    case PVRVER:
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    case GUNPOS:
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    case TA_POLYPOS:
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    case TA_LISTPOS:
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	/* Readonly registers */
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	break;
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    case RENDER_START:
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	if( val == 0xFFFFFFFF )
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	    pvr2_render_scene();
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	break;
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    case PVRUNK1:
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    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
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    	break;
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    case RENDER_POLYBASE:
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    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
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    	break;
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    case RENDER_TSPCFG:
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    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
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    	break;
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   238
    case DISPBORDER:
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    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
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    	break;
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   241
    case DISPMODE:
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   242
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
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    	break;
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   244
    case RENDER_MODE:
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    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
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    	break;
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   247
    case RENDER_SIZE:
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    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
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    	break;
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   250
    case DISPADDR1:
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   251
	val &= 0x00FFFFFC;
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   252
	MMIO_WRITE( PVR2, reg, val );
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   253
	if( pvr2_state.retrace ) {
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   254
	    pvr2_display_frame();
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   255
	    pvr2_state.retrace = FALSE;
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   256
	}
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   257
	break;
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   258
    case DISPADDR2:
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   259
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
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   260
    	break;
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   261
    case DISPSIZE:
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   262
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
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    	break;
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   264
    case RENDER_ADDR1:
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   265
    case RENDER_ADDR2:
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   266
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   267
    	break;
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   268
    case RENDER_HCLIP:
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   269
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   270
	break;
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   271
    case RENDER_VCLIP:
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   272
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   273
	break;
nkeynes@189
   274
    case HPOS_IRQ:
nkeynes@191
   275
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@189
   276
	break;
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   277
    case VPOS_IRQ:
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   278
	val = val & 0x03FF03FF;
nkeynes@189
   279
	pvr2_state.irq_vpos1 = (val >> 16);
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   280
	pvr2_state.irq_vpos2 = val & 0x03FF;
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   281
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   282
	break;
nkeynes@191
   283
    case RENDER_SHADOW:
nkeynes@191
   284
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   285
	break;
nkeynes@191
   286
    case RENDER_OBJCFG:
nkeynes@191
   287
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   288
    	break;
nkeynes@191
   289
    case RENDER_TSPCLIP:
nkeynes@191
   290
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   291
    	break;
nkeynes@191
   292
    case RENDER_BGPLANE:
nkeynes@191
   293
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   294
    	break;
nkeynes@191
   295
    case RENDER_ISPCFG:
nkeynes@191
   296
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   297
    	break;
nkeynes@189
   298
    case TA_TILEBASE:
nkeynes@189
   299
    case TA_TILEEND:
nkeynes@189
   300
    case TA_LISTBASE:
nkeynes@191
   301
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   302
	break;
nkeynes@191
   303
    case RENDER_TILEBASE:
nkeynes@189
   304
    case TA_POLYBASE:
nkeynes@189
   305
    case TA_POLYEND:
nkeynes@191
   306
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   307
	break;
nkeynes@189
   308
    case TA_TILESIZE:
nkeynes@191
   309
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   310
	break;
nkeynes@189
   311
    case TA_TILECFG:
nkeynes@191
   312
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   313
	break;
nkeynes@189
   314
    case TA_INIT:
nkeynes@100
   315
	if( val & 0x80000000 )
nkeynes@100
   316
	    pvr2_ta_init();
nkeynes@100
   317
	break;
nkeynes@189
   318
	
nkeynes@191
   319
    /* Nonexistent registers (as far as we know, anyway) */
nkeynes@191
   320
    case 0x01C:
nkeynes@191
   321
    case 0x024:
nkeynes@191
   322
    case 0x028:
nkeynes@191
   323
    case 0x058:
nkeynes@191
   324
    	break;
nkeynes@189
   325
    default:
nkeynes@189
   326
	MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   327
    }
nkeynes@1
   328
}
nkeynes@1
   329
nkeynes@1
   330
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   331
{
nkeynes@1
   332
    switch( reg ) {
nkeynes@1
   333
        case BEAMPOS:
nkeynes@2
   334
            return sh4r.icount&0x20 ? 0x2000 : 1;
nkeynes@1
   335
        default:
nkeynes@1
   336
            return MMIO_READ( PVR2, reg );
nkeynes@1
   337
    }
nkeynes@1
   338
}
nkeynes@19
   339
nkeynes@85
   340
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   341
nkeynes@19
   342
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   343
{
nkeynes@19
   344
    mmio_region_PVR2_write( DISPADDR1, base );
nkeynes@19
   345
}
nkeynes@56
   346
nkeynes@56
   347
nkeynes@65
   348
nkeynes@98
   349
nkeynes@56
   350
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   351
{
nkeynes@56
   352
    return 0xFFFFFFFF;
nkeynes@56
   353
}
nkeynes@56
   354
nkeynes@56
   355
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   356
{
nkeynes@189
   357
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   358
}
nkeynes@56
   359
nkeynes@85
   360
nkeynes@103
   361
void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
nkeynes@103
   362
{
nkeynes@103
   363
    int bank_flag = (destaddr & 0x04) >> 2;
nkeynes@103
   364
    uint32_t *banks[2];
nkeynes@103
   365
    uint32_t *dwsrc;
nkeynes@103
   366
    int i;
nkeynes@65
   367
nkeynes@103
   368
    destaddr = destaddr & 0x7FFFFF;
nkeynes@103
   369
    if( destaddr + length > 0x800000 ) {
nkeynes@103
   370
	length = 0x800000 - destaddr;
nkeynes@103
   371
    }
nkeynes@103
   372
nkeynes@103
   373
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
nkeynes@103
   374
	texcache_invalidate_page( i );
nkeynes@103
   375
    }
nkeynes@103
   376
nkeynes@108
   377
    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
nkeynes@103
   378
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   379
    if( bank_flag ) 
nkeynes@108
   380
	banks[0]++;
nkeynes@103
   381
    
nkeynes@103
   382
    /* Handle non-aligned start of source */
nkeynes@103
   383
    if( destaddr & 0x03 ) {
nkeynes@103
   384
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
nkeynes@103
   385
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   386
	    *dest++ = *src++;
nkeynes@103
   387
	}
nkeynes@103
   388
	bank_flag = !bank_flag;
nkeynes@103
   389
    }
nkeynes@103
   390
nkeynes@103
   391
    dwsrc = (uint32_t *)src;
nkeynes@103
   392
    while( length >= 4 ) {
nkeynes@103
   393
	*banks[bank_flag]++ = *dwsrc++;
nkeynes@103
   394
	bank_flag = !bank_flag;
nkeynes@103
   395
	length -= 4;
nkeynes@103
   396
    }
nkeynes@103
   397
    
nkeynes@103
   398
    /* Handle non-aligned end of source */
nkeynes@103
   399
    if( length ) {
nkeynes@103
   400
	src = (char *)dwsrc;
nkeynes@103
   401
	char *dest = (char *)banks[bank_flag];
nkeynes@103
   402
	while( length-- > 0 ) {
nkeynes@103
   403
	    *dest++ = *src++;
nkeynes@103
   404
	}
nkeynes@103
   405
    }  
nkeynes@103
   406
nkeynes@103
   407
}
nkeynes@103
   408
nkeynes@103
   409
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   410
{
nkeynes@103
   411
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   412
    uint32_t *banks[2];
nkeynes@103
   413
    uint32_t *dwdest;
nkeynes@103
   414
    int i;
nkeynes@103
   415
nkeynes@103
   416
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   417
    if( srcaddr + length > 0x800000 )
nkeynes@103
   418
	length = 0x800000 - srcaddr;
nkeynes@103
   419
nkeynes@108
   420
    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
nkeynes@103
   421
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   422
    if( bank_flag )
nkeynes@108
   423
	banks[0]++;
nkeynes@103
   424
    
nkeynes@103
   425
    /* Handle non-aligned start of source */
nkeynes@103
   426
    if( srcaddr & 0x03 ) {
nkeynes@103
   427
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   428
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   429
	    *dest++ = *src++;
nkeynes@103
   430
	}
nkeynes@103
   431
	bank_flag = !bank_flag;
nkeynes@103
   432
    }
nkeynes@103
   433
nkeynes@103
   434
    dwdest = (uint32_t *)dest;
nkeynes@103
   435
    while( length >= 4 ) {
nkeynes@103
   436
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   437
	bank_flag = !bank_flag;
nkeynes@103
   438
	length -= 4;
nkeynes@103
   439
    }
nkeynes@103
   440
    
nkeynes@103
   441
    /* Handle non-aligned end of source */
nkeynes@103
   442
    if( length ) {
nkeynes@103
   443
	dest = (char *)dwdest;
nkeynes@103
   444
	char *src = (char *)banks[bank_flag];
nkeynes@103
   445
	while( length-- > 0 ) {
nkeynes@103
   446
	    *dest++ = *src++;
nkeynes@103
   447
	}
nkeynes@103
   448
    }
nkeynes@103
   449
}
nkeynes@127
   450
nkeynes@127
   451
void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
nkeynes@127
   452
{
nkeynes@127
   453
    char tmp[length];
nkeynes@127
   454
    pvr2_vram64_read( tmp, addr, length );
nkeynes@127
   455
    fwrite_dump( tmp, length, f );
nkeynes@127
   456
}
.