nkeynes@359 | 1 | /**
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nkeynes@586 | 2 | * $Id$
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nkeynes@359 | 3 | *
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nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
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nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
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nkeynes@359 | 6 | * to test the optimizing versions against.
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nkeynes@359 | 7 | *
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nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
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nkeynes@359 | 9 | *
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nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@359 | 13 | * (at your option) any later version.
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nkeynes@359 | 14 | *
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nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@359 | 18 | * GNU General Public License for more details.
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nkeynes@359 | 19 | */
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nkeynes@359 | 20 |
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nkeynes@368 | 21 | #include <assert.h>
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nkeynes@388 | 22 | #include <math.h>
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nkeynes@368 | 23 |
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nkeynes@380 | 24 | #ifndef NDEBUG
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nkeynes@380 | 25 | #define DEBUG_JUMPS 1
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nkeynes@380 | 26 | #endif
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nkeynes@380 | 27 |
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nkeynes@417 | 28 | #include "sh4/xltcache.h"
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nkeynes@368 | 29 | #include "sh4/sh4core.h"
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nkeynes@368 | 30 | #include "sh4/sh4trans.h"
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nkeynes@388 | 31 | #include "sh4/sh4mmio.h"
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nkeynes@368 | 32 | #include "sh4/x86op.h"
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nkeynes@368 | 33 | #include "clock.h"
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nkeynes@368 | 34 |
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nkeynes@368 | 35 | #define DEFAULT_BACKPATCH_SIZE 4096
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nkeynes@368 | 36 |
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nkeynes@586 | 37 | struct backpatch_record {
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nkeynes@586 | 38 | uint32_t *fixup_addr;
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nkeynes@586 | 39 | uint32_t fixup_icount;
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nkeynes@596 | 40 | int32_t exc_code;
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nkeynes@586 | 41 | };
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nkeynes@586 | 42 |
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nkeynes@586 | 43 | #define MAX_RECOVERY_SIZE 2048
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nkeynes@586 | 44 |
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nkeynes@590 | 45 | #define DELAY_NONE 0
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nkeynes@590 | 46 | #define DELAY_PC 1
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nkeynes@590 | 47 | #define DELAY_PC_PR 2
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nkeynes@590 | 48 |
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nkeynes@368 | 49 | /**
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nkeynes@368 | 50 | * Struct to manage internal translation state. This state is not saved -
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nkeynes@368 | 51 | * it is only valid between calls to sh4_translate_begin_block() and
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nkeynes@368 | 52 | * sh4_translate_end_block()
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nkeynes@368 | 53 | */
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nkeynes@368 | 54 | struct sh4_x86_state {
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nkeynes@590 | 55 | int in_delay_slot;
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nkeynes@368 | 56 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
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nkeynes@368 | 57 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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nkeynes@409 | 58 | gboolean branch_taken; /* true if we branched unconditionally */
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nkeynes@408 | 59 | uint32_t block_start_pc;
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nkeynes@547 | 60 | uint32_t stack_posn; /* Trace stack height for alignment purposes */
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nkeynes@417 | 61 | int tstate;
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nkeynes@368 | 62 |
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nkeynes@586 | 63 | /* mode flags */
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nkeynes@586 | 64 | gboolean tlb_on; /* True if tlb translation is active */
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nkeynes@586 | 65 |
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nkeynes@368 | 66 | /* Allocated memory for the (block-wide) back-patch list */
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nkeynes@586 | 67 | struct backpatch_record *backpatch_list;
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nkeynes@368 | 68 | uint32_t backpatch_posn;
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nkeynes@368 | 69 | uint32_t backpatch_size;
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nkeynes@368 | 70 | };
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nkeynes@368 | 71 |
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nkeynes@417 | 72 | #define TSTATE_NONE -1
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nkeynes@417 | 73 | #define TSTATE_O 0
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nkeynes@417 | 74 | #define TSTATE_C 2
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nkeynes@417 | 75 | #define TSTATE_E 4
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nkeynes@417 | 76 | #define TSTATE_NE 5
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nkeynes@417 | 77 | #define TSTATE_G 0xF
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nkeynes@417 | 78 | #define TSTATE_GE 0xD
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nkeynes@417 | 79 | #define TSTATE_A 7
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nkeynes@417 | 80 | #define TSTATE_AE 3
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nkeynes@417 | 81 |
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nkeynes@417 | 82 | /** Branch if T is set (either in the current cflags, or in sh4r.t) */
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nkeynes@417 | 83 | #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 84 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@417 | 85 | OP(0x70+sh4_x86.tstate); OP(rel8); \
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nkeynes@417 | 86 | MARK_JMP(rel8,label)
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nkeynes@417 | 87 | /** Branch if T is clear (either in the current cflags or in sh4r.t) */
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nkeynes@417 | 88 | #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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nkeynes@417 | 89 | CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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nkeynes@417 | 90 | OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
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nkeynes@417 | 91 | MARK_JMP(rel8, label)
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nkeynes@417 | 92 |
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nkeynes@368 | 93 | static struct sh4_x86_state sh4_x86;
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nkeynes@368 | 94 |
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nkeynes@388 | 95 | static uint32_t max_int = 0x7FFFFFFF;
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nkeynes@388 | 96 | static uint32_t min_int = 0x80000000;
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nkeynes@394 | 97 | static uint32_t save_fcw; /* save value for fpu control word */
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nkeynes@394 | 98 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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nkeynes@386 | 99 |
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nkeynes@368 | 100 | void sh4_x86_init()
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nkeynes@368 | 101 | {
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nkeynes@368 | 102 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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nkeynes@586 | 103 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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nkeynes@368 | 104 | }
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nkeynes@368 | 105 |
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nkeynes@368 | 106 |
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nkeynes@586 | 107 | static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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nkeynes@368 | 108 | {
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nkeynes@368 | 109 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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nkeynes@368 | 110 | sh4_x86.backpatch_size <<= 1;
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nkeynes@586 | 111 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,
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nkeynes@586 | 112 | sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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nkeynes@368 | 113 | assert( sh4_x86.backpatch_list != NULL );
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nkeynes@368 | 114 | }
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nkeynes@586 | 115 | if( sh4_x86.in_delay_slot ) {
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nkeynes@586 | 116 | fixup_pc -= 2;
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nkeynes@586 | 117 | }
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nkeynes@586 | 118 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
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nkeynes@586 | 119 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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nkeynes@586 | 120 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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nkeynes@586 | 121 | sh4_x86.backpatch_posn++;
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nkeynes@368 | 122 | }
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nkeynes@368 | 123 |
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nkeynes@359 | 124 | /**
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nkeynes@359 | 125 | * Emit an instruction to load an SH4 reg into a real register
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nkeynes@359 | 126 | */
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nkeynes@359 | 127 | static inline void load_reg( int x86reg, int sh4reg )
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nkeynes@359 | 128 | {
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nkeynes@359 | 129 | /* mov [bp+n], reg */
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nkeynes@361 | 130 | OP(0x8B);
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nkeynes@361 | 131 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 132 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 133 | }
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nkeynes@359 | 134 |
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nkeynes@374 | 135 | static inline void load_reg16s( int x86reg, int sh4reg )
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nkeynes@368 | 136 | {
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nkeynes@374 | 137 | OP(0x0F);
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nkeynes@374 | 138 | OP(0xBF);
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nkeynes@374 | 139 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@368 | 140 | }
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nkeynes@368 | 141 |
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nkeynes@374 | 142 | static inline void load_reg16u( int x86reg, int sh4reg )
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nkeynes@368 | 143 | {
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nkeynes@374 | 144 | OP(0x0F);
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nkeynes@374 | 145 | OP(0xB7);
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nkeynes@374 | 146 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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nkeynes@374 | 147 |
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nkeynes@368 | 148 | }
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nkeynes@368 | 149 |
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nkeynes@380 | 150 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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nkeynes@380 | 151 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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nkeynes@359 | 152 | /**
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nkeynes@359 | 153 | * Emit an instruction to load an immediate value into a register
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nkeynes@359 | 154 | */
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nkeynes@359 | 155 | static inline void load_imm32( int x86reg, uint32_t value ) {
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nkeynes@359 | 156 | /* mov #value, reg */
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nkeynes@359 | 157 | OP(0xB8 + x86reg);
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nkeynes@359 | 158 | OP32(value);
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nkeynes@359 | 159 | }
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nkeynes@359 | 160 |
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nkeynes@359 | 161 | /**
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nkeynes@527 | 162 | * Load an immediate 64-bit quantity (note: x86-64 only)
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nkeynes@527 | 163 | */
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nkeynes@527 | 164 | static inline void load_imm64( int x86reg, uint32_t value ) {
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nkeynes@527 | 165 | /* mov #value, reg */
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nkeynes@527 | 166 | REXW();
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nkeynes@527 | 167 | OP(0xB8 + x86reg);
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nkeynes@527 | 168 | OP64(value);
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nkeynes@527 | 169 | }
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nkeynes@527 | 170 |
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nkeynes@527 | 171 |
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nkeynes@527 | 172 | /**
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nkeynes@359 | 173 | * Emit an instruction to store an SH4 reg (RN)
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nkeynes@359 | 174 | */
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nkeynes@359 | 175 | void static inline store_reg( int x86reg, int sh4reg ) {
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nkeynes@359 | 176 | /* mov reg, [bp+n] */
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nkeynes@361 | 177 | OP(0x89);
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nkeynes@361 | 178 | OP(0x45 + (x86reg<<3));
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nkeynes@359 | 179 | OP(REG_OFFSET(r[sh4reg]));
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nkeynes@359 | 180 | }
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nkeynes@374 | 181 |
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nkeynes@374 | 182 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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nkeynes@374 | 183 |
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nkeynes@375 | 184 | /**
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nkeynes@375 | 185 | * Load an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 186 | * register (eg for register-to-register moves)
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nkeynes@375 | 187 | */
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nkeynes@375 | 188 | void static inline load_fr( int bankreg, int x86reg, int frm )
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nkeynes@375 | 189 | {
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nkeynes@375 | 190 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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nkeynes@375 | 191 | }
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nkeynes@375 | 192 |
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nkeynes@375 | 193 | /**
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nkeynes@375 | 194 | * Store an FR register (single-precision floating point) into an integer x86
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nkeynes@375 | 195 | * register (eg for register-to-register moves)
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nkeynes@375 | 196 | */
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nkeynes@375 | 197 | void static inline store_fr( int bankreg, int x86reg, int frn )
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nkeynes@375 | 198 | {
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nkeynes@375 | 199 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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nkeynes@375 | 200 | }
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nkeynes@375 | 201 |
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nkeynes@375 | 202 |
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nkeynes@375 | 203 | /**
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nkeynes@375 | 204 | * Load a pointer to the back fp back into the specified x86 register. The
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nkeynes@375 | 205 | * bankreg must have been previously loaded with FPSCR.
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nkeynes@388 | 206 | * NB: 12 bytes
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nkeynes@375 | 207 | */
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nkeynes@374 | 208 | static inline void load_xf_bank( int bankreg )
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nkeynes@374 | 209 | {
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nkeynes@386 | 210 | NOT_r32( bankreg );
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nkeynes@374 | 211 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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nkeynes@374 | 212 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
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nkeynes@374 | 213 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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nkeynes@374 | 214 | }
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nkeynes@374 | 215 |
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nkeynes@375 | 216 | /**
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nkeynes@386 | 217 | * Update the fr_bank pointer based on the current fpscr value.
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nkeynes@386 | 218 | */
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nkeynes@386 | 219 | static inline void update_fr_bank( int fpscrreg )
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nkeynes@386 | 220 | {
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nkeynes@386 | 221 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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nkeynes@386 | 222 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
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nkeynes@386 | 223 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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nkeynes@386 | 224 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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nkeynes@386 | 225 | }
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nkeynes@386 | 226 | /**
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nkeynes@377 | 227 | * Push FPUL (as a 32-bit float) onto the FPU stack
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nkeynes@377 | 228 | */
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nkeynes@377 | 229 | static inline void push_fpul( )
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nkeynes@377 | 230 | {
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nkeynes@377 | 231 | OP(0xD9); OP(0x45); OP(R_FPUL);
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nkeynes@377 | 232 | }
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nkeynes@377 | 233 |
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nkeynes@377 | 234 | /**
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nkeynes@377 | 235 | * Pop FPUL (as a 32-bit float) from the FPU stack
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nkeynes@377 | 236 | */
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nkeynes@377 | 237 | static inline void pop_fpul( )
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nkeynes@377 | 238 | {
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nkeynes@377 | 239 | OP(0xD9); OP(0x5D); OP(R_FPUL);
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nkeynes@377 | 240 | }
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nkeynes@377 | 241 |
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nkeynes@377 | 242 | /**
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nkeynes@375 | 243 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 244 | * with the location of the current fp bank.
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nkeynes@375 | 245 | */
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nkeynes@374 | 246 | static inline void push_fr( int bankreg, int frm )
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nkeynes@374 | 247 | {
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nkeynes@374 | 248 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
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nkeynes@374 | 249 | }
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nkeynes@374 | 250 |
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nkeynes@375 | 251 | /**
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nkeynes@375 | 252 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
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nkeynes@375 | 253 | * with bankreg previously loaded with the location of the current fp bank.
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nkeynes@375 | 254 | */
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nkeynes@374 | 255 | static inline void pop_fr( int bankreg, int frm )
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nkeynes@374 | 256 | {
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nkeynes@374 | 257 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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nkeynes@374 | 258 | }
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nkeynes@374 | 259 |
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nkeynes@375 | 260 | /**
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nkeynes@375 | 261 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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nkeynes@375 | 262 | * with the location of the current fp bank.
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nkeynes@375 | 263 | */
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nkeynes@374 | 264 | static inline void push_dr( int bankreg, int frm )
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nkeynes@374 | 265 | {
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nkeynes@377 | 266 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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nkeynes@374 | 267 | }
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nkeynes@374 | 268 |
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nkeynes@374 | 269 | static inline void pop_dr( int bankreg, int frm )
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nkeynes@374 | 270 | {
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nkeynes@377 | 271 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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nkeynes@374 | 272 | }
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nkeynes@374 | 273 |
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nkeynes@368 | 274 | /* Exception checks - Note that all exception checks will clobber EAX */
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nkeynes@416 | 275 |
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nkeynes@416 | 276 | #define check_priv( ) \
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nkeynes@416 | 277 | if( !sh4_x86.priv_checked ) { \
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nkeynes@416 | 278 | sh4_x86.priv_checked = TRUE;\
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nkeynes@416 | 279 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 280 | AND_imm32_r32( SR_MD, R_EAX );\
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nkeynes@416 | 281 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 282 | JE_exc( EXC_SLOT_ILLEGAL );\
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nkeynes@416 | 283 | } else {\
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nkeynes@586 | 284 | JE_exc( EXC_ILLEGAL );\
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nkeynes@416 | 285 | }\
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nkeynes@416 | 286 | }\
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nkeynes@416 | 287 |
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nkeynes@416 | 288 | #define check_fpuen( ) \
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nkeynes@416 | 289 | if( !sh4_x86.fpuen_checked ) {\
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nkeynes@416 | 290 | sh4_x86.fpuen_checked = TRUE;\
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nkeynes@416 | 291 | load_spreg( R_EAX, R_SR );\
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nkeynes@416 | 292 | AND_imm32_r32( SR_FD, R_EAX );\
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nkeynes@416 | 293 | if( sh4_x86.in_delay_slot ) {\
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nkeynes@586 | 294 | JNE_exc(EXC_SLOT_FPU_DISABLED);\
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nkeynes@416 | 295 | } else {\
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nkeynes@586 | 296 | JNE_exc(EXC_FPU_DISABLED);\
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nkeynes@416 | 297 | }\
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nkeynes@416 | 298 | }
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nkeynes@416 | 299 |
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nkeynes@586 | 300 | #define check_ralign16( x86reg ) \
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nkeynes@586 | 301 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 302 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@416 | 303 |
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nkeynes@586 | 304 | #define check_walign16( x86reg ) \
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nkeynes@586 | 305 | TEST_imm32_r32( 0x00000001, x86reg ); \
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nkeynes@586 | 306 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 307 |
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nkeynes@586 | 308 | #define check_ralign32( x86reg ) \
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nkeynes@586 | 309 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 310 | JNE_exc(EXC_DATA_ADDR_READ)
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nkeynes@368 | 311 |
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nkeynes@586 | 312 | #define check_walign32( x86reg ) \
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nkeynes@586 | 313 | TEST_imm32_r32( 0x00000003, x86reg ); \
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nkeynes@586 | 314 | JNE_exc(EXC_DATA_ADDR_WRITE);
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nkeynes@368 | 315 |
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nkeynes@361 | 316 | #define UNDEF()
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nkeynes@361 | 317 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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nkeynes@361 | 318 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 319 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 320 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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nkeynes@361 | 321 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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nkeynes@361 | 322 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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nkeynes@361 | 323 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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nkeynes@361 | 324 |
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nkeynes@586 | 325 | /**
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nkeynes@586 | 326 | * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned
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nkeynes@586 | 327 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 328 | */
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nkeynes@586 | 329 | #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@596 | 330 |
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nkeynes@596 | 331 | #define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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nkeynes@586 | 332 | /**
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nkeynes@586 | 333 | * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned
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nkeynes@586 | 334 | * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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nkeynes@586 | 335 | */
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nkeynes@586 | 336 | #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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nkeynes@368 | 337 |
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nkeynes@586 | 338 | #define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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nkeynes@586 | 339 | #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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nkeynes@586 | 340 | #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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nkeynes@586 | 341 |
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nkeynes@590 | 342 | #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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nkeynes@388 | 343 |
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nkeynes@539 | 344 | /****** Import appropriate calling conventions ******/
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nkeynes@539 | 345 | #if SH4_TRANSLATOR == TARGET_X86_64
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nkeynes@539 | 346 | #include "sh4/ia64abi.h"
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nkeynes@539 | 347 | #else /* SH4_TRANSLATOR == TARGET_X86 */
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nkeynes@539 | 348 | #ifdef APPLE_BUILD
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nkeynes@539 | 349 | #include "sh4/ia32mac.h"
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nkeynes@539 | 350 | #else
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nkeynes@539 | 351 | #include "sh4/ia32abi.h"
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nkeynes@539 | 352 | #endif
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nkeynes@539 | 353 | #endif
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nkeynes@539 | 354 |
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nkeynes@593 | 355 | uint32_t sh4_translate_end_block_size()
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nkeynes@593 | 356 | {
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nkeynes@596 | 357 | if( sh4_x86.backpatch_posn <= 3 ) {
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nkeynes@596 | 358 | return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
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nkeynes@596 | 359 | } else {
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nkeynes@596 | 360 | return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
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nkeynes@596 | 361 | }
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nkeynes@593 | 362 | }
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nkeynes@593 | 363 |
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nkeynes@593 | 364 |
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nkeynes@590 | 365 | /**
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nkeynes@590 | 366 | * Embed a breakpoint into the generated code
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nkeynes@590 | 367 | */
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nkeynes@586 | 368 | void sh4_translate_emit_breakpoint( sh4vma_t pc )
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nkeynes@586 | 369 | {
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nkeynes@591 | 370 | load_imm32( R_EAX, pc );
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nkeynes@591 | 371 | call_func1( sh4_translate_breakpoint_hit, R_EAX );
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nkeynes@586 | 372 | }
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nkeynes@590 | 373 |
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nkeynes@590 | 374 | /**
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nkeynes@590 | 375 | * Embed a call to sh4_execute_instruction for situations that we
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nkeynes@590 | 376 | * can't translate (mainly page-crossing delay slots at the moment).
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nkeynes@590 | 377 | * Caller is responsible for setting new_pc.
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nkeynes@590 | 378 | */
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nkeynes@590 | 379 | void sh4_emulator_exit( sh4vma_t endpc )
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nkeynes@590 | 380 | {
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nkeynes@590 | 381 | load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 5
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nkeynes@590 | 382 | ADD_r32_sh4r( R_ECX, R_PC );
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nkeynes@586 | 383 |
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nkeynes@590 | 384 | load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
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nkeynes@590 | 385 | ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
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nkeynes@590 | 386 | load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
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nkeynes@590 | 387 | store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
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nkeynes@590 | 388 |
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nkeynes@590 | 389 | call_func0( sh4_execute_instruction );
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nkeynes@590 | 390 | load_imm32( R_EAX, R_PC );
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nkeynes@590 | 391 | if( sh4_x86.tlb_on ) {
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nkeynes@590 | 392 | call_func1(xlat_get_code_by_vma,R_EAX);
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nkeynes@590 | 393 | } else {
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nkeynes@590 | 394 | call_func1(xlat_get_code,R_EAX);
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nkeynes@590 | 395 | }
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nkeynes@590 | 396 | AND_imm8s_r32( 0xFC, R_EAX ); // 3
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nkeynes@590 | 397 | POP_r32(R_EBP);
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nkeynes@590 | 398 | RET();
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nkeynes@590 | 399 | }
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nkeynes@539 | 400 |
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nkeynes@359 | 401 | /**
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nkeynes@359 | 402 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 403 | * by translating both branch and delayed instruction as a single unit (as
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nkeynes@359 | 404 | *
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nkeynes@586 | 405 | * The instruction MUST be in the icache (assert check)
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nkeynes@359 | 406 | *
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nkeynes@359 | 407 | * @return true if the instruction marks the end of a basic block
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nkeynes@359 | 408 | * (eg a branch or
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nkeynes@359 | 409 | */
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nkeynes@590 | 410 | uint32_t sh4_translate_instruction( sh4vma_t pc )
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nkeynes@359 | 411 | {
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nkeynes@388 | 412 | uint32_t ir;
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nkeynes@586 | 413 | /* Read instruction from icache */
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nkeynes@586 | 414 | assert( IS_IN_ICACHE(pc) );
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nkeynes@586 | 415 | ir = *(uint16_t *)GET_ICACHE_PTR(pc);
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nkeynes@586 | 416 |
|
nkeynes@586 | 417 | /* PC is not in the current icache - this usually means we're running
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nkeynes@586 | 418 | * with MMU on, and we've gone past the end of the page. And since
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nkeynes@586 | 419 | * sh4_translate_block is pretty careful about this, it means we're
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nkeynes@586 | 420 | * almost certainly in a delay slot.
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nkeynes@586 | 421 | *
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nkeynes@586 | 422 | * Since we can't assume the page is present (and we can't fault it in
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nkeynes@586 | 423 | * at this point, inline a call to sh4_execute_instruction (with a few
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nkeynes@586 | 424 | * small repairs to cope with the different environment).
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nkeynes@586 | 425 | */
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nkeynes@586 | 426 |
|
nkeynes@586 | 427 | if( !sh4_x86.in_delay_slot ) {
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nkeynes@596 | 428 | sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
|
nkeynes@388 | 429 | }
|
nkeynes@359 | 430 | switch( (ir&0xF000) >> 12 ) {
|
nkeynes@359 | 431 | case 0x0:
|
nkeynes@359 | 432 | switch( ir&0xF ) {
|
nkeynes@359 | 433 | case 0x2:
|
nkeynes@359 | 434 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 435 | case 0x0:
|
nkeynes@359 | 436 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 437 | case 0x0:
|
nkeynes@359 | 438 | { /* STC SR, Rn */
|
nkeynes@359 | 439 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 440 | check_priv();
|
nkeynes@374 | 441 | call_func0(sh4_read_sr);
|
nkeynes@368 | 442 | store_reg( R_EAX, Rn );
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nkeynes@417 | 443 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 444 | }
|
nkeynes@359 | 445 | break;
|
nkeynes@359 | 446 | case 0x1:
|
nkeynes@359 | 447 | { /* STC GBR, Rn */
|
nkeynes@359 | 448 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 449 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 450 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 451 | }
|
nkeynes@359 | 452 | break;
|
nkeynes@359 | 453 | case 0x2:
|
nkeynes@359 | 454 | { /* STC VBR, Rn */
|
nkeynes@359 | 455 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 456 | check_priv();
|
nkeynes@359 | 457 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 458 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 459 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 460 | }
|
nkeynes@359 | 461 | break;
|
nkeynes@359 | 462 | case 0x3:
|
nkeynes@359 | 463 | { /* STC SSR, Rn */
|
nkeynes@359 | 464 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 465 | check_priv();
|
nkeynes@359 | 466 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 467 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 468 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 469 | }
|
nkeynes@359 | 470 | break;
|
nkeynes@359 | 471 | case 0x4:
|
nkeynes@359 | 472 | { /* STC SPC, Rn */
|
nkeynes@359 | 473 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 474 | check_priv();
|
nkeynes@359 | 475 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 476 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 477 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 478 | }
|
nkeynes@359 | 479 | break;
|
nkeynes@359 | 480 | default:
|
nkeynes@359 | 481 | UNDEF();
|
nkeynes@359 | 482 | break;
|
nkeynes@359 | 483 | }
|
nkeynes@359 | 484 | break;
|
nkeynes@359 | 485 | case 0x1:
|
nkeynes@359 | 486 | { /* STC Rm_BANK, Rn */
|
nkeynes@359 | 487 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 488 | check_priv();
|
nkeynes@374 | 489 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 490 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 491 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 492 | }
|
nkeynes@359 | 493 | break;
|
nkeynes@359 | 494 | }
|
nkeynes@359 | 495 | break;
|
nkeynes@359 | 496 | case 0x3:
|
nkeynes@359 | 497 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 498 | case 0x0:
|
nkeynes@359 | 499 | { /* BSRF Rn */
|
nkeynes@359 | 500 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 501 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 502 | SLOTILLEGAL();
|
nkeynes@374 | 503 | } else {
|
nkeynes@590 | 504 | load_spreg( R_EAX, R_PC );
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nkeynes@590 | 505 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
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nkeynes@590 | 506 | store_spreg( R_EAX, R_PR );
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nkeynes@590 | 507 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
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nkeynes@590 | 508 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@590 | 509 |
|
nkeynes@417 | 510 | sh4_x86.tstate = TSTATE_NONE;
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nkeynes@526 | 511 | sh4_translate_instruction( pc + 2 );
|
nkeynes@590 | 512 | exit_block_newpcset(pc+2);
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nkeynes@409 | 513 | sh4_x86.branch_taken = TRUE;
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nkeynes@408 | 514 | return 4;
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nkeynes@374 | 515 | }
|
nkeynes@359 | 516 | }
|
nkeynes@359 | 517 | break;
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nkeynes@359 | 518 | case 0x2:
|
nkeynes@359 | 519 | { /* BRAF Rn */
|
nkeynes@359 | 520 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 521 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 522 | SLOTILLEGAL();
|
nkeynes@374 | 523 | } else {
|
nkeynes@590 | 524 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 525 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@590 | 526 | ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
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nkeynes@590 | 527 | store_spreg( R_EAX, R_NEW_PC );
|
nkeynes@590 | 528 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 529 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 530 | sh4_translate_instruction( pc + 2 );
|
nkeynes@590 | 531 | exit_block_newpcset(pc+2);
|
nkeynes@409 | 532 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 533 | return 4;
|
nkeynes@374 | 534 | }
|
nkeynes@359 | 535 | }
|
nkeynes@359 | 536 | break;
|
nkeynes@359 | 537 | case 0x8:
|
nkeynes@359 | 538 | { /* PREF @Rn */
|
nkeynes@359 | 539 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 540 | load_reg( R_EAX, Rn );
|
nkeynes@532 | 541 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 542 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 543 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@586 | 544 | JNE_rel8(8+CALL_FUNC1_SIZE, end);
|
nkeynes@532 | 545 | call_func1( sh4_flush_store_queue, R_ECX );
|
nkeynes@586 | 546 | TEST_r32_r32( R_EAX, R_EAX );
|
nkeynes@586 | 547 | JE_exc(-1);
|
nkeynes@380 | 548 | JMP_TARGET(end);
|
nkeynes@417 | 549 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 550 | }
|
nkeynes@359 | 551 | break;
|
nkeynes@359 | 552 | case 0x9:
|
nkeynes@359 | 553 | { /* OCBI @Rn */
|
nkeynes@359 | 554 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 555 | }
|
nkeynes@359 | 556 | break;
|
nkeynes@359 | 557 | case 0xA:
|
nkeynes@359 | 558 | { /* OCBP @Rn */
|
nkeynes@359 | 559 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 560 | }
|
nkeynes@359 | 561 | break;
|
nkeynes@359 | 562 | case 0xB:
|
nkeynes@359 | 563 | { /* OCBWB @Rn */
|
nkeynes@359 | 564 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 565 | }
|
nkeynes@359 | 566 | break;
|
nkeynes@359 | 567 | case 0xC:
|
nkeynes@359 | 568 | { /* MOVCA.L R0, @Rn */
|
nkeynes@359 | 569 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 570 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 571 | check_walign32( R_EAX );
|
nkeynes@586 | 572 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 573 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 574 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 575 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 576 | }
|
nkeynes@359 | 577 | break;
|
nkeynes@359 | 578 | default:
|
nkeynes@359 | 579 | UNDEF();
|
nkeynes@359 | 580 | break;
|
nkeynes@359 | 581 | }
|
nkeynes@359 | 582 | break;
|
nkeynes@359 | 583 | case 0x4:
|
nkeynes@359 | 584 | { /* MOV.B Rm, @(R0, Rn) */
|
nkeynes@359 | 585 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 586 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 587 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 588 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 589 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 590 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 591 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 592 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 593 | }
|
nkeynes@359 | 594 | break;
|
nkeynes@359 | 595 | case 0x5:
|
nkeynes@359 | 596 | { /* MOV.W Rm, @(R0, Rn) */
|
nkeynes@359 | 597 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 598 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 599 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 600 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 601 | check_walign16( R_EAX );
|
nkeynes@586 | 602 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 603 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 604 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 605 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 606 | }
|
nkeynes@359 | 607 | break;
|
nkeynes@359 | 608 | case 0x6:
|
nkeynes@359 | 609 | { /* MOV.L Rm, @(R0, Rn) */
|
nkeynes@359 | 610 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 611 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 612 | load_reg( R_ECX, Rn );
|
nkeynes@586 | 613 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 614 | check_walign32( R_EAX );
|
nkeynes@586 | 615 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 616 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 617 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 618 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 619 | }
|
nkeynes@359 | 620 | break;
|
nkeynes@359 | 621 | case 0x7:
|
nkeynes@359 | 622 | { /* MUL.L Rm, Rn */
|
nkeynes@359 | 623 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 624 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 625 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 626 | MUL_r32( R_ECX );
|
nkeynes@361 | 627 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 628 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 629 | }
|
nkeynes@359 | 630 | break;
|
nkeynes@359 | 631 | case 0x8:
|
nkeynes@359 | 632 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 633 | case 0x0:
|
nkeynes@359 | 634 | { /* CLRT */
|
nkeynes@374 | 635 | CLC();
|
nkeynes@374 | 636 | SETC_t();
|
nkeynes@417 | 637 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 638 | }
|
nkeynes@359 | 639 | break;
|
nkeynes@359 | 640 | case 0x1:
|
nkeynes@359 | 641 | { /* SETT */
|
nkeynes@374 | 642 | STC();
|
nkeynes@374 | 643 | SETC_t();
|
nkeynes@417 | 644 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 645 | }
|
nkeynes@359 | 646 | break;
|
nkeynes@359 | 647 | case 0x2:
|
nkeynes@359 | 648 | { /* CLRMAC */
|
nkeynes@374 | 649 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 650 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 651 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 652 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 653 | }
|
nkeynes@359 | 654 | break;
|
nkeynes@359 | 655 | case 0x3:
|
nkeynes@359 | 656 | { /* LDTLB */
|
nkeynes@553 | 657 | call_func0( MMU_ldtlb );
|
nkeynes@359 | 658 | }
|
nkeynes@359 | 659 | break;
|
nkeynes@359 | 660 | case 0x4:
|
nkeynes@359 | 661 | { /* CLRS */
|
nkeynes@374 | 662 | CLC();
|
nkeynes@374 | 663 | SETC_sh4r(R_S);
|
nkeynes@417 | 664 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 665 | }
|
nkeynes@359 | 666 | break;
|
nkeynes@359 | 667 | case 0x5:
|
nkeynes@359 | 668 | { /* SETS */
|
nkeynes@374 | 669 | STC();
|
nkeynes@374 | 670 | SETC_sh4r(R_S);
|
nkeynes@417 | 671 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 672 | }
|
nkeynes@359 | 673 | break;
|
nkeynes@359 | 674 | default:
|
nkeynes@359 | 675 | UNDEF();
|
nkeynes@359 | 676 | break;
|
nkeynes@359 | 677 | }
|
nkeynes@359 | 678 | break;
|
nkeynes@359 | 679 | case 0x9:
|
nkeynes@359 | 680 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 681 | case 0x0:
|
nkeynes@359 | 682 | { /* NOP */
|
nkeynes@359 | 683 | /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
|
nkeynes@359 | 684 | }
|
nkeynes@359 | 685 | break;
|
nkeynes@359 | 686 | case 0x1:
|
nkeynes@359 | 687 | { /* DIV0U */
|
nkeynes@361 | 688 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 689 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 690 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 691 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 692 | sh4_x86.tstate = TSTATE_C; // works for DIV1
|
nkeynes@359 | 693 | }
|
nkeynes@359 | 694 | break;
|
nkeynes@359 | 695 | case 0x2:
|
nkeynes@359 | 696 | { /* MOVT Rn */
|
nkeynes@359 | 697 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 698 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 699 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 700 | }
|
nkeynes@359 | 701 | break;
|
nkeynes@359 | 702 | default:
|
nkeynes@359 | 703 | UNDEF();
|
nkeynes@359 | 704 | break;
|
nkeynes@359 | 705 | }
|
nkeynes@359 | 706 | break;
|
nkeynes@359 | 707 | case 0xA:
|
nkeynes@359 | 708 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 709 | case 0x0:
|
nkeynes@359 | 710 | { /* STS MACH, Rn */
|
nkeynes@359 | 711 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 712 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 713 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 714 | }
|
nkeynes@359 | 715 | break;
|
nkeynes@359 | 716 | case 0x1:
|
nkeynes@359 | 717 | { /* STS MACL, Rn */
|
nkeynes@359 | 718 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 719 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 720 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 721 | }
|
nkeynes@359 | 722 | break;
|
nkeynes@359 | 723 | case 0x2:
|
nkeynes@359 | 724 | { /* STS PR, Rn */
|
nkeynes@359 | 725 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 726 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 727 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 728 | }
|
nkeynes@359 | 729 | break;
|
nkeynes@359 | 730 | case 0x3:
|
nkeynes@359 | 731 | { /* STC SGR, Rn */
|
nkeynes@359 | 732 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 733 | check_priv();
|
nkeynes@359 | 734 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 735 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 736 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 737 | }
|
nkeynes@359 | 738 | break;
|
nkeynes@359 | 739 | case 0x5:
|
nkeynes@359 | 740 | { /* STS FPUL, Rn */
|
nkeynes@359 | 741 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 742 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 743 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 744 | }
|
nkeynes@359 | 745 | break;
|
nkeynes@359 | 746 | case 0x6:
|
nkeynes@359 | 747 | { /* STS FPSCR, Rn */
|
nkeynes@359 | 748 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 749 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 750 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 751 | }
|
nkeynes@359 | 752 | break;
|
nkeynes@359 | 753 | case 0xF:
|
nkeynes@359 | 754 | { /* STC DBR, Rn */
|
nkeynes@359 | 755 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@386 | 756 | check_priv();
|
nkeynes@359 | 757 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 758 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 759 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 760 | }
|
nkeynes@359 | 761 | break;
|
nkeynes@359 | 762 | default:
|
nkeynes@359 | 763 | UNDEF();
|
nkeynes@359 | 764 | break;
|
nkeynes@359 | 765 | }
|
nkeynes@359 | 766 | break;
|
nkeynes@359 | 767 | case 0xB:
|
nkeynes@359 | 768 | switch( (ir&0xFF0) >> 4 ) {
|
nkeynes@359 | 769 | case 0x0:
|
nkeynes@359 | 770 | { /* RTS */
|
nkeynes@374 | 771 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 772 | SLOTILLEGAL();
|
nkeynes@374 | 773 | } else {
|
nkeynes@408 | 774 | load_spreg( R_ECX, R_PR );
|
nkeynes@590 | 775 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@590 | 776 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@526 | 777 | sh4_translate_instruction(pc+2);
|
nkeynes@590 | 778 | exit_block_newpcset(pc+2);
|
nkeynes@409 | 779 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 780 | return 4;
|
nkeynes@374 | 781 | }
|
nkeynes@359 | 782 | }
|
nkeynes@359 | 783 | break;
|
nkeynes@359 | 784 | case 0x1:
|
nkeynes@359 | 785 | { /* SLEEP */
|
nkeynes@388 | 786 | check_priv();
|
nkeynes@388 | 787 | call_func0( sh4_sleep );
|
nkeynes@417 | 788 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@590 | 789 | sh4_x86.in_delay_slot = DELAY_NONE;
|
nkeynes@408 | 790 | return 2;
|
nkeynes@359 | 791 | }
|
nkeynes@359 | 792 | break;
|
nkeynes@359 | 793 | case 0x2:
|
nkeynes@359 | 794 | { /* RTE */
|
nkeynes@374 | 795 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 796 | SLOTILLEGAL();
|
nkeynes@374 | 797 | } else {
|
nkeynes@408 | 798 | check_priv();
|
nkeynes@408 | 799 | load_spreg( R_ECX, R_SPC );
|
nkeynes@590 | 800 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@374 | 801 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 802 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@590 | 803 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@377 | 804 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 805 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 806 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@526 | 807 | sh4_translate_instruction(pc+2);
|
nkeynes@590 | 808 | exit_block_newpcset(pc+2);
|
nkeynes@409 | 809 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 810 | return 4;
|
nkeynes@374 | 811 | }
|
nkeynes@359 | 812 | }
|
nkeynes@359 | 813 | break;
|
nkeynes@359 | 814 | default:
|
nkeynes@359 | 815 | UNDEF();
|
nkeynes@359 | 816 | break;
|
nkeynes@359 | 817 | }
|
nkeynes@359 | 818 | break;
|
nkeynes@359 | 819 | case 0xC:
|
nkeynes@359 | 820 | { /* MOV.B @(R0, Rm), Rn */
|
nkeynes@359 | 821 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 822 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 823 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 824 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 825 | MMU_TRANSLATE_READ( R_EAX )
|
nkeynes@586 | 826 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 827 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 828 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 829 | }
|
nkeynes@359 | 830 | break;
|
nkeynes@359 | 831 | case 0xD:
|
nkeynes@359 | 832 | { /* MOV.W @(R0, Rm), Rn */
|
nkeynes@359 | 833 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 834 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 835 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 836 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 837 | check_ralign16( R_EAX );
|
nkeynes@586 | 838 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 839 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 840 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 841 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 842 | }
|
nkeynes@359 | 843 | break;
|
nkeynes@359 | 844 | case 0xE:
|
nkeynes@359 | 845 | { /* MOV.L @(R0, Rm), Rn */
|
nkeynes@359 | 846 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 847 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 848 | load_reg( R_ECX, Rm );
|
nkeynes@586 | 849 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 850 | check_ralign32( R_EAX );
|
nkeynes@586 | 851 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 852 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 853 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 854 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 855 | }
|
nkeynes@359 | 856 | break;
|
nkeynes@359 | 857 | case 0xF:
|
nkeynes@359 | 858 | { /* MAC.L @Rm+, @Rn+ */
|
nkeynes@359 | 859 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 860 | if( Rm == Rn ) {
|
nkeynes@586 | 861 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 862 | check_ralign32( R_EAX );
|
nkeynes@586 | 863 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 864 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 865 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 866 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@596 | 867 | MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
|
nkeynes@586 | 868 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 869 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 870 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 871 | } else {
|
nkeynes@586 | 872 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 873 | check_ralign32( R_EAX );
|
nkeynes@586 | 874 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@596 | 875 | load_reg( R_ECX, Rn );
|
nkeynes@596 | 876 | check_ralign32( R_ECX );
|
nkeynes@586 | 877 | PUSH_realigned_r32( R_EAX );
|
nkeynes@596 | 878 | MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
|
nkeynes@596 | 879 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 880 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 881 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 882 | }
|
nkeynes@586 | 883 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 884 | POP_r32( R_ECX );
|
nkeynes@586 | 885 | PUSH_r32( R_EAX );
|
nkeynes@386 | 886 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@547 | 887 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 888 |
|
nkeynes@386 | 889 | IMUL_r32( R_ECX );
|
nkeynes@386 | 890 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 891 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 892 |
|
nkeynes@386 | 893 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 894 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@527 | 895 | JE_rel8( CALL_FUNC0_SIZE, nosat );
|
nkeynes@386 | 896 | call_func0( signsat48 );
|
nkeynes@386 | 897 | JMP_TARGET( nosat );
|
nkeynes@417 | 898 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 899 | }
|
nkeynes@359 | 900 | break;
|
nkeynes@359 | 901 | default:
|
nkeynes@359 | 902 | UNDEF();
|
nkeynes@359 | 903 | break;
|
nkeynes@359 | 904 | }
|
nkeynes@359 | 905 | break;
|
nkeynes@359 | 906 | case 0x1:
|
nkeynes@359 | 907 | { /* MOV.L Rm, @(disp, Rn) */
|
nkeynes@359 | 908 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@586 | 909 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 910 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 911 | check_walign32( R_EAX );
|
nkeynes@586 | 912 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 913 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 914 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 915 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 916 | }
|
nkeynes@359 | 917 | break;
|
nkeynes@359 | 918 | case 0x2:
|
nkeynes@359 | 919 | switch( ir&0xF ) {
|
nkeynes@359 | 920 | case 0x0:
|
nkeynes@359 | 921 | { /* MOV.B Rm, @Rn */
|
nkeynes@359 | 922 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 923 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 924 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 925 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 926 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 927 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 928 | }
|
nkeynes@359 | 929 | break;
|
nkeynes@359 | 930 | case 0x1:
|
nkeynes@359 | 931 | { /* MOV.W Rm, @Rn */
|
nkeynes@359 | 932 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 933 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 934 | check_walign16( R_EAX );
|
nkeynes@586 | 935 | MMU_TRANSLATE_WRITE( R_EAX )
|
nkeynes@586 | 936 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 937 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 938 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 939 | }
|
nkeynes@359 | 940 | break;
|
nkeynes@359 | 941 | case 0x2:
|
nkeynes@359 | 942 | { /* MOV.L Rm, @Rn */
|
nkeynes@359 | 943 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 944 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 945 | check_walign32(R_EAX);
|
nkeynes@586 | 946 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 947 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 948 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 949 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 950 | }
|
nkeynes@359 | 951 | break;
|
nkeynes@359 | 952 | case 0x4:
|
nkeynes@359 | 953 | { /* MOV.B Rm, @-Rn */
|
nkeynes@359 | 954 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 955 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 956 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@586 | 957 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 958 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 959 | ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 960 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 961 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 962 | }
|
nkeynes@359 | 963 | break;
|
nkeynes@359 | 964 | case 0x5:
|
nkeynes@359 | 965 | { /* MOV.W Rm, @-Rn */
|
nkeynes@359 | 966 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 967 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 968 | ADD_imm8s_r32( -2, R_EAX );
|
nkeynes@586 | 969 | check_walign16( R_EAX );
|
nkeynes@586 | 970 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 971 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 972 | ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 973 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 974 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 975 | }
|
nkeynes@359 | 976 | break;
|
nkeynes@359 | 977 | case 0x6:
|
nkeynes@359 | 978 | { /* MOV.L Rm, @-Rn */
|
nkeynes@359 | 979 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 980 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 981 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 982 | check_walign32( R_EAX );
|
nkeynes@586 | 983 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 984 | load_reg( R_EDX, Rm );
|
nkeynes@586 | 985 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 986 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 987 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 988 | }
|
nkeynes@359 | 989 | break;
|
nkeynes@359 | 990 | case 0x7:
|
nkeynes@359 | 991 | { /* DIV0S Rm, Rn */
|
nkeynes@359 | 992 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 993 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 994 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 995 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 996 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 997 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 998 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 999 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 1000 | SETNE_t();
|
nkeynes@417 | 1001 | sh4_x86.tstate = TSTATE_NE;
|
nkeynes@359 | 1002 | }
|
nkeynes@359 | 1003 | break;
|
nkeynes@359 | 1004 | case 0x8:
|
nkeynes@359 | 1005 | { /* TST Rm, Rn */
|
nkeynes@359 | 1006 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1007 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1008 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1009 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1010 | SETE_t();
|
nkeynes@417 | 1011 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1012 | }
|
nkeynes@359 | 1013 | break;
|
nkeynes@359 | 1014 | case 0x9:
|
nkeynes@359 | 1015 | { /* AND Rm, Rn */
|
nkeynes@359 | 1016 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1017 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1018 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1019 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1020 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1021 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1022 | }
|
nkeynes@359 | 1023 | break;
|
nkeynes@359 | 1024 | case 0xA:
|
nkeynes@359 | 1025 | { /* XOR Rm, Rn */
|
nkeynes@359 | 1026 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1027 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1028 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1029 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1030 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1031 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1032 | }
|
nkeynes@359 | 1033 | break;
|
nkeynes@359 | 1034 | case 0xB:
|
nkeynes@359 | 1035 | { /* OR Rm, Rn */
|
nkeynes@359 | 1036 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1037 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1038 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1039 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1040 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1041 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1042 | }
|
nkeynes@359 | 1043 | break;
|
nkeynes@359 | 1044 | case 0xC:
|
nkeynes@359 | 1045 | { /* CMP/STR Rm, Rn */
|
nkeynes@359 | 1046 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 1047 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 1048 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 1049 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 1050 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 1051 | JE_rel8(13, target1);
|
nkeynes@368 | 1052 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1053 | JE_rel8(9, target2);
|
nkeynes@368 | 1054 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 1055 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 1056 | JE_rel8(2, target3);
|
nkeynes@368 | 1057 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 1058 | JMP_TARGET(target1);
|
nkeynes@380 | 1059 | JMP_TARGET(target2);
|
nkeynes@380 | 1060 | JMP_TARGET(target3);
|
nkeynes@368 | 1061 | SETE_t();
|
nkeynes@417 | 1062 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1063 | }
|
nkeynes@359 | 1064 | break;
|
nkeynes@359 | 1065 | case 0xD:
|
nkeynes@359 | 1066 | { /* XTRCT Rm, Rn */
|
nkeynes@359 | 1067 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1068 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1069 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1070 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1071 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1072 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1073 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1074 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1075 | }
|
nkeynes@359 | 1076 | break;
|
nkeynes@359 | 1077 | case 0xE:
|
nkeynes@359 | 1078 | { /* MULU.W Rm, Rn */
|
nkeynes@359 | 1079 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1080 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 1081 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 1082 | MUL_r32( R_ECX );
|
nkeynes@374 | 1083 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1084 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1085 | }
|
nkeynes@359 | 1086 | break;
|
nkeynes@359 | 1087 | case 0xF:
|
nkeynes@359 | 1088 | { /* MULS.W Rm, Rn */
|
nkeynes@359 | 1089 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@374 | 1090 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 1091 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 1092 | MUL_r32( R_ECX );
|
nkeynes@374 | 1093 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1094 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1095 | }
|
nkeynes@359 | 1096 | break;
|
nkeynes@359 | 1097 | default:
|
nkeynes@359 | 1098 | UNDEF();
|
nkeynes@359 | 1099 | break;
|
nkeynes@359 | 1100 | }
|
nkeynes@359 | 1101 | break;
|
nkeynes@359 | 1102 | case 0x3:
|
nkeynes@359 | 1103 | switch( ir&0xF ) {
|
nkeynes@359 | 1104 | case 0x0:
|
nkeynes@359 | 1105 | { /* CMP/EQ Rm, Rn */
|
nkeynes@359 | 1106 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1107 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1108 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1109 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1110 | SETE_t();
|
nkeynes@417 | 1111 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1112 | }
|
nkeynes@359 | 1113 | break;
|
nkeynes@359 | 1114 | case 0x2:
|
nkeynes@359 | 1115 | { /* CMP/HS Rm, Rn */
|
nkeynes@359 | 1116 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1117 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1118 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1119 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1120 | SETAE_t();
|
nkeynes@417 | 1121 | sh4_x86.tstate = TSTATE_AE;
|
nkeynes@359 | 1122 | }
|
nkeynes@359 | 1123 | break;
|
nkeynes@359 | 1124 | case 0x3:
|
nkeynes@359 | 1125 | { /* CMP/GE Rm, Rn */
|
nkeynes@359 | 1126 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1127 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1128 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1129 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1130 | SETGE_t();
|
nkeynes@417 | 1131 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1132 | }
|
nkeynes@359 | 1133 | break;
|
nkeynes@359 | 1134 | case 0x4:
|
nkeynes@359 | 1135 | { /* DIV1 Rm, Rn */
|
nkeynes@359 | 1136 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@386 | 1137 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 1138 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1139 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1140 | LDC_t();
|
nkeynes@417 | 1141 | }
|
nkeynes@386 | 1142 | RCL1_r32( R_EAX );
|
nkeynes@386 | 1143 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 1144 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 1145 | JE_rel8(5, mqequal);
|
nkeynes@386 | 1146 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1147 | JMP_rel8(3, end);
|
nkeynes@380 | 1148 | JMP_TARGET(mqequal);
|
nkeynes@386 | 1149 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 1150 | JMP_TARGET(end);
|
nkeynes@386 | 1151 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 1152 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 1153 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 1154 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 1155 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 1156 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 1157 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 1158 | store_spreg( R_EAX, R_T );
|
nkeynes@417 | 1159 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1160 | }
|
nkeynes@359 | 1161 | break;
|
nkeynes@359 | 1162 | case 0x5:
|
nkeynes@359 | 1163 | { /* DMULU.L Rm, Rn */
|
nkeynes@359 | 1164 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1165 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1166 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1167 | MUL_r32(R_ECX);
|
nkeynes@361 | 1168 | store_spreg( R_EDX, R_MACH );
|
nkeynes@417 | 1169 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1170 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1171 | }
|
nkeynes@359 | 1172 | break;
|
nkeynes@359 | 1173 | case 0x6:
|
nkeynes@359 | 1174 | { /* CMP/HI Rm, Rn */
|
nkeynes@359 | 1175 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1176 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1177 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1178 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1179 | SETA_t();
|
nkeynes@417 | 1180 | sh4_x86.tstate = TSTATE_A;
|
nkeynes@359 | 1181 | }
|
nkeynes@359 | 1182 | break;
|
nkeynes@359 | 1183 | case 0x7:
|
nkeynes@359 | 1184 | { /* CMP/GT Rm, Rn */
|
nkeynes@359 | 1185 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1186 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1187 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1188 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1189 | SETG_t();
|
nkeynes@417 | 1190 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1191 | }
|
nkeynes@359 | 1192 | break;
|
nkeynes@359 | 1193 | case 0x8:
|
nkeynes@359 | 1194 | { /* SUB Rm, Rn */
|
nkeynes@359 | 1195 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1196 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1197 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1198 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1199 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1200 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1201 | }
|
nkeynes@359 | 1202 | break;
|
nkeynes@359 | 1203 | case 0xA:
|
nkeynes@359 | 1204 | { /* SUBC Rm, Rn */
|
nkeynes@359 | 1205 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1206 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1207 | load_reg( R_ECX, Rn );
|
nkeynes@417 | 1208 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1209 | LDC_t();
|
nkeynes@417 | 1210 | }
|
nkeynes@359 | 1211 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1212 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 1213 | SETC_t();
|
nkeynes@417 | 1214 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1215 | }
|
nkeynes@359 | 1216 | break;
|
nkeynes@359 | 1217 | case 0xB:
|
nkeynes@359 | 1218 | { /* SUBV Rm, Rn */
|
nkeynes@359 | 1219 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1220 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1221 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1222 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1223 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1224 | SETO_t();
|
nkeynes@417 | 1225 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1226 | }
|
nkeynes@359 | 1227 | break;
|
nkeynes@359 | 1228 | case 0xC:
|
nkeynes@359 | 1229 | { /* ADD Rm, Rn */
|
nkeynes@359 | 1230 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1231 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1232 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1233 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1234 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 1235 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1236 | }
|
nkeynes@359 | 1237 | break;
|
nkeynes@359 | 1238 | case 0xD:
|
nkeynes@359 | 1239 | { /* DMULS.L Rm, Rn */
|
nkeynes@359 | 1240 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 1241 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1242 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1243 | IMUL_r32(R_ECX);
|
nkeynes@361 | 1244 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 1245 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1246 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1247 | }
|
nkeynes@359 | 1248 | break;
|
nkeynes@359 | 1249 | case 0xE:
|
nkeynes@359 | 1250 | { /* ADDC Rm, Rn */
|
nkeynes@359 | 1251 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@417 | 1252 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1253 | LDC_t();
|
nkeynes@417 | 1254 | }
|
nkeynes@359 | 1255 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1256 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1257 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1258 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1259 | SETC_t();
|
nkeynes@417 | 1260 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1261 | }
|
nkeynes@359 | 1262 | break;
|
nkeynes@359 | 1263 | case 0xF:
|
nkeynes@359 | 1264 | { /* ADDV Rm, Rn */
|
nkeynes@359 | 1265 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1266 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1267 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1268 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1269 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1270 | SETO_t();
|
nkeynes@417 | 1271 | sh4_x86.tstate = TSTATE_O;
|
nkeynes@359 | 1272 | }
|
nkeynes@359 | 1273 | break;
|
nkeynes@359 | 1274 | default:
|
nkeynes@359 | 1275 | UNDEF();
|
nkeynes@359 | 1276 | break;
|
nkeynes@359 | 1277 | }
|
nkeynes@359 | 1278 | break;
|
nkeynes@359 | 1279 | case 0x4:
|
nkeynes@359 | 1280 | switch( ir&0xF ) {
|
nkeynes@359 | 1281 | case 0x0:
|
nkeynes@359 | 1282 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1283 | case 0x0:
|
nkeynes@359 | 1284 | { /* SHLL Rn */
|
nkeynes@359 | 1285 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1286 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1287 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1288 | SETC_t();
|
nkeynes@359 | 1289 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1290 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1291 | }
|
nkeynes@359 | 1292 | break;
|
nkeynes@359 | 1293 | case 0x1:
|
nkeynes@359 | 1294 | { /* DT Rn */
|
nkeynes@359 | 1295 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1296 | load_reg( R_EAX, Rn );
|
nkeynes@386 | 1297 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 1298 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1299 | SETE_t();
|
nkeynes@417 | 1300 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 1301 | }
|
nkeynes@359 | 1302 | break;
|
nkeynes@359 | 1303 | case 0x2:
|
nkeynes@359 | 1304 | { /* SHAL Rn */
|
nkeynes@359 | 1305 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1306 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1307 | SHL1_r32( R_EAX );
|
nkeynes@397 | 1308 | SETC_t();
|
nkeynes@359 | 1309 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1310 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1311 | }
|
nkeynes@359 | 1312 | break;
|
nkeynes@359 | 1313 | default:
|
nkeynes@359 | 1314 | UNDEF();
|
nkeynes@359 | 1315 | break;
|
nkeynes@359 | 1316 | }
|
nkeynes@359 | 1317 | break;
|
nkeynes@359 | 1318 | case 0x1:
|
nkeynes@359 | 1319 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1320 | case 0x0:
|
nkeynes@359 | 1321 | { /* SHLR Rn */
|
nkeynes@359 | 1322 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1323 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1324 | SHR1_r32( R_EAX );
|
nkeynes@397 | 1325 | SETC_t();
|
nkeynes@359 | 1326 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1327 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1328 | }
|
nkeynes@359 | 1329 | break;
|
nkeynes@359 | 1330 | case 0x1:
|
nkeynes@359 | 1331 | { /* CMP/PZ Rn */
|
nkeynes@359 | 1332 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1333 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1334 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1335 | SETGE_t();
|
nkeynes@417 | 1336 | sh4_x86.tstate = TSTATE_GE;
|
nkeynes@359 | 1337 | }
|
nkeynes@359 | 1338 | break;
|
nkeynes@359 | 1339 | case 0x2:
|
nkeynes@359 | 1340 | { /* SHAR Rn */
|
nkeynes@359 | 1341 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1342 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1343 | SAR1_r32( R_EAX );
|
nkeynes@397 | 1344 | SETC_t();
|
nkeynes@359 | 1345 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1346 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1347 | }
|
nkeynes@359 | 1348 | break;
|
nkeynes@359 | 1349 | default:
|
nkeynes@359 | 1350 | UNDEF();
|
nkeynes@359 | 1351 | break;
|
nkeynes@359 | 1352 | }
|
nkeynes@359 | 1353 | break;
|
nkeynes@359 | 1354 | case 0x2:
|
nkeynes@359 | 1355 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1356 | case 0x0:
|
nkeynes@359 | 1357 | { /* STS.L MACH, @-Rn */
|
nkeynes@359 | 1358 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1359 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1360 | check_walign32( R_EAX );
|
nkeynes@586 | 1361 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1362 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1363 | load_spreg( R_EDX, R_MACH );
|
nkeynes@586 | 1364 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1365 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1366 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1367 | }
|
nkeynes@359 | 1368 | break;
|
nkeynes@359 | 1369 | case 0x1:
|
nkeynes@359 | 1370 | { /* STS.L MACL, @-Rn */
|
nkeynes@359 | 1371 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1372 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1373 | check_walign32( R_EAX );
|
nkeynes@586 | 1374 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1375 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1376 | load_spreg( R_EDX, R_MACL );
|
nkeynes@586 | 1377 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1378 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1379 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1380 | }
|
nkeynes@359 | 1381 | break;
|
nkeynes@359 | 1382 | case 0x2:
|
nkeynes@359 | 1383 | { /* STS.L PR, @-Rn */
|
nkeynes@359 | 1384 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1385 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1386 | check_walign32( R_EAX );
|
nkeynes@586 | 1387 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1388 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1389 | load_spreg( R_EDX, R_PR );
|
nkeynes@586 | 1390 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1391 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1392 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1393 | }
|
nkeynes@359 | 1394 | break;
|
nkeynes@359 | 1395 | case 0x3:
|
nkeynes@359 | 1396 | { /* STC.L SGR, @-Rn */
|
nkeynes@359 | 1397 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1398 | check_priv();
|
nkeynes@586 | 1399 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1400 | check_walign32( R_EAX );
|
nkeynes@586 | 1401 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1402 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1403 | load_spreg( R_EDX, R_SGR );
|
nkeynes@586 | 1404 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1405 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1406 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1407 | }
|
nkeynes@359 | 1408 | break;
|
nkeynes@359 | 1409 | case 0x5:
|
nkeynes@359 | 1410 | { /* STS.L FPUL, @-Rn */
|
nkeynes@359 | 1411 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1412 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1413 | check_walign32( R_EAX );
|
nkeynes@586 | 1414 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1415 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1416 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@586 | 1417 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1418 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1419 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1420 | }
|
nkeynes@359 | 1421 | break;
|
nkeynes@359 | 1422 | case 0x6:
|
nkeynes@359 | 1423 | { /* STS.L FPSCR, @-Rn */
|
nkeynes@359 | 1424 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1425 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1426 | check_walign32( R_EAX );
|
nkeynes@586 | 1427 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1428 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1429 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@586 | 1430 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1431 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1432 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1433 | }
|
nkeynes@359 | 1434 | break;
|
nkeynes@359 | 1435 | case 0xF:
|
nkeynes@359 | 1436 | { /* STC.L DBR, @-Rn */
|
nkeynes@359 | 1437 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1438 | check_priv();
|
nkeynes@586 | 1439 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1440 | check_walign32( R_EAX );
|
nkeynes@586 | 1441 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1442 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1443 | load_spreg( R_EDX, R_DBR );
|
nkeynes@586 | 1444 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1445 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1446 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1447 | }
|
nkeynes@359 | 1448 | break;
|
nkeynes@359 | 1449 | default:
|
nkeynes@359 | 1450 | UNDEF();
|
nkeynes@359 | 1451 | break;
|
nkeynes@359 | 1452 | }
|
nkeynes@359 | 1453 | break;
|
nkeynes@359 | 1454 | case 0x3:
|
nkeynes@359 | 1455 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1456 | case 0x0:
|
nkeynes@359 | 1457 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1458 | case 0x0:
|
nkeynes@359 | 1459 | { /* STC.L SR, @-Rn */
|
nkeynes@359 | 1460 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1461 | check_priv();
|
nkeynes@586 | 1462 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1463 | check_walign32( R_EAX );
|
nkeynes@586 | 1464 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1465 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1466 | PUSH_realigned_r32( R_EAX );
|
nkeynes@395 | 1467 | call_func0( sh4_read_sr );
|
nkeynes@586 | 1468 | POP_realigned_r32( R_ECX );
|
nkeynes@586 | 1469 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@374 | 1470 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@417 | 1471 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1472 | }
|
nkeynes@359 | 1473 | break;
|
nkeynes@359 | 1474 | case 0x1:
|
nkeynes@359 | 1475 | { /* STC.L GBR, @-Rn */
|
nkeynes@359 | 1476 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1477 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1478 | check_walign32( R_EAX );
|
nkeynes@586 | 1479 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1480 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1481 | load_spreg( R_EDX, R_GBR );
|
nkeynes@586 | 1482 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1483 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1484 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1485 | }
|
nkeynes@359 | 1486 | break;
|
nkeynes@359 | 1487 | case 0x2:
|
nkeynes@359 | 1488 | { /* STC.L VBR, @-Rn */
|
nkeynes@359 | 1489 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1490 | check_priv();
|
nkeynes@586 | 1491 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1492 | check_walign32( R_EAX );
|
nkeynes@586 | 1493 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1494 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1495 | load_spreg( R_EDX, R_VBR );
|
nkeynes@586 | 1496 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1497 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1498 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1499 | }
|
nkeynes@359 | 1500 | break;
|
nkeynes@359 | 1501 | case 0x3:
|
nkeynes@359 | 1502 | { /* STC.L SSR, @-Rn */
|
nkeynes@359 | 1503 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1504 | check_priv();
|
nkeynes@586 | 1505 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1506 | check_walign32( R_EAX );
|
nkeynes@586 | 1507 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1508 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1509 | load_spreg( R_EDX, R_SSR );
|
nkeynes@586 | 1510 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1511 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1512 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1513 | }
|
nkeynes@359 | 1514 | break;
|
nkeynes@359 | 1515 | case 0x4:
|
nkeynes@359 | 1516 | { /* STC.L SPC, @-Rn */
|
nkeynes@359 | 1517 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1518 | check_priv();
|
nkeynes@586 | 1519 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1520 | check_walign32( R_EAX );
|
nkeynes@586 | 1521 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1522 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1523 | load_spreg( R_EDX, R_SPC );
|
nkeynes@586 | 1524 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1525 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1526 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1527 | }
|
nkeynes@359 | 1528 | break;
|
nkeynes@359 | 1529 | default:
|
nkeynes@359 | 1530 | UNDEF();
|
nkeynes@359 | 1531 | break;
|
nkeynes@359 | 1532 | }
|
nkeynes@359 | 1533 | break;
|
nkeynes@359 | 1534 | case 0x1:
|
nkeynes@359 | 1535 | { /* STC.L Rm_BANK, @-Rn */
|
nkeynes@359 | 1536 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
|
nkeynes@586 | 1537 | check_priv();
|
nkeynes@586 | 1538 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1539 | check_walign32( R_EAX );
|
nkeynes@586 | 1540 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 1541 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1542 | load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@586 | 1543 | ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 1544 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 1545 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1546 | }
|
nkeynes@359 | 1547 | break;
|
nkeynes@359 | 1548 | }
|
nkeynes@359 | 1549 | break;
|
nkeynes@359 | 1550 | case 0x4:
|
nkeynes@359 | 1551 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1552 | case 0x0:
|
nkeynes@359 | 1553 | { /* ROTL Rn */
|
nkeynes@359 | 1554 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1555 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1556 | ROL1_r32( R_EAX );
|
nkeynes@359 | 1557 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1558 | SETC_t();
|
nkeynes@417 | 1559 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1560 | }
|
nkeynes@359 | 1561 | break;
|
nkeynes@359 | 1562 | case 0x2:
|
nkeynes@359 | 1563 | { /* ROTCL Rn */
|
nkeynes@359 | 1564 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1565 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1566 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1567 | LDC_t();
|
nkeynes@417 | 1568 | }
|
nkeynes@359 | 1569 | RCL1_r32( R_EAX );
|
nkeynes@359 | 1570 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1571 | SETC_t();
|
nkeynes@417 | 1572 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1573 | }
|
nkeynes@359 | 1574 | break;
|
nkeynes@359 | 1575 | default:
|
nkeynes@359 | 1576 | UNDEF();
|
nkeynes@359 | 1577 | break;
|
nkeynes@359 | 1578 | }
|
nkeynes@359 | 1579 | break;
|
nkeynes@359 | 1580 | case 0x5:
|
nkeynes@359 | 1581 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1582 | case 0x0:
|
nkeynes@359 | 1583 | { /* ROTR Rn */
|
nkeynes@359 | 1584 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1585 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1586 | ROR1_r32( R_EAX );
|
nkeynes@359 | 1587 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1588 | SETC_t();
|
nkeynes@417 | 1589 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1590 | }
|
nkeynes@359 | 1591 | break;
|
nkeynes@359 | 1592 | case 0x1:
|
nkeynes@359 | 1593 | { /* CMP/PL Rn */
|
nkeynes@359 | 1594 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1595 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1596 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 1597 | SETG_t();
|
nkeynes@417 | 1598 | sh4_x86.tstate = TSTATE_G;
|
nkeynes@359 | 1599 | }
|
nkeynes@359 | 1600 | break;
|
nkeynes@359 | 1601 | case 0x2:
|
nkeynes@359 | 1602 | { /* ROTCR Rn */
|
nkeynes@359 | 1603 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1604 | load_reg( R_EAX, Rn );
|
nkeynes@417 | 1605 | if( sh4_x86.tstate != TSTATE_C ) {
|
nkeynes@417 | 1606 | LDC_t();
|
nkeynes@417 | 1607 | }
|
nkeynes@359 | 1608 | RCR1_r32( R_EAX );
|
nkeynes@359 | 1609 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1610 | SETC_t();
|
nkeynes@417 | 1611 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 1612 | }
|
nkeynes@359 | 1613 | break;
|
nkeynes@359 | 1614 | default:
|
nkeynes@359 | 1615 | UNDEF();
|
nkeynes@359 | 1616 | break;
|
nkeynes@359 | 1617 | }
|
nkeynes@359 | 1618 | break;
|
nkeynes@359 | 1619 | case 0x6:
|
nkeynes@359 | 1620 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1621 | case 0x0:
|
nkeynes@359 | 1622 | { /* LDS.L @Rm+, MACH */
|
nkeynes@359 | 1623 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1624 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1625 | check_ralign32( R_EAX );
|
nkeynes@586 | 1626 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1627 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1628 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1629 | store_spreg( R_EAX, R_MACH );
|
nkeynes@417 | 1630 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1631 | }
|
nkeynes@359 | 1632 | break;
|
nkeynes@359 | 1633 | case 0x1:
|
nkeynes@359 | 1634 | { /* LDS.L @Rm+, MACL */
|
nkeynes@359 | 1635 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1636 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1637 | check_ralign32( R_EAX );
|
nkeynes@586 | 1638 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1639 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1640 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1641 | store_spreg( R_EAX, R_MACL );
|
nkeynes@417 | 1642 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1643 | }
|
nkeynes@359 | 1644 | break;
|
nkeynes@359 | 1645 | case 0x2:
|
nkeynes@359 | 1646 | { /* LDS.L @Rm+, PR */
|
nkeynes@359 | 1647 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1648 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1649 | check_ralign32( R_EAX );
|
nkeynes@586 | 1650 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1651 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1652 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1653 | store_spreg( R_EAX, R_PR );
|
nkeynes@417 | 1654 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1655 | }
|
nkeynes@359 | 1656 | break;
|
nkeynes@359 | 1657 | case 0x3:
|
nkeynes@359 | 1658 | { /* LDC.L @Rm+, SGR */
|
nkeynes@359 | 1659 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1660 | check_priv();
|
nkeynes@359 | 1661 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1662 | check_ralign32( R_EAX );
|
nkeynes@586 | 1663 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1664 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1665 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1666 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1667 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1668 | }
|
nkeynes@359 | 1669 | break;
|
nkeynes@359 | 1670 | case 0x5:
|
nkeynes@359 | 1671 | { /* LDS.L @Rm+, FPUL */
|
nkeynes@359 | 1672 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1673 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1674 | check_ralign32( R_EAX );
|
nkeynes@586 | 1675 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1676 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1677 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1678 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 1679 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1680 | }
|
nkeynes@359 | 1681 | break;
|
nkeynes@359 | 1682 | case 0x6:
|
nkeynes@359 | 1683 | { /* LDS.L @Rm+, FPSCR */
|
nkeynes@359 | 1684 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1685 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1686 | check_ralign32( R_EAX );
|
nkeynes@586 | 1687 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1688 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1689 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1690 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1691 | update_fr_bank( R_EAX );
|
nkeynes@417 | 1692 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1693 | }
|
nkeynes@359 | 1694 | break;
|
nkeynes@359 | 1695 | case 0xF:
|
nkeynes@359 | 1696 | { /* LDC.L @Rm+, DBR */
|
nkeynes@359 | 1697 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1698 | check_priv();
|
nkeynes@359 | 1699 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1700 | check_ralign32( R_EAX );
|
nkeynes@586 | 1701 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1702 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1703 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1704 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1705 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1706 | }
|
nkeynes@359 | 1707 | break;
|
nkeynes@359 | 1708 | default:
|
nkeynes@359 | 1709 | UNDEF();
|
nkeynes@359 | 1710 | break;
|
nkeynes@359 | 1711 | }
|
nkeynes@359 | 1712 | break;
|
nkeynes@359 | 1713 | case 0x7:
|
nkeynes@359 | 1714 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 1715 | case 0x0:
|
nkeynes@359 | 1716 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 1717 | case 0x0:
|
nkeynes@359 | 1718 | { /* LDC.L @Rm+, SR */
|
nkeynes@359 | 1719 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1720 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 1721 | SLOTILLEGAL();
|
nkeynes@386 | 1722 | } else {
|
nkeynes@586 | 1723 | check_priv();
|
nkeynes@386 | 1724 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1725 | check_ralign32( R_EAX );
|
nkeynes@586 | 1726 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1727 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1728 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@386 | 1729 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 1730 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 1731 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 1732 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 1733 | }
|
nkeynes@359 | 1734 | }
|
nkeynes@359 | 1735 | break;
|
nkeynes@359 | 1736 | case 0x1:
|
nkeynes@359 | 1737 | { /* LDC.L @Rm+, GBR */
|
nkeynes@359 | 1738 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1739 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1740 | check_ralign32( R_EAX );
|
nkeynes@586 | 1741 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1742 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1743 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1744 | store_spreg( R_EAX, R_GBR );
|
nkeynes@417 | 1745 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1746 | }
|
nkeynes@359 | 1747 | break;
|
nkeynes@359 | 1748 | case 0x2:
|
nkeynes@359 | 1749 | { /* LDC.L @Rm+, VBR */
|
nkeynes@359 | 1750 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1751 | check_priv();
|
nkeynes@359 | 1752 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1753 | check_ralign32( R_EAX );
|
nkeynes@586 | 1754 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1755 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1756 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1757 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 1758 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1759 | }
|
nkeynes@359 | 1760 | break;
|
nkeynes@359 | 1761 | case 0x3:
|
nkeynes@359 | 1762 | { /* LDC.L @Rm+, SSR */
|
nkeynes@359 | 1763 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1764 | check_priv();
|
nkeynes@359 | 1765 | load_reg( R_EAX, Rm );
|
nkeynes@416 | 1766 | check_ralign32( R_EAX );
|
nkeynes@586 | 1767 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1768 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1769 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1770 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 1771 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1772 | }
|
nkeynes@359 | 1773 | break;
|
nkeynes@359 | 1774 | case 0x4:
|
nkeynes@359 | 1775 | { /* LDC.L @Rm+, SPC */
|
nkeynes@359 | 1776 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@586 | 1777 | check_priv();
|
nkeynes@359 | 1778 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1779 | check_ralign32( R_EAX );
|
nkeynes@586 | 1780 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1781 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1782 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@359 | 1783 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 1784 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1785 | }
|
nkeynes@359 | 1786 | break;
|
nkeynes@359 | 1787 | default:
|
nkeynes@359 | 1788 | UNDEF();
|
nkeynes@359 | 1789 | break;
|
nkeynes@359 | 1790 | }
|
nkeynes@359 | 1791 | break;
|
nkeynes@359 | 1792 | case 0x1:
|
nkeynes@359 | 1793 | { /* LDC.L @Rm+, Rn_BANK */
|
nkeynes@359 | 1794 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@586 | 1795 | check_priv();
|
nkeynes@374 | 1796 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 1797 | check_ralign32( R_EAX );
|
nkeynes@586 | 1798 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 1799 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 1800 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@374 | 1801 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 1802 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1803 | }
|
nkeynes@359 | 1804 | break;
|
nkeynes@359 | 1805 | }
|
nkeynes@359 | 1806 | break;
|
nkeynes@359 | 1807 | case 0x8:
|
nkeynes@359 | 1808 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1809 | case 0x0:
|
nkeynes@359 | 1810 | { /* SHLL2 Rn */
|
nkeynes@359 | 1811 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1812 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1813 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1814 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1815 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1816 | }
|
nkeynes@359 | 1817 | break;
|
nkeynes@359 | 1818 | case 0x1:
|
nkeynes@359 | 1819 | { /* SHLL8 Rn */
|
nkeynes@359 | 1820 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1821 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1822 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1823 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1824 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1825 | }
|
nkeynes@359 | 1826 | break;
|
nkeynes@359 | 1827 | case 0x2:
|
nkeynes@359 | 1828 | { /* SHLL16 Rn */
|
nkeynes@359 | 1829 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1830 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1831 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1832 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1833 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1834 | }
|
nkeynes@359 | 1835 | break;
|
nkeynes@359 | 1836 | default:
|
nkeynes@359 | 1837 | UNDEF();
|
nkeynes@359 | 1838 | break;
|
nkeynes@359 | 1839 | }
|
nkeynes@359 | 1840 | break;
|
nkeynes@359 | 1841 | case 0x9:
|
nkeynes@359 | 1842 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1843 | case 0x0:
|
nkeynes@359 | 1844 | { /* SHLR2 Rn */
|
nkeynes@359 | 1845 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1846 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1847 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 1848 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1849 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1850 | }
|
nkeynes@359 | 1851 | break;
|
nkeynes@359 | 1852 | case 0x1:
|
nkeynes@359 | 1853 | { /* SHLR8 Rn */
|
nkeynes@359 | 1854 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1855 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1856 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 1857 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1858 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1859 | }
|
nkeynes@359 | 1860 | break;
|
nkeynes@359 | 1861 | case 0x2:
|
nkeynes@359 | 1862 | { /* SHLR16 Rn */
|
nkeynes@359 | 1863 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@359 | 1864 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 1865 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 1866 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 1867 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1868 | }
|
nkeynes@359 | 1869 | break;
|
nkeynes@359 | 1870 | default:
|
nkeynes@359 | 1871 | UNDEF();
|
nkeynes@359 | 1872 | break;
|
nkeynes@359 | 1873 | }
|
nkeynes@359 | 1874 | break;
|
nkeynes@359 | 1875 | case 0xA:
|
nkeynes@359 | 1876 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1877 | case 0x0:
|
nkeynes@359 | 1878 | { /* LDS Rm, MACH */
|
nkeynes@359 | 1879 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1880 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1881 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 1882 | }
|
nkeynes@359 | 1883 | break;
|
nkeynes@359 | 1884 | case 0x1:
|
nkeynes@359 | 1885 | { /* LDS Rm, MACL */
|
nkeynes@359 | 1886 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1887 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1888 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 1889 | }
|
nkeynes@359 | 1890 | break;
|
nkeynes@359 | 1891 | case 0x2:
|
nkeynes@359 | 1892 | { /* LDS Rm, PR */
|
nkeynes@359 | 1893 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1894 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1895 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 1896 | }
|
nkeynes@359 | 1897 | break;
|
nkeynes@359 | 1898 | case 0x3:
|
nkeynes@359 | 1899 | { /* LDC Rm, SGR */
|
nkeynes@359 | 1900 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1901 | check_priv();
|
nkeynes@359 | 1902 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1903 | store_spreg( R_EAX, R_SGR );
|
nkeynes@417 | 1904 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1905 | }
|
nkeynes@359 | 1906 | break;
|
nkeynes@359 | 1907 | case 0x5:
|
nkeynes@359 | 1908 | { /* LDS Rm, FPUL */
|
nkeynes@359 | 1909 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1910 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1911 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 1912 | }
|
nkeynes@359 | 1913 | break;
|
nkeynes@359 | 1914 | case 0x6:
|
nkeynes@359 | 1915 | { /* LDS Rm, FPSCR */
|
nkeynes@359 | 1916 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 1917 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1918 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 1919 | update_fr_bank( R_EAX );
|
nkeynes@417 | 1920 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1921 | }
|
nkeynes@359 | 1922 | break;
|
nkeynes@359 | 1923 | case 0xF:
|
nkeynes@359 | 1924 | { /* LDC Rm, DBR */
|
nkeynes@359 | 1925 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 1926 | check_priv();
|
nkeynes@359 | 1927 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1928 | store_spreg( R_EAX, R_DBR );
|
nkeynes@417 | 1929 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1930 | }
|
nkeynes@359 | 1931 | break;
|
nkeynes@359 | 1932 | default:
|
nkeynes@359 | 1933 | UNDEF();
|
nkeynes@359 | 1934 | break;
|
nkeynes@359 | 1935 | }
|
nkeynes@359 | 1936 | break;
|
nkeynes@359 | 1937 | case 0xB:
|
nkeynes@359 | 1938 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 1939 | case 0x0:
|
nkeynes@359 | 1940 | { /* JSR @Rn */
|
nkeynes@359 | 1941 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1942 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1943 | SLOTILLEGAL();
|
nkeynes@374 | 1944 | } else {
|
nkeynes@590 | 1945 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 1946 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@374 | 1947 | store_spreg( R_EAX, R_PR );
|
nkeynes@408 | 1948 | load_reg( R_ECX, Rn );
|
nkeynes@590 | 1949 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@526 | 1950 | sh4_translate_instruction(pc+2);
|
nkeynes@590 | 1951 | exit_block_newpcset(pc+2);
|
nkeynes@409 | 1952 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1953 | return 4;
|
nkeynes@374 | 1954 | }
|
nkeynes@359 | 1955 | }
|
nkeynes@359 | 1956 | break;
|
nkeynes@359 | 1957 | case 0x1:
|
nkeynes@359 | 1958 | { /* TAS.B @Rn */
|
nkeynes@359 | 1959 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@586 | 1960 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 1961 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 1962 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 1963 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@361 | 1964 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 1965 | SETE_t();
|
nkeynes@361 | 1966 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@586 | 1967 | POP_realigned_r32( R_ECX );
|
nkeynes@361 | 1968 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 1969 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 1970 | }
|
nkeynes@359 | 1971 | break;
|
nkeynes@359 | 1972 | case 0x2:
|
nkeynes@359 | 1973 | { /* JMP @Rn */
|
nkeynes@359 | 1974 | uint32_t Rn = ((ir>>8)&0xF);
|
nkeynes@374 | 1975 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1976 | SLOTILLEGAL();
|
nkeynes@374 | 1977 | } else {
|
nkeynes@408 | 1978 | load_reg( R_ECX, Rn );
|
nkeynes@590 | 1979 | store_spreg( R_ECX, R_NEW_PC );
|
nkeynes@590 | 1980 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@526 | 1981 | sh4_translate_instruction(pc+2);
|
nkeynes@590 | 1982 | exit_block_newpcset(pc+2);
|
nkeynes@409 | 1983 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 1984 | return 4;
|
nkeynes@374 | 1985 | }
|
nkeynes@359 | 1986 | }
|
nkeynes@359 | 1987 | break;
|
nkeynes@359 | 1988 | default:
|
nkeynes@359 | 1989 | UNDEF();
|
nkeynes@359 | 1990 | break;
|
nkeynes@359 | 1991 | }
|
nkeynes@359 | 1992 | break;
|
nkeynes@359 | 1993 | case 0xC:
|
nkeynes@359 | 1994 | { /* SHAD Rm, Rn */
|
nkeynes@359 | 1995 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 1996 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 1997 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 1998 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1999 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 2000 | JGE_rel8(16, doshl);
|
nkeynes@361 | 2001 |
|
nkeynes@361 | 2002 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 2003 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2004 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 2005 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2006 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 2007 |
|
nkeynes@386 | 2008 | JMP_TARGET(emptysar);
|
nkeynes@386 | 2009 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 2010 | JMP_rel8(5, end2);
|
nkeynes@386 | 2011 |
|
nkeynes@380 | 2012 | JMP_TARGET(doshl);
|
nkeynes@361 | 2013 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 2014 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 2015 | JMP_TARGET(end);
|
nkeynes@386 | 2016 | JMP_TARGET(end2);
|
nkeynes@361 | 2017 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2018 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2019 | }
|
nkeynes@359 | 2020 | break;
|
nkeynes@359 | 2021 | case 0xD:
|
nkeynes@359 | 2022 | { /* SHLD Rm, Rn */
|
nkeynes@359 | 2023 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@368 | 2024 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 2025 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 2026 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 2027 | JGE_rel8(15, doshl);
|
nkeynes@368 | 2028 |
|
nkeynes@386 | 2029 | NEG_r32( R_ECX ); // 2
|
nkeynes@386 | 2030 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2031 | JE_rel8( 4, emptyshr );
|
nkeynes@386 | 2032 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2033 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 2034 |
|
nkeynes@386 | 2035 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 2036 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 2037 | JMP_rel8(5, end2);
|
nkeynes@386 | 2038 |
|
nkeynes@386 | 2039 | JMP_TARGET(doshl);
|
nkeynes@386 | 2040 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 2041 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 2042 | JMP_TARGET(end);
|
nkeynes@386 | 2043 | JMP_TARGET(end2);
|
nkeynes@368 | 2044 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2045 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2046 | }
|
nkeynes@359 | 2047 | break;
|
nkeynes@359 | 2048 | case 0xE:
|
nkeynes@359 | 2049 | switch( (ir&0x80) >> 7 ) {
|
nkeynes@359 | 2050 | case 0x0:
|
nkeynes@359 | 2051 | switch( (ir&0x70) >> 4 ) {
|
nkeynes@359 | 2052 | case 0x0:
|
nkeynes@359 | 2053 | { /* LDC Rm, SR */
|
nkeynes@359 | 2054 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2055 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2056 | SLOTILLEGAL();
|
nkeynes@386 | 2057 | } else {
|
nkeynes@386 | 2058 | check_priv();
|
nkeynes@386 | 2059 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2060 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2061 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2062 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@417 | 2063 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@386 | 2064 | }
|
nkeynes@359 | 2065 | }
|
nkeynes@359 | 2066 | break;
|
nkeynes@359 | 2067 | case 0x1:
|
nkeynes@359 | 2068 | { /* LDC Rm, GBR */
|
nkeynes@359 | 2069 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@359 | 2070 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2071 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2072 | }
|
nkeynes@359 | 2073 | break;
|
nkeynes@359 | 2074 | case 0x2:
|
nkeynes@359 | 2075 | { /* LDC Rm, VBR */
|
nkeynes@359 | 2076 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2077 | check_priv();
|
nkeynes@359 | 2078 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2079 | store_spreg( R_EAX, R_VBR );
|
nkeynes@417 | 2080 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2081 | }
|
nkeynes@359 | 2082 | break;
|
nkeynes@359 | 2083 | case 0x3:
|
nkeynes@359 | 2084 | { /* LDC Rm, SSR */
|
nkeynes@359 | 2085 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2086 | check_priv();
|
nkeynes@359 | 2087 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2088 | store_spreg( R_EAX, R_SSR );
|
nkeynes@417 | 2089 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2090 | }
|
nkeynes@359 | 2091 | break;
|
nkeynes@359 | 2092 | case 0x4:
|
nkeynes@359 | 2093 | { /* LDC Rm, SPC */
|
nkeynes@359 | 2094 | uint32_t Rm = ((ir>>8)&0xF);
|
nkeynes@386 | 2095 | check_priv();
|
nkeynes@359 | 2096 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2097 | store_spreg( R_EAX, R_SPC );
|
nkeynes@417 | 2098 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2099 | }
|
nkeynes@359 | 2100 | break;
|
nkeynes@359 | 2101 | default:
|
nkeynes@359 | 2102 | UNDEF();
|
nkeynes@359 | 2103 | break;
|
nkeynes@359 | 2104 | }
|
nkeynes@359 | 2105 | break;
|
nkeynes@359 | 2106 | case 0x1:
|
nkeynes@359 | 2107 | { /* LDC Rm, Rn_BANK */
|
nkeynes@359 | 2108 | uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
|
nkeynes@386 | 2109 | check_priv();
|
nkeynes@374 | 2110 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2111 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@417 | 2112 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2113 | }
|
nkeynes@359 | 2114 | break;
|
nkeynes@359 | 2115 | }
|
nkeynes@359 | 2116 | break;
|
nkeynes@359 | 2117 | case 0xF:
|
nkeynes@359 | 2118 | { /* MAC.W @Rm+, @Rn+ */
|
nkeynes@359 | 2119 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2120 | if( Rm == Rn ) {
|
nkeynes@586 | 2121 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2122 | check_ralign16( R_EAX );
|
nkeynes@586 | 2123 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2124 | PUSH_realigned_r32( R_EAX );
|
nkeynes@586 | 2125 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2126 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@596 | 2127 | MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
|
nkeynes@586 | 2128 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2129 | // Note translate twice in case of page boundaries. Maybe worth
|
nkeynes@586 | 2130 | // adding a page-boundary check to skip the second translation
|
nkeynes@586 | 2131 | } else {
|
nkeynes@586 | 2132 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2133 | check_ralign16( R_EAX );
|
nkeynes@586 | 2134 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@596 | 2135 | load_reg( R_ECX, Rn );
|
nkeynes@596 | 2136 | check_ralign16( R_ECX );
|
nkeynes@586 | 2137 | PUSH_realigned_r32( R_EAX );
|
nkeynes@596 | 2138 | MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
|
nkeynes@596 | 2139 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2140 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@586 | 2141 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2142 | }
|
nkeynes@586 | 2143 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 2144 | POP_r32( R_ECX );
|
nkeynes@586 | 2145 | PUSH_r32( R_EAX );
|
nkeynes@386 | 2146 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@547 | 2147 | POP_realigned_r32( R_ECX );
|
nkeynes@386 | 2148 | IMUL_r32( R_ECX );
|
nkeynes@386 | 2149 |
|
nkeynes@386 | 2150 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 2151 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 2152 | JE_rel8( 47, nosat );
|
nkeynes@386 | 2153 |
|
nkeynes@386 | 2154 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2155 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 2156 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 2157 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2158 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 2159 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 2160 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2161 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 2162 |
|
nkeynes@386 | 2163 | JMP_TARGET(positive);
|
nkeynes@386 | 2164 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 2165 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2166 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 2167 |
|
nkeynes@386 | 2168 | JMP_TARGET(nosat);
|
nkeynes@386 | 2169 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 2170 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 2171 | JMP_TARGET(end);
|
nkeynes@386 | 2172 | JMP_TARGET(end2);
|
nkeynes@386 | 2173 | JMP_TARGET(end3);
|
nkeynes@417 | 2174 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2175 | }
|
nkeynes@359 | 2176 | break;
|
nkeynes@359 | 2177 | }
|
nkeynes@359 | 2178 | break;
|
nkeynes@359 | 2179 | case 0x5:
|
nkeynes@359 | 2180 | { /* MOV.L @(disp, Rm), Rn */
|
nkeynes@359 | 2181 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
|
nkeynes@586 | 2182 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2183 | ADD_imm8s_r32( disp, R_EAX );
|
nkeynes@586 | 2184 | check_ralign32( R_EAX );
|
nkeynes@586 | 2185 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2186 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2187 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2188 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2189 | }
|
nkeynes@359 | 2190 | break;
|
nkeynes@359 | 2191 | case 0x6:
|
nkeynes@359 | 2192 | switch( ir&0xF ) {
|
nkeynes@359 | 2193 | case 0x0:
|
nkeynes@359 | 2194 | { /* MOV.B @Rm, Rn */
|
nkeynes@359 | 2195 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2196 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2197 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2198 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@386 | 2199 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2200 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2201 | }
|
nkeynes@359 | 2202 | break;
|
nkeynes@359 | 2203 | case 0x1:
|
nkeynes@359 | 2204 | { /* MOV.W @Rm, Rn */
|
nkeynes@359 | 2205 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2206 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2207 | check_ralign16( R_EAX );
|
nkeynes@586 | 2208 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2209 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2210 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2211 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2212 | }
|
nkeynes@359 | 2213 | break;
|
nkeynes@359 | 2214 | case 0x2:
|
nkeynes@359 | 2215 | { /* MOV.L @Rm, Rn */
|
nkeynes@359 | 2216 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2217 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2218 | check_ralign32( R_EAX );
|
nkeynes@586 | 2219 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2220 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2221 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2222 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2223 | }
|
nkeynes@359 | 2224 | break;
|
nkeynes@359 | 2225 | case 0x3:
|
nkeynes@359 | 2226 | { /* MOV Rm, Rn */
|
nkeynes@359 | 2227 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2228 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2229 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2230 | }
|
nkeynes@359 | 2231 | break;
|
nkeynes@359 | 2232 | case 0x4:
|
nkeynes@359 | 2233 | { /* MOV.B @Rm+, Rn */
|
nkeynes@359 | 2234 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2235 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2236 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2237 | ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2238 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2239 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2240 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2241 | }
|
nkeynes@359 | 2242 | break;
|
nkeynes@359 | 2243 | case 0x5:
|
nkeynes@359 | 2244 | { /* MOV.W @Rm+, Rn */
|
nkeynes@359 | 2245 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2246 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2247 | check_ralign16( R_EAX );
|
nkeynes@586 | 2248 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2249 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2250 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2251 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2252 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2253 | }
|
nkeynes@359 | 2254 | break;
|
nkeynes@359 | 2255 | case 0x6:
|
nkeynes@359 | 2256 | { /* MOV.L @Rm+, Rn */
|
nkeynes@359 | 2257 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2258 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2259 | check_ralign32( R_EAX );
|
nkeynes@586 | 2260 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2261 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 2262 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2263 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2264 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2265 | }
|
nkeynes@359 | 2266 | break;
|
nkeynes@359 | 2267 | case 0x7:
|
nkeynes@359 | 2268 | { /* NOT Rm, Rn */
|
nkeynes@359 | 2269 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2270 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2271 | NOT_r32( R_EAX );
|
nkeynes@359 | 2272 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2273 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2274 | }
|
nkeynes@359 | 2275 | break;
|
nkeynes@359 | 2276 | case 0x8:
|
nkeynes@359 | 2277 | { /* SWAP.B Rm, Rn */
|
nkeynes@359 | 2278 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2279 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2280 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 2281 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2282 | }
|
nkeynes@359 | 2283 | break;
|
nkeynes@359 | 2284 | case 0x9:
|
nkeynes@359 | 2285 | { /* SWAP.W Rm, Rn */
|
nkeynes@359 | 2286 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2287 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2288 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2289 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 2290 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 2291 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2292 | store_reg( R_ECX, Rn );
|
nkeynes@417 | 2293 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2294 | }
|
nkeynes@359 | 2295 | break;
|
nkeynes@359 | 2296 | case 0xA:
|
nkeynes@359 | 2297 | { /* NEGC Rm, Rn */
|
nkeynes@359 | 2298 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2299 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2300 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 2301 | LDC_t();
|
nkeynes@359 | 2302 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2303 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2304 | SETC_t();
|
nkeynes@417 | 2305 | sh4_x86.tstate = TSTATE_C;
|
nkeynes@359 | 2306 | }
|
nkeynes@359 | 2307 | break;
|
nkeynes@359 | 2308 | case 0xB:
|
nkeynes@359 | 2309 | { /* NEG Rm, Rn */
|
nkeynes@359 | 2310 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2311 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2312 | NEG_r32( R_EAX );
|
nkeynes@359 | 2313 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2314 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2315 | }
|
nkeynes@359 | 2316 | break;
|
nkeynes@359 | 2317 | case 0xC:
|
nkeynes@359 | 2318 | { /* EXTU.B Rm, Rn */
|
nkeynes@359 | 2319 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2320 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2321 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2322 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2323 | }
|
nkeynes@359 | 2324 | break;
|
nkeynes@359 | 2325 | case 0xD:
|
nkeynes@359 | 2326 | { /* EXTU.W Rm, Rn */
|
nkeynes@359 | 2327 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2328 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2329 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2330 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2331 | }
|
nkeynes@359 | 2332 | break;
|
nkeynes@359 | 2333 | case 0xE:
|
nkeynes@359 | 2334 | { /* EXTS.B Rm, Rn */
|
nkeynes@359 | 2335 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@359 | 2336 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2337 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 2338 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2339 | }
|
nkeynes@359 | 2340 | break;
|
nkeynes@359 | 2341 | case 0xF:
|
nkeynes@359 | 2342 | { /* EXTS.W Rm, Rn */
|
nkeynes@359 | 2343 | uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@361 | 2344 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 2345 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 2346 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2347 | }
|
nkeynes@359 | 2348 | break;
|
nkeynes@359 | 2349 | }
|
nkeynes@359 | 2350 | break;
|
nkeynes@359 | 2351 | case 0x7:
|
nkeynes@359 | 2352 | { /* ADD #imm, Rn */
|
nkeynes@359 | 2353 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2354 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 2355 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 2356 | store_reg( R_EAX, Rn );
|
nkeynes@417 | 2357 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2358 | }
|
nkeynes@359 | 2359 | break;
|
nkeynes@359 | 2360 | case 0x8:
|
nkeynes@359 | 2361 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2362 | case 0x0:
|
nkeynes@359 | 2363 | { /* MOV.B R0, @(disp, Rn) */
|
nkeynes@359 | 2364 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@586 | 2365 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2366 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2367 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2368 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2369 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 2370 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2371 | }
|
nkeynes@359 | 2372 | break;
|
nkeynes@359 | 2373 | case 0x1:
|
nkeynes@359 | 2374 | { /* MOV.W R0, @(disp, Rn) */
|
nkeynes@359 | 2375 | uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@586 | 2376 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2377 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2378 | check_walign16( R_EAX );
|
nkeynes@586 | 2379 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2380 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2381 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 2382 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2383 | }
|
nkeynes@359 | 2384 | break;
|
nkeynes@359 | 2385 | case 0x4:
|
nkeynes@359 | 2386 | { /* MOV.B @(disp, Rm), R0 */
|
nkeynes@359 | 2387 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
|
nkeynes@586 | 2388 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2389 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2390 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2391 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2392 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2393 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2394 | }
|
nkeynes@359 | 2395 | break;
|
nkeynes@359 | 2396 | case 0x5:
|
nkeynes@359 | 2397 | { /* MOV.W @(disp, Rm), R0 */
|
nkeynes@359 | 2398 | uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
|
nkeynes@586 | 2399 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2400 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2401 | check_ralign16( R_EAX );
|
nkeynes@586 | 2402 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2403 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2404 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2405 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2406 | }
|
nkeynes@359 | 2407 | break;
|
nkeynes@359 | 2408 | case 0x8:
|
nkeynes@359 | 2409 | { /* CMP/EQ #imm, R0 */
|
nkeynes@359 | 2410 | int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2411 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2412 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 2413 | SETE_t();
|
nkeynes@417 | 2414 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2415 | }
|
nkeynes@359 | 2416 | break;
|
nkeynes@359 | 2417 | case 0x9:
|
nkeynes@359 | 2418 | { /* BT disp */
|
nkeynes@359 | 2419 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2420 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2421 | SLOTILLEGAL();
|
nkeynes@374 | 2422 | } else {
|
nkeynes@586 | 2423 | sh4vma_t target = disp + pc + 4;
|
nkeynes@586 | 2424 | JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
|
nkeynes@586 | 2425 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 2426 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2427 | return 2;
|
nkeynes@374 | 2428 | }
|
nkeynes@359 | 2429 | }
|
nkeynes@359 | 2430 | break;
|
nkeynes@359 | 2431 | case 0xB:
|
nkeynes@359 | 2432 | { /* BF disp */
|
nkeynes@359 | 2433 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2434 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2435 | SLOTILLEGAL();
|
nkeynes@374 | 2436 | } else {
|
nkeynes@586 | 2437 | sh4vma_t target = disp + pc + 4;
|
nkeynes@586 | 2438 | JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
|
nkeynes@586 | 2439 | exit_block_rel(target, pc+2 );
|
nkeynes@380 | 2440 | JMP_TARGET(nottaken);
|
nkeynes@408 | 2441 | return 2;
|
nkeynes@374 | 2442 | }
|
nkeynes@359 | 2443 | }
|
nkeynes@359 | 2444 | break;
|
nkeynes@359 | 2445 | case 0xD:
|
nkeynes@359 | 2446 | { /* BT/S disp */
|
nkeynes@359 | 2447 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2448 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2449 | SLOTILLEGAL();
|
nkeynes@374 | 2450 | } else {
|
nkeynes@590 | 2451 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 2452 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 2453 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 2454 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 2455 | }
|
nkeynes@417 | 2456 | OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
|
nkeynes@526 | 2457 | sh4_translate_instruction(pc+2);
|
nkeynes@586 | 2458 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@408 | 2459 | // not taken
|
nkeynes@408 | 2460 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 2461 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2462 | return 4;
|
nkeynes@374 | 2463 | }
|
nkeynes@359 | 2464 | }
|
nkeynes@359 | 2465 | break;
|
nkeynes@359 | 2466 | case 0xF:
|
nkeynes@359 | 2467 | { /* BF/S disp */
|
nkeynes@359 | 2468 | int32_t disp = SIGNEXT8(ir&0xFF)<<1;
|
nkeynes@374 | 2469 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2470 | SLOTILLEGAL();
|
nkeynes@374 | 2471 | } else {
|
nkeynes@586 | 2472 | sh4vma_t target = disp + pc + 4;
|
nkeynes@590 | 2473 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@417 | 2474 | if( sh4_x86.tstate == TSTATE_NONE ) {
|
nkeynes@417 | 2475 | CMP_imm8s_sh4r( 1, R_T );
|
nkeynes@417 | 2476 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@417 | 2477 | }
|
nkeynes@417 | 2478 | OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
|
nkeynes@526 | 2479 | sh4_translate_instruction(pc+2);
|
nkeynes@586 | 2480 | exit_block_rel( target, pc+4 );
|
nkeynes@408 | 2481 | // not taken
|
nkeynes@408 | 2482 | *patch = (xlat_output - ((uint8_t *)patch)) - 4;
|
nkeynes@526 | 2483 | sh4_translate_instruction(pc+2);
|
nkeynes@408 | 2484 | return 4;
|
nkeynes@374 | 2485 | }
|
nkeynes@359 | 2486 | }
|
nkeynes@359 | 2487 | break;
|
nkeynes@359 | 2488 | default:
|
nkeynes@359 | 2489 | UNDEF();
|
nkeynes@359 | 2490 | break;
|
nkeynes@359 | 2491 | }
|
nkeynes@359 | 2492 | break;
|
nkeynes@359 | 2493 | case 0x9:
|
nkeynes@359 | 2494 | { /* MOV.W @(disp, PC), Rn */
|
nkeynes@359 | 2495 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@374 | 2496 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2497 | SLOTILLEGAL();
|
nkeynes@374 | 2498 | } else {
|
nkeynes@586 | 2499 | // See comments for MOV.L @(disp, PC), Rn
|
nkeynes@586 | 2500 | uint32_t target = pc + disp + 4;
|
nkeynes@586 | 2501 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 2502 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@586 | 2503 | MOV_moff32_EAX( ptr );
|
nkeynes@586 | 2504 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@586 | 2505 | } else {
|
nkeynes@586 | 2506 | load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
|
nkeynes@586 | 2507 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 2508 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2509 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@586 | 2510 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@586 | 2511 | }
|
nkeynes@374 | 2512 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2513 | }
|
nkeynes@359 | 2514 | }
|
nkeynes@359 | 2515 | break;
|
nkeynes@359 | 2516 | case 0xA:
|
nkeynes@359 | 2517 | { /* BRA disp */
|
nkeynes@359 | 2518 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2519 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2520 | SLOTILLEGAL();
|
nkeynes@374 | 2521 | } else {
|
nkeynes@590 | 2522 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@526 | 2523 | sh4_translate_instruction( pc + 2 );
|
nkeynes@586 | 2524 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@409 | 2525 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2526 | return 4;
|
nkeynes@374 | 2527 | }
|
nkeynes@359 | 2528 | }
|
nkeynes@359 | 2529 | break;
|
nkeynes@359 | 2530 | case 0xB:
|
nkeynes@359 | 2531 | { /* BSR disp */
|
nkeynes@359 | 2532 | int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
|
nkeynes@374 | 2533 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2534 | SLOTILLEGAL();
|
nkeynes@374 | 2535 | } else {
|
nkeynes@590 | 2536 | load_spreg( R_EAX, R_PC );
|
nkeynes@590 | 2537 | ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
|
nkeynes@374 | 2538 | store_spreg( R_EAX, R_PR );
|
nkeynes@590 | 2539 | sh4_x86.in_delay_slot = DELAY_PC;
|
nkeynes@526 | 2540 | sh4_translate_instruction( pc + 2 );
|
nkeynes@586 | 2541 | exit_block_rel( disp + pc + 4, pc+4 );
|
nkeynes@409 | 2542 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2543 | return 4;
|
nkeynes@374 | 2544 | }
|
nkeynes@359 | 2545 | }
|
nkeynes@359 | 2546 | break;
|
nkeynes@359 | 2547 | case 0xC:
|
nkeynes@359 | 2548 | switch( (ir&0xF00) >> 8 ) {
|
nkeynes@359 | 2549 | case 0x0:
|
nkeynes@359 | 2550 | { /* MOV.B R0, @(disp, GBR) */
|
nkeynes@359 | 2551 | uint32_t disp = (ir&0xFF);
|
nkeynes@586 | 2552 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2553 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2554 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2555 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2556 | MEM_WRITE_BYTE( R_EAX, R_EDX );
|
nkeynes@417 | 2557 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2558 | }
|
nkeynes@359 | 2559 | break;
|
nkeynes@359 | 2560 | case 0x1:
|
nkeynes@359 | 2561 | { /* MOV.W R0, @(disp, GBR) */
|
nkeynes@359 | 2562 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@586 | 2563 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2564 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2565 | check_walign16( R_EAX );
|
nkeynes@586 | 2566 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2567 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2568 | MEM_WRITE_WORD( R_EAX, R_EDX );
|
nkeynes@417 | 2569 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2570 | }
|
nkeynes@359 | 2571 | break;
|
nkeynes@359 | 2572 | case 0x2:
|
nkeynes@359 | 2573 | { /* MOV.L R0, @(disp, GBR) */
|
nkeynes@359 | 2574 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@586 | 2575 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2576 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2577 | check_walign32( R_EAX );
|
nkeynes@586 | 2578 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2579 | load_reg( R_EDX, 0 );
|
nkeynes@586 | 2580 | MEM_WRITE_LONG( R_EAX, R_EDX );
|
nkeynes@417 | 2581 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2582 | }
|
nkeynes@359 | 2583 | break;
|
nkeynes@359 | 2584 | case 0x3:
|
nkeynes@359 | 2585 | { /* TRAPA #imm */
|
nkeynes@359 | 2586 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2587 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2588 | SLOTILLEGAL();
|
nkeynes@374 | 2589 | } else {
|
nkeynes@590 | 2590 | load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 5
|
nkeynes@590 | 2591 | ADD_r32_sh4r( R_ECX, R_PC );
|
nkeynes@527 | 2592 | load_imm32( R_EAX, imm );
|
nkeynes@527 | 2593 | call_func1( sh4_raise_trap, R_EAX );
|
nkeynes@417 | 2594 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@408 | 2595 | exit_block_pcset(pc);
|
nkeynes@409 | 2596 | sh4_x86.branch_taken = TRUE;
|
nkeynes@408 | 2597 | return 2;
|
nkeynes@374 | 2598 | }
|
nkeynes@359 | 2599 | }
|
nkeynes@359 | 2600 | break;
|
nkeynes@359 | 2601 | case 0x4:
|
nkeynes@359 | 2602 | { /* MOV.B @(disp, GBR), R0 */
|
nkeynes@359 | 2603 | uint32_t disp = (ir&0xFF);
|
nkeynes@586 | 2604 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2605 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2606 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2607 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@359 | 2608 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2609 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2610 | }
|
nkeynes@359 | 2611 | break;
|
nkeynes@359 | 2612 | case 0x5:
|
nkeynes@359 | 2613 | { /* MOV.W @(disp, GBR), R0 */
|
nkeynes@359 | 2614 | uint32_t disp = (ir&0xFF)<<1;
|
nkeynes@586 | 2615 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2616 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2617 | check_ralign16( R_EAX );
|
nkeynes@586 | 2618 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2619 | MEM_READ_WORD( R_EAX, R_EAX );
|
nkeynes@361 | 2620 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2621 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2622 | }
|
nkeynes@359 | 2623 | break;
|
nkeynes@359 | 2624 | case 0x6:
|
nkeynes@359 | 2625 | { /* MOV.L @(disp, GBR), R0 */
|
nkeynes@359 | 2626 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@586 | 2627 | load_spreg( R_EAX, R_GBR );
|
nkeynes@586 | 2628 | ADD_imm32_r32( disp, R_EAX );
|
nkeynes@586 | 2629 | check_ralign32( R_EAX );
|
nkeynes@586 | 2630 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2631 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@361 | 2632 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2633 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2634 | }
|
nkeynes@359 | 2635 | break;
|
nkeynes@359 | 2636 | case 0x7:
|
nkeynes@359 | 2637 | { /* MOVA @(disp, PC), R0 */
|
nkeynes@359 | 2638 | uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2639 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2640 | SLOTILLEGAL();
|
nkeynes@374 | 2641 | } else {
|
nkeynes@586 | 2642 | load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 2643 | ADD_sh4r_r32( R_PC, R_ECX );
|
nkeynes@374 | 2644 | store_reg( R_ECX, 0 );
|
nkeynes@586 | 2645 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@374 | 2646 | }
|
nkeynes@359 | 2647 | }
|
nkeynes@359 | 2648 | break;
|
nkeynes@359 | 2649 | case 0x8:
|
nkeynes@359 | 2650 | { /* TST #imm, R0 */
|
nkeynes@359 | 2651 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2652 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 2653 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 2654 | SETE_t();
|
nkeynes@417 | 2655 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2656 | }
|
nkeynes@359 | 2657 | break;
|
nkeynes@359 | 2658 | case 0x9:
|
nkeynes@359 | 2659 | { /* AND #imm, R0 */
|
nkeynes@359 | 2660 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2661 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2662 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2663 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2664 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2665 | }
|
nkeynes@359 | 2666 | break;
|
nkeynes@359 | 2667 | case 0xA:
|
nkeynes@359 | 2668 | { /* XOR #imm, R0 */
|
nkeynes@359 | 2669 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2670 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2671 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2672 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2673 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2674 | }
|
nkeynes@359 | 2675 | break;
|
nkeynes@359 | 2676 | case 0xB:
|
nkeynes@359 | 2677 | { /* OR #imm, R0 */
|
nkeynes@359 | 2678 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2679 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2680 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 2681 | store_reg( R_EAX, 0 );
|
nkeynes@417 | 2682 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2683 | }
|
nkeynes@359 | 2684 | break;
|
nkeynes@359 | 2685 | case 0xC:
|
nkeynes@359 | 2686 | { /* TST.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2687 | uint32_t imm = (ir&0xFF);
|
nkeynes@368 | 2688 | load_reg( R_EAX, 0);
|
nkeynes@368 | 2689 | load_reg( R_ECX, R_GBR);
|
nkeynes@586 | 2690 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2691 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2692 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@394 | 2693 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 2694 | SETE_t();
|
nkeynes@417 | 2695 | sh4_x86.tstate = TSTATE_E;
|
nkeynes@359 | 2696 | }
|
nkeynes@359 | 2697 | break;
|
nkeynes@359 | 2698 | case 0xD:
|
nkeynes@359 | 2699 | { /* AND.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2700 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2701 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2702 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2703 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2704 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2705 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2706 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 2707 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 2708 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 2709 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2710 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2711 | }
|
nkeynes@359 | 2712 | break;
|
nkeynes@359 | 2713 | case 0xE:
|
nkeynes@359 | 2714 | { /* XOR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2715 | uint32_t imm = (ir&0xFF);
|
nkeynes@359 | 2716 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 2717 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2718 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2719 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2720 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2721 | MEM_READ_BYTE(R_EAX, R_EAX);
|
nkeynes@547 | 2722 | POP_realigned_r32(R_ECX);
|
nkeynes@359 | 2723 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 2724 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2725 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2726 | }
|
nkeynes@359 | 2727 | break;
|
nkeynes@359 | 2728 | case 0xF:
|
nkeynes@359 | 2729 | { /* OR.B #imm, @(R0, GBR) */
|
nkeynes@359 | 2730 | uint32_t imm = (ir&0xFF);
|
nkeynes@374 | 2731 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 2732 | load_spreg( R_ECX, R_GBR );
|
nkeynes@586 | 2733 | ADD_r32_r32( R_ECX, R_EAX );
|
nkeynes@586 | 2734 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@586 | 2735 | PUSH_realigned_r32(R_EAX);
|
nkeynes@586 | 2736 | MEM_READ_BYTE( R_EAX, R_EAX );
|
nkeynes@547 | 2737 | POP_realigned_r32(R_ECX);
|
nkeynes@386 | 2738 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 2739 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@417 | 2740 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2741 | }
|
nkeynes@359 | 2742 | break;
|
nkeynes@359 | 2743 | }
|
nkeynes@359 | 2744 | break;
|
nkeynes@359 | 2745 | case 0xD:
|
nkeynes@359 | 2746 | { /* MOV.L @(disp, PC), Rn */
|
nkeynes@359 | 2747 | uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
|
nkeynes@374 | 2748 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 2749 | SLOTILLEGAL();
|
nkeynes@374 | 2750 | } else {
|
nkeynes@388 | 2751 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@586 | 2752 | if( IS_IN_ICACHE(target) ) {
|
nkeynes@586 | 2753 | // If the target address is in the same page as the code, it's
|
nkeynes@586 | 2754 | // pretty safe to just ref it directly and circumvent the whole
|
nkeynes@586 | 2755 | // memory subsystem. (this is a big performance win)
|
nkeynes@586 | 2756 |
|
nkeynes@586 | 2757 | // FIXME: There's a corner-case that's not handled here when
|
nkeynes@586 | 2758 | // the current code-page is in the ITLB but not in the UTLB.
|
nkeynes@586 | 2759 | // (should generate a TLB miss although need to test SH4
|
nkeynes@586 | 2760 | // behaviour to confirm) Unlikely to be anyone depending on this
|
nkeynes@586 | 2761 | // behaviour though.
|
nkeynes@586 | 2762 | sh4ptr_t ptr = GET_ICACHE_PTR(target);
|
nkeynes@527 | 2763 | MOV_moff32_EAX( ptr );
|
nkeynes@388 | 2764 | } else {
|
nkeynes@586 | 2765 | // Note: we use sh4r.pc for the calc as we could be running at a
|
nkeynes@586 | 2766 | // different virtual address than the translation was done with,
|
nkeynes@586 | 2767 | // but we can safely assume that the low bits are the same.
|
nkeynes@586 | 2768 | load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
|
nkeynes@586 | 2769 | ADD_sh4r_r32( R_PC, R_EAX );
|
nkeynes@586 | 2770 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@586 | 2771 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@586 | 2772 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@388 | 2773 | }
|
nkeynes@386 | 2774 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 2775 | }
|
nkeynes@359 | 2776 | }
|
nkeynes@359 | 2777 | break;
|
nkeynes@359 | 2778 | case 0xE:
|
nkeynes@359 | 2779 | { /* MOV #imm, Rn */
|
nkeynes@359 | 2780 | uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
|
nkeynes@359 | 2781 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 2782 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2783 | }
|
nkeynes@359 | 2784 | break;
|
nkeynes@359 | 2785 | case 0xF:
|
nkeynes@359 | 2786 | switch( ir&0xF ) {
|
nkeynes@359 | 2787 | case 0x0:
|
nkeynes@359 | 2788 | { /* FADD FRm, FRn */
|
nkeynes@359 | 2789 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2790 | check_fpuen();
|
nkeynes@377 | 2791 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2792 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2793 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2794 | JNE_rel8(13,doubleprec);
|
nkeynes@377 | 2795 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2796 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2797 | FADDP_st(1);
|
nkeynes@377 | 2798 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2799 | JMP_rel8(11,end);
|
nkeynes@380 | 2800 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2801 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2802 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2803 | FADDP_st(1);
|
nkeynes@377 | 2804 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2805 | JMP_TARGET(end);
|
nkeynes@417 | 2806 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2807 | }
|
nkeynes@359 | 2808 | break;
|
nkeynes@359 | 2809 | case 0x1:
|
nkeynes@359 | 2810 | { /* FSUB FRm, FRn */
|
nkeynes@359 | 2811 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2812 | check_fpuen();
|
nkeynes@377 | 2813 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2814 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2815 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2816 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2817 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2818 | push_fr(R_EDX, FRm);
|
nkeynes@388 | 2819 | FSUBP_st(1);
|
nkeynes@377 | 2820 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2821 | JMP_rel8(11, end);
|
nkeynes@380 | 2822 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2823 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2824 | push_dr(R_EDX, FRm);
|
nkeynes@388 | 2825 | FSUBP_st(1);
|
nkeynes@377 | 2826 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2827 | JMP_TARGET(end);
|
nkeynes@417 | 2828 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2829 | }
|
nkeynes@359 | 2830 | break;
|
nkeynes@359 | 2831 | case 0x2:
|
nkeynes@359 | 2832 | { /* FMUL FRm, FRn */
|
nkeynes@359 | 2833 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2834 | check_fpuen();
|
nkeynes@377 | 2835 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2836 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2837 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2838 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2839 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2840 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2841 | FMULP_st(1);
|
nkeynes@377 | 2842 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2843 | JMP_rel8(11, end);
|
nkeynes@380 | 2844 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2845 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2846 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2847 | FMULP_st(1);
|
nkeynes@377 | 2848 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2849 | JMP_TARGET(end);
|
nkeynes@417 | 2850 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2851 | }
|
nkeynes@359 | 2852 | break;
|
nkeynes@359 | 2853 | case 0x3:
|
nkeynes@359 | 2854 | { /* FDIV FRm, FRn */
|
nkeynes@359 | 2855 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2856 | check_fpuen();
|
nkeynes@377 | 2857 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2858 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2859 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2860 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 2861 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 2862 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2863 | FDIVP_st(1);
|
nkeynes@377 | 2864 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 2865 | JMP_rel8(11, end);
|
nkeynes@380 | 2866 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2867 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 2868 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2869 | FDIVP_st(1);
|
nkeynes@377 | 2870 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 2871 | JMP_TARGET(end);
|
nkeynes@417 | 2872 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2873 | }
|
nkeynes@359 | 2874 | break;
|
nkeynes@359 | 2875 | case 0x4:
|
nkeynes@359 | 2876 | { /* FCMP/EQ FRm, FRn */
|
nkeynes@359 | 2877 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2878 | check_fpuen();
|
nkeynes@377 | 2879 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2880 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2881 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2882 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2883 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2884 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2885 | JMP_rel8(6, end);
|
nkeynes@380 | 2886 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2887 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2888 | push_dr(R_EDX, FRn);
|
nkeynes@386 | 2889 | JMP_TARGET(end);
|
nkeynes@377 | 2890 | FCOMIP_st(1);
|
nkeynes@377 | 2891 | SETE_t();
|
nkeynes@377 | 2892 | FPOP_st();
|
nkeynes@417 | 2893 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2894 | }
|
nkeynes@359 | 2895 | break;
|
nkeynes@359 | 2896 | case 0x5:
|
nkeynes@359 | 2897 | { /* FCMP/GT FRm, FRn */
|
nkeynes@359 | 2898 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 2899 | check_fpuen();
|
nkeynes@377 | 2900 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2901 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 2902 | load_fr_bank( R_EDX );
|
nkeynes@380 | 2903 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 2904 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 2905 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 2906 | JMP_rel8(6, end);
|
nkeynes@380 | 2907 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2908 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 2909 | push_dr(R_EDX, FRn);
|
nkeynes@380 | 2910 | JMP_TARGET(end);
|
nkeynes@377 | 2911 | FCOMIP_st(1);
|
nkeynes@377 | 2912 | SETA_t();
|
nkeynes@377 | 2913 | FPOP_st();
|
nkeynes@417 | 2914 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 2915 | }
|
nkeynes@359 | 2916 | break;
|
nkeynes@359 | 2917 | case 0x6:
|
nkeynes@359 | 2918 | { /* FMOV @(R0, Rm), FRn */
|
nkeynes@359 | 2919 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2920 | check_fpuen();
|
nkeynes@586 | 2921 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2922 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
|
nkeynes@586 | 2923 | check_ralign32( R_EAX );
|
nkeynes@586 | 2924 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@416 | 2925 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 2926 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@586 | 2927 | JNE_rel8(8 + MEM_READ_SIZE, doublesize);
|
nkeynes@586 | 2928 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@416 | 2929 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2930 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 2931 | if( FRn&1 ) {
|
nkeynes@527 | 2932 | JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 2933 | JMP_TARGET(doublesize);
|
nkeynes@586 | 2934 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@416 | 2935 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@416 | 2936 | load_xf_bank( R_EDX );
|
nkeynes@586 | 2937 | store_fr( R_EDX, R_ECX, FRn&0x0E );
|
nkeynes@586 | 2938 | store_fr( R_EDX, R_EAX, FRn|0x01 );
|
nkeynes@380 | 2939 | JMP_TARGET(end);
|
nkeynes@375 | 2940 | } else {
|
nkeynes@527 | 2941 | JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 2942 | JMP_TARGET(doublesize);
|
nkeynes@586 | 2943 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@416 | 2944 | load_fr_bank( R_EDX );
|
nkeynes@586 | 2945 | store_fr( R_EDX, R_ECX, FRn&0x0E );
|
nkeynes@586 | 2946 | store_fr( R_EDX, R_EAX, FRn|0x01 );
|
nkeynes@380 | 2947 | JMP_TARGET(end);
|
nkeynes@377 | 2948 | }
|
nkeynes@417 | 2949 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2950 | }
|
nkeynes@377 | 2951 | break;
|
nkeynes@377 | 2952 | case 0x7:
|
nkeynes@377 | 2953 | { /* FMOV FRm, @(R0, Rn) */
|
nkeynes@377 | 2954 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@586 | 2955 | check_fpuen();
|
nkeynes@586 | 2956 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 2957 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
|
nkeynes@586 | 2958 | check_walign32( R_EAX );
|
nkeynes@586 | 2959 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 2960 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 2961 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@586 | 2962 | JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
|
nkeynes@416 | 2963 | load_fr_bank( R_EDX );
|
nkeynes@586 | 2964 | load_fr( R_EDX, R_ECX, FRm );
|
nkeynes@586 | 2965 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@377 | 2966 | if( FRm&1 ) {
|
nkeynes@527 | 2967 | JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 2968 | JMP_TARGET(doublesize);
|
nkeynes@416 | 2969 | load_xf_bank( R_EDX );
|
nkeynes@586 | 2970 | load_fr( R_EDX, R_ECX, FRm&0x0E );
|
nkeynes@416 | 2971 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@586 | 2972 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@380 | 2973 | JMP_TARGET(end);
|
nkeynes@377 | 2974 | } else {
|
nkeynes@527 | 2975 | JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 2976 | JMP_TARGET(doublesize);
|
nkeynes@416 | 2977 | load_fr_bank( R_EDX );
|
nkeynes@586 | 2978 | load_fr( R_EDX, R_ECX, FRm&0x0E );
|
nkeynes@416 | 2979 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@586 | 2980 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@380 | 2981 | JMP_TARGET(end);
|
nkeynes@377 | 2982 | }
|
nkeynes@417 | 2983 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@377 | 2984 | }
|
nkeynes@377 | 2985 | break;
|
nkeynes@377 | 2986 | case 0x8:
|
nkeynes@377 | 2987 | { /* FMOV @Rm, FRn */
|
nkeynes@377 | 2988 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 2989 | check_fpuen();
|
nkeynes@586 | 2990 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 2991 | check_ralign32( R_EAX );
|
nkeynes@586 | 2992 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@416 | 2993 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 2994 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@586 | 2995 | JNE_rel8(8 + MEM_READ_SIZE, doublesize);
|
nkeynes@586 | 2996 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@416 | 2997 | load_fr_bank( R_EDX );
|
nkeynes@416 | 2998 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@377 | 2999 | if( FRn&1 ) {
|
nkeynes@527 | 3000 | JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 3001 | JMP_TARGET(doublesize);
|
nkeynes@586 | 3002 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@416 | 3003 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@416 | 3004 | load_xf_bank( R_EDX );
|
nkeynes@586 | 3005 | store_fr( R_EDX, R_ECX, FRn&0x0E );
|
nkeynes@586 | 3006 | store_fr( R_EDX, R_EAX, FRn|0x01 );
|
nkeynes@380 | 3007 | JMP_TARGET(end);
|
nkeynes@377 | 3008 | } else {
|
nkeynes@527 | 3009 | JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 3010 | JMP_TARGET(doublesize);
|
nkeynes@586 | 3011 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@416 | 3012 | load_fr_bank( R_EDX );
|
nkeynes@586 | 3013 | store_fr( R_EDX, R_ECX, FRn&0x0E );
|
nkeynes@586 | 3014 | store_fr( R_EDX, R_EAX, FRn|0x01 );
|
nkeynes@380 | 3015 | JMP_TARGET(end);
|
nkeynes@375 | 3016 | }
|
nkeynes@417 | 3017 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3018 | }
|
nkeynes@359 | 3019 | break;
|
nkeynes@359 | 3020 | case 0x9:
|
nkeynes@359 | 3021 | { /* FMOV @Rm+, FRn */
|
nkeynes@359 | 3022 | uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
|
nkeynes@586 | 3023 | check_fpuen();
|
nkeynes@586 | 3024 | load_reg( R_EAX, Rm );
|
nkeynes@586 | 3025 | check_ralign32( R_EAX );
|
nkeynes@586 | 3026 | MMU_TRANSLATE_READ( R_EAX );
|
nkeynes@416 | 3027 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3028 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@586 | 3029 | JNE_rel8(12 + MEM_READ_SIZE, doublesize);
|
nkeynes@586 | 3030 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 3031 | MEM_READ_LONG( R_EAX, R_EAX );
|
nkeynes@416 | 3032 | load_fr_bank( R_EDX );
|
nkeynes@416 | 3033 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@377 | 3034 | if( FRn&1 ) {
|
nkeynes@586 | 3035 | JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@380 | 3036 | JMP_TARGET(doublesize);
|
nkeynes@586 | 3037 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 3038 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@416 | 3039 | load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@416 | 3040 | load_xf_bank( R_EDX );
|
nkeynes@586 | 3041 | store_fr( R_EDX, R_ECX, FRn&0x0E );
|
nkeynes@586 | 3042 | store_fr( R_EDX, R_EAX, FRn|0x01 );
|
nkeynes@380 | 3043 | JMP_TARGET(end);
|
nkeynes@377 | 3044 | } else {
|
nkeynes@586 | 3045 | JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
|
nkeynes@586 | 3046 | ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
|
nkeynes@586 | 3047 | MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
|
nkeynes@416 | 3048 | load_fr_bank( R_EDX );
|
nkeynes@586 | 3049 | store_fr( R_EDX, R_ECX, FRn&0x0E );
|
nkeynes@586 | 3050 | store_fr( R_EDX, R_EAX, FRn|0x01 );
|
nkeynes@380 | 3051 | JMP_TARGET(end);
|
nkeynes@377 | 3052 | }
|
nkeynes@417 | 3053 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3054 | }
|
nkeynes@359 | 3055 | break;
|
nkeynes@359 | 3056 | case 0xA:
|
nkeynes@359 | 3057 | { /* FMOV FRm, @Rn */
|
nkeynes@359 | 3058 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@586 | 3059 | check_fpuen();
|
nkeynes@586 | 3060 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 3061 | check_walign32( R_EAX );
|
nkeynes@586 | 3062 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 3063 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3064 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@586 | 3065 | JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
|
nkeynes@416 | 3066 | load_fr_bank( R_EDX );
|
nkeynes@586 | 3067 | load_fr( R_EDX, R_ECX, FRm );
|
nkeynes@586 | 3068 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@375 | 3069 | if( FRm&1 ) {
|
nkeynes@527 | 3070 | JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 3071 | JMP_TARGET(doublesize);
|
nkeynes@416 | 3072 | load_xf_bank( R_EDX );
|
nkeynes@586 | 3073 | load_fr( R_EDX, R_ECX, FRm&0x0E );
|
nkeynes@416 | 3074 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@586 | 3075 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@380 | 3076 | JMP_TARGET(end);
|
nkeynes@375 | 3077 | } else {
|
nkeynes@527 | 3078 | JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
|
nkeynes@380 | 3079 | JMP_TARGET(doublesize);
|
nkeynes@416 | 3080 | load_fr_bank( R_EDX );
|
nkeynes@586 | 3081 | load_fr( R_EDX, R_ECX, FRm&0x0E );
|
nkeynes@416 | 3082 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@586 | 3083 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@380 | 3084 | JMP_TARGET(end);
|
nkeynes@375 | 3085 | }
|
nkeynes@417 | 3086 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3087 | }
|
nkeynes@359 | 3088 | break;
|
nkeynes@359 | 3089 | case 0xB:
|
nkeynes@359 | 3090 | { /* FMOV FRm, @-Rn */
|
nkeynes@359 | 3091 | uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@586 | 3092 | check_fpuen();
|
nkeynes@586 | 3093 | load_reg( R_EAX, Rn );
|
nkeynes@586 | 3094 | check_walign32( R_EAX );
|
nkeynes@416 | 3095 | load_spreg( R_EDX, R_FPSCR );
|
nkeynes@416 | 3096 | TEST_imm32_r32( FPSCR_SZ, R_EDX );
|
nkeynes@586 | 3097 | JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
|
nkeynes@586 | 3098 | ADD_imm8s_r32( -4, R_EAX );
|
nkeynes@586 | 3099 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 3100 | load_fr_bank( R_EDX );
|
nkeynes@586 | 3101 | load_fr( R_EDX, R_ECX, FRm );
|
nkeynes@586 | 3102 | ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
|
nkeynes@586 | 3103 | MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
|
nkeynes@377 | 3104 | if( FRm&1 ) {
|
nkeynes@586 | 3105 | JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
|
nkeynes@380 | 3106 | JMP_TARGET(doublesize);
|
nkeynes@586 | 3107 | ADD_imm8s_r32(-8,R_EAX);
|
nkeynes@586 | 3108 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 3109 | load_xf_bank( R_EDX );
|
nkeynes@586 | 3110 | load_fr( R_EDX, R_ECX, FRm&0x0E );
|
nkeynes@416 | 3111 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@586 | 3112 | ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
|
nkeynes@586 | 3113 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@380 | 3114 | JMP_TARGET(end);
|
nkeynes@377 | 3115 | } else {
|
nkeynes@586 | 3116 | JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
|
nkeynes@380 | 3117 | JMP_TARGET(doublesize);
|
nkeynes@586 | 3118 | ADD_imm8s_r32(-8,R_EAX);
|
nkeynes@586 | 3119 | MMU_TRANSLATE_WRITE( R_EAX );
|
nkeynes@416 | 3120 | load_fr_bank( R_EDX );
|
nkeynes@586 | 3121 | load_fr( R_EDX, R_ECX, FRm&0x0E );
|
nkeynes@416 | 3122 | load_fr( R_EDX, R_EDX, FRm|0x01 );
|
nkeynes@586 | 3123 | ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
|
nkeynes@586 | 3124 | MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
|
nkeynes@380 | 3125 | JMP_TARGET(end);
|
nkeynes@377 | 3126 | }
|
nkeynes@417 | 3127 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3128 | }
|
nkeynes@359 | 3129 | break;
|
nkeynes@359 | 3130 | case 0xC:
|
nkeynes@359 | 3131 | { /* FMOV FRm, FRn */
|
nkeynes@359 | 3132 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@375 | 3133 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 3134 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 3135 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 3136 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 3137 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 3138 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 3139 | */
|
nkeynes@377 | 3140 | check_fpuen();
|
nkeynes@375 | 3141 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3142 | load_fr_bank( R_EDX );
|
nkeynes@375 | 3143 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 3144 | JNE_rel8(8, doublesize);
|
nkeynes@375 | 3145 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
|
nkeynes@375 | 3146 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 3147 | if( FRm&1 ) {
|
nkeynes@386 | 3148 | JMP_rel8(24, end);
|
nkeynes@380 | 3149 | JMP_TARGET(doublesize);
|
nkeynes@375 | 3150 | load_xf_bank( R_ECX );
|
nkeynes@375 | 3151 | load_fr( R_ECX, R_EAX, FRm-1 );
|
nkeynes@375 | 3152 | if( FRn&1 ) {
|
nkeynes@375 | 3153 | load_fr( R_ECX, R_EDX, FRm );
|
nkeynes@375 | 3154 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 3155 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 3156 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 3157 | load_fr( R_ECX, R_ECX, FRm );
|
nkeynes@388 | 3158 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@388 | 3159 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@375 | 3160 | }
|
nkeynes@380 | 3161 | JMP_TARGET(end);
|
nkeynes@375 | 3162 | } else /* FRm&1 == 0 */ {
|
nkeynes@375 | 3163 | if( FRn&1 ) {
|
nkeynes@386 | 3164 | JMP_rel8(24, end);
|
nkeynes@375 | 3165 | load_xf_bank( R_ECX );
|
nkeynes@375 | 3166 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 3167 | load_fr( R_EDX, R_EDX, FRm+1 );
|
nkeynes@375 | 3168 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 3169 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@380 | 3170 | JMP_TARGET(end);
|
nkeynes@375 | 3171 | } else /* FRn&1 == 0 */ {
|
nkeynes@380 | 3172 | JMP_rel8(12, end);
|
nkeynes@375 | 3173 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 3174 | load_fr( R_EDX, R_ECX, FRm+1 );
|
nkeynes@375 | 3175 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 3176 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@380 | 3177 | JMP_TARGET(end);
|
nkeynes@375 | 3178 | }
|
nkeynes@375 | 3179 | }
|
nkeynes@417 | 3180 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3181 | }
|
nkeynes@359 | 3182 | break;
|
nkeynes@359 | 3183 | case 0xD:
|
nkeynes@359 | 3184 | switch( (ir&0xF0) >> 4 ) {
|
nkeynes@359 | 3185 | case 0x0:
|
nkeynes@359 | 3186 | { /* FSTS FPUL, FRn */
|
nkeynes@359 | 3187 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3188 | check_fpuen();
|
nkeynes@377 | 3189 | load_fr_bank( R_ECX );
|
nkeynes@377 | 3190 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 3191 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@417 | 3192 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3193 | }
|
nkeynes@359 | 3194 | break;
|
nkeynes@359 | 3195 | case 0x1:
|
nkeynes@359 | 3196 | { /* FLDS FRm, FPUL */
|
nkeynes@359 | 3197 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@377 | 3198 | check_fpuen();
|
nkeynes@377 | 3199 | load_fr_bank( R_ECX );
|
nkeynes@377 | 3200 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 3201 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@417 | 3202 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3203 | }
|
nkeynes@359 | 3204 | break;
|
nkeynes@359 | 3205 | case 0x2:
|
nkeynes@359 | 3206 | { /* FLOAT FPUL, FRn */
|
nkeynes@359 | 3207 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3208 | check_fpuen();
|
nkeynes@377 | 3209 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3210 | load_spreg(R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 3211 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 3212 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3213 | JNE_rel8(5, doubleprec);
|
nkeynes@377 | 3214 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 3215 | JMP_rel8(3, end);
|
nkeynes@380 | 3216 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3217 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 3218 | JMP_TARGET(end);
|
nkeynes@417 | 3219 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3220 | }
|
nkeynes@359 | 3221 | break;
|
nkeynes@359 | 3222 | case 0x3:
|
nkeynes@359 | 3223 | { /* FTRC FRm, FPUL */
|
nkeynes@359 | 3224 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@377 | 3225 | check_fpuen();
|
nkeynes@388 | 3226 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3227 | load_fr_bank( R_EDX );
|
nkeynes@388 | 3228 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 3229 | JNE_rel8(5, doubleprec);
|
nkeynes@388 | 3230 | push_fr( R_EDX, FRm );
|
nkeynes@388 | 3231 | JMP_rel8(3, doop);
|
nkeynes@388 | 3232 | JMP_TARGET(doubleprec);
|
nkeynes@388 | 3233 | push_dr( R_EDX, FRm );
|
nkeynes@388 | 3234 | JMP_TARGET( doop );
|
nkeynes@388 | 3235 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 3236 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 3237 | FCOMIP_st(1);
|
nkeynes@394 | 3238 | JNA_rel8( 32, sat );
|
nkeynes@388 | 3239 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 3240 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 3241 | FCOMIP_st(1); // 2
|
nkeynes@394 | 3242 | JAE_rel8( 21, sat2 ); // 2
|
nkeynes@394 | 3243 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 3244 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 3245 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 3246 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 3247 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 3248 | FLDCW_r32ind( R_EAX );
|
nkeynes@388 | 3249 | JMP_rel8( 9, end ); // 2
|
nkeynes@388 | 3250 |
|
nkeynes@388 | 3251 | JMP_TARGET(sat);
|
nkeynes@388 | 3252 | JMP_TARGET(sat2);
|
nkeynes@388 | 3253 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 3254 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 3255 | FPOP_st();
|
nkeynes@388 | 3256 | JMP_TARGET(end);
|
nkeynes@417 | 3257 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3258 | }
|
nkeynes@359 | 3259 | break;
|
nkeynes@359 | 3260 | case 0x4:
|
nkeynes@359 | 3261 | { /* FNEG FRn */
|
nkeynes@359 | 3262 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3263 | check_fpuen();
|
nkeynes@377 | 3264 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3265 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 3266 | load_fr_bank( R_EDX );
|
nkeynes@380 | 3267 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 3268 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 3269 | FCHS_st0();
|
nkeynes@377 | 3270 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 3271 | JMP_rel8(8, end);
|
nkeynes@380 | 3272 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3273 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 3274 | FCHS_st0();
|
nkeynes@377 | 3275 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 3276 | JMP_TARGET(end);
|
nkeynes@417 | 3277 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3278 | }
|
nkeynes@359 | 3279 | break;
|
nkeynes@359 | 3280 | case 0x5:
|
nkeynes@359 | 3281 | { /* FABS FRn */
|
nkeynes@359 | 3282 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3283 | check_fpuen();
|
nkeynes@374 | 3284 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3285 | load_fr_bank( R_EDX );
|
nkeynes@374 | 3286 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3287 | JNE_rel8(10, doubleprec);
|
nkeynes@374 | 3288 | push_fr(R_EDX, FRn); // 3
|
nkeynes@374 | 3289 | FABS_st0(); // 2
|
nkeynes@374 | 3290 | pop_fr( R_EDX, FRn); //3
|
nkeynes@380 | 3291 | JMP_rel8(8,end); // 2
|
nkeynes@380 | 3292 | JMP_TARGET(doubleprec);
|
nkeynes@374 | 3293 | push_dr(R_EDX, FRn);
|
nkeynes@374 | 3294 | FABS_st0();
|
nkeynes@374 | 3295 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 3296 | JMP_TARGET(end);
|
nkeynes@417 | 3297 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3298 | }
|
nkeynes@359 | 3299 | break;
|
nkeynes@359 | 3300 | case 0x6:
|
nkeynes@359 | 3301 | { /* FSQRT FRn */
|
nkeynes@359 | 3302 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3303 | check_fpuen();
|
nkeynes@377 | 3304 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3305 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 3306 | load_fr_bank( R_EDX );
|
nkeynes@380 | 3307 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 3308 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 3309 | FSQRT_st0();
|
nkeynes@377 | 3310 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 3311 | JMP_rel8(8, end);
|
nkeynes@380 | 3312 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3313 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 3314 | FSQRT_st0();
|
nkeynes@377 | 3315 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 3316 | JMP_TARGET(end);
|
nkeynes@417 | 3317 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3318 | }
|
nkeynes@359 | 3319 | break;
|
nkeynes@359 | 3320 | case 0x7:
|
nkeynes@359 | 3321 | { /* FSRRA FRn */
|
nkeynes@359 | 3322 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3323 | check_fpuen();
|
nkeynes@377 | 3324 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3325 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 3326 | load_fr_bank( R_EDX );
|
nkeynes@380 | 3327 | JNE_rel8(12, end); // PR=0 only
|
nkeynes@377 | 3328 | FLD1_st0();
|
nkeynes@377 | 3329 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 3330 | FSQRT_st0();
|
nkeynes@377 | 3331 | FDIVP_st(1);
|
nkeynes@377 | 3332 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 3333 | JMP_TARGET(end);
|
nkeynes@417 | 3334 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3335 | }
|
nkeynes@359 | 3336 | break;
|
nkeynes@359 | 3337 | case 0x8:
|
nkeynes@359 | 3338 | { /* FLDI0 FRn */
|
nkeynes@359 | 3339 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3340 | /* IFF PR=0 */
|
nkeynes@377 | 3341 | check_fpuen();
|
nkeynes@377 | 3342 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3343 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3344 | JNE_rel8(8, end);
|
nkeynes@377 | 3345 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@377 | 3346 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 3347 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 3348 | JMP_TARGET(end);
|
nkeynes@417 | 3349 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3350 | }
|
nkeynes@359 | 3351 | break;
|
nkeynes@359 | 3352 | case 0x9:
|
nkeynes@359 | 3353 | { /* FLDI1 FRn */
|
nkeynes@359 | 3354 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3355 | /* IFF PR=0 */
|
nkeynes@377 | 3356 | check_fpuen();
|
nkeynes@377 | 3357 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3358 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3359 | JNE_rel8(11, end);
|
nkeynes@377 | 3360 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@377 | 3361 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 3362 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 3363 | JMP_TARGET(end);
|
nkeynes@417 | 3364 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3365 | }
|
nkeynes@359 | 3366 | break;
|
nkeynes@359 | 3367 | case 0xA:
|
nkeynes@359 | 3368 | { /* FCNVSD FPUL, FRn */
|
nkeynes@359 | 3369 | uint32_t FRn = ((ir>>8)&0xF);
|
nkeynes@377 | 3370 | check_fpuen();
|
nkeynes@377 | 3371 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3372 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3373 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 3374 | load_fr_bank( R_ECX );
|
nkeynes@377 | 3375 | push_fpul();
|
nkeynes@377 | 3376 | pop_dr( R_ECX, FRn );
|
nkeynes@380 | 3377 | JMP_TARGET(end);
|
nkeynes@417 | 3378 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3379 | }
|
nkeynes@359 | 3380 | break;
|
nkeynes@359 | 3381 | case 0xB:
|
nkeynes@359 | 3382 | { /* FCNVDS FRm, FPUL */
|
nkeynes@359 | 3383 | uint32_t FRm = ((ir>>8)&0xF);
|
nkeynes@377 | 3384 | check_fpuen();
|
nkeynes@377 | 3385 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3386 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3387 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 3388 | load_fr_bank( R_ECX );
|
nkeynes@377 | 3389 | push_dr( R_ECX, FRm );
|
nkeynes@377 | 3390 | pop_fpul();
|
nkeynes@380 | 3391 | JMP_TARGET(end);
|
nkeynes@417 | 3392 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3393 | }
|
nkeynes@359 | 3394 | break;
|
nkeynes@359 | 3395 | case 0xE:
|
nkeynes@359 | 3396 | { /* FIPR FVm, FVn */
|
nkeynes@359 | 3397 | uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
|
nkeynes@377 | 3398 | check_fpuen();
|
nkeynes@388 | 3399 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3400 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 3401 | JNE_rel8(44, doubleprec);
|
nkeynes@388 | 3402 |
|
nkeynes@388 | 3403 | load_fr_bank( R_ECX );
|
nkeynes@388 | 3404 | push_fr( R_ECX, FVm<<2 );
|
nkeynes@388 | 3405 | push_fr( R_ECX, FVn<<2 );
|
nkeynes@388 | 3406 | FMULP_st(1);
|
nkeynes@388 | 3407 | push_fr( R_ECX, (FVm<<2)+1);
|
nkeynes@388 | 3408 | push_fr( R_ECX, (FVn<<2)+1);
|
nkeynes@388 | 3409 | FMULP_st(1);
|
nkeynes@388 | 3410 | FADDP_st(1);
|
nkeynes@388 | 3411 | push_fr( R_ECX, (FVm<<2)+2);
|
nkeynes@388 | 3412 | push_fr( R_ECX, (FVn<<2)+2);
|
nkeynes@388 | 3413 | FMULP_st(1);
|
nkeynes@388 | 3414 | FADDP_st(1);
|
nkeynes@388 | 3415 | push_fr( R_ECX, (FVm<<2)+3);
|
nkeynes@388 | 3416 | push_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 3417 | FMULP_st(1);
|
nkeynes@388 | 3418 | FADDP_st(1);
|
nkeynes@388 | 3419 | pop_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 3420 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 3421 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3422 | }
|
nkeynes@359 | 3423 | break;
|
nkeynes@359 | 3424 | case 0xF:
|
nkeynes@359 | 3425 | switch( (ir&0x100) >> 8 ) {
|
nkeynes@359 | 3426 | case 0x0:
|
nkeynes@359 | 3427 | { /* FSCA FPUL, FRn */
|
nkeynes@359 | 3428 | uint32_t FRn = ((ir>>9)&0x7)<<1;
|
nkeynes@377 | 3429 | check_fpuen();
|
nkeynes@388 | 3430 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3431 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@527 | 3432 | JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
|
nkeynes@388 | 3433 | load_fr_bank( R_ECX );
|
nkeynes@388 | 3434 | ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
|
nkeynes@388 | 3435 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 3436 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 3437 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 3438 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3439 | }
|
nkeynes@359 | 3440 | break;
|
nkeynes@359 | 3441 | case 0x1:
|
nkeynes@359 | 3442 | switch( (ir&0x200) >> 9 ) {
|
nkeynes@359 | 3443 | case 0x0:
|
nkeynes@359 | 3444 | { /* FTRV XMTRX, FVn */
|
nkeynes@359 | 3445 | uint32_t FVn = ((ir>>10)&0x3);
|
nkeynes@377 | 3446 | check_fpuen();
|
nkeynes@388 | 3447 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 3448 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@527 | 3449 | JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
|
nkeynes@388 | 3450 | load_fr_bank( R_EDX ); // 3
|
nkeynes@388 | 3451 | ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
|
nkeynes@388 | 3452 | load_xf_bank( R_ECX ); // 12
|
nkeynes@388 | 3453 | call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
|
nkeynes@388 | 3454 | JMP_TARGET(doubleprec);
|
nkeynes@417 | 3455 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3456 | }
|
nkeynes@359 | 3457 | break;
|
nkeynes@359 | 3458 | case 0x1:
|
nkeynes@359 | 3459 | switch( (ir&0xC00) >> 10 ) {
|
nkeynes@359 | 3460 | case 0x0:
|
nkeynes@359 | 3461 | { /* FSCHG */
|
nkeynes@377 | 3462 | check_fpuen();
|
nkeynes@377 | 3463 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3464 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 3465 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@417 | 3466 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3467 | }
|
nkeynes@359 | 3468 | break;
|
nkeynes@359 | 3469 | case 0x2:
|
nkeynes@359 | 3470 | { /* FRCHG */
|
nkeynes@377 | 3471 | check_fpuen();
|
nkeynes@377 | 3472 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3473 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 3474 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@386 | 3475 | update_fr_bank( R_ECX );
|
nkeynes@417 | 3476 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3477 | }
|
nkeynes@359 | 3478 | break;
|
nkeynes@359 | 3479 | case 0x3:
|
nkeynes@359 | 3480 | { /* UNDEF */
|
nkeynes@374 | 3481 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 3482 | SLOTILLEGAL();
|
nkeynes@374 | 3483 | } else {
|
nkeynes@586 | 3484 | JMP_exc(EXC_ILLEGAL);
|
nkeynes@408 | 3485 | return 2;
|
nkeynes@374 | 3486 | }
|
nkeynes@359 | 3487 | }
|
nkeynes@359 | 3488 | break;
|
nkeynes@359 | 3489 | default:
|
nkeynes@359 | 3490 | UNDEF();
|
nkeynes@359 | 3491 | break;
|
nkeynes@359 | 3492 | }
|
nkeynes@359 | 3493 | break;
|
nkeynes@359 | 3494 | }
|
nkeynes@359 | 3495 | break;
|
nkeynes@359 | 3496 | }
|
nkeynes@359 | 3497 | break;
|
nkeynes@359 | 3498 | default:
|
nkeynes@359 | 3499 | UNDEF();
|
nkeynes@359 | 3500 | break;
|
nkeynes@359 | 3501 | }
|
nkeynes@359 | 3502 | break;
|
nkeynes@359 | 3503 | case 0xE:
|
nkeynes@359 | 3504 | { /* FMAC FR0, FRm, FRn */
|
nkeynes@359 | 3505 | uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
|
nkeynes@377 | 3506 | check_fpuen();
|
nkeynes@377 | 3507 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 3508 | load_spreg( R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 3509 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 3510 | JNE_rel8(18, doubleprec);
|
nkeynes@377 | 3511 | push_fr( R_EDX, 0 );
|
nkeynes@377 | 3512 | push_fr( R_EDX, FRm );
|
nkeynes@377 | 3513 | FMULP_st(1);
|
nkeynes@377 | 3514 | push_fr( R_EDX, FRn );
|
nkeynes@377 | 3515 | FADDP_st(1);
|
nkeynes@377 | 3516 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 3517 | JMP_rel8(16, end);
|
nkeynes@380 | 3518 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 3519 | push_dr( R_EDX, 0 );
|
nkeynes@377 | 3520 | push_dr( R_EDX, FRm );
|
nkeynes@377 | 3521 | FMULP_st(1);
|
nkeynes@377 | 3522 | push_dr( R_EDX, FRn );
|
nkeynes@377 | 3523 | FADDP_st(1);
|
nkeynes@377 | 3524 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 3525 | JMP_TARGET(end);
|
nkeynes@417 | 3526 | sh4_x86.tstate = TSTATE_NONE;
|
nkeynes@359 | 3527 | }
|
nkeynes@359 | 3528 | break;
|
nkeynes@359 | 3529 | default:
|
nkeynes@359 | 3530 | UNDEF();
|
nkeynes@359 | 3531 | break;
|
nkeynes@359 | 3532 | }
|
nkeynes@359 | 3533 | break;
|
nkeynes@359 | 3534 | }
|
nkeynes@359 | 3535 |
|
nkeynes@590 | 3536 | sh4_x86.in_delay_slot = DELAY_NONE;
|
nkeynes@359 | 3537 | return 0;
|
nkeynes@359 | 3538 | }
|