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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 1193:dff55bdc4f46
prev1191:12fdf3aafcd4
next1194:ee6ce5804608
author nkeynes
date Mon Dec 12 21:10:04 2011 +1000 (8 years ago)
permissions -rw-r--r--
last change Fix MAC.W operand ordering - reads from Rn first, then Rm (per the manual)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4dasm.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/mmu.h"
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#include "xlat/xltcache.h"
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#include "xlat/x86/x86op.h"
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#include "x86dasm/x86dasm.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/* Offset of a reg relative to the sh4r structure */
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#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
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#define R_T      REG_OFFSET(t)
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#define R_Q      REG_OFFSET(q)
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#define R_S      REG_OFFSET(s)
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#define R_M      REG_OFFSET(m)
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#define R_SR     REG_OFFSET(sr)
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#define R_GBR    REG_OFFSET(gbr)
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#define R_SSR    REG_OFFSET(ssr)
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#define R_SPC    REG_OFFSET(spc)
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#define R_VBR    REG_OFFSET(vbr)
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#define R_MACH   REG_OFFSET(mac)+4
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#define R_MACL   REG_OFFSET(mac)
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#define R_PC     REG_OFFSET(pc)
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#define R_NEW_PC REG_OFFSET(new_pc)
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#define R_PR     REG_OFFSET(pr)
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#define R_SGR    REG_OFFSET(sgr)
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#define R_FPUL   REG_OFFSET(fpul)
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#define R_FPSCR  REG_OFFSET(fpscr)
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#define R_DBR    REG_OFFSET(dbr)
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#define R_R(rn)  REG_OFFSET(r[rn])
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#define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
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#define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
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#define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
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#define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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#define SH4_MODE_UNKNOWN -1
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    uint8_t *code;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    uint32_t sh4_mode;     /* Mirror of sh4r.xlat_sh4_mode */
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    int tstate;
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    /* mode settings */
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    gboolean tlb_on; /* True if tlb translation is active */
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    struct mem_region_fn **priv_address_space;
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    struct mem_region_fn **user_address_space;
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    /* Instrumentation */
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    xlat_block_begin_callback_t begin_callback;
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    xlat_block_end_callback_t end_callback;
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    gboolean fastmem;
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    gboolean profile_blocks;
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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static struct x86_symbol x86_symbol_table[] = {
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    { "sh4r+128", ((char *)&sh4r)+128 },
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    { "sh4_cpu_period", &sh4_cpu_period },
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    { "sh4_address_space", NULL },
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    { "sh4_user_address_space", NULL },
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    { "sh4_translate_breakpoint_hit", sh4_translate_breakpoint_hit },
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    { "sh4_write_fpscr", sh4_write_fpscr },
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    { "sh4_write_sr", sh4_write_sr },
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    { "sh4_read_sr", sh4_read_sr },
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    { "sh4_raise_exception", sh4_raise_exception },
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    { "sh4_sleep", sh4_sleep },
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    { "sh4_fsca", sh4_fsca },
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    { "sh4_ftrv", sh4_ftrv },
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    { "sh4_switch_fr_banks", sh4_switch_fr_banks },
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    { "sh4_execute_instruction", sh4_execute_instruction },
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    { "signsat48", signsat48 },
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    { "xlat_get_code_by_vma", xlat_get_code_by_vma },
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    { "xlat_get_code", xlat_get_code }
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};
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_set_address_space( struct mem_region_fn **priv, struct mem_region_fn **user )
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{
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    sh4_x86.priv_address_space = priv;
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    sh4_x86.user_address_space = user;
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    x86_symbol_table[2].ptr = priv;
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    x86_symbol_table[3].ptr = user;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.begin_callback = NULL;
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    sh4_x86.end_callback = NULL;
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    sh4_translate_set_address_space( sh4_address_space, sh4_user_address_space );
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    sh4_x86.fastmem = TRUE;
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    sh4_x86.profile_blocks = FALSE;
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    sh4_x86.sse3_enabled = is_sse3_supported();
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    x86_disasm_init();
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    x86_set_symtab( x86_symbol_table, sizeof(x86_symbol_table)/sizeof(struct x86_symbol) );
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}
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void sh4_translate_set_callbacks( xlat_block_begin_callback_t begin, xlat_block_end_callback_t end )
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{
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    sh4_x86.begin_callback = begin;
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    sh4_x86.end_callback = end;
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}
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void sh4_translate_set_fastmem( gboolean flag )
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{
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    sh4_x86.fastmem = flag;
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}
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void sh4_translate_set_profile_blocks( gboolean flag )
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{
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    sh4_x86.profile_blocks = flag;
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}
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gboolean sh4_translate_get_profile_blocks()
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{
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    return sh4_x86.profile_blocks;
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}
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/**
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 * Disassemble the given translated code block, and it's source SH4 code block
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 * side-by-side. The current native pc will be marked if non-null.
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 */
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void sh4_translate_disasm_block( FILE *out, void *code, sh4addr_t source_start, void *native_pc )
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{
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    char buf[256];
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    char op[256];
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    uintptr_t target_start = (uintptr_t)code, target_pc;
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    uintptr_t target_end = target_start + xlat_get_code_size(code);
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    uint32_t source_pc = source_start;
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    uint32_t source_end = source_pc;
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    xlat_recovery_record_t source_recov_table = XLAT_RECOVERY_TABLE(code);
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    xlat_recovery_record_t source_recov_end = source_recov_table + XLAT_BLOCK_FOR_CODE(code)->recover_table_size - 1;
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    for( target_pc = target_start; target_pc < target_end;  ) {
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        uintptr_t pc2 = x86_disasm_instruction( target_pc, buf, sizeof(buf), op );
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#if SIZEOF_VOID_P == 8
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        fprintf( out, "%c%016lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '),
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                      target_pc, op, buf );
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#else
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        fprintf( out, "%c%08lx: %-30s %-40s", (target_pc == (uintptr_t)native_pc ? '*' : ' '),
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                      target_pc, op, buf );
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#endif        
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        if( source_recov_table < source_recov_end && 
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            target_pc >= (target_start + source_recov_table->xlat_offset) ) {
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            source_recov_table++;
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            if( source_end < (source_start + (source_recov_table->sh4_icount)*2) )
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                source_end = source_start + (source_recov_table->sh4_icount)*2;
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        }
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        if( source_pc < source_end ) {
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            uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op );
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            fprintf( out, " %08X: %s  %s\n", source_pc, op, buf );
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            source_pc = source_pc2;
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        } else {
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            fprintf( out, "\n" );
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        }
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        target_pc = pc2;
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    }
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    while( source_pc < source_end ) {
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        uint32_t source_pc2 = sh4_disasm_instruction( source_pc, buf, sizeof(buf), op );
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        fprintf( out, "%*c %08X: %s  %s\n", 72,' ', source_pc, op, buf );
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        source_pc = source_pc2;
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    }
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    int reloc_size = 4;
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    if( exc_code == -2 ) {
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        reloc_size = sizeof(void *);
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    }
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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#define TSTATE_NONE -1
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#define TSTATE_O    X86_COND_O
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#define TSTATE_C    X86_COND_C
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#define TSTATE_E    X86_COND_E
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#define TSTATE_NE   X86_COND_NE
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#define TSTATE_G    X86_COND_G
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#define TSTATE_GE   X86_COND_GE
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#define TSTATE_A    X86_COND_A
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#define TSTATE_AE   X86_COND_AE
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#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
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#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
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/* Convenience instructions */
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#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
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#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
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#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
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#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
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#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
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#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
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#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
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#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
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#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
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#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
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#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
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#define JBE_label(label) JCC_cc_rel8(X86_COND_BE,-1); MARK_JMP8(label)
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#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
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#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
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#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
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#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
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#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
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#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
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#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
nkeynes@991
   306
#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
nkeynes@374
   307
nkeynes@991
   308
/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@991
   309
#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@991
   310
	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@991
   311
    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
nkeynes@368
   312
nkeynes@991
   313
/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@991
   314
#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@991
   315
	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@991
   316
    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
nkeynes@359
   317
nkeynes@939
   318
nkeynes@991
   319
#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
nkeynes@991
   320
#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
nkeynes@374
   321
nkeynes@375
   322
/**
nkeynes@375
   323
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   324
 * register (eg for register-to-register moves)
nkeynes@375
   325
 */
nkeynes@991
   326
#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
nkeynes@991
   327
#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
nkeynes@375
   328
nkeynes@375
   329
/**
nkeynes@669
   330
 * Load the low half of a DR register (DR or XD) into an integer x86 register 
nkeynes@669
   331
 */
nkeynes@991
   332
#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
nkeynes@991
   333
#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
nkeynes@669
   334
nkeynes@669
   335
/**
nkeynes@669
   336
 * Store an FR register (single-precision floating point) from an integer x86+
nkeynes@375
   337
 * register (eg for register-to-register moves)
nkeynes@375
   338
 */
nkeynes@991
   339
#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   340
#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@375
   341
nkeynes@991
   342
#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
nkeynes@991
   343
#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
nkeynes@375
   344
nkeynes@374
   345
nkeynes@991
   346
#define push_fpul()  FLDF_rbpdisp(R_FPUL)
nkeynes@991
   347
#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
nkeynes@991
   348
#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   349
#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991
   350
#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   351
#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991
   352
#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   353
#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991
   354
#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@991
   355
#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377
   356
nkeynes@991
   357
#ifdef ENABLE_SH4STATS
nkeynes@995
   358
#define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@991
   359
#else
nkeynes@991
   360
#define COUNT_INST(id)
nkeynes@991
   361
#endif
nkeynes@377
   362
nkeynes@374
   363
nkeynes@368
   364
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416
   365
nkeynes@416
   366
#define check_priv( ) \
nkeynes@1112
   367
    if( (sh4_x86.sh4_mode & SR_MD) == 0 ) { \
nkeynes@937
   368
        if( sh4_x86.in_delay_slot ) { \
nkeynes@1191
   369
            exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2), 4 ); \
nkeynes@937
   370
        } else { \
nkeynes@1191
   371
            exit_block_exc(EXC_ILLEGAL, pc, 2); \
nkeynes@937
   372
        } \
nkeynes@956
   373
        sh4_x86.branch_taken = TRUE; \
nkeynes@937
   374
        sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@937
   375
        return 2; \
nkeynes@937
   376
    }
nkeynes@416
   377
nkeynes@416
   378
#define check_fpuen( ) \
nkeynes@416
   379
    if( !sh4_x86.fpuen_checked ) {\
nkeynes@416
   380
	sh4_x86.fpuen_checked = TRUE;\
nkeynes@995
   381
	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
nkeynes@991
   382
	ANDL_imms_r32( SR_FD, REG_EAX );\
nkeynes@416
   383
	if( sh4_x86.in_delay_slot ) {\
nkeynes@586
   384
	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416
   385
	} else {\
nkeynes@586
   386
	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416
   387
	}\
nkeynes@875
   388
	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416
   389
    }
nkeynes@416
   390
nkeynes@586
   391
#define check_ralign16( x86reg ) \
nkeynes@991
   392
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   393
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416
   394
nkeynes@586
   395
#define check_walign16( x86reg ) \
nkeynes@991
   396
    TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@586
   397
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   398
nkeynes@586
   399
#define check_ralign32( x86reg ) \
nkeynes@991
   400
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   401
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368
   402
nkeynes@586
   403
#define check_walign32( x86reg ) \
nkeynes@991
   404
    TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@586
   405
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368
   406
nkeynes@732
   407
#define check_ralign64( x86reg ) \
nkeynes@991
   408
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   409
    JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732
   410
nkeynes@732
   411
#define check_walign64( x86reg ) \
nkeynes@991
   412
    TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732
   413
    JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732
   414
nkeynes@1125
   415
#define address_space() ((sh4_x86.sh4_mode&SR_MD) ? (uintptr_t)sh4_x86.priv_address_space : (uintptr_t)sh4_x86.user_address_space)
nkeynes@1004
   416
nkeynes@824
   417
#define UNDEF(ir)
nkeynes@939
   418
/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@939
   419
 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@586
   420
 */
nkeynes@941
   421
#ifdef HAVE_FRAME_ADDRESS
nkeynes@995
   422
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   423
{
nkeynes@1004
   424
    decode_address(address_space(), addr_reg);
nkeynes@1112
   425
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@995
   426
        CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   427
    } else {
nkeynes@995
   428
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   429
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   430
        }
nkeynes@995
   431
        MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995
   432
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   433
        CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
nkeynes@995
   434
    }
nkeynes@995
   435
    if( value_reg != REG_RESULT1 ) { 
nkeynes@995
   436
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   437
    }
nkeynes@995
   438
}
nkeynes@995
   439
nkeynes@995
   440
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   441
{
nkeynes@1004
   442
    decode_address(address_space(), addr_reg);
nkeynes@1112
   443
    if( !sh4_x86.tlb_on && (sh4_x86.sh4_mode & SR_MD) ) { 
nkeynes@995
   444
        CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   445
    } else {
nkeynes@995
   446
        if( value_reg != REG_ARG2 ) {
nkeynes@995
   447
            MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995
   448
	}        
nkeynes@995
   449
        if( addr_reg != REG_ARG1 ) {
nkeynes@995
   450
            MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995
   451
        }
nkeynes@995
   452
#if MAX_REG_ARG > 2        
nkeynes@995
   453
        MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995
   454
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   455
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995
   456
#else
nkeynes@995
   457
        MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995
   458
        sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995
   459
        CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995
   460
#endif
nkeynes@995
   461
    }
nkeynes@995
   462
}
nkeynes@995
   463
#else
nkeynes@995
   464
static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   465
{
nkeynes@1004
   466
    decode_address(address_space(), addr_reg);
nkeynes@995
   467
    CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995
   468
    if( value_reg != REG_RESULT1 ) {
nkeynes@995
   469
        MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995
   470
    }
nkeynes@995
   471
}     
nkeynes@995
   472
nkeynes@996
   473
static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995
   474
{
nkeynes@1004
   475
    decode_address(address_space(), addr_reg);
nkeynes@995
   476
    CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995
   477
}
nkeynes@941
   478
#endif
nkeynes@939
   479
                
nkeynes@995
   480
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995
   481
#define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995
   482
#define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995
   483
#define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995
   484
#define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995
   485
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995
   486
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995
   487
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995
   488
#define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@368
   489
nkeynes@1191
   490
#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@539
   491
nkeynes@1182
   492
/** Offset of xlat_sh4_mode field relative to the code pointer */ 
nkeynes@1186
   493
#define XLAT_SH4_MODE_CODE_OFFSET  (int32_t)(offsetof(struct xlat_cache_block, xlat_sh4_mode) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   494
#define XLAT_CHAIN_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, chain) - offsetof(struct xlat_cache_block,code) )
nkeynes@1186
   495
#define XLAT_ACTIVE_CODE_OFFSET (int32_t)(offsetof(struct xlat_cache_block, active) - offsetof(struct xlat_cache_block,code) )
nkeynes@1182
   496
nkeynes@901
   497
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   498
{
nkeynes@1112
   499
	sh4_x86.code = xlat_output;
nkeynes@901
   500
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   501
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   502
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   503
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   504
    sh4_x86.block_start_pc = pc;
nkeynes@939
   505
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   507
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   508
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@1112
   509
    sh4_x86.sh4_mode = sh4r.xlat_sh4_mode;
nkeynes@1125
   510
    emit_prologue();
nkeynes@1125
   511
    if( sh4_x86.begin_callback ) {
nkeynes@1125
   512
        CALL_ptr( sh4_x86.begin_callback );
nkeynes@1125
   513
    }
nkeynes@1182
   514
    if( sh4_x86.profile_blocks ) {
nkeynes@1186
   515
    	MOVP_immptr_rptr( sh4_x86.code + XLAT_ACTIVE_CODE_OFFSET, REG_EAX );
nkeynes@1182
   516
    	ADDL_imms_r32disp( 1, REG_EAX, 0 );
nkeynes@1182
   517
    }  
nkeynes@901
   518
}
nkeynes@901
   519
nkeynes@901
   520
nkeynes@593
   521
uint32_t sh4_translate_end_block_size()
nkeynes@593
   522
{
nkeynes@596
   523
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1146
   524
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*(12+CALL1_PTR_MIN_SIZE));
nkeynes@596
   525
    } else {
nkeynes@1146
   526
        return EPILOGUE_SIZE + (3*(12+CALL1_PTR_MIN_SIZE)) + (sh4_x86.backpatch_posn-3)*(15+CALL1_PTR_MIN_SIZE);
nkeynes@596
   527
    }
nkeynes@593
   528
}
nkeynes@593
   529
nkeynes@593
   530
nkeynes@590
   531
/**
nkeynes@590
   532
 * Embed a breakpoint into the generated code
nkeynes@590
   533
 */
nkeynes@586
   534
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   535
{
nkeynes@995
   536
    MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995
   537
    CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875
   538
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   539
}
nkeynes@590
   540
nkeynes@601
   541
nkeynes@601
   542
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   543
nkeynes@1112
   544
/**
nkeynes@1112
   545
 * Test if the loaded target code pointer in %eax is valid, and if so jump
nkeynes@1112
   546
 * directly into it, bypassing the normal exit.
nkeynes@1112
   547
 */
nkeynes@1112
   548
static void jump_next_block()
nkeynes@1112
   549
{
nkeynes@1149
   550
	uint8_t *ptr = xlat_output;
nkeynes@1112
   551
	TESTP_rptr_rptr(REG_EAX, REG_EAX);
nkeynes@1112
   552
	JE_label(nocode);
nkeynes@1112
   553
	if( sh4_x86.sh4_mode == SH4_MODE_UNKNOWN ) {
nkeynes@1112
   554
	    /* sr/fpscr was changed, possibly updated xlat_sh4_mode, so reload it */
nkeynes@1112
   555
	    MOVL_rbpdisp_r32( REG_OFFSET(xlat_sh4_mode), REG_ECX );
nkeynes@1112
   556
	    CMPL_r32_r32disp( REG_ECX, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   557
	} else {
nkeynes@1112
   558
	    CMPL_imms_r32disp( sh4_x86.sh4_mode, REG_EAX, XLAT_SH4_MODE_CODE_OFFSET );
nkeynes@1112
   559
	}
nkeynes@1112
   560
	JNE_label(wrongmode);
nkeynes@1112
   561
	LEAP_rptrdisp_rptr(REG_EAX, PROLOGUE_SIZE,REG_EAX);
nkeynes@1125
   562
	if( sh4_x86.end_callback ) {
nkeynes@1125
   563
	    /* Note this does leave the stack out of alignment, but doesn't matter
nkeynes@1125
   564
	     * for what we're currently using it for.
nkeynes@1125
   565
	     */
nkeynes@1125
   566
	    PUSH_r32(REG_EAX);
nkeynes@1125
   567
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   568
	    JMP_rptr(REG_ECX);
nkeynes@1125
   569
	} else {
nkeynes@1125
   570
	    JMP_rptr(REG_EAX);
nkeynes@1125
   571
	}
nkeynes@1149
   572
	JMP_TARGET(wrongmode);
nkeynes@1176
   573
	MOVP_rptrdisp_rptr( REG_EAX, XLAT_CHAIN_CODE_OFFSET, REG_EAX );
nkeynes@1149
   574
	int rel = ptr - xlat_output;
nkeynes@1149
   575
    JMP_prerel(rel);
nkeynes@1149
   576
	JMP_TARGET(nocode); 
nkeynes@1112
   577
}
nkeynes@1112
   578
nkeynes@1186
   579
/**
nkeynes@1186
   580
 * 
nkeynes@1186
   581
 */
nkeynes@1186
   582
static void FASTCALL sh4_translate_get_code_and_backpatch( uint32_t pc )
nkeynes@1186
   583
{
nkeynes@1186
   584
    uint8_t *target = (uint8_t *)xlat_get_code_by_vma(pc);
nkeynes@1186
   585
    while( target != NULL && sh4r.xlat_sh4_mode != XLAT_BLOCK_MODE(target) ) {
nkeynes@1186
   586
        target = XLAT_BLOCK_CHAIN(target);
nkeynes@1186
   587
	}
nkeynes@1186
   588
    if( target == NULL ) {
nkeynes@1186
   589
        target = sh4_translate_basic_block( pc );
nkeynes@1186
   590
    }
nkeynes@1186
   591
    uint8_t *backpatch = ((uint8_t *)__builtin_return_address(0)) - (CALL1_PTR_MIN_SIZE);
nkeynes@1186
   592
    *backpatch = 0xE9;
nkeynes@1186
   593
    *(uint32_t *)(backpatch+1) = (uint32_t)(target-backpatch)+PROLOGUE_SIZE-5;
nkeynes@1186
   594
    *(void **)(backpatch+5) = XLAT_BLOCK_FOR_CODE(target)->use_list;
nkeynes@1186
   595
    XLAT_BLOCK_FOR_CODE(target)->use_list = backpatch; 
nkeynes@1186
   596
nkeynes@1186
   597
    uint8_t **retptr = ((uint8_t **)__builtin_frame_address(0))+1;
nkeynes@1186
   598
    assert( *retptr == ((uint8_t *)__builtin_return_address(0)) );
nkeynes@1186
   599
	*retptr = backpatch;
nkeynes@1186
   600
}
nkeynes@1186
   601
nkeynes@1186
   602
static void emit_translate_and_backpatch()
nkeynes@1186
   603
{
nkeynes@1186
   604
    /* NB: this is either 7 bytes (i386) or 12 bytes (x86-64) */
nkeynes@1186
   605
    CALL1_ptr_r32(sh4_translate_get_code_and_backpatch, REG_ARG1);
nkeynes@1186
   606
nkeynes@1186
   607
    /* When patched, the jmp instruction will be 5 bytes (either platform) -
nkeynes@1186
   608
     * we need to reserve sizeof(void*) bytes for the use-list
nkeynes@1186
   609
	 * pointer
nkeynes@1186
   610
	 */ 
nkeynes@1186
   611
    if( sizeof(void*) == 8 ) {
nkeynes@1186
   612
        NOP();
nkeynes@1186
   613
    } else {
nkeynes@1186
   614
        NOP2();
nkeynes@1186
   615
    }
nkeynes@1186
   616
}
nkeynes@1186
   617
nkeynes@1186
   618
/**
nkeynes@1186
   619
 * If we're jumping to a fixed address (or at least fixed relative to the
nkeynes@1186
   620
 * current PC, then we can do a direct branch. REG_ARG1 should contain
nkeynes@1186
   621
 * the PC at this point.
nkeynes@1186
   622
 */
nkeynes@1186
   623
static void jump_next_block_fixed_pc( sh4addr_t pc )
nkeynes@1186
   624
{
nkeynes@1186
   625
	if( IS_IN_ICACHE(pc) ) {
nkeynes@1186
   626
	    if( sh4_x86.sh4_mode != SH4_MODE_UNKNOWN ) {
nkeynes@1186
   627
	        /* Fixed address, in cache, and fixed SH4 mode - generate a call to the
nkeynes@1186
   628
	         * fetch-and-backpatch routine, which will replace the call with a branch */
nkeynes@1186
   629
           emit_translate_and_backpatch();	         
nkeynes@1186
   630
           return;
nkeynes@1186
   631
		} else {
nkeynes@1186
   632
            MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@1186
   633
            ANDP_imms_rptr( -4, REG_EAX );
nkeynes@1186
   634
        }
nkeynes@1186
   635
	} else if( sh4_x86.tlb_on ) {
nkeynes@1186
   636
        CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@1186
   637
    } else {
nkeynes@1186
   638
        CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@1186
   639
    }
nkeynes@1186
   640
    jump_next_block();
nkeynes@1186
   641
nkeynes@1186
   642
nkeynes@1186
   643
}
nkeynes@1186
   644
nkeynes@1186
   645
void sh4_translate_unlink_block( void *use_list )
nkeynes@1186
   646
{
nkeynes@1186
   647
	uint8_t *tmp = xlat_output; /* In case something is active, which should never happen */
nkeynes@1186
   648
	void *next = use_list;
nkeynes@1186
   649
	while( next != NULL ) {
nkeynes@1186
   650
    	xlat_output = (uint8_t *)next;
nkeynes@1186
   651
 	    next = *(void **)(xlat_output+5);
nkeynes@1186
   652
 		emit_translate_and_backpatch();
nkeynes@1186
   653
 	}
nkeynes@1186
   654
 	xlat_output = tmp;
nkeynes@1186
   655
}
nkeynes@1186
   656
nkeynes@1186
   657
nkeynes@1186
   658
nkeynes@1125
   659
static void exit_block()
nkeynes@1125
   660
{
nkeynes@1125
   661
	emit_epilogue();
nkeynes@1125
   662
	if( sh4_x86.end_callback ) {
nkeynes@1125
   663
	    MOVP_immptr_rptr(sh4_x86.end_callback, REG_ECX);
nkeynes@1125
   664
	    JMP_rptr(REG_ECX);
nkeynes@1125
   665
	} else {
nkeynes@1125
   666
	    RET();
nkeynes@1125
   667
	}
nkeynes@1125
   668
}
nkeynes@1125
   669
nkeynes@590
   670
/**
nkeynes@995
   671
 * Exit the block with sh4r.pc already written
nkeynes@995
   672
 */
nkeynes@995
   673
void exit_block_pcset( sh4addr_t pc )
nkeynes@995
   674
{
nkeynes@995
   675
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   676
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   677
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   678
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   679
    JBE_label(exitloop);
nkeynes@995
   680
    MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995
   681
    if( sh4_x86.tlb_on ) {
nkeynes@995
   682
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   683
    } else {
nkeynes@995
   684
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   685
    }
nkeynes@1112
   686
    
nkeynes@1112
   687
    jump_next_block();
nkeynes@1112
   688
    JMP_TARGET(exitloop);
nkeynes@995
   689
    exit_block();
nkeynes@995
   690
}
nkeynes@995
   691
nkeynes@995
   692
/**
nkeynes@995
   693
 * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995
   694
 */
nkeynes@995
   695
void exit_block_newpcset( sh4addr_t pc )
nkeynes@995
   696
{
nkeynes@995
   697
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   698
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   699
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   700
    MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995
   701
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   702
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   703
    JBE_label(exitloop);
nkeynes@995
   704
    if( sh4_x86.tlb_on ) {
nkeynes@995
   705
        CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995
   706
    } else {
nkeynes@995
   707
        CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995
   708
    }
nkeynes@1112
   709
	
nkeynes@1112
   710
	jump_next_block();
nkeynes@1112
   711
    JMP_TARGET(exitloop);
nkeynes@995
   712
    exit_block();
nkeynes@995
   713
}
nkeynes@995
   714
nkeynes@995
   715
nkeynes@995
   716
/**
nkeynes@995
   717
 * Exit the block to an absolute PC
nkeynes@995
   718
 */
nkeynes@995
   719
void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   720
{
nkeynes@1112
   721
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   722
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   723
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   724
nkeynes@1112
   725
    MOVL_imm32_r32( pc, REG_ARG1 );
nkeynes@1112
   726
    MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   727
    CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   728
    JBE_label(exitloop);
nkeynes@1186
   729
    jump_next_block_fixed_pc(pc);    
nkeynes@1112
   730
    JMP_TARGET(exitloop);
nkeynes@995
   731
    exit_block();
nkeynes@995
   732
}
nkeynes@995
   733
nkeynes@995
   734
/**
nkeynes@995
   735
 * Exit the block to a relative PC
nkeynes@995
   736
 */
nkeynes@995
   737
void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995
   738
{
nkeynes@1112
   739
    MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@1112
   740
    ADDL_rbpdisp_r32( REG_OFFSET(slice_cycle), REG_ECX );
nkeynes@1112
   741
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@1112
   742
nkeynes@1112
   743
	if( pc == sh4_x86.block_start_pc && sh4_x86.sh4_mode == sh4r.xlat_sh4_mode ) {
nkeynes@1112
   744
	    /* Special case for tight loops - the PC doesn't change, and
nkeynes@1112
   745
	     * we already know the target address. Just check events pending before
nkeynes@1112
   746
	     * looping.
nkeynes@1112
   747
	     */
nkeynes@1112
   748
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   749
        uint32_t backdisp = ((uintptr_t)(sh4_x86.code - xlat_output)) + PROLOGUE_SIZE;
nkeynes@1112
   750
        JCC_cc_prerel(X86_COND_A, backdisp);
nkeynes@1112
   751
	} else {
nkeynes@1112
   752
        MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ARG1 );
nkeynes@1112
   753
        ADDL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@1112
   754
        MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@1112
   755
        CMPL_r32_rbpdisp( REG_ECX, REG_OFFSET(event_pending) );
nkeynes@1112
   756
        JBE_label(exitloop2);
nkeynes@1186
   757
        
nkeynes@1186
   758
        jump_next_block_fixed_pc(pc);
nkeynes@1112
   759
        JMP_TARGET(exitloop2);
nkeynes@995
   760
    }
nkeynes@995
   761
    exit_block();
nkeynes@995
   762
}
nkeynes@995
   763
nkeynes@995
   764
/**
nkeynes@995
   765
 * Exit unconditionally with a general exception
nkeynes@995
   766
 */
nkeynes@1191
   767
void exit_block_exc( int code, sh4addr_t pc, int inst_adjust )
nkeynes@995
   768
{
nkeynes@995
   769
    MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995
   770
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@1191
   771
    MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc + inst_adjust)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995
   772
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995
   773
    MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995
   774
    CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   775
    exit_block();
nkeynes@995
   776
}    
nkeynes@995
   777
nkeynes@995
   778
/**
nkeynes@590
   779
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   780
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   781
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   782
 *
nkeynes@601
   783
 * Performs:
nkeynes@601
   784
 *   Set PC = endpc
nkeynes@601
   785
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   786
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   787
 *   Call sh4_execute_instruction
nkeynes@601
   788
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   789
 */
nkeynes@601
   790
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   791
{
nkeynes@995
   792
    MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
   793
    ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@586
   794
    
nkeynes@995
   795
    MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991
   796
    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995
   797
    MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995
   798
    MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   799
nkeynes@1112
   800
    CALL_ptr( sh4_execute_instruction );
nkeynes@926
   801
    exit_block();
nkeynes@590
   802
} 
nkeynes@539
   803
nkeynes@359
   804
/**
nkeynes@995
   805
 * Write the block trailer (exception handling block)
nkeynes@995
   806
 */
nkeynes@995
   807
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995
   808
    if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995
   809
        // Didn't exit unconditionally already, so write the termination here
nkeynes@995
   810
        exit_block_rel( pc, pc );
nkeynes@995
   811
    }
nkeynes@995
   812
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995
   813
        unsigned int i;
nkeynes@995
   814
        // Exception raised - cleanup and exit
nkeynes@995
   815
        uint8_t *end_ptr = xlat_output;
nkeynes@995
   816
        MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   817
        ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995
   818
        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995
   819
        MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@1191
   820
        INC_r32( REG_EDX );  /* Add 1 for the aborting instruction itself */ 
nkeynes@995
   821
        MULL_r32( REG_EDX );
nkeynes@995
   822
        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995
   823
        exit_block();
nkeynes@995
   824
nkeynes@995
   825
        for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995
   826
            uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995
   827
            if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995
   828
                if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995
   829
                    *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995
   830
                } else {
nkeynes@995
   831
                    *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   832
                }
nkeynes@995
   833
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   834
                int rel = end_ptr - xlat_output;
nkeynes@995
   835
                JMP_prerel(rel);
nkeynes@995
   836
            } else {
nkeynes@995
   837
                *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995
   838
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995
   839
                CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995
   840
                MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995
   841
                int rel = end_ptr - xlat_output;
nkeynes@995
   842
                JMP_prerel(rel);
nkeynes@995
   843
            }
nkeynes@995
   844
        }
nkeynes@995
   845
    }
nkeynes@995
   846
}
nkeynes@539
   847
nkeynes@359
   848
/**
nkeynes@359
   849
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   850
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   851
 * 
nkeynes@586
   852
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   853
 *
nkeynes@359
   854
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   855
 * (eg a branch or 
nkeynes@359
   856
 */
nkeynes@590
   857
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   858
{
nkeynes@388
   859
    uint32_t ir;
nkeynes@586
   860
    /* Read instruction from icache */
nkeynes@586
   861
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   862
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   863
    
nkeynes@586
   864
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   865
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   866
    }
nkeynes@1003
   867
    
nkeynes@1003
   868
    /* check for breakpoints at this pc */
nkeynes@1003
   869
    for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003
   870
        if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003
   871
            sh4_translate_emit_breakpoint(pc);
nkeynes@1003
   872
            break;
nkeynes@1003
   873
        }
nkeynes@571
   874
    }
nkeynes@359
   875
%%
nkeynes@359
   876
/* ALU operations */
nkeynes@359
   877
ADD Rm, Rn {:
nkeynes@671
   878
    COUNT_INST(I_ADD);
nkeynes@991
   879
    load_reg( REG_EAX, Rm );
nkeynes@991
   880
    load_reg( REG_ECX, Rn );
nkeynes@991
   881
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   882
    store_reg( REG_ECX, Rn );
nkeynes@417
   883
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   884
:}
nkeynes@359
   885
ADD #imm, Rn {:  
nkeynes@671
   886
    COUNT_INST(I_ADDI);
nkeynes@991
   887
    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   888
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   889
:}
nkeynes@359
   890
ADDC Rm, Rn {:
nkeynes@671
   891
    COUNT_INST(I_ADDC);
nkeynes@417
   892
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   893
        LDC_t();
nkeynes@417
   894
    }
nkeynes@991
   895
    load_reg( REG_EAX, Rm );
nkeynes@991
   896
    load_reg( REG_ECX, Rn );
nkeynes@991
   897
    ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   898
    store_reg( REG_ECX, Rn );
nkeynes@359
   899
    SETC_t();
nkeynes@417
   900
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   901
:}
nkeynes@359
   902
ADDV Rm, Rn {:
nkeynes@671
   903
    COUNT_INST(I_ADDV);
nkeynes@991
   904
    load_reg( REG_EAX, Rm );
nkeynes@991
   905
    load_reg( REG_ECX, Rn );
nkeynes@991
   906
    ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   907
    store_reg( REG_ECX, Rn );
nkeynes@359
   908
    SETO_t();
nkeynes@417
   909
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   910
:}
nkeynes@359
   911
AND Rm, Rn {:
nkeynes@671
   912
    COUNT_INST(I_AND);
nkeynes@991
   913
    load_reg( REG_EAX, Rm );
nkeynes@991
   914
    load_reg( REG_ECX, Rn );
nkeynes@991
   915
    ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
   916
    store_reg( REG_ECX, Rn );
nkeynes@417
   917
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   918
:}
nkeynes@359
   919
AND #imm, R0 {:  
nkeynes@671
   920
    COUNT_INST(I_ANDI);
nkeynes@991
   921
    load_reg( REG_EAX, 0 );
nkeynes@991
   922
    ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991
   923
    store_reg( REG_EAX, 0 );
nkeynes@417
   924
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   925
:}
nkeynes@359
   926
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   927
    COUNT_INST(I_ANDB);
nkeynes@991
   928
    load_reg( REG_EAX, 0 );
nkeynes@991
   929
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
   930
    MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
   931
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
   932
    MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991
   933
    ANDL_imms_r32(imm, REG_EDX );
nkeynes@991
   934
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
   935
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   936
:}
nkeynes@359
   937
CMP/EQ Rm, Rn {:  
nkeynes@671
   938
    COUNT_INST(I_CMPEQ);
nkeynes@991
   939
    load_reg( REG_EAX, Rm );
nkeynes@991
   940
    load_reg( REG_ECX, Rn );
nkeynes@991
   941
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   942
    SETE_t();
nkeynes@417
   943
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   944
:}
nkeynes@359
   945
CMP/EQ #imm, R0 {:  
nkeynes@671
   946
    COUNT_INST(I_CMPEQI);
nkeynes@991
   947
    load_reg( REG_EAX, 0 );
nkeynes@991
   948
    CMPL_imms_r32(imm, REG_EAX);
nkeynes@359
   949
    SETE_t();
nkeynes@417
   950
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   951
:}
nkeynes@359
   952
CMP/GE Rm, Rn {:  
nkeynes@671
   953
    COUNT_INST(I_CMPGE);
nkeynes@991
   954
    load_reg( REG_EAX, Rm );
nkeynes@991
   955
    load_reg( REG_ECX, Rn );
nkeynes@991
   956
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   957
    SETGE_t();
nkeynes@417
   958
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   959
:}
nkeynes@359
   960
CMP/GT Rm, Rn {: 
nkeynes@671
   961
    COUNT_INST(I_CMPGT);
nkeynes@991
   962
    load_reg( REG_EAX, Rm );
nkeynes@991
   963
    load_reg( REG_ECX, Rn );
nkeynes@991
   964
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   965
    SETG_t();
nkeynes@417
   966
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   967
:}
nkeynes@359
   968
CMP/HI Rm, Rn {:  
nkeynes@671
   969
    COUNT_INST(I_CMPHI);
nkeynes@991
   970
    load_reg( REG_EAX, Rm );
nkeynes@991
   971
    load_reg( REG_ECX, Rn );
nkeynes@991
   972
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   973
    SETA_t();
nkeynes@417
   974
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   975
:}
nkeynes@359
   976
CMP/HS Rm, Rn {: 
nkeynes@671
   977
    COUNT_INST(I_CMPHS);
nkeynes@991
   978
    load_reg( REG_EAX, Rm );
nkeynes@991
   979
    load_reg( REG_ECX, Rn );
nkeynes@991
   980
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359
   981
    SETAE_t();
nkeynes@417
   982
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   983
 :}
nkeynes@359
   984
CMP/PL Rn {: 
nkeynes@671
   985
    COUNT_INST(I_CMPPL);
nkeynes@991
   986
    load_reg( REG_EAX, Rn );
nkeynes@991
   987
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   988
    SETG_t();
nkeynes@417
   989
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   990
:}
nkeynes@359
   991
CMP/PZ Rn {:  
nkeynes@671
   992
    COUNT_INST(I_CMPPZ);
nkeynes@991
   993
    load_reg( REG_EAX, Rn );
nkeynes@991
   994
    CMPL_imms_r32( 0, REG_EAX );
nkeynes@359
   995
    SETGE_t();
nkeynes@417
   996
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   997
:}
nkeynes@361
   998
CMP/STR Rm, Rn {:  
nkeynes@671
   999
    COUNT_INST(I_CMPSTR);
nkeynes@991
  1000
    load_reg( REG_EAX, Rm );
nkeynes@991
  1001
    load_reg( REG_ECX, Rn );
nkeynes@991
  1002
    XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991
  1003
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
  1004
    JE_label(target1);
nkeynes@991
  1005
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991
  1006
    JE_label(target2);
nkeynes@991
  1007
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1008
    TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991
  1009
    JE_label(target3);
nkeynes@991
  1010
    TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380
  1011
    JMP_TARGET(target1);
nkeynes@380
  1012
    JMP_TARGET(target2);
nkeynes@380
  1013
    JMP_TARGET(target3);
nkeynes@368
  1014
    SETE_t();
nkeynes@417
  1015
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1016
:}
nkeynes@361
  1017
DIV0S Rm, Rn {:
nkeynes@671
  1018
    COUNT_INST(I_DIV0S);
nkeynes@991
  1019
    load_reg( REG_EAX, Rm );
nkeynes@991
  1020
    load_reg( REG_ECX, Rn );
nkeynes@991
  1021
    SHRL_imm_r32( 31, REG_EAX );
nkeynes@991
  1022
    SHRL_imm_r32( 31, REG_ECX );
nkeynes@995
  1023
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
  1024
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
  1025
    CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386
  1026
    SETNE_t();
nkeynes@417
  1027
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
  1028
:}
nkeynes@361
  1029
DIV0U {:  
nkeynes@671
  1030
    COUNT_INST(I_DIV0U);
nkeynes@991
  1031
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995
  1032
    MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995
  1033
    MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995
  1034
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
  1035
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
  1036
:}
nkeynes@386
  1037
DIV1 Rm, Rn {:
nkeynes@671
  1038
    COUNT_INST(I_DIV1);
nkeynes@995
  1039
    MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991
  1040
    load_reg( REG_EAX, Rn );
nkeynes@417
  1041
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1042
	LDC_t();
nkeynes@417
  1043
    }
nkeynes@991
  1044
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1045
    SETC_r8( REG_DL ); // Q'
nkeynes@991
  1046
    CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991
  1047
    JE_label(mqequal);
nkeynes@991
  1048
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1049
    JMP_label(end);
nkeynes@380
  1050
    JMP_TARGET(mqequal);
nkeynes@991
  1051
    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386
  1052
    JMP_TARGET(end);
nkeynes@991
  1053
    store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991
  1054
    SETC_r8(REG_AL); // tmp1
nkeynes@991
  1055
    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991
  1056
    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995
  1057
    MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991
  1058
    XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991
  1059
    MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995
  1060
    MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417
  1061
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1062
:}
nkeynes@361
  1063
DMULS.L Rm, Rn {:  
nkeynes@671
  1064
    COUNT_INST(I_DMULS);
nkeynes@991
  1065
    load_reg( REG_EAX, Rm );
nkeynes@991
  1066
    load_reg( REG_ECX, Rn );
nkeynes@991
  1067
    IMULL_r32(REG_ECX);
nkeynes@995
  1068
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1069
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1071
:}
nkeynes@361
  1072
DMULU.L Rm, Rn {:  
nkeynes@671
  1073
    COUNT_INST(I_DMULU);
nkeynes@991
  1074
    load_reg( REG_EAX, Rm );
nkeynes@991
  1075
    load_reg( REG_ECX, Rn );
nkeynes@991
  1076
    MULL_r32(REG_ECX);
nkeynes@995
  1077
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995
  1078
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417
  1079
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1080
:}
nkeynes@359
  1081
DT Rn {:  
nkeynes@671
  1082
    COUNT_INST(I_DT);
nkeynes@991
  1083
    load_reg( REG_EAX, Rn );
nkeynes@991
  1084
    ADDL_imms_r32( -1, REG_EAX );
nkeynes@991
  1085
    store_reg( REG_EAX, Rn );
nkeynes@359
  1086
    SETE_t();
nkeynes@417
  1087
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1088
:}
nkeynes@359
  1089
EXTS.B Rm, Rn {:  
nkeynes@671
  1090
    COUNT_INST(I_EXTSB);
nkeynes@991
  1091
    load_reg( REG_EAX, Rm );
nkeynes@991
  1092
    MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1093
    store_reg( REG_EAX, Rn );
nkeynes@359
  1094
:}
nkeynes@361
  1095
EXTS.W Rm, Rn {:  
nkeynes@671
  1096
    COUNT_INST(I_EXTSW);
nkeynes@991
  1097
    load_reg( REG_EAX, Rm );
nkeynes@991
  1098
    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1099
    store_reg( REG_EAX, Rn );
nkeynes@361
  1100
:}
nkeynes@361
  1101
EXTU.B Rm, Rn {:  
nkeynes@671
  1102
    COUNT_INST(I_EXTUB);
nkeynes@991
  1103
    load_reg( REG_EAX, Rm );
nkeynes@991
  1104
    MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991
  1105
    store_reg( REG_EAX, Rn );
nkeynes@361
  1106
:}
nkeynes@361
  1107
EXTU.W Rm, Rn {:  
nkeynes@671
  1108
    COUNT_INST(I_EXTUW);
nkeynes@991
  1109
    load_reg( REG_EAX, Rm );
nkeynes@991
  1110
    MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991
  1111
    store_reg( REG_EAX, Rn );
nkeynes@361
  1112
:}
nkeynes@586
  1113
MAC.L @Rm+, @Rn+ {:
nkeynes@671
  1114
    COUNT_INST(I_MACL);
nkeynes@586
  1115
    if( Rm == Rn ) {
nkeynes@991
  1116
	load_reg( REG_EAX, Rm );
nkeynes@991
  1117
	check_ralign32( REG_EAX );
nkeynes@991
  1118
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1119
	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991
  1120
	load_reg( REG_EAX, Rm );
nkeynes@991
  1121
	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  1122
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1123
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
  1124
    } else {
nkeynes@991
  1125
	load_reg( REG_EAX, Rm );
nkeynes@991
  1126
	check_ralign32( REG_EAX );
nkeynes@991
  1127
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1128
	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1129
	load_reg( REG_EAX, Rn );
nkeynes@991
  1130
	check_ralign32( REG_EAX );
nkeynes@991
  1131
	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1132
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991
  1133
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1134
    }
nkeynes@939
  1135
    
nkeynes@991
  1136
    IMULL_rspdisp( 0 );
nkeynes@991
  1137
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991
  1138
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@386
  1139
nkeynes@995
  1140
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1141
    TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991
  1142
    JE_label( nosat );
nkeynes@995
  1143
    CALL_ptr( signsat48 );
nkeynes@386
  1144
    JMP_TARGET( nosat );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1146
:}
nkeynes@386
  1147
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
  1148
    COUNT_INST(I_MACW);
nkeynes@586
  1149
    if( Rm == Rn ) {
nkeynes@991
  1150
	load_reg( REG_EAX, Rm );
nkeynes@991
  1151
	check_ralign16( REG_EAX );
nkeynes@991
  1152
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1153
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1154
	load_reg( REG_EAX, Rm );
nkeynes@991
  1155
	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991
  1156
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1157
	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1158
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  1159
	// adding a page-boundary check to skip the second translation
nkeynes@586
  1160
    } else {
nkeynes@1193
  1161
	load_reg( REG_EAX, Rn );
nkeynes@991
  1162
	check_ralign16( REG_EAX );
nkeynes@991
  1163
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1164
        MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@1193
  1165
	load_reg( REG_EAX, Rm );
nkeynes@991
  1166
	check_ralign16( REG_EAX );
nkeynes@991
  1167
	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1168
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991
  1169
	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1170
    }
nkeynes@991
  1171
    IMULL_rspdisp( 0 );
nkeynes@995
  1172
    MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991
  1173
    TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991
  1174
    JE_label( nosat );
nkeynes@386
  1175
nkeynes@991
  1176
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1177
    JNO_label( end );            // 2
nkeynes@995
  1178
    MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995
  1179
    MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991
  1180
    JS_label( positive );        // 2
nkeynes@995
  1181
    MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995
  1182
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1183
    JMP_label(end2);           // 2
nkeynes@386
  1184
nkeynes@386
  1185
    JMP_TARGET(positive);
nkeynes@995
  1186
    MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995
  1187
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991
  1188
    JMP_label(end3);            // 2
nkeynes@386
  1189
nkeynes@386
  1190
    JMP_TARGET(nosat);
nkeynes@991
  1191
    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991
  1192
    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386
  1193
    JMP_TARGET(end);
nkeynes@386
  1194
    JMP_TARGET(end2);
nkeynes@386
  1195
    JMP_TARGET(end3);
nkeynes@417
  1196
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1197
:}
nkeynes@359
  1198
MOVT Rn {:  
nkeynes@671
  1199
    COUNT_INST(I_MOVT);
nkeynes@995
  1200
    MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991
  1201
    store_reg( REG_EAX, Rn );
nkeynes@359
  1202
:}
nkeynes@361
  1203
MUL.L Rm, Rn {:  
nkeynes@671
  1204
    COUNT_INST(I_MULL);
nkeynes@991
  1205
    load_reg( REG_EAX, Rm );
nkeynes@991
  1206
    load_reg( REG_ECX, Rn );
nkeynes@991
  1207
    MULL_r32( REG_ECX );
nkeynes@995
  1208
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1209
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1210
:}
nkeynes@374
  1211
MULS.W Rm, Rn {:
nkeynes@671
  1212
    COUNT_INST(I_MULSW);
nkeynes@995
  1213
    MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1214
    MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1215
    MULL_r32( REG_ECX );
nkeynes@995
  1216
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1217
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1218
:}
nkeynes@374
  1219
MULU.W Rm, Rn {:  
nkeynes@671
  1220
    COUNT_INST(I_MULUW);
nkeynes@995
  1221
    MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995
  1222
    MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991
  1223
    MULL_r32( REG_ECX );
nkeynes@995
  1224
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417
  1225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1226
:}
nkeynes@359
  1227
NEG Rm, Rn {:
nkeynes@671
  1228
    COUNT_INST(I_NEG);
nkeynes@991
  1229
    load_reg( REG_EAX, Rm );
nkeynes@991
  1230
    NEGL_r32( REG_EAX );
nkeynes@991
  1231
    store_reg( REG_EAX, Rn );
nkeynes@417
  1232
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1233
:}
nkeynes@359
  1234
NEGC Rm, Rn {:  
nkeynes@671
  1235
    COUNT_INST(I_NEGC);
nkeynes@991
  1236
    load_reg( REG_EAX, Rm );
nkeynes@991
  1237
    XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359
  1238
    LDC_t();
nkeynes@991
  1239
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1240
    store_reg( REG_ECX, Rn );
nkeynes@359
  1241
    SETC_t();
nkeynes@417
  1242
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1243
:}
nkeynes@359
  1244
NOT Rm, Rn {:  
nkeynes@671
  1245
    COUNT_INST(I_NOT);
nkeynes@991
  1246
    load_reg( REG_EAX, Rm );
nkeynes@991
  1247
    NOTL_r32( REG_EAX );
nkeynes@991
  1248
    store_reg( REG_EAX, Rn );
nkeynes@417
  1249
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1250
:}
nkeynes@359
  1251
OR Rm, Rn {:  
nkeynes@671
  1252
    COUNT_INST(I_OR);
nkeynes@991
  1253
    load_reg( REG_EAX, Rm );
nkeynes@991
  1254
    load_reg( REG_ECX, Rn );
nkeynes@991
  1255
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1256
    store_reg( REG_ECX, Rn );
nkeynes@417
  1257
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1258
:}
nkeynes@359
  1259
OR #imm, R0 {:
nkeynes@671
  1260
    COUNT_INST(I_ORI);
nkeynes@991
  1261
    load_reg( REG_EAX, 0 );
nkeynes@991
  1262
    ORL_imms_r32(imm, REG_EAX);
nkeynes@991
  1263
    store_reg( REG_EAX, 0 );
nkeynes@417
  1264
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1265
:}
nkeynes@374
  1266
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1267
    COUNT_INST(I_ORB);
nkeynes@991
  1268
    load_reg( REG_EAX, 0 );
nkeynes@991
  1269
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1270
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1271
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1272
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1273
    ORL_imms_r32(imm, REG_EDX );
nkeynes@991
  1274
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1275
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1276
:}
nkeynes@359
  1277
ROTCL Rn {:
nkeynes@671
  1278
    COUNT_INST(I_ROTCL);
nkeynes@991
  1279
    load_reg( REG_EAX, Rn );
nkeynes@417
  1280
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1281
	LDC_t();
nkeynes@417
  1282
    }
nkeynes@991
  1283
    RCLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1284
    store_reg( REG_EAX, Rn );
nkeynes@359
  1285
    SETC_t();
nkeynes@417
  1286
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1287
:}
nkeynes@359
  1288
ROTCR Rn {:  
nkeynes@671
  1289
    COUNT_INST(I_ROTCR);
nkeynes@991
  1290
    load_reg( REG_EAX, Rn );
nkeynes@417
  1291
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1292
	LDC_t();
nkeynes@417
  1293
    }
nkeynes@991
  1294
    RCRL_imm_r32( 1, REG_EAX );
nkeynes@991
  1295
    store_reg( REG_EAX, Rn );
nkeynes@359
  1296
    SETC_t();
nkeynes@417
  1297
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1298
:}
nkeynes@359
  1299
ROTL Rn {:  
nkeynes@671
  1300
    COUNT_INST(I_ROTL);
nkeynes@991
  1301
    load_reg( REG_EAX, Rn );
nkeynes@991
  1302
    ROLL_imm_r32( 1, REG_EAX );
nkeynes@991
  1303
    store_reg( REG_EAX, Rn );
nkeynes@359
  1304
    SETC_t();
nkeynes@417
  1305
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1306
:}
nkeynes@359
  1307
ROTR Rn {:  
nkeynes@671
  1308
    COUNT_INST(I_ROTR);
nkeynes@991
  1309
    load_reg( REG_EAX, Rn );
nkeynes@991
  1310
    RORL_imm_r32( 1, REG_EAX );
nkeynes@991
  1311
    store_reg( REG_EAX, Rn );
nkeynes@359
  1312
    SETC_t();
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1314
:}
nkeynes@359
  1315
SHAD Rm, Rn {:
nkeynes@671
  1316
    COUNT_INST(I_SHAD);
nkeynes@359
  1317
    /* Annoyingly enough, not directly convertible */
nkeynes@991
  1318
    load_reg( REG_EAX, Rn );
nkeynes@991
  1319
    load_reg( REG_ECX, Rm );
nkeynes@991
  1320
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1321
    JGE_label(doshl);
nkeynes@361
  1322
                    
nkeynes@991
  1323
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1324
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1325
    JE_label(emptysar);     // 2
nkeynes@991
  1326
    SARL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1327
    JMP_label(end);          // 2
nkeynes@386
  1328
nkeynes@386
  1329
    JMP_TARGET(emptysar);
nkeynes@991
  1330
    SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991
  1331
    JMP_label(end2);
nkeynes@382
  1332
nkeynes@380
  1333
    JMP_TARGET(doshl);
nkeynes@991
  1334
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1335
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380
  1336
    JMP_TARGET(end);
nkeynes@386
  1337
    JMP_TARGET(end2);
nkeynes@991
  1338
    store_reg( REG_EAX, Rn );
nkeynes@417
  1339
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1340
:}
nkeynes@359
  1341
SHLD Rm, Rn {:  
nkeynes@671
  1342
    COUNT_INST(I_SHLD);
nkeynes@991
  1343
    load_reg( REG_EAX, Rn );
nkeynes@991
  1344
    load_reg( REG_ECX, Rm );
nkeynes@991
  1345
    CMPL_imms_r32( 0, REG_ECX );
nkeynes@991
  1346
    JGE_label(doshl);
nkeynes@368
  1347
nkeynes@991
  1348
    NEGL_r32( REG_ECX );      // 2
nkeynes@991
  1349
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1350
    JE_label(emptyshr );
nkeynes@991
  1351
    SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991
  1352
    JMP_label(end);          // 2
nkeynes@386
  1353
nkeynes@386
  1354
    JMP_TARGET(emptyshr);
nkeynes@991
  1355
    XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  1356
    JMP_label(end2);
nkeynes@382
  1357
nkeynes@382
  1358
    JMP_TARGET(doshl);
nkeynes@991
  1359
    ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991
  1360
    SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382
  1361
    JMP_TARGET(end);
nkeynes@386
  1362
    JMP_TARGET(end2);
nkeynes@991
  1363
    store_reg( REG_EAX, Rn );
nkeynes@417
  1364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1365
:}
nkeynes@359
  1366
SHAL Rn {: 
nkeynes@671
  1367
    COUNT_INST(I_SHAL);
nkeynes@991
  1368
    load_reg( REG_EAX, Rn );
nkeynes@991
  1369
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1370
    SETC_t();
nkeynes@991
  1371
    store_reg( REG_EAX, Rn );
nkeynes@417
  1372
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1373
:}
nkeynes@359
  1374
SHAR Rn {:  
nkeynes@671
  1375
    COUNT_INST(I_SHAR);
nkeynes@991
  1376
    load_reg( REG_EAX, Rn );
nkeynes@991
  1377
    SARL_imm_r32( 1, REG_EAX );
nkeynes@397
  1378
    SETC_t();
nkeynes@991
  1379
    store_reg( REG_EAX, Rn );
nkeynes@417
  1380
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1381
:}
nkeynes@359
  1382
SHLL Rn {:  
nkeynes@671
  1383
    COUNT_INST(I_SHLL);
nkeynes@991
  1384
    load_reg( REG_EAX, Rn );
nkeynes@991
  1385
    SHLL_imm_r32( 1, REG_EAX );
nkeynes@397
  1386
    SETC_t();
nkeynes@991
  1387
    store_reg( REG_EAX, Rn );
nkeynes@417
  1388
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1389
:}
nkeynes@359
  1390
SHLL2 Rn {:
nkeynes@671
  1391
    COUNT_INST(I_SHLL);
nkeynes@991
  1392
    load_reg( REG_EAX, Rn );
nkeynes@991
  1393
    SHLL_imm_r32( 2, REG_EAX );
nkeynes@991
  1394
    store_reg( REG_EAX, Rn );
nkeynes@417
  1395
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1396
:}
nkeynes@359
  1397
SHLL8 Rn {:  
nkeynes@671
  1398
    COUNT_INST(I_SHLL);
nkeynes@991
  1399
    load_reg( REG_EAX, Rn );
nkeynes@991
  1400
    SHLL_imm_r32( 8, REG_EAX );
nkeynes@991
  1401
    store_reg( REG_EAX, Rn );
nkeynes@417
  1402
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1403
:}
nkeynes@359
  1404
SHLL16 Rn {:  
nkeynes@671
  1405
    COUNT_INST(I_SHLL);
nkeynes@991
  1406
    load_reg( REG_EAX, Rn );
nkeynes@991
  1407
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1408
    store_reg( REG_EAX, Rn );
nkeynes@417
  1409
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1410
:}
nkeynes@359
  1411
SHLR Rn {:  
nkeynes@671
  1412
    COUNT_INST(I_SHLR);
nkeynes@991
  1413
    load_reg( REG_EAX, Rn );
nkeynes@991
  1414
    SHRL_imm_r32( 1, REG_EAX );
nkeynes@397
  1415
    SETC_t();
nkeynes@991
  1416
    store_reg( REG_EAX, Rn );
nkeynes@417
  1417
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1418
:}
nkeynes@359
  1419
SHLR2 Rn {:  
nkeynes@671
  1420
    COUNT_INST(I_SHLR);
nkeynes@991
  1421
    load_reg( REG_EAX, Rn );
nkeynes@991
  1422
    SHRL_imm_r32( 2, REG_EAX );
nkeynes@991
  1423
    store_reg( REG_EAX, Rn );
nkeynes@417
  1424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1425
:}
nkeynes@359
  1426
SHLR8 Rn {:  
nkeynes@671
  1427
    COUNT_INST(I_SHLR);
nkeynes@991
  1428
    load_reg( REG_EAX, Rn );
nkeynes@991
  1429
    SHRL_imm_r32( 8, REG_EAX );
nkeynes@991
  1430
    store_reg( REG_EAX, Rn );
nkeynes@417
  1431
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1432
:}
nkeynes@359
  1433
SHLR16 Rn {:  
nkeynes@671
  1434
    COUNT_INST(I_SHLR);
nkeynes@991
  1435
    load_reg( REG_EAX, Rn );
nkeynes@991
  1436
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1437
    store_reg( REG_EAX, Rn );
nkeynes@417
  1438
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1439
:}
nkeynes@359
  1440
SUB Rm, Rn {:  
nkeynes@671
  1441
    COUNT_INST(I_SUB);
nkeynes@991
  1442
    load_reg( REG_EAX, Rm );
nkeynes@991
  1443
    load_reg( REG_ECX, Rn );
nkeynes@991
  1444
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1445
    store_reg( REG_ECX, Rn );
nkeynes@417
  1446
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1447
:}
nkeynes@359
  1448
SUBC Rm, Rn {:  
nkeynes@671
  1449
    COUNT_INST(I_SUBC);
nkeynes@991
  1450
    load_reg( REG_EAX, Rm );
nkeynes@991
  1451
    load_reg( REG_ECX, Rn );
nkeynes@417
  1452
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1453
	LDC_t();
nkeynes@417
  1454
    }
nkeynes@991
  1455
    SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1456
    store_reg( REG_ECX, Rn );
nkeynes@394
  1457
    SETC_t();
nkeynes@417
  1458
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1459
:}
nkeynes@359
  1460
SUBV Rm, Rn {:  
nkeynes@671
  1461
    COUNT_INST(I_SUBV);
nkeynes@991
  1462
    load_reg( REG_EAX, Rm );
nkeynes@991
  1463
    load_reg( REG_ECX, Rn );
nkeynes@991
  1464
    SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1465
    store_reg( REG_ECX, Rn );
nkeynes@359
  1466
    SETO_t();
nkeynes@417
  1467
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1468
:}
nkeynes@359
  1469
SWAP.B Rm, Rn {:  
nkeynes@671
  1470
    COUNT_INST(I_SWAPB);
nkeynes@991
  1471
    load_reg( REG_EAX, Rm );
nkeynes@991
  1472
    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991
  1473
    store_reg( REG_EAX, Rn );
nkeynes@359
  1474
:}
nkeynes@359
  1475
SWAP.W Rm, Rn {:  
nkeynes@671
  1476
    COUNT_INST(I_SWAPB);
nkeynes@991
  1477
    load_reg( REG_EAX, Rm );
nkeynes@991
  1478
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1479
    SHLL_imm_r32( 16, REG_ECX );
nkeynes@991
  1480
    SHRL_imm_r32( 16, REG_EAX );
nkeynes@991
  1481
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1482
    store_reg( REG_ECX, Rn );
nkeynes@417
  1483
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1484
:}
nkeynes@361
  1485
TAS.B @Rn {:  
nkeynes@671
  1486
    COUNT_INST(I_TASB);
nkeynes@991
  1487
    load_reg( REG_EAX, Rn );
nkeynes@991
  1488
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1489
    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991
  1490
    TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361
  1491
    SETE_t();
nkeynes@991
  1492
    ORB_imms_r8( 0x80, REG_DL );
nkeynes@991
  1493
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1494
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1495
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1496
:}
nkeynes@361
  1497
TST Rm, Rn {:  
nkeynes@671
  1498
    COUNT_INST(I_TST);
nkeynes@991
  1499
    load_reg( REG_EAX, Rm );
nkeynes@991
  1500
    load_reg( REG_ECX, Rn );
nkeynes@991
  1501
    TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361
  1502
    SETE_t();
nkeynes@417
  1503
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1504
:}
nkeynes@368
  1505
TST #imm, R0 {:  
nkeynes@671
  1506
    COUNT_INST(I_TSTI);
nkeynes@991
  1507
    load_reg( REG_EAX, 0 );
nkeynes@991
  1508
    TESTL_imms_r32( imm, REG_EAX );
nkeynes@368
  1509
    SETE_t();
nkeynes@417
  1510
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1511
:}
nkeynes@368
  1512
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1513
    COUNT_INST(I_TSTB);
nkeynes@991
  1514
    load_reg( REG_EAX, 0);
nkeynes@991
  1515
    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1516
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1517
    TESTB_imms_r8( imm, REG_AL );
nkeynes@368
  1518
    SETE_t();
nkeynes@417
  1519
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1520
:}
nkeynes@359
  1521
XOR Rm, Rn {:  
nkeynes@671
  1522
    COUNT_INST(I_XOR);
nkeynes@991
  1523
    load_reg( REG_EAX, Rm );
nkeynes@991
  1524
    load_reg( REG_ECX, Rn );
nkeynes@991
  1525
    XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1526
    store_reg( REG_ECX, Rn );
nkeynes@417
  1527
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1528
:}
nkeynes@359
  1529
XOR #imm, R0 {:  
nkeynes@671
  1530
    COUNT_INST(I_XORI);
nkeynes@991
  1531
    load_reg( REG_EAX, 0 );
nkeynes@991
  1532
    XORL_imms_r32( imm, REG_EAX );
nkeynes@991
  1533
    store_reg( REG_EAX, 0 );
nkeynes@417
  1534
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1535
:}
nkeynes@359
  1536
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1537
    COUNT_INST(I_XORB);
nkeynes@991
  1538
    load_reg( REG_EAX, 0 );
nkeynes@991
  1539
    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991
  1540
    MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991
  1541
    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991
  1542
    MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991
  1543
    XORL_imms_r32( imm, REG_EDX );
nkeynes@991
  1544
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1545
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1546
:}
nkeynes@361
  1547
XTRCT Rm, Rn {:
nkeynes@671
  1548
    COUNT_INST(I_XTRCT);
nkeynes@991
  1549
    load_reg( REG_EAX, Rm );
nkeynes@991
  1550
    load_reg( REG_ECX, Rn );
nkeynes@991
  1551
    SHLL_imm_r32( 16, REG_EAX );
nkeynes@991
  1552
    SHRL_imm_r32( 16, REG_ECX );
nkeynes@991
  1553
    ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1554
    store_reg( REG_ECX, Rn );
nkeynes@417
  1555
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1556
:}
nkeynes@359
  1557
nkeynes@359
  1558
/* Data move instructions */
nkeynes@359
  1559
MOV Rm, Rn {:  
nkeynes@671
  1560
    COUNT_INST(I_MOV);
nkeynes@991
  1561
    load_reg( REG_EAX, Rm );
nkeynes@991
  1562
    store_reg( REG_EAX, Rn );
nkeynes@359
  1563
:}
nkeynes@359
  1564
MOV #imm, Rn {:  
nkeynes@671
  1565
    COUNT_INST(I_MOVI);
nkeynes@995
  1566
    MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991
  1567
    store_reg( REG_EAX, Rn );
nkeynes@359
  1568
:}
nkeynes@359
  1569
MOV.B Rm, @Rn {:  
nkeynes@671
  1570
    COUNT_INST(I_MOVB);
nkeynes@991
  1571
    load_reg( REG_EAX, Rn );
nkeynes@991
  1572
    load_reg( REG_EDX, Rm );
nkeynes@991
  1573
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1574
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1575
:}
nkeynes@359
  1576
MOV.B Rm, @-Rn {:  
nkeynes@671
  1577
    COUNT_INST(I_MOVB);
nkeynes@991
  1578
    load_reg( REG_EAX, Rn );
nkeynes@991
  1579
    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991
  1580
    load_reg( REG_EDX, Rm );
nkeynes@991
  1581
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991
  1582
    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1583
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1584
:}
nkeynes@359
  1585
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1586
    COUNT_INST(I_MOVB);
nkeynes@991
  1587
    load_reg( REG_EAX, 0 );
nkeynes@991
  1588
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1589
    load_reg( REG_EDX, Rm );
nkeynes@991
  1590
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1592
:}
nkeynes@359
  1593
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1594
    COUNT_INST(I_MOVB);
nkeynes@995
  1595
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1596
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1597
    load_reg( REG_EDX, 0 );
nkeynes@991
  1598
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1599
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1600
:}
nkeynes@359
  1601
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1602
    COUNT_INST(I_MOVB);
nkeynes@991
  1603
    load_reg( REG_EAX, Rn );
nkeynes@991
  1604
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1605
    load_reg( REG_EDX, 0 );
nkeynes@991
  1606
    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417
  1607
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1608
:}
nkeynes@359
  1609
MOV.B @Rm, Rn {:  
nkeynes@671
  1610
    COUNT_INST(I_MOVB);
nkeynes@991
  1611
    load_reg( REG_EAX, Rm );
nkeynes@991
  1612
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1613
    store_reg( REG_EAX, Rn );
nkeynes@417
  1614
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1615
:}
nkeynes@359
  1616
MOV.B @Rm+, Rn {:  
nkeynes@671
  1617
    COUNT_INST(I_MOVB);
nkeynes@991
  1618
    load_reg( REG_EAX, Rm );
nkeynes@991
  1619
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@939
  1620
    if( Rm != Rn ) {
nkeynes@991
  1621
    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@939
  1622
    }
nkeynes@991
  1623
    store_reg( REG_EAX, Rn );
nkeynes@417
  1624
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1625
:}
nkeynes@359
  1626
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1627
    COUNT_INST(I_MOVB);
nkeynes@991
  1628
    load_reg( REG_EAX, 0 );
nkeynes@991
  1629
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1630
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1631
    store_reg( REG_EAX, Rn );
nkeynes@417
  1632
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1633
:}
nkeynes@359
  1634
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1635
    COUNT_INST(I_MOVB);
nkeynes@995
  1636
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1637
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1638
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1639
    store_reg( REG_EAX, 0 );
nkeynes@417
  1640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1641
:}
nkeynes@359
  1642
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1643
    COUNT_INST(I_MOVB);
nkeynes@991
  1644
    load_reg( REG_EAX, Rm );
nkeynes@991
  1645
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1646
    MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991
  1647
    store_reg( REG_EAX, 0 );
nkeynes@417
  1648
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1649
:}
nkeynes@374
  1650
MOV.L Rm, @Rn {:
nkeynes@671
  1651
    COUNT_INST(I_MOVL);
nkeynes@991
  1652
    load_reg( REG_EAX, Rn );
nkeynes@991
  1653
    check_walign32(REG_EAX);
nkeynes@991
  1654
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1655
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1656
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1657
    JNE_label( notsq );
nkeynes@991
  1658
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1659
    load_reg( REG_EDX, Rm );
nkeynes@991
  1660
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1661
    JMP_label(end);
nkeynes@930
  1662
    JMP_TARGET(notsq);
nkeynes@991
  1663
    load_reg( REG_EDX, Rm );
nkeynes@991
  1664
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1665
    JMP_TARGET(end);
nkeynes@417
  1666
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1667
:}
nkeynes@361
  1668
MOV.L Rm, @-Rn {:  
nkeynes@671
  1669
    COUNT_INST(I_MOVL);
nkeynes@991
  1670
    load_reg( REG_EAX, Rn );
nkeynes@991
  1671
    ADDL_imms_r32( -4, REG_EAX );
nkeynes@991
  1672
    check_walign32( REG_EAX );
nkeynes@991
  1673
    load_reg( REG_EDX, Rm );
nkeynes@991
  1674
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  1675
    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1676
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1677
:}
nkeynes@361
  1678
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1679
    COUNT_INST(I_MOVL);
nkeynes@991
  1680
    load_reg( REG_EAX, 0 );
nkeynes@991
  1681
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1682
    check_walign32( REG_EAX );
nkeynes@991
  1683
    load_reg( REG_EDX, Rm );
nkeynes@991
  1684
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1686
:}
nkeynes@361
  1687
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1688
    COUNT_INST(I_MOVL);
nkeynes@995
  1689
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1690
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1691
    check_walign32( REG_EAX );
nkeynes@991
  1692
    load_reg( REG_EDX, 0 );
nkeynes@991
  1693
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1694
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1695
:}
nkeynes@361
  1696
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1697
    COUNT_INST(I_MOVL);
nkeynes@991
  1698
    load_reg( REG_EAX, Rn );
nkeynes@991
  1699
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1700
    check_walign32( REG_EAX );
nkeynes@991
  1701
    MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991
  1702
    ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991
  1703
    CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991
  1704
    JNE_label( notsq );
nkeynes@991
  1705
    ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991
  1706
    load_reg( REG_EDX, Rm );
nkeynes@991
  1707
    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991
  1708
    JMP_label(end);
nkeynes@930
  1709
    JMP_TARGET(notsq);
nkeynes@991
  1710
    load_reg( REG_EDX, Rm );
nkeynes@991
  1711
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@930
  1712
    JMP_TARGET(end);
nkeynes@417
  1713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1714
:}
nkeynes@361
  1715
MOV.L @Rm, Rn {:  
nkeynes@671
  1716
    COUNT_INST(I_MOVL);
nkeynes@991
  1717
    load_reg( REG_EAX, Rm );
nkeynes@991
  1718
    check_ralign32( REG_EAX );
nkeynes@991
  1719
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1720
    store_reg( REG_EAX, Rn );
nkeynes@417
  1721
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1722
:}
nkeynes@361
  1723
MOV.L @Rm+, Rn {:  
nkeynes@671
  1724
    COUNT_INST(I_MOVL);
nkeynes@991
  1725
    load_reg( REG_EAX, Rm );
nkeynes@991
  1726
    check_ralign32( REG_EAX );
nkeynes@991
  1727
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@939
  1728
    if( Rm != Rn ) {
nkeynes@991
  1729
    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@939
  1730
    }
nkeynes@991
  1731
    store_reg( REG_EAX, Rn );
nkeynes@417
  1732
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1733
:}
nkeynes@361
  1734
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1735
    COUNT_INST(I_MOVL);
nkeynes@991
  1736
    load_reg( REG_EAX, 0 );
nkeynes@991
  1737
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1738
    check_ralign32( REG_EAX );
nkeynes@991
  1739
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1740
    store_reg( REG_EAX, Rn );
nkeynes@417
  1741
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1742
:}
nkeynes@361
  1743
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1744
    COUNT_INST(I_MOVL);
nkeynes@995
  1745
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1746
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1747
    check_ralign32( REG_EAX );
nkeynes@991
  1748
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1749
    store_reg( REG_EAX, 0 );
nkeynes@417
  1750
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1751
:}
nkeynes@361
  1752
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1753
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1754
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1755
	SLOTILLEGAL();
nkeynes@374
  1756
    } else {
nkeynes@388
  1757
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@1125
  1758
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1759
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1760
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1761
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1762
nkeynes@586
  1763
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1764
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1765
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1766
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1767
	    // behaviour though.
nkeynes@586
  1768
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1769
	    MOVL_moffptr_eax( ptr );
nkeynes@388
  1770
	} else {
nkeynes@586
  1771
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1772
	    // different virtual address than the translation was done with,
nkeynes@586
  1773
	    // but we can safely assume that the low bits are the same.
nkeynes@995
  1774
	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991
  1775
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1776
	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@586
  1777
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1778
	}
nkeynes@991
  1779
	store_reg( REG_EAX, Rn );
nkeynes@374
  1780
    }
nkeynes@361
  1781
:}
nkeynes@361
  1782
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1783
    COUNT_INST(I_MOVL);
nkeynes@991
  1784
    load_reg( REG_EAX, Rm );
nkeynes@991
  1785
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1786
    check_ralign32( REG_EAX );
nkeynes@991
  1787
    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  1788
    store_reg( REG_EAX, Rn );
nkeynes@417
  1789
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1790
:}
nkeynes@361
  1791
MOV.W Rm, @Rn {:  
nkeynes@671
  1792
    COUNT_INST(I_MOVW);
nkeynes@991
  1793
    load_reg( REG_EAX, Rn );
nkeynes@991
  1794
    check_walign16( REG_EAX );
nkeynes@991
  1795
    load_reg( REG_EDX, Rm );
nkeynes@991
  1796
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1797
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1798
:}
nkeynes@361
  1799
MOV.W Rm, @-Rn {:  
nkeynes@671
  1800
    COUNT_INST(I_MOVW);
nkeynes@991
  1801
    load_reg( REG_EAX, Rn );
nkeynes@991
  1802
    check_walign16( REG_EAX );
nkeynes@991
  1803
    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991
  1804
    load_reg( REG_EDX, Rm );
nkeynes@991
  1805
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991
  1806
    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1807
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1808
:}
nkeynes@361
  1809
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1810
    COUNT_INST(I_MOVW);
nkeynes@991
  1811
    load_reg( REG_EAX, 0 );
nkeynes@991
  1812
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991
  1813
    check_walign16( REG_EAX );
nkeynes@991
  1814
    load_reg( REG_EDX, Rm );
nkeynes@991
  1815
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1816
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1817
:}
nkeynes@361
  1818
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1819
    COUNT_INST(I_MOVW);
nkeynes@995
  1820
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1821
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1822
    check_walign16( REG_EAX );
nkeynes@991
  1823
    load_reg( REG_EDX, 0 );
nkeynes@991
  1824
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1825
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1826
:}
nkeynes@361
  1827
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1828
    COUNT_INST(I_MOVW);
nkeynes@991
  1829
    load_reg( REG_EAX, Rn );
nkeynes@991
  1830
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1831
    check_walign16( REG_EAX );
nkeynes@991
  1832
    load_reg( REG_EDX, 0 );
nkeynes@991
  1833
    MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417
  1834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1835
:}
nkeynes@361
  1836
MOV.W @Rm, Rn {:  
nkeynes@671
  1837
    COUNT_INST(I_MOVW);
nkeynes@991
  1838
    load_reg( REG_EAX, Rm );
nkeynes@991
  1839
    check_ralign16( REG_EAX );
nkeynes@991
  1840
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1841
    store_reg( REG_EAX, Rn );
nkeynes@417
  1842
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1843
:}
nkeynes@361
  1844
MOV.W @Rm+, Rn {:  
nkeynes@671
  1845
    COUNT_INST(I_MOVW);
nkeynes@991
  1846
    load_reg( REG_EAX, Rm );
nkeynes@991
  1847
    check_ralign16( REG_EAX );
nkeynes@991
  1848
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@939
  1849
    if( Rm != Rn ) {
nkeynes@991
  1850
        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@939
  1851
    }
nkeynes@991
  1852
    store_reg( REG_EAX, Rn );
nkeynes@417
  1853
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1854
:}
nkeynes@361
  1855
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1856
    COUNT_INST(I_MOVW);
nkeynes@991
  1857
    load_reg( REG_EAX, 0 );
nkeynes@991
  1858
    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991
  1859
    check_ralign16( REG_EAX );
nkeynes@991
  1860
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1861
    store_reg( REG_EAX, Rn );
nkeynes@417
  1862
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1863
:}
nkeynes@361
  1864
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1865
    COUNT_INST(I_MOVW);
nkeynes@995
  1866
    MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991
  1867
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1868
    check_ralign16( REG_EAX );
nkeynes@991
  1869
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1870
    store_reg( REG_EAX, 0 );
nkeynes@417
  1871
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1872
:}
nkeynes@361
  1873
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1874
    COUNT_INST(I_MOVW);
nkeynes@374
  1875
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1876
	SLOTILLEGAL();
nkeynes@374
  1877
    } else {
nkeynes@586
  1878
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1879
	uint32_t target = pc + disp + 4;
nkeynes@1125
  1880
	if( sh4_x86.fastmem && IS_IN_ICACHE(target) ) {
nkeynes@586
  1881
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991
  1882
	    MOVL_moffptr_eax( ptr );
nkeynes@991
  1883
	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@586
  1884
	} else {
nkeynes@995
  1885
	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991
  1886
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1887
	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@586
  1888
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1889
	}
nkeynes@991
  1890
	store_reg( REG_EAX, Rn );
nkeynes@374
  1891
    }
nkeynes@361
  1892
:}
nkeynes@361
  1893
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1894
    COUNT_INST(I_MOVW);
nkeynes@991
  1895
    load_reg( REG_EAX, Rm );
nkeynes@991
  1896
    ADDL_imms_r32( disp, REG_EAX );
nkeynes@991
  1897
    check_ralign16( REG_EAX );
nkeynes@991
  1898
    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991
  1899
    store_reg( REG_EAX, 0 );
nkeynes@417
  1900
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1901
:}
nkeynes@361
  1902
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1903
    COUNT_INST(I_MOVA);
nkeynes@374
  1904
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1905
	SLOTILLEGAL();
nkeynes@374
  1906
    } else {
nkeynes@995
  1907
	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991
  1908
	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991
  1909
	store_reg( REG_ECX, 0 );
nkeynes@586
  1910
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1911
    }
nkeynes@361
  1912
:}
nkeynes@361
  1913
MOVCA.L R0, @Rn {:  
nkeynes@671
  1914
    COUNT_INST(I_MOVCA);
nkeynes@991
  1915
    load_reg( REG_EAX, Rn );
nkeynes@991
  1916
    check_walign32( REG_EAX );
nkeynes@991
  1917
    load_reg( REG_EDX, 0 );
nkeynes@991
  1918
    MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417
  1919
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1920
:}
nkeynes@359
  1921
nkeynes@359
  1922
/* Control transfer instructions */
nkeynes@374
  1923
BF disp {:
nkeynes@671
  1924
    COUNT_INST(I_BF);
nkeynes@374
  1925
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1926
	SLOTILLEGAL();
nkeynes@374
  1927
    } else {
nkeynes@586
  1928
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  1929
	JT_label( nottaken );
nkeynes@586
  1930
	exit_block_rel(target, pc+2 );
nkeynes@380
  1931
	JMP_TARGET(nottaken);
nkeynes@408
  1932
	return 2;
nkeynes@374
  1933
    }
nkeynes@374
  1934
:}
nkeynes@374
  1935
BF/S disp {:
nkeynes@671
  1936
    COUNT_INST(I_BFS);
nkeynes@374
  1937
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1938
	SLOTILLEGAL();
nkeynes@374
  1939
    } else {
nkeynes@590
  1940
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1941
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1942
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1943
	    JT_label(nottaken);
nkeynes@991
  1944
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  1945
	    JMP_TARGET(nottaken);
nkeynes@991
  1946
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  1947
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1948
	    exit_block_emu(pc+2);
nkeynes@601
  1949
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1950
	    return 2;
nkeynes@601
  1951
	} else {
nkeynes@601
  1952
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  1953
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  1954
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1955
	    }
nkeynes@601
  1956
	    sh4vma_t target = disp + pc + 4;
nkeynes@991
  1957
	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991
  1958
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879
  1959
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1960
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  1961
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  1962
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1963
	    
nkeynes@601
  1964
	    // not taken
nkeynes@601
  1965
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1966
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1967
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1968
	    return 4;
nkeynes@417
  1969
	}
nkeynes@374
  1970
    }
nkeynes@374
  1971
:}
nkeynes@374
  1972
BRA disp {:  
nkeynes@671
  1973
    COUNT_INST(I_BRA);
nkeynes@374
  1974
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1975
	SLOTILLEGAL();
nkeynes@374
  1976
    } else {
nkeynes@590
  1977
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1978
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1979
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  1980
	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1981
	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  1982
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  1983
	    exit_block_emu(pc+2);
nkeynes@601
  1984
	    return 2;
nkeynes@601
  1985
	} else {
nkeynes@601
  1986
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1987
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1988
	    return 4;
nkeynes@601
  1989
	}
nkeynes@374
  1990
    }
nkeynes@374
  1991
:}
nkeynes@374
  1992
BRAF Rn {:  
nkeynes@671
  1993
    COUNT_INST(I_BRAF);
nkeynes@374
  1994
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1995
	SLOTILLEGAL();
nkeynes@374
  1996
    } else {
nkeynes@995
  1997
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  1998
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  1999
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  2000
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  2001
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2002
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2003
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2004
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2005
	    exit_block_emu(pc+2);
nkeynes@601
  2006
	    return 2;
nkeynes@601
  2007
	} else {
nkeynes@601
  2008
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  2009
	    exit_block_newpcset(pc+4);
nkeynes@601
  2010
	    return 4;
nkeynes@601
  2011
	}
nkeynes@374
  2012
    }
nkeynes@374
  2013
:}
nkeynes@374
  2014
BSR disp {:  
nkeynes@671
  2015
    COUNT_INST(I_BSR);
nkeynes@374
  2016
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2017
	SLOTILLEGAL();
nkeynes@374
  2018
    } else {
nkeynes@995
  2019
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2020
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2021
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590
  2022
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2023
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2024
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2025
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991
  2026
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995
  2027
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  2028
	    exit_block_emu(pc+2);
nkeynes@601
  2029
	    return 2;
nkeynes@601
  2030
	} else {
nkeynes@601
  2031
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  2032
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2033
	    return 4;
nkeynes@601
  2034
	}
nkeynes@374
  2035
    }
nkeynes@374
  2036
:}
nkeynes@374
  2037
BSRF Rn {:  
nkeynes@671
  2038
    COUNT_INST(I_BSRF);
nkeynes@374
  2039
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2040
	SLOTILLEGAL();
nkeynes@374
  2041
    } else {
nkeynes@995
  2042
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2043
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2044
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2045
	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995
  2046
	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590
  2047
nkeynes@601
  2048
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  2049
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2050
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2051
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2052
	    exit_block_emu(pc+2);
nkeynes@601
  2053
	    return 2;
nkeynes@601
  2054
	} else {
nkeynes@601
  2055
	    sh4_translate_instruction( pc + 2 );
nkeynes@974
  2056
	    exit_block_newpcset(pc+4);
nkeynes@601
  2057
	    return 4;
nkeynes@601
  2058
	}
nkeynes@374
  2059
    }
nkeynes@374
  2060
:}
nkeynes@374
  2061
BT disp {:
nkeynes@671
  2062
    COUNT_INST(I_BT);
nkeynes@374
  2063
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2064
	SLOTILLEGAL();
nkeynes@374
  2065
    } else {
nkeynes@586
  2066
	sh4vma_t target = disp + pc + 4;
nkeynes@991
  2067
	JF_label( nottaken );
nkeynes@586
  2068
	exit_block_rel(target, pc+2 );
nkeynes@380
  2069
	JMP_TARGET(nottaken);
nkeynes@408
  2070
	return 2;
nkeynes@374
  2071
    }
nkeynes@374
  2072
:}
nkeynes@374
  2073
BT/S disp {:
nkeynes@671
  2074
    COUNT_INST(I_BTS);
nkeynes@374
  2075
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2076
	SLOTILLEGAL();
nkeynes@374
  2077
    } else {
nkeynes@590
  2078
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2079
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995
  2080
	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991
  2081
	    JF_label(nottaken);
nkeynes@991
  2082
	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601
  2083
	    JMP_TARGET(nottaken);
nkeynes@991
  2084
	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995
  2085
	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601
  2086
	    exit_block_emu(pc+2);
nkeynes@601
  2087
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2088
	    return 2;
nkeynes@601
  2089
	} else {
nkeynes@601
  2090
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991
  2091
		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601
  2092
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2093
	    }
nkeynes@991
  2094
	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991
  2095
	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991
  2096
nkeynes@879
  2097
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  2098
	    sh4_translate_instruction(pc+2);
nkeynes@1091
  2099
            sh4_x86.in_delay_slot = DELAY_PC; /* Cleared by sh4_translate_instruction */
nkeynes@601
  2100
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2101
	    // not taken
nkeynes@601
  2102
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  2103
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  2104
	    sh4_translate_instruction(pc+2);
nkeynes@601
  2105
	    return 4;
nkeynes@417
  2106
	}
nkeynes@374
  2107
    }
nkeynes@374
  2108
:}
nkeynes@374
  2109
JMP @Rn {:  
nkeynes@671
  2110
    COUNT_INST(I_JMP);
nkeynes@374
  2111
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2112
	SLOTILLEGAL();
nkeynes@374
  2113
    } else {
nkeynes@991
  2114
	load_reg( REG_ECX, Rn );
nkeynes@995
  2115
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2116
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2117
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2118
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2119
	    exit_block_emu(pc+2);
nkeynes@601
  2120
	    return 2;
nkeynes@601
  2121
	} else {
nkeynes@601
  2122
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2123
	    exit_block_newpcset(pc+4);
nkeynes@601
  2124
	    return 4;
nkeynes@601
  2125
	}
nkeynes@374
  2126
    }
nkeynes@374
  2127
:}
nkeynes@374
  2128
JSR @Rn {:  
nkeynes@671
  2129
    COUNT_INST(I_JSR);
nkeynes@374
  2130
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2131
	SLOTILLEGAL();
nkeynes@374
  2132
    } else {
nkeynes@995
  2133
	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991
  2134
	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995
  2135
	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991
  2136
	load_reg( REG_ECX, Rn );
nkeynes@995
  2137
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601
  2138
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2139
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2140
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2141
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2142
	    exit_block_emu(pc+2);
nkeynes@601
  2143
	    return 2;
nkeynes@601
  2144
	} else {
nkeynes@601
  2145
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2146
	    exit_block_newpcset(pc+4);
nkeynes@601
  2147
	    return 4;
nkeynes@601
  2148
	}
nkeynes@374
  2149
    }
nkeynes@374
  2150
:}
nkeynes@374
  2151
RTE {:  
nkeynes@671
  2152
    COUNT_INST(I_RTE);
nkeynes@374
  2153
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2154
	SLOTILLEGAL();
nkeynes@374
  2155
    } else {
nkeynes@408
  2156
	check_priv();
nkeynes@995
  2157
	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995
  2158
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995
  2159
	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995
  2160
	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590
  2161
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  2162
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2163
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  2164
	sh4_x86.branch_taken = TRUE;
nkeynes@1112
  2165
    sh4_x86.sh4_mode = SH4_MODE_UNKNOWN;
nkeynes@601
  2166
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2167
	    exit_block_emu(pc+2);
nkeynes@601
  2168
	    return 2;
nkeynes@601
  2169
	} else {
nkeynes@601
  2170
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2171
	    exit_block_newpcset(pc+4);
nkeynes@601
  2172
	    return 4;
nkeynes@601
  2173
	}
nkeynes@374
  2174
    }
nkeynes@374
  2175
:}
nkeynes@374
  2176
RTS {:  
nkeynes@671
  2177
    COUNT_INST(I_RTS);
nkeynes@374
  2178
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2179
	SLOTILLEGAL();
nkeynes@374
  2180
    } else {
nkeynes@995
  2181
	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995
  2182
	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590
  2183
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2184
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2185
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2186
	    exit_block_emu(pc+2);
nkeynes@601
  2187
	    return 2;
nkeynes@601
  2188
	} else {
nkeynes@601
  2189
	    sh4_translate_instruction(pc+2);
nkeynes@974
  2190
	    exit_block_newpcset(pc+4);
nkeynes@601
  2191
	    return 4;
nkeynes@601
  2192
	}
nkeynes@374
  2193
    }
nkeynes@374
  2194
:}
nkeynes@374
  2195
TRAPA #imm {:  
nkeynes@671
  2196
    COUNT_INST(I_TRAPA);
nkeynes@374
  2197
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2198
	SLOTILLEGAL();
nkeynes@374
  2199
    } else {
nkeynes@995
  2200
	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991
  2201
	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995
  2202
	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995
  2203
	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417
  2204
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974
  2205
	exit_block_pcset(pc+2);
nkeynes@409
  2206
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  2207
	return 2;
nkeynes@374
  2208
    }
nkeynes@374
  2209
:}
nkeynes@374
  2210
UNDEF {:  
nkeynes@671
  2211
    COUNT_INST(I_UNDEF);
nkeynes@374
  2212
    if( sh4_x86.in_delay_slot ) {
nkeynes@1191
  2213
	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2, 4);    
nkeynes@374
  2214
    } else {
nkeynes@1191
  2215
	exit_block_exc(EXC_ILLEGAL, pc, 2);    
nkeynes@408
  2216
	return 2;
nkeynes@374
  2217
    }
nkeynes@368
  2218
:}
nkeynes@374
  2219
nkeynes@374
  2220
CLRMAC {:  
nkeynes@671
  2221
    COUNT_INST(I_CLRMAC);
nkeynes@991
  2222
    XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995
  2223
    MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995
  2224
    MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417
  2225
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2226
:}
nkeynes@374
  2227
CLRS {:
nkeynes@671
  2228
    COUNT_INST(I_CLRS);
nkeynes@374
  2229
    CLC();
nkeynes@991
  2230
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2231
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  2232
:}
nkeynes@374
  2233
CLRT {:  
nkeynes@671
  2234
    COUNT_INST(I_CLRT);
nkeynes@374
  2235
    CLC();
nkeynes@374
  2236
    SETC_t();
nkeynes@417
  2237
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2238
:}
nkeynes@374
  2239
SETS {:  
nkeynes@671
  2240
    COUNT_INST(I_SETS);
nkeynes@374
  2241
    STC();
nkeynes@991
  2242
    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872
  2243
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2244
:}
nkeynes@374
  2245
SETT {:  
nkeynes@671
  2246
    COUNT_INST(I_SETT);
nkeynes@374
  2247
    STC();
nkeynes@374
  2248
    SETC_t();
nkeynes@417
  2249
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  2250
:}
nkeynes@359
  2251
nkeynes@375
  2252
/* Floating point moves */
nkeynes@375
  2253
FMOV FRm, FRn {:  
nkeynes@671
  2254
    COUNT_INST(I_FMOV1);
nkeynes@377
  2255
    check_fpuen();
nkeynes@901
  2256
    if( sh4_x86.double_size ) {
nkeynes@991
  2257
        load_dr0( REG_EAX, FRm );
nkeynes@991
  2258
        load_dr1( REG_ECX, FRm );
nkeynes@991
  2259
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2260
        store_dr1( REG_ECX, FRn );
nkeynes@901
  2261
    } else {
nkeynes@991
  2262
        load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991
  2263
        store_fr( REG_EAX, FRn );
nkeynes@901
  2264
    }
nkeynes@375
  2265
:}
nkeynes@416
  2266
FMOV FRm, @Rn {: 
nkeynes@671
  2267
    COUNT_INST(I_FMOV2);
nkeynes@586
  2268
    check_fpuen();
nkeynes@991
  2269
    load_reg( REG_EAX, Rn );
nkeynes@901
  2270
    if( sh4_x86.double_size ) {
nkeynes@991
  2271
        check_walign64( REG_EAX );
nkeynes@991
  2272
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2273
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2274
        load_reg( REG_EAX, Rn );
nkeynes@991
  2275
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2276
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2277
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2278
    } else {
nkeynes@991
  2279
        check_walign32( REG_EAX );
nkeynes@991
  2280
        load_fr( REG_EDX, FRm );
nkeynes@991
  2281
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2282
    }
nkeynes@417
  2283
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2284
:}
nkeynes@375
  2285
FMOV @Rm, FRn {:  
nkeynes@671
  2286
    COUNT_INST(I_FMOV5);
nkeynes@586
  2287
    check_fpuen();
nkeynes@991
  2288
    load_reg( REG_EAX, Rm );
nkeynes@901
  2289
    if( sh4_x86.double_size ) {
nkeynes@991
  2290
        check_ralign64( REG_EAX );
nkeynes@991
  2291
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2292
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2293
        load_reg( REG_EAX, Rm );
nkeynes@991
  2294
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2295
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2296
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2297
    } else {
nkeynes@991
  2298
        check_ralign32( REG_EAX );
nkeynes@991
  2299
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2300
        store_fr( REG_EAX, FRn );
nkeynes@901
  2301
    }
nkeynes@417
  2302
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2303
:}
nkeynes@377
  2304
FMOV FRm, @-Rn {:  
nkeynes@671
  2305
    COUNT_INST(I_FMOV3);
nkeynes@586
  2306
    check_fpuen();
nkeynes@991
  2307
    load_reg( REG_EAX, Rn );
nkeynes@901
  2308
    if( sh4_x86.double_size ) {
nkeynes@991
  2309
        check_walign64( REG_EAX );
nkeynes@991
  2310
        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991
  2311
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2312
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2313
        load_reg( REG_EAX, Rn );
nkeynes@991
  2314
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2315
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2316
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2317
        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  2318
    } else {
nkeynes@991
  2319
        check_walign32( REG_EAX );
nkeynes@991
  2320
        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991
  2321
        load_fr( REG_EDX, FRm );
nkeynes@991
  2322
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2323
        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  2324
    }
nkeynes@417
  2325
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2326
:}
nkeynes@416
  2327
FMOV @Rm+, FRn {:
nkeynes@671
  2328
    COUNT_INST(I_FMOV6);
nkeynes@586
  2329
    check_fpuen();
nkeynes@991
  2330
    load_reg( REG_EAX, Rm );
nkeynes@901
  2331
    if( sh4_x86.double_size ) {
nkeynes@991
  2332
        check_ralign64( REG_EAX );
nkeynes@991
  2333
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2334
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2335
        load_reg( REG_EAX, Rm );
nkeynes@991
  2336
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2337
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2338
        store_dr1( REG_EAX, FRn );
nkeynes@991
  2339
        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  2340
    } else {
nkeynes@991
  2341
        check_ralign32( REG_EAX );
nkeynes@991
  2342
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2343
        store_fr( REG_EAX, FRn );
nkeynes@991
  2344
        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  2345
    }
nkeynes@417
  2346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2347
:}
nkeynes@377
  2348
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  2349
    COUNT_INST(I_FMOV4);
nkeynes@586
  2350
    check_fpuen();
nkeynes@991
  2351
    load_reg( REG_EAX, Rn );
nkeynes@991
  2352
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2353
    if( sh4_x86.double_size ) {
nkeynes@991
  2354
        check_walign64( REG_EAX );
nkeynes@991
  2355
        load_dr0( REG_EDX, FRm );
nkeynes@991
  2356
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991
  2357
        load_reg( REG_EAX, Rn );
nkeynes@991
  2358
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2359
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2360
        load_dr1( REG_EDX, FRm );
nkeynes@991
  2361
        MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@901
  2362
    } else {
nkeynes@991
  2363
        check_walign32( REG_EAX );
nkeynes@991
  2364
        load_fr( REG_EDX, FRm );
nkeynes@991
  2365
        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@901
  2366
    }
nkeynes@417
  2367
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2368
:}
nkeynes@377
  2369
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2370
    COUNT_INST(I_FMOV7);
nkeynes@586
  2371
    check_fpuen();
nkeynes@991
  2372
    load_reg( REG_EAX, Rm );
nkeynes@991
  2373
    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901
  2374
    if( sh4_x86.double_size ) {
nkeynes@991
  2375
        check_ralign64( REG_EAX );
nkeynes@991
  2376
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2377
        store_dr0( REG_EAX, FRn );
nkeynes@991
  2378
        load_reg( REG_EAX, Rm );
nkeynes@991
  2379
        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991
  2380
        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991
  2381
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2382
        store_dr1( REG_EAX, FRn );
nkeynes@901
  2383
    } else {
nkeynes@991
  2384
        check_ralign32( REG_EAX );
nkeynes@991
  2385
        MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991
  2386
        store_fr( REG_EAX, FRn );
nkeynes@901
  2387
    }
nkeynes@417
  2388
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2389
:}
nkeynes@377
  2390
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2391
    COUNT_INST(I_FLDI0);
nkeynes@377
  2392
    check_fpuen();
nkeynes@901
  2393
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2394
        XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991
  2395
        store_fr( REG_EAX, FRn );
nkeynes@901
  2396
    }
nkeynes@417
  2397
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2398
:}
nkeynes@377
  2399
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2400
    COUNT_INST(I_FLDI1);
nkeynes@377
  2401
    check_fpuen();
nkeynes@901
  2402
    if( sh4_x86.double_prec == 0 ) {
nkeynes@995
  2403
        MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991
  2404
        store_fr( REG_EAX, FRn );
nkeynes@901
  2405
    }
nkeynes@377
  2406
:}
nkeynes@377
  2407
nkeynes@377
  2408
FLOAT FPUL, FRn {:  
nkeynes@671
  2409
    COUNT_INST(I_FLOAT);
nkeynes@377
  2410
    check_fpuen();
nkeynes@991
  2411
    FILD_rbpdisp(R_FPUL);
nkeynes@901
  2412
    if( sh4_x86.double_prec ) {
nkeynes@901
  2413
        pop_dr( FRn );
nkeynes@901
  2414
    } else {
nkeynes@901
  2415
        pop_fr( FRn );
nkeynes@901
  2416
    }
nkeynes@377
  2417
:}
nkeynes@377
  2418
FTRC FRm, FPUL {:  
nkeynes@671
  2419
    COUNT_INST(I_FTRC);
nkeynes@377
  2420
    check_fpuen();
nkeynes@901
  2421
    if( sh4_x86.double_prec ) {
nkeynes@901
  2422
        push_dr( FRm );
nkeynes@901
  2423
    } else {
nkeynes@901
  2424
        push_fr( FRm );
nkeynes@901
  2425
    }
nkeynes@995
  2426
    MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991
  2427
    FILD_r32disp( REG_ECX, 0 );
nkeynes@388
  2428
    FCOMIP_st(1);
nkeynes@991
  2429
    JNA_label( sat );
nkeynes@995
  2430
    MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@995
  2431
    FILD_r32disp( REG_ECX, 0 );
nkeynes@995
  2432
    FCOMIP_st(1);              
nkeynes@995
  2433
    JAE_label( sat2 );            
nkeynes@995
  2434
    MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991
  2435
    FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2436
    MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991
  2437
    FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995
  2438
    FISTP_rbpdisp(R_FPUL);             
nkeynes@991
  2439
    FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995
  2440
    JMP_label(end);             
nkeynes@388
  2441
nkeynes@388
  2442
    JMP_TARGET(sat);
nkeynes@388
  2443
    JMP_TARGET(sat2);
nkeynes@991
  2444
    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995
  2445
    MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388
  2446
    FPOP_st();
nkeynes@388
  2447
    JMP_TARGET(end);
nkeynes@417
  2448
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2449
:}
nkeynes@377
  2450
FLDS FRm, FPUL {:  
nkeynes@671
  2451
    COUNT_INST(I_FLDS);
nkeynes@377
  2452
    check_fpuen();
nkeynes@991
  2453
    load_fr( REG_EAX, FRm );
nkeynes@995
  2454
    MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377
  2455
:}
nkeynes@377
  2456
FSTS FPUL, FRn {:  
nkeynes@671
  2457
    COUNT_INST(I_FSTS);
nkeynes@377
  2458
    check_fpuen();
nkeynes@995
  2459
    MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991
  2460
    store_fr( REG_EAX, FRn );
nkeynes@377
  2461
:}
nkeynes@377
  2462
FCNVDS FRm, FPUL {:  
nkeynes@671
  2463
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2464
    check_fpuen();
nkeynes@901
  2465
    if( sh4_x86.double_prec ) {
nkeynes@901
  2466
        push_dr( FRm );
nkeynes@901
  2467
        pop_fpul();
nkeynes@901
  2468
    }
nkeynes@377
  2469
:}
nkeynes@377
  2470
FCNVSD FPUL, FRn {:  
nkeynes@671
  2471
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2472
    check_fpuen();
nkeynes@901
  2473
    if( sh4_x86.double_prec ) {
nkeynes@901
  2474
        push_fpul();
nkeynes@901
  2475
        pop_dr( FRn );
nkeynes@901
  2476
    }
nkeynes@377
  2477
:}
nkeynes@375
  2478
nkeynes@359
  2479
/* Floating point instructions */
nkeynes@374
  2480
FABS FRn {:  
nkeynes@671
  2481
    COUNT_INST(I_FABS);
nkeynes@377
  2482
    check_fpuen();
nkeynes@901
  2483
    if( sh4_x86.double_prec ) {
nkeynes@901
  2484
        push_dr(FRn);
nkeynes@901
  2485
        FABS_st0();
nkeynes@901
  2486
        pop_dr(FRn);
nkeynes@901
  2487
    } else {
nkeynes@901
  2488
        push_fr(FRn);
nkeynes@901
  2489
        FABS_st0();
nkeynes@901
  2490
        pop_fr(FRn);
nkeynes@901
  2491
    }
nkeynes@374
  2492
:}
nkeynes@377
  2493
FADD FRm, FRn {:  
nkeynes@671
  2494
    COUNT_INST(I_FADD);
nkeynes@377
  2495
    check_fpuen();
nkeynes@901
  2496
    if( sh4_x86.double_prec ) {
nkeynes@901
  2497
        push_dr(FRm);
nkeynes@901
  2498
        push_dr(FRn);
nkeynes@901
  2499
        FADDP_st(1);
nkeynes@901
  2500
        pop_dr(FRn);
nkeynes@901
  2501
    } else {
nkeynes@901
  2502
        push_fr(FRm);
nkeynes@901
  2503
        push_fr(FRn);
nkeynes@901
  2504
        FADDP_st(1);
nkeynes@901
  2505
        pop_fr(FRn);
nkeynes@901
  2506
    }
nkeynes@375
  2507
:}
nkeynes@377
  2508
FDIV FRm, FRn {:  
nkeynes@671
  2509
    COUNT_INST(I_FDIV);
nkeynes@377
  2510
    check_fpuen();
nkeynes@901
  2511
    if( sh4_x86.double_prec ) {
nkeynes@901
  2512
        push_dr(FRn);
nkeynes@901
  2513
        push_dr(FRm);
nkeynes@901
  2514
        FDIVP_st(1);
nkeynes@901
  2515
        pop_dr(FRn);
nkeynes@901
  2516
    } else {
nkeynes@901
  2517
        push_fr(FRn);
nkeynes@901
  2518
        push_fr(FRm);
nkeynes@901
  2519
        FDIVP_st(1);
nkeynes@901
  2520
        pop_fr(FRn);
nkeynes@901
  2521
    }
nkeynes@375
  2522
:}
nkeynes@375
  2523
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2524
    COUNT_INST(I_FMAC);
nkeynes@377
  2525
    check_fpuen();
nkeynes@901
  2526
    if( sh4_x86.double_prec ) {
nkeynes@901
  2527
        push_dr( 0 );
nkeynes@901
  2528
        push_dr( FRm );
nkeynes@901
  2529
        FMULP_st(1);
nkeynes@901
  2530
        push_dr( FRn );
nkeynes@901
  2531
        FADDP_st(1);
nkeynes@901
  2532
        pop_dr( FRn );
nkeynes@901
  2533
    } else {
nkeynes@901
  2534
        push_fr( 0 );
nkeynes@901
  2535
        push_fr( FRm );
nkeynes@901
  2536
        FMULP_st(1);
nkeynes@901
  2537
        push_fr( FRn );
nkeynes@901
  2538
        FADDP_st(1);
nkeynes@901
  2539
        pop_fr( FRn );
nkeynes@901
  2540
    }
nkeynes@375
  2541
:}
nkeynes@375
  2542
nkeynes@377
  2543
FMUL FRm, FRn {:  
nkeynes@671
  2544
    COUNT_INST(I_FMUL);
nkeynes@377
  2545
    check_fpuen();
nkeynes@901
  2546
    if( sh4_x86.double_prec ) {
nkeynes@901
  2547
        push_dr(FRm);
nkeynes@901
  2548
        push_dr(FRn);
nkeynes@901
  2549
        FMULP_st(1);
nkeynes@901
  2550
        pop_dr(FRn);
nkeynes@901
  2551
    } else {
nkeynes@901
  2552
        push_fr(FRm);
nkeynes@901
  2553
        push_fr(FRn);
nkeynes@901
  2554
        FMULP_st(1);
nkeynes@901
  2555
        pop_fr(FRn);
nkeynes@901
  2556
    }
nkeynes@377
  2557
:}
nkeynes@377
  2558
FNEG FRn {:  
nkeynes@671
  2559
    COUNT_INST(I_FNEG);
nkeynes@377
  2560
    check_fpuen();
nkeynes@901
  2561
    if( sh4_x86.double_prec ) {
nkeynes@901
  2562
        push_dr(FRn);
nkeynes@901
  2563
        FCHS_st0();
nkeynes@901
  2564
        pop_dr(FRn);
nkeynes@901
  2565
    } else {
nkeynes@901
  2566
        push_fr(FRn);
nkeynes@901
  2567
        FCHS_st0();
nkeynes@901
  2568
        pop_fr(FRn);
nkeynes@901
  2569
    }
nkeynes@377
  2570
:}
nkeynes@377
  2571
FSRRA FRn {:  
nkeynes@671
  2572
    COUNT_INST(I_FSRRA);
nkeynes@377
  2573
    check_fpuen();
nkeynes@901
  2574
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2575
        FLD1_st0();
nkeynes@901
  2576
        push_fr(FRn);
nkeynes@901
  2577
        FSQRT_st0();
nkeynes@901
  2578
        FDIVP_st(1);
nkeynes@901
  2579
        pop_fr(FRn);
nkeynes@901
  2580
    }
nkeynes@377
  2581
:}
nkeynes@377
  2582
FSQRT FRn {:  
nkeynes@671
  2583
    COUNT_INST(I_FSQRT);
nkeynes@377
  2584
    check_fpuen();
nkeynes@901
  2585
    if( sh4_x86.double_prec ) {
nkeynes@901
  2586
        push_dr(FRn);
nkeynes@901
  2587
        FSQRT_st0();
nkeynes@901
  2588
        pop_dr(FRn);
nkeynes@901
  2589
    } else {
nkeynes@901
  2590
        push_fr(FRn);
nkeynes@901
  2591
        FSQRT_st0();
nkeynes@901
  2592
        pop_fr(FRn);
nkeynes@901
  2593
    }
nkeynes@377
  2594
:}
nkeynes@377
  2595
FSUB FRm, FRn {:  
nkeynes@671
  2596
    COUNT_INST(I_FSUB);
nkeynes@377
  2597
    check_fpuen();
nkeynes@901
  2598
    if( sh4_x86.double_prec ) {
nkeynes@901
  2599
        push_dr(FRn);
nkeynes@901
  2600
        push_dr(FRm);
nkeynes@901
  2601
        FSUBP_st(1);
nkeynes@901
  2602
        pop_dr(FRn);
nkeynes@901
  2603
    } else {
nkeynes@901
  2604
        push_fr(FRn);
nkeynes@901
  2605
        push_fr(FRm);
nkeynes@901
  2606
        FSUBP_st(1);
nkeynes@901
  2607
        pop_fr(FRn);
nkeynes@901
  2608
    }
nkeynes@377
  2609
:}
nkeynes@377
  2610
nkeynes@377
  2611
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2612
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2613
    check_fpuen();
nkeynes@901
  2614
    if( sh4_x86.double_prec ) {
nkeynes@901
  2615
        push_dr(FRm);
nkeynes@901
  2616
        push_dr(FRn);
nkeynes@901
  2617
    } else {
nkeynes@901
  2618
        push_fr(FRm);
nkeynes@901
  2619
        push_fr(FRn);
nkeynes@901
  2620
    }
nkeynes@377
  2621
    FCOMIP_st(1);
nkeynes@377
  2622
    SETE_t();
nkeynes@377
  2623
    FPOP_st();
nkeynes@901
  2624
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2625
:}
nkeynes@377
  2626
FCMP/GT FRm, FRn {:  
nkeynes@671
  2627
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2628
    check_fpuen();
nkeynes@901
  2629
    if( sh4_x86.double_prec ) {
nkeynes@901
  2630
        push_dr(FRm);
nkeynes@901
  2631
        push_dr(FRn);
nkeynes@901
  2632
    } else {
nkeynes@901
  2633
        push_fr(FRm);
nkeynes@901
  2634
        push_fr(FRn);
nkeynes@901
  2635
    }
nkeynes@377
  2636
    FCOMIP_st(1);
nkeynes@377
  2637
    SETA_t();
nkeynes@377
  2638
    FPOP_st();
nkeynes@901
  2639
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2640
:}
nkeynes@377
  2641
nkeynes@377
  2642
FSCA FPUL, FRn {:  
nkeynes@671
  2643
    COUNT_INST(I_FSCA);
nkeynes@377
  2644
    check_fpuen();
nkeynes@901
  2645
    if( sh4_x86.double_prec == 0 ) {
nkeynes@991
  2646
        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995
  2647
        MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995
  2648
        CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901
  2649
    }
nkeynes@417
  2650
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2651
:}
nkeynes@377
  2652
FIPR FVm, FVn {:  
nkeynes@671
  2653
    COUNT_INST(I_FIPR);
nkeynes@377
  2654
    check_fpuen();
nkeynes@901
  2655
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2656
        if( sh4_x86.sse3_enabled ) {
nkeynes@991
  2657
            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991
  2658
            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2659
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2660
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@991
  2661
            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2662
        } else {
nkeynes@904
  2663
            push_fr( FVm<<2 );
nkeynes@903
  2664
            push_fr( FVn<<2 );
nkeynes@903
  2665
            FMULP_st(1);
nkeynes@903
  2666
            push_fr( (FVm<<2)+1);
nkeynes@903
  2667
            push_fr( (FVn<<2)+1);
nkeynes@903
  2668
            FMULP_st(1);
nkeynes@903
  2669
            FADDP_st(1);
nkeynes@903
  2670
            push_fr( (FVm<<2)+2);
nkeynes@903
  2671
            push_fr( (FVn<<2)+2);
nkeynes@903
  2672
            FMULP_st(1);