nkeynes@31 | 1 | /**
|
nkeynes@561 | 2 | * $Id$
|
nkeynes@31 | 3 | *
|
nkeynes@103 | 4 | * PVR2 (video chip) functions and macros.
|
nkeynes@31 | 5 | *
|
nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes.
|
nkeynes@31 | 7 | *
|
nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify
|
nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by
|
nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or
|
nkeynes@31 | 11 | * (at your option) any later version.
|
nkeynes@31 | 12 | *
|
nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful,
|
nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
nkeynes@31 | 16 | * GNU General Public License for more details.
|
nkeynes@31 | 17 | */
|
nkeynes@31 | 18 |
|
nkeynes@653 | 19 | #ifndef lxdream_pvr2_H
|
nkeynes@653 | 20 | #define lxdream_pvr2_H 1
|
nkeynes@653 | 21 |
|
nkeynes@653 | 22 | #include <stdio.h>
|
nkeynes@653 | 23 | #include "lxdream.h"
|
nkeynes@103 | 24 | #include "mem.h"
|
nkeynes@144 | 25 | #include "display.h"
|
nkeynes@1 | 26 |
|
nkeynes@736 | 27 | #ifdef __cplusplus
|
nkeynes@736 | 28 | extern "C" {
|
nkeynes@736 | 29 | #endif
|
nkeynes@736 | 30 |
|
nkeynes@189 | 31 | typedef unsigned int pvraddr_t;
|
nkeynes@189 | 32 | typedef unsigned int pvr64addr_t;
|
nkeynes@1 | 33 |
|
nkeynes@335 | 34 | #define DISPMODE_ENABLE 0x00000001 /* Display enable */
|
nkeynes@335 | 35 | #define DISPMODE_LINEDOUBLE 0x00000002 /* scanline double */
|
nkeynes@335 | 36 | #define DISPMODE_COLFMT 0x0000000C /* Colour mode */
|
nkeynes@335 | 37 | #define DISPMODE_CLOCKDIV 0x08000000 /* Clock divide-by-2 */
|
nkeynes@1 | 38 |
|
nkeynes@1 | 39 | #define DISPSIZE_MODULO 0x3FF00000 /* line skip +1 (32-bit words)*/
|
nkeynes@1 | 40 | #define DISPSIZE_LPF 0x000FFC00 /* lines per field */
|
nkeynes@1 | 41 | #define DISPSIZE_PPL 0x000003FF /* pixel words (32 bit) per line */
|
nkeynes@1 | 42 |
|
nkeynes@103 | 43 | #define DISPCFG_VP 0x00000001 /* V-sync polarity */
|
nkeynes@103 | 44 | #define DISPCFG_HP 0x00000002 /* H-sync polarity */
|
nkeynes@103 | 45 | #define DISPCFG_I 0x00000010 /* Interlace enable */
|
nkeynes@103 | 46 | #define DISPCFG_BS 0x000000C0 /* Broadcast standard */
|
nkeynes@103 | 47 | #define DISPCFG_VO 0x00000100 /* Video output enable */
|
nkeynes@1 | 48 |
|
nkeynes@432 | 49 | #define DISPSYNC_LINE_MASK 0x000003FF
|
nkeynes@432 | 50 | #define DISPSYNC_EVEN_FIELD 0x00000000
|
nkeynes@432 | 51 | #define DISPSYNC_ODD_FIELD 0x00000400
|
nkeynes@432 | 52 | #define DISPSYNC_ACTIVE 0x00000800
|
nkeynes@432 | 53 | #define DISPSYNC_HSYNC 0x00001000
|
nkeynes@432 | 54 | #define DISPSYNC_VSYNC 0x00002000
|
nkeynes@432 | 55 |
|
nkeynes@1 | 56 | #define BS_NTSC 0x00000000
|
nkeynes@1 | 57 | #define BS_PAL 0x00000040
|
nkeynes@1 | 58 | #define BS_PALM 0x00000080 /* ? */
|
nkeynes@1 | 59 | #define BS_PALN 0x000000C0 /* ? */
|
nkeynes@1 | 60 |
|
nkeynes@827 | 61 | #define SCALER_HSCALE 0x00010000
|
nkeynes@827 | 62 |
|
nkeynes@103 | 63 | #define PVR2_RAM_BASE 0x05000000
|
nkeynes@103 | 64 | #define PVR2_RAM_BASE_INT 0x04000000
|
nkeynes@103 | 65 | #define PVR2_RAM_SIZE (8 * 1024 * 1024)
|
nkeynes@103 | 66 | #define PVR2_RAM_PAGES (PVR2_RAM_SIZE>>12)
|
nkeynes@189 | 67 | #define PVR2_RAM_MASK 0x7FFFFF
|
nkeynes@103 | 68 |
|
nkeynes@222 | 69 | #define RENDER_ZONLY 0
|
nkeynes@222 | 70 | #define RENDER_NORMAL 1 /* Render non-modified polygons */
|
nkeynes@222 | 71 | #define RENDER_CHEAPMOD 2 /* Render cheap-modified polygons */
|
nkeynes@222 | 72 | #define RENDER_FULLMOD 3 /* Render the fully-modified version of the polygons */
|
nkeynes@222 | 73 |
|
nkeynes@1 | 74 | void pvr2_next_frame( void );
|
nkeynes@19 | 75 | void pvr2_set_base_address( uint32_t );
|
nkeynes@133 | 76 | int pvr2_get_frame_count( void );
|
nkeynes@677 | 77 | void pvr2_redraw_display();
|
nkeynes@295 | 78 | gboolean pvr2_save_next_scene( const gchar *filename );
|
nkeynes@56 | 79 |
|
nkeynes@103 | 80 | #define PVR2_CMD_END_OF_LIST 0x00
|
nkeynes@103 | 81 | #define PVR2_CMD_USER_CLIP 0x20
|
nkeynes@103 | 82 | #define PVR2_CMD_POLY_OPAQUE 0x80
|
nkeynes@103 | 83 | #define PVR2_CMD_MOD_OPAQUE 0x81
|
nkeynes@103 | 84 | #define PVR2_CMD_POLY_TRANS 0x82
|
nkeynes@103 | 85 | #define PVR2_CMD_MOD_TRANS 0x83
|
nkeynes@103 | 86 | #define PVR2_CMD_POLY_PUNCHOUT 0x84
|
nkeynes@103 | 87 | #define PVR2_CMD_VERTEX 0xE0
|
nkeynes@103 | 88 | #define PVR2_CMD_VERTEX_LAST 0xF0
|
nkeynes@103 | 89 |
|
nkeynes@864 | 90 | #define PVR2_VOLUME_NORMAL 0x00000000
|
nkeynes@864 | 91 | #define PVR2_VOLUME_REGION1 0x20000000
|
nkeynes@864 | 92 | #define PVR2_VOLUME_REGION0 0x40000000
|
nkeynes@864 | 93 |
|
nkeynes@103 | 94 | #define PVR2_POLY_TEXTURED 0x00000008
|
nkeynes@103 | 95 | #define PVR2_POLY_SPECULAR 0x00000004
|
nkeynes@103 | 96 | #define PVR2_POLY_SHADED 0x00000002
|
nkeynes@103 | 97 | #define PVR2_POLY_UV_16BIT 0x00000001
|
nkeynes@103 | 98 |
|
nkeynes@133 | 99 | #define PVR2_POLY_MODE_CLAMP_RGB 0x00200000
|
nkeynes@133 | 100 | #define PVR2_POLY_MODE_ALPHA 0x00100000
|
nkeynes@133 | 101 | #define PVR2_POLY_MODE_TEXALPHA 0x00080000
|
nkeynes@133 | 102 | #define PVR2_POLY_MODE_FLIP_S 0x00040000
|
nkeynes@133 | 103 | #define PVR2_POLY_MODE_FLIP_T 0x00020000
|
nkeynes@133 | 104 | #define PVR2_POLY_MODE_CLAMP_S 0x00010000
|
nkeynes@133 | 105 | #define PVR2_POLY_MODE_CLAMP_T 0x00008000
|
nkeynes@133 | 106 |
|
nkeynes@337 | 107 | #define PVR2_POLY_FOG_LOOKUP 0x00000000
|
nkeynes@337 | 108 | #define PVR2_POLY_FOG_VERTEX 0x00400000
|
nkeynes@337 | 109 | #define PVR2_POLY_FOG_DISABLED 0x00800000
|
nkeynes@337 | 110 | #define PVR2_POLY_FOG_LOOKUP2 0x00C00000
|
nkeynes@337 | 111 |
|
nkeynes@337 | 112 |
|
nkeynes@103 | 113 | #define PVR2_TEX_FORMAT_ARGB1555 0x00000000
|
nkeynes@103 | 114 | #define PVR2_TEX_FORMAT_RGB565 0x08000000
|
nkeynes@103 | 115 | #define PVR2_TEX_FORMAT_ARGB4444 0x10000000
|
nkeynes@103 | 116 | #define PVR2_TEX_FORMAT_YUV422 0x18000000
|
nkeynes@103 | 117 | #define PVR2_TEX_FORMAT_BUMPMAP 0x20000000
|
nkeynes@103 | 118 | #define PVR2_TEX_FORMAT_IDX4 0x28000000
|
nkeynes@103 | 119 | #define PVR2_TEX_FORMAT_IDX8 0x30000000
|
nkeynes@103 | 120 |
|
nkeynes@103 | 121 | #define PVR2_TEX_MIPMAP 0x80000000
|
nkeynes@103 | 122 | #define PVR2_TEX_COMPRESSED 0x40000000
|
nkeynes@103 | 123 | #define PVR2_TEX_FORMAT_MASK 0x38000000
|
nkeynes@103 | 124 | #define PVR2_TEX_UNTWIDDLED 0x04000000
|
nkeynes@284 | 125 | #define PVR2_TEX_STRIDE 0x02000000
|
nkeynes@337 | 126 | #define PVR2_TEX_IS_PALETTE(mode) ( (mode & PVR2_TEX_FORMAT_MASK) == PVR2_TEX_FORMAT_IDX4 || (mode&PVR2_TEX_FORMAT_MASK) == PVR2_TEX_FORMAT_IDX8 )
|
nkeynes@337 | 127 |
|
nkeynes@103 | 128 |
|
nkeynes@108 | 129 | #define PVR2_TEX_ADDR(x) ( ((x)&0x01FFFFF)<<3 );
|
nkeynes@348 | 130 | #define PVR2_TEX_IS_MIPMAPPED(x) ( ((x) & 0x84000000) == 0x80000000 )
|
nkeynes@103 | 131 | #define PVR2_TEX_IS_COMPRESSED(x) ( (x) & PVR2_TEX_COMPRESSED )
|
nkeynes@103 | 132 | #define PVR2_TEX_IS_TWIDDLED(x) (((x) & PVR2_TEX_UNTWIDDLED) == 0)
|
nkeynes@284 | 133 | #define PVR2_TEX_IS_STRIDE(x) (((x) & 0x06000000) == 0x06000000)
|
nkeynes@103 | 134 |
|
nkeynes@103 | 135 | /****************************** Frame Buffer *****************************/
|
nkeynes@103 | 136 |
|
nkeynes@103 | 137 | /**
|
nkeynes@827 | 138 | * Write a block of data to an address in the DMA range (0x10000000 -
|
nkeynes@325 | 139 | * 0x13FFFFFF), ie TA, YUV, or texture ram.
|
nkeynes@325 | 140 | */
|
nkeynes@429 | 141 | void pvr2_dma_write( sh4addr_t dest, unsigned char *src, uint32_t length );
|
nkeynes@325 | 142 |
|
nkeynes@325 | 143 | /**
|
nkeynes@103 | 144 | * Write to the interleaved memory address space (aka 64-bit address space).
|
nkeynes@103 | 145 | */
|
nkeynes@429 | 146 | void pvr2_vram64_write( sh4addr_t dest, unsigned char *src, uint32_t length );
|
nkeynes@103 | 147 |
|
nkeynes@103 | 148 | /**
|
nkeynes@282 | 149 | * Write to the interleaved memory address space (aka 64-bit address space),
|
nkeynes@282 | 150 | * using a line length and stride.
|
nkeynes@282 | 151 | */
|
nkeynes@429 | 152 | void pvr2_vram64_write_stride( sh4addr_t dest, unsigned char *src, uint32_t line_bytes,
|
nkeynes@736 | 153 | uint32_t line_stride_bytes, uint32_t line_count );
|
nkeynes@282 | 154 |
|
nkeynes@282 | 155 | /**
|
nkeynes@103 | 156 | * Read from the interleaved memory address space (aka 64-bit address space)
|
nkeynes@103 | 157 | */
|
nkeynes@429 | 158 | void pvr2_vram64_read( unsigned char *dest, sh4addr_t src, uint32_t length );
|
nkeynes@103 | 159 |
|
nkeynes@127 | 160 | /**
|
nkeynes@310 | 161 | * Read a twiddled image from interleaved memory address space (aka 64-bit address
|
nkeynes@827 | 162 | * space), writing the image to the destination buffer in detwiddled format.
|
nkeynes@310 | 163 | * Width and height must be powers of 2
|
nkeynes@315 | 164 | * This version reads 4-bit pixels.
|
nkeynes@315 | 165 | */
|
nkeynes@429 | 166 | void pvr2_vram64_read_twiddled_4( unsigned char *dest, sh4addr_t src, uint32_t width, uint32_t height );
|
nkeynes@315 | 167 |
|
nkeynes@315 | 168 |
|
nkeynes@315 | 169 | /**
|
nkeynes@315 | 170 | * Read a twiddled image from interleaved memory address space (aka 64-bit address
|
nkeynes@827 | 171 | * space), writing the image to the destination buffer in detwiddled format.
|
nkeynes@315 | 172 | * Width and height must be powers of 2
|
nkeynes@310 | 173 | * This version reads 8-bit pixels.
|
nkeynes@310 | 174 | */
|
nkeynes@429 | 175 | void pvr2_vram64_read_twiddled_8( unsigned char *dest, sh4addr_t src, uint32_t width, uint32_t height );
|
nkeynes@310 | 176 |
|
nkeynes@310 | 177 | /**
|
nkeynes@310 | 178 | * Read a twiddled image from interleaved memory address space (aka 64-bit address
|
nkeynes@827 | 179 | * space), writing the image to the destination buffer in detwiddled format.
|
nkeynes@310 | 180 | * Width and height must be powers of 2, and src must be 16-bit aligned.
|
nkeynes@310 | 181 | * This version reads 16-bit pixels.
|
nkeynes@310 | 182 | */
|
nkeynes@429 | 183 | void pvr2_vram64_read_twiddled_16( unsigned char *dest, sh4addr_t src, uint32_t width, uint32_t height );
|
nkeynes@310 | 184 |
|
nkeynes@310 | 185 | /**
|
nkeynes@827 | 186 | * Read an image from the interleaved memory address space (aka 64-bit address space)
|
nkeynes@284 | 187 | * where the source and destination line sizes may differ. Note that both byte
|
nkeynes@284 | 188 | * counts must be a multiple of 4, and the src address must be 32-bit aligned.
|
nkeynes@284 | 189 | */
|
nkeynes@429 | 190 | void pvr2_vram64_read_stride( unsigned char *dest, uint32_t dest_line_bytes, sh4addr_t srcaddr,
|
nkeynes@736 | 191 | uint32_t src_line_bytes, uint32_t line_count );
|
nkeynes@284 | 192 | /**
|
nkeynes@827 | 193 | * Dump a portion of vram to a stream from the interleaved memory address
|
nkeynes@127 | 194 | * space.
|
nkeynes@127 | 195 | */
|
nkeynes@127 | 196 | void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f );
|
nkeynes@127 | 197 |
|
nkeynes@315 | 198 | /**
|
nkeynes@315 | 199 | * Flush the indicated render buffer back to PVR. Caller is responsible for
|
nkeynes@315 | 200 | * tracking whether there is actually anything in the buffer.
|
nkeynes@315 | 201 | *
|
nkeynes@315 | 202 | * @param buffer A render buffer indicating the address to store to, and the
|
nkeynes@315 | 203 | * format the data needs to be in.
|
nkeynes@827 | 204 | * @param backBuffer TRUE to flush the back buffer, FALSE for
|
nkeynes@315 | 205 | * the front buffer.
|
nkeynes@315 | 206 | */
|
nkeynes@352 | 207 | void pvr2_render_buffer_copy_to_sh4( render_buffer_t buffer );
|
nkeynes@315 | 208 |
|
nkeynes@315 | 209 | /**
|
nkeynes@315 | 210 | * Invalidate any caching on the supplied SH4 address
|
nkeynes@315 | 211 | */
|
nkeynes@352 | 212 | gboolean pvr2_render_buffer_invalidate( sh4addr_t addr, gboolean isWrite );
|
nkeynes@315 | 213 |
|
nkeynes@315 | 214 |
|
nkeynes@103 | 215 | /**************************** Tile Accelerator ***************************/
|
nkeynes@56 | 216 | /**
|
nkeynes@56 | 217 | * Process the data in the supplied buffer as an array of TA command lists.
|
nkeynes@56 | 218 | * Any excess bytes are held pending until a complete list is sent
|
nkeynes@56 | 219 | */
|
nkeynes@429 | 220 | void pvr2_ta_write( unsigned char *buf, uint32_t length );
|
nkeynes@100 | 221 |
|
nkeynes@753 | 222 | /**
|
nkeynes@753 | 223 | * Find the first polygon or sprite context in the supplied buffer of TA
|
nkeynes@753 | 224 | * data.
|
nkeynes@827 | 225 | * @return A pointer to the context, or NULL if it cannot be found
|
nkeynes@753 | 226 | */
|
nkeynes@753 | 227 | uint32_t *pvr2_ta_find_polygon_context( uint32_t *buf, uint32_t length );
|
nkeynes@100 | 228 |
|
nkeynes@103 | 229 | /**
|
nkeynes@103 | 230 | * (Re)initialize the tile accelerator in preparation for the next scene.
|
nkeynes@103 | 231 | * Normally called immediately before commencing polygon transmission.
|
nkeynes@103 | 232 | */
|
nkeynes@103 | 233 | void pvr2_ta_init( void );
|
nkeynes@103 | 234 |
|
nkeynes@429 | 235 | void pvr2_ta_reset( void );
|
nkeynes@429 | 236 |
|
nkeynes@429 | 237 | void pvr2_ta_save_state( FILE *f );
|
nkeynes@429 | 238 |
|
nkeynes@429 | 239 | int pvr2_ta_load_state( FILE *f );
|
nkeynes@282 | 240 |
|
nkeynes@282 | 241 | /****************************** YUV Converter ****************************/
|
nkeynes@282 | 242 |
|
nkeynes@282 | 243 | /**
|
nkeynes@282 | 244 | * Process a block of YUV data.
|
nkeynes@282 | 245 | */
|
nkeynes@429 | 246 | void pvr2_yuv_write( unsigned char *buf, uint32_t length );
|
nkeynes@282 | 247 |
|
nkeynes@282 | 248 | /**
|
nkeynes@282 | 249 | * Initialize the YUV converter.
|
nkeynes@282 | 250 | */
|
nkeynes@284 | 251 | void pvr2_yuv_init( uint32_t target_addr );
|
nkeynes@284 | 252 |
|
nkeynes@284 | 253 | void pvr2_yuv_set_config( uint32_t config );
|
nkeynes@282 | 254 |
|
nkeynes@429 | 255 | void pvr2_yuv_save_state( FILE *f );
|
nkeynes@429 | 256 |
|
nkeynes@429 | 257 | int pvr2_yuv_load_state( FILE *f );
|
nkeynes@429 | 258 |
|
nkeynes@103 | 259 | /********************************* Renderer ******************************/
|
nkeynes@103 | 260 |
|
nkeynes@103 | 261 | /**
|
nkeynes@103 | 262 | * Render the current scene stored in PVR ram to the GL back buffer.
|
nkeynes@103 | 263 | */
|
nkeynes@669 | 264 | void pvr2_scene_render( render_buffer_t buffer );
|
nkeynes@103 | 265 |
|
nkeynes@103 | 266 | /**
|
nkeynes@669 | 267 | * Perform the initial once-off GL setup, usually immediately after the GL
|
nkeynes@669 | 268 | * context is first bound.
|
nkeynes@103 | 269 | */
|
nkeynes@669 | 270 | void pvr2_setup_gl_context();
|
nkeynes@219 | 271 |
|
nkeynes@219 | 272 | void render_backplane( uint32_t *polygon, uint32_t width, uint32_t height, uint32_t mode );
|
nkeynes@219 | 273 |
|
nkeynes@669 | 274 | void render_autosort_tile( pvraddr_t tile_entry, int render_mode );
|
nkeynes@669 | 275 |
|
nkeynes@865 | 276 | void render_set_context( uint32_t *context, GLint depth_mode );
|
nkeynes@219 | 277 |
|
nkeynes@865 | 278 | void gl_render_tilelist( pvraddr_t tile_entry, GLint depth_mode );
|
nkeynes@429 | 279 |
|
nkeynes@856 | 280 | render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id );
|
nkeynes@856 | 281 |
|
nkeynes@861 | 282 | void pvr2_finish_render_buffer( render_buffer_t buffer );
|
nkeynes@861 | 283 |
|
nkeynes@856 | 284 | void pvr2_destroy_render_buffer( render_buffer_t buffer );
|
nkeynes@856 | 285 |
|
nkeynes@856 | 286 |
|
nkeynes@319 | 287 | /**
|
nkeynes@319 | 288 | * Structure to hold a complete unpacked vertex (excluding modifier
|
nkeynes@319 | 289 | * volume parameters - generate separate vertexes in that case).
|
nkeynes@319 | 290 | */
|
nkeynes@319 | 291 | struct vertex_unpacked {
|
nkeynes@319 | 292 | float x,y,z;
|
nkeynes@319 | 293 | float u,v; /* Texture coordinates */
|
nkeynes@319 | 294 | float rgba[4]; /* Fragment colour (RGBA order) */
|
nkeynes@319 | 295 | float offset_rgba[4]; /* Offset color (RGBA order) */
|
nkeynes@319 | 296 | };
|
nkeynes@319 | 297 |
|
nkeynes@103 | 298 | /****************************** Texture Cache ****************************/
|
nkeynes@103 | 299 |
|
nkeynes@103 | 300 | /**
|
nkeynes@108 | 301 | * Initialize the texture cache.
|
nkeynes@103 | 302 | */
|
nkeynes@103 | 303 | void texcache_init( void );
|
nkeynes@103 | 304 |
|
nkeynes@108 | 305 | /**
|
nkeynes@108 | 306 | * Initialize the GL side of the texture cache (texture ids and such).
|
nkeynes@108 | 307 | */
|
nkeynes@108 | 308 | void texcache_gl_init( void );
|
nkeynes@103 | 309 |
|
nkeynes@103 | 310 | /**
|
nkeynes@103 | 311 | * Flush all textures and delete. The cache will be non-functional until
|
nkeynes@103 | 312 | * the next call to texcache_init(). This would typically be done if
|
nkeynes@103 | 313 | * switching GL targets.
|
nkeynes@827 | 314 | */
|
nkeynes@103 | 315 | void texcache_shutdown( void );
|
nkeynes@103 | 316 |
|
nkeynes@103 | 317 | /**
|
nkeynes@432 | 318 | * Flush (ie free) all textures.
|
nkeynes@432 | 319 | */
|
nkeynes@432 | 320 | void texcache_flush( void );
|
nkeynes@432 | 321 |
|
nkeynes@432 | 322 | /**
|
nkeynes@432 | 323 | * Flush all palette-based textures (if any)
|
nkeynes@432 | 324 | */
|
nkeynes@432 | 325 | void texcache_invalidate_palette(void);
|
nkeynes@432 | 326 |
|
nkeynes@432 | 327 | /**
|
nkeynes@103 | 328 | * Evict all textures contained in the page identified by a texture address.
|
nkeynes@103 | 329 | */
|
nkeynes@103 | 330 | void texcache_invalidate_page( uint32_t texture_addr );
|
nkeynes@103 | 331 |
|
nkeynes@103 | 332 | /**
|
nkeynes@103 | 333 | * Return a texture ID for the texture specified at the supplied address
|
nkeynes@103 | 334 | * and given parameters (the same sequence of bytes could in theory have
|
nkeynes@103 | 335 | * multiple interpretations). We use the texture address as the primary
|
nkeynes@103 | 336 | * index, but allow for multiple instances at each address. The texture
|
nkeynes@103 | 337 | * will be bound to the GL_TEXTURE_2D target before being returned.
|
nkeynes@827 | 338 | *
|
nkeynes@103 | 339 | * If the texture has already been bound, return the ID to which it was
|
nkeynes@103 | 340 | * bound. Otherwise obtain an unused texture ID and set it up appropriately.
|
nkeynes@103 | 341 | */
|
nkeynes@653 | 342 | GLuint texcache_get_texture( uint32_t texture_word, int width, int height );
|
nkeynes@221 | 343 |
|
nkeynes@856 | 344 | render_buffer_t texcache_get_render_buffer( uint32_t texture_addr, int mode, int width, int height );
|
nkeynes@856 | 345 |
|
nkeynes@429 | 346 | void pvr2_check_palette_changed(void);
|
nkeynes@429 | 347 |
|
nkeynes@432 | 348 | int pvr2_render_save_scene( const gchar *filename );
|
nkeynes@432 | 349 |
|
nkeynes@850 | 350 | /**
|
nkeynes@850 | 351 | * Queue a gun position event to occur at the specified position. Unless
|
nkeynes@850 | 352 | * cancelled, when the display reaches the position:
|
nkeynes@850 | 353 | * GUNPOS is updated with the position, and
|
nkeynes@850 | 354 | * EVENT_MAPLE_DMA is fired.
|
nkeynes@850 | 355 | */
|
nkeynes@850 | 356 | void pvr2_queue_gun_event( int xpos, int ypos );
|
nkeynes@432 | 357 |
|
nkeynes@221 | 358 | /************************* Rendering support macros **************************/
|
nkeynes@864 | 359 | #define POLY1_VOLUME_MODE(poly1) ((poly1)&0xE0000000)
|
nkeynes@221 | 360 | #define POLY1_DEPTH_MODE(poly1) ( pvr2_poly_depthmode[(poly1)>>29] )
|
nkeynes@653 | 361 | #define POLY1_DEPTH_WRITE(poly1) (((poly1)&0x04000000) == 0 )
|
nkeynes@221 | 362 | #define POLY1_CULL_MODE(poly1) (((poly1)>>27)&0x03)
|
nkeynes@653 | 363 | #define POLY1_CULL_ENABLE(poly1) (((poly1)>>28)&0x01)
|
nkeynes@221 | 364 | #define POLY1_TEXTURED(poly1) (((poly1)&0x02000000))
|
nkeynes@221 | 365 | #define POLY1_SPECULAR(poly1) (((poly1)&0x01000000))
|
nkeynes@319 | 366 | #define POLY1_GOURAUD_SHADED(poly1) ((poly1)&0x00800000)
|
nkeynes@221 | 367 | #define POLY1_SHADE_MODEL(poly1) (((poly1)&0x00800000) ? GL_SMOOTH : GL_FLAT)
|
nkeynes@221 | 368 | #define POLY1_UV16(poly1) (((poly1)&0x00400000))
|
nkeynes@221 | 369 | #define POLY1_SINGLE_TILE(poly1) (((poly1)&0x00200000))
|
nkeynes@221 | 370 |
|
nkeynes@221 | 371 | #define POLY2_SRC_BLEND(poly2) ( pvr2_poly_srcblend[(poly2) >> 29] )
|
nkeynes@221 | 372 | #define POLY2_DEST_BLEND(poly2) ( pvr2_poly_dstblend[((poly2)>>26)&0x07] )
|
nkeynes@322 | 373 | #define POLY2_SRC_BLEND_TARGET(poly2) ((poly2)&0x02000000)
|
nkeynes@322 | 374 | #define POLY2_DEST_BLEND_TARGET(poly2) ((poly2)&0x01000000)
|
nkeynes@337 | 375 | #define POLY2_FOG_MODE(poly2) ((poly2)&0x00C00000)
|
nkeynes@221 | 376 | #define POLY2_COLOUR_CLAMP_ENABLE(poly2) ((poly2)&0x00200000)
|
nkeynes@322 | 377 | #define POLY2_ALPHA_ENABLE(poly2) ((poly2)&0x00100000)
|
nkeynes@322 | 378 | #define POLY2_TEX_ALPHA_ENABLE(poly2) (((poly2)&0x00080000) == 0 )
|
nkeynes@655 | 379 | #define POLY2_TEX_MIRROR_U(poly2) ((poly2)&0x00040000)
|
nkeynes@655 | 380 | #define POLY2_TEX_MIRROR_V(poly2) ((poly2)&0x00020000)
|
nkeynes@322 | 381 | #define POLY2_TEX_CLAMP_U(poly2) ((poly2)&0x00010000)
|
nkeynes@322 | 382 | #define POLY2_TEX_CLAMP_V(poly2) ((poly2)&0x00008000)
|
nkeynes@221 | 383 | #define POLY2_TEX_WIDTH(poly2) ( 1<< ((((poly2) >> 3) & 0x07 ) + 3) )
|
nkeynes@221 | 384 | #define POLY2_TEX_HEIGHT(poly2) ( 1<< (((poly2) & 0x07 ) + 3) )
|
nkeynes@338 | 385 | #define POLY2_TEX_BLEND(poly2) (((poly2) >> 6)&0x03)
|
nkeynes@221 | 386 | extern int pvr2_poly_depthmode[8];
|
nkeynes@221 | 387 | extern int pvr2_poly_srcblend[8];
|
nkeynes@221 | 388 | extern int pvr2_poly_dstblend[8];
|
nkeynes@221 | 389 | extern int pvr2_poly_texblend[4];
|
nkeynes@221 | 390 | extern int pvr2_render_colour_format[8];
|
nkeynes@221 | 391 |
|
nkeynes@653 | 392 | #define CULL_NONE 0
|
nkeynes@653 | 393 | #define CULL_SMALL 1
|
nkeynes@653 | 394 | #define CULL_CCW 2
|
nkeynes@653 | 395 | #define CULL_CW 3
|
nkeynes@653 | 396 |
|
nkeynes@653 | 397 | #define SEGMENT_END 0x80000000
|
nkeynes@653 | 398 | #define SEGMENT_ZCLEAR 0x40000000
|
nkeynes@653 | 399 | #define SEGMENT_SORT_TRANS 0x20000000
|
nkeynes@653 | 400 | #define SEGMENT_START 0x10000000
|
nkeynes@653 | 401 | #define SEGMENT_X(c) (((c) >> 2) & 0x3F)
|
nkeynes@653 | 402 | #define SEGMENT_Y(c) (((c) >> 8) & 0x3F)
|
nkeynes@653 | 403 | #define NO_POINTER 0x80000000
|
nkeynes@653 | 404 | #define IS_TILE_PTR(p) ( ((p)&NO_POINTER) == 0 )
|
nkeynes@653 | 405 | #define IS_LAST_SEGMENT(s) (((s)->control) & SEGMENT_END)
|
nkeynes@653 | 406 |
|
nkeynes@653 | 407 | struct tile_segment {
|
nkeynes@653 | 408 | uint32_t control;
|
nkeynes@653 | 409 | pvraddr_t opaque_ptr;
|
nkeynes@653 | 410 | pvraddr_t opaquemod_ptr;
|
nkeynes@653 | 411 | pvraddr_t trans_ptr;
|
nkeynes@653 | 412 | pvraddr_t transmod_ptr;
|
nkeynes@653 | 413 | pvraddr_t punchout_ptr;
|
nkeynes@653 | 414 | };
|
nkeynes@653 | 415 |
|
nkeynes@736 | 416 | #ifdef __cplusplus
|
nkeynes@736 | 417 | }
|
nkeynes@736 | 418 | #endif
|
nkeynes@736 | 419 |
|
nkeynes@653 | 420 | #endif /* !lxdream_pvr2_H */
|