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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 269:e41f9b1490d1
prev265:5daf59b7f31b
next274:4e8f1e988d80
author nkeynes
date Thu Jan 11 06:50:11 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Double hsync width (as per hw)
Add temporary debug statements on the YUV registers
Fix sync status on the back porch
file annotate diff log raw
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/**
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 * $Id: pvr2.c,v 1.36 2007-01-11 06:50:11 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_line_event( int eventid, int line );
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static void pvr2_schedule_scanline_event( int eventid, int line );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 31945 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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/**
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 * Event handler for the retrace callback (fires on line 0 normally)
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 */
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static void pvr2_retrace_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    pvr2_schedule_line_event( EVENT_RETRACE, 0 );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2 );
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    }
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}
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_RETRACE, pvr2_retrace_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.timing = ntsc_timing;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    return pvr2_ta_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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	break;
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    case 3: 
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	buffer->colour_format = COLFMT_ARGB8888;
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	buffer->hres = vid_ppl; 
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	break;
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    }
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    if( buffer->hres <=8 )
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	buffer->hres = 640;
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    if( buffer->vres <=8 )
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	buffer->vres = 480;
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    if( display_driver != NULL ) {
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	if( buffer->hres != last->hres ||
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	    buffer->vres != last->vres ||
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	    buffer->colour_format != last->colour_format) {
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	    display_driver->set_display_format( buffer->hres, buffer->vres,
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						buffer->colour_format );
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	}
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	if( !bEnabled ) {
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	    display_driver->display_blank_frame( 0 );
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	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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	    display_driver->display_blank_frame( colour );
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	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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	    display_driver->display_frame( buffer );
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	}
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    }
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    pvr2_state.frame_count++;
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}
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/**
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 * This has to handle every single register individually as they all get masked 
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 * off differently (and its easier to do it at write time)
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 */
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        return;
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   278
    }
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   279
    
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    switch(reg) {
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    case PVRID:
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   282
    case PVRVER:
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    case GUNPOS: /* Read only registers */
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	break;
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    case PVRRESET:
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	val &= 0x00000007; /* Do stuff? */
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	MMIO_WRITE( PVR2, reg, val );
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   288
	break;
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   289
    case RENDER_START:
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   290
	if( val == 0xFFFFFFFF || val == 0x00000001 )
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	    pvr2_render_scene();
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   292
	break;
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   293
    case RENDER_POLYBASE:
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    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
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    	break;
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   296
    case RENDER_TSPCFG:
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    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
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   298
    	break;
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   299
    case DISP_BORDER:
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   300
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
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   301
    	break;
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   302
    case DISP_MODE:
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   303
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
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   304
    	break;
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   305
    case RENDER_MODE:
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   306
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
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   307
    	break;
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   308
    case RENDER_SIZE:
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   309
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
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   310
    	break;
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   311
    case DISP_ADDR1:
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   312
	val &= 0x00FFFFFC;
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   313
	MMIO_WRITE( PVR2, reg, val );
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   314
	pvr2_update_raster_posn(sh4r.slice_cycle);
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	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
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   316
	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
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   317
	    pvr2_display_frame();
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   318
	}
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   319
	break;
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   320
    case DISP_ADDR2:
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   321
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
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   322
    	break;
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   323
    case DISP_SIZE:
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   324
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   325
    	break;
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   326
    case RENDER_ADDR1:
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   327
    case RENDER_ADDR2:
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   328
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
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   329
    	break;
nkeynes@191
   330
    case RENDER_HCLIP:
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   331
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   332
	break;
nkeynes@191
   333
    case RENDER_VCLIP:
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   334
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   335
	break;
nkeynes@197
   336
    case DISP_HPOSIRQ:
nkeynes@191
   337
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@189
   338
	break;
nkeynes@197
   339
    case DISP_VPOSIRQ:
nkeynes@189
   340
	val = val & 0x03FF03FF;
nkeynes@189
   341
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   342
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   343
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   344
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1 );
nkeynes@265
   345
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2 );
nkeynes@189
   346
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   347
	break;
nkeynes@197
   348
    case RENDER_NEARCLIP:
nkeynes@197
   349
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   350
	break;
nkeynes@191
   351
    case RENDER_SHADOW:
nkeynes@191
   352
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   353
	break;
nkeynes@191
   354
    case RENDER_OBJCFG:
nkeynes@191
   355
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   356
    	break;
nkeynes@191
   357
    case RENDER_TSPCLIP:
nkeynes@191
   358
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   359
    	break;
nkeynes@197
   360
    case RENDER_FARCLIP:
nkeynes@197
   361
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   362
	break;
nkeynes@191
   363
    case RENDER_BGPLANE:
nkeynes@191
   364
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   365
    	break;
nkeynes@191
   366
    case RENDER_ISPCFG:
nkeynes@191
   367
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   368
    	break;
nkeynes@197
   369
    case VRAM_CFG1:
nkeynes@197
   370
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   371
	break;
nkeynes@197
   372
    case VRAM_CFG2:
nkeynes@197
   373
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   374
	break;
nkeynes@197
   375
    case VRAM_CFG3:
nkeynes@197
   376
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   377
	break;
nkeynes@197
   378
    case RENDER_FOGTBLCOL:
nkeynes@197
   379
    case RENDER_FOGVRTCOL:
nkeynes@197
   380
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   381
	break;
nkeynes@197
   382
    case RENDER_FOGCOEFF:
nkeynes@197
   383
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   384
	break;
nkeynes@197
   385
    case RENDER_CLAMPHI:
nkeynes@197
   386
    case RENDER_CLAMPLO:
nkeynes@197
   387
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   388
	break;
nkeynes@261
   389
    case RENDER_TEXSIZE:
nkeynes@261
   390
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   391
	break;
nkeynes@261
   392
    case RENDER_PALETTE:
nkeynes@261
   393
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   394
	break;
nkeynes@261
   395
nkeynes@261
   396
	/********** CRTC registers *************/
nkeynes@197
   397
    case DISP_HBORDER:
nkeynes@197
   398
    case DISP_VBORDER:
nkeynes@197
   399
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   400
	break;
nkeynes@261
   401
    case DISP_TOTAL:
nkeynes@261
   402
	val = val & 0x03FF03FF;
nkeynes@261
   403
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   404
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   405
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   406
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   407
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   408
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   409
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@265
   410
	pvr2_schedule_line_event( EVENT_RETRACE, 0 );
nkeynes@265
   411
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1 );
nkeynes@265
   412
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2 );
nkeynes@261
   413
	break;
nkeynes@261
   414
    case DISP_SYNCCFG:
nkeynes@261
   415
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   416
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   417
	break;
nkeynes@261
   418
    case DISP_SYNCTIME:
nkeynes@261
   419
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   420
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   421
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   422
	break;
nkeynes@197
   423
    case DISP_CFG2:
nkeynes@197
   424
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   425
	break;
nkeynes@197
   426
    case DISP_HPOS:
nkeynes@261
   427
	val = val & 0x03FF;
nkeynes@261
   428
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   429
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   430
	break;
nkeynes@197
   431
    case DISP_VPOS:
nkeynes@197
   432
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   433
	break;
nkeynes@261
   434
nkeynes@261
   435
	/*********** Tile accelerator registers ***********/
nkeynes@261
   436
    case TA_POLYPOS:
nkeynes@261
   437
    case TA_LISTPOS:
nkeynes@261
   438
	/* Readonly registers */
nkeynes@197
   439
	break;
nkeynes@189
   440
    case TA_TILEBASE:
nkeynes@193
   441
    case TA_LISTEND:
nkeynes@189
   442
    case TA_LISTBASE:
nkeynes@191
   443
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   444
	break;
nkeynes@191
   445
    case RENDER_TILEBASE:
nkeynes@189
   446
    case TA_POLYBASE:
nkeynes@189
   447
    case TA_POLYEND:
nkeynes@191
   448
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   449
	break;
nkeynes@189
   450
    case TA_TILESIZE:
nkeynes@191
   451
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   452
	break;
nkeynes@189
   453
    case TA_TILECFG:
nkeynes@191
   454
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   455
	break;
nkeynes@261
   456
    case TA_INIT:
nkeynes@261
   457
	if( val & 0x80000000 )
nkeynes@261
   458
	    pvr2_ta_init();
nkeynes@261
   459
	break;
nkeynes@261
   460
    case TA_REINIT:
nkeynes@261
   461
	break;
nkeynes@261
   462
	/**************** Scaler registers? ****************/
nkeynes@261
   463
    case SCALERCFG:
nkeynes@269
   464
	/* KOS suggests bits as follows:
nkeynes@269
   465
	 *   0: enable vertical scaling
nkeynes@269
   466
	 *  10: ???
nkeynes@269
   467
	 *  16: enable FSAA
nkeynes@269
   468
	 */
nkeynes@269
   469
	DEBUG( "Scaler config set to %08X", val );
nkeynes@261
   470
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   471
	break;
nkeynes@261
   472
nkeynes@197
   473
    case YUV_ADDR:
nkeynes@197
   474
	MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
nkeynes@197
   475
	break;
nkeynes@197
   476
    case YUV_CFG:
nkeynes@269
   477
	DEBUG( "YUV config set to %08X", val );
nkeynes@197
   478
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@197
   479
	break;
nkeynes@261
   480
nkeynes@261
   481
nkeynes@261
   482
	/**************** Unknowns ***************/
nkeynes@261
   483
    case PVRUNK1:
nkeynes@261
   484
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   485
    	break;
nkeynes@261
   486
    case PVRUNK2:
nkeynes@261
   487
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   488
	break;
nkeynes@261
   489
    case PVRUNK3:
nkeynes@261
   490
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   491
	break;
nkeynes@261
   492
    case PVRUNK5:
nkeynes@261
   493
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   494
	break;
nkeynes@261
   495
    case PVRUNK6:
nkeynes@261
   496
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   497
	break;
nkeynes@197
   498
    case PVRUNK7:
nkeynes@197
   499
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   500
	break;
nkeynes@1
   501
    }
nkeynes@1
   502
}
nkeynes@1
   503
nkeynes@261
   504
/**
nkeynes@261
   505
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   506
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   507
 * The register reads (LSB to MSB) as:
nkeynes@261
   508
 *     0..9  Current scan line
nkeynes@261
   509
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   510
 *     11    Display active (including border and overscan)
nkeynes@261
   511
 *     12    Horizontal sync off
nkeynes@261
   512
 *     13    Vertical sync off
nkeynes@261
   513
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   514
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   515
 */
nkeynes@261
   516
uint32_t pvr2_get_sync_status()
nkeynes@261
   517
{
nkeynes@265
   518
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   519
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   520
nkeynes@265
   521
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   522
	result |= 0x0400;
nkeynes@261
   523
    }
nkeynes@265
   524
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   525
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   526
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   527
	}
nkeynes@265
   528
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   529
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   530
		result |= 0x2800; /* Display active */
nkeynes@261
   531
	    } else {
nkeynes@261
   532
		result |= 0x2000; /* Front porch */
nkeynes@261
   533
	    }
nkeynes@261
   534
	}
nkeynes@261
   535
    } else {
nkeynes@269
   536
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   537
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   538
		result |= 0x3800; /* Display active */
nkeynes@269
   539
	    } else {
nkeynes@269
   540
		result |= 0x3000;
nkeynes@269
   541
	    }
nkeynes@261
   542
	} else {
nkeynes@261
   543
	    result |= 0x1000; /* Back porch */
nkeynes@261
   544
	}
nkeynes@261
   545
    }
nkeynes@261
   546
    return result;
nkeynes@261
   547
}
nkeynes@261
   548
nkeynes@265
   549
/**
nkeynes@265
   550
 * Schedule an event for the start of the given line. If the line is actually
nkeynes@265
   551
 * the current line, schedules it for the next field. 
nkeynes@265
   552
 * The raster position should be updated before calling this method.
nkeynes@265
   553
 */
nkeynes@265
   554
static void pvr2_schedule_line_event( int eventid, int line )
nkeynes@265
   555
{
nkeynes@265
   556
    uint32_t time;
nkeynes@265
   557
    if( line <= pvr2_state.line_count ) {
nkeynes@265
   558
	time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns
nkeynes@265
   559
	    - pvr2_state.line_remainder;
nkeynes@265
   560
    } else {
nkeynes@265
   561
	time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder;
nkeynes@265
   562
    }
nkeynes@265
   563
nkeynes@265
   564
    if( line < pvr2_state.total_lines ) {
nkeynes@265
   565
	event_schedule( eventid, time );
nkeynes@265
   566
    } else {
nkeynes@265
   567
	event_cancel( eventid );
nkeynes@265
   568
    }
nkeynes@265
   569
}
nkeynes@265
   570
nkeynes@265
   571
/**
nkeynes@265
   572
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   573
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   574
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   575
 * The raster position should be updated before calling this
nkeynes@265
   576
 * method.
nkeynes@265
   577
 */
nkeynes@265
   578
static void pvr2_schedule_scanline_event( int eventid, int line )
nkeynes@265
   579
{
nkeynes@265
   580
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   581
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   582
	field = !field;
nkeynes@265
   583
    }
nkeynes@265
   584
nkeynes@265
   585
    line <<= 1;
nkeynes@265
   586
    if( field ) {
nkeynes@265
   587
	line += 1;
nkeynes@265
   588
    }
nkeynes@265
   589
    pvr2_schedule_line_event( eventid, line );
nkeynes@265
   590
}
nkeynes@265
   591
nkeynes@1
   592
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   593
{
nkeynes@1
   594
    switch( reg ) {
nkeynes@261
   595
        case DISP_SYNCSTAT:
nkeynes@261
   596
            return pvr2_get_sync_status();
nkeynes@1
   597
        default:
nkeynes@1
   598
            return MMIO_READ( PVR2, reg );
nkeynes@1
   599
    }
nkeynes@1
   600
}
nkeynes@19
   601
nkeynes@85
   602
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   603
nkeynes@19
   604
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   605
{
nkeynes@197
   606
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   607
}
nkeynes@56
   608
nkeynes@56
   609
nkeynes@65
   610
nkeynes@98
   611
nkeynes@56
   612
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   613
{
nkeynes@56
   614
    return 0xFFFFFFFF;
nkeynes@56
   615
}
nkeynes@56
   616
nkeynes@56
   617
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   618
{
nkeynes@189
   619
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   620
}
nkeynes@56
   621
nkeynes@85
   622
nkeynes@103
   623
void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
nkeynes@103
   624
{
nkeynes@103
   625
    int bank_flag = (destaddr & 0x04) >> 2;
nkeynes@103
   626
    uint32_t *banks[2];
nkeynes@103
   627
    uint32_t *dwsrc;
nkeynes@103
   628
    int i;
nkeynes@65
   629
nkeynes@103
   630
    destaddr = destaddr & 0x7FFFFF;
nkeynes@103
   631
    if( destaddr + length > 0x800000 ) {
nkeynes@103
   632
	length = 0x800000 - destaddr;
nkeynes@103
   633
    }
nkeynes@103
   634
nkeynes@103
   635
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
nkeynes@103
   636
	texcache_invalidate_page( i );
nkeynes@103
   637
    }
nkeynes@103
   638
nkeynes@108
   639
    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
nkeynes@103
   640
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   641
    if( bank_flag ) 
nkeynes@108
   642
	banks[0]++;
nkeynes@103
   643
    
nkeynes@103
   644
    /* Handle non-aligned start of source */
nkeynes@103
   645
    if( destaddr & 0x03 ) {
nkeynes@103
   646
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
nkeynes@103
   647
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   648
	    *dest++ = *src++;
nkeynes@103
   649
	}
nkeynes@103
   650
	bank_flag = !bank_flag;
nkeynes@103
   651
    }
nkeynes@103
   652
nkeynes@103
   653
    dwsrc = (uint32_t *)src;
nkeynes@103
   654
    while( length >= 4 ) {
nkeynes@103
   655
	*banks[bank_flag]++ = *dwsrc++;
nkeynes@103
   656
	bank_flag = !bank_flag;
nkeynes@103
   657
	length -= 4;
nkeynes@103
   658
    }
nkeynes@103
   659
    
nkeynes@103
   660
    /* Handle non-aligned end of source */
nkeynes@103
   661
    if( length ) {
nkeynes@103
   662
	src = (char *)dwsrc;
nkeynes@103
   663
	char *dest = (char *)banks[bank_flag];
nkeynes@103
   664
	while( length-- > 0 ) {
nkeynes@103
   665
	    *dest++ = *src++;
nkeynes@103
   666
	}
nkeynes@103
   667
    }  
nkeynes@218
   668
}
nkeynes@103
   669
nkeynes@218
   670
void pvr2_vram_write_invert( sh4addr_t destaddr, char *src, uint32_t length, uint32_t line_length )
nkeynes@218
   671
{
nkeynes@218
   672
    char *dest = video_base + (destaddr & 0x007FFFFF);
nkeynes@218
   673
    char *p = src + length - line_length;
nkeynes@218
   674
    while( p >= src ) {
nkeynes@218
   675
	memcpy( dest, p, line_length );
nkeynes@218
   676
	p -= line_length;
nkeynes@218
   677
	dest += line_length;
nkeynes@218
   678
    }
nkeynes@103
   679
}
nkeynes@103
   680
nkeynes@103
   681
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   682
{
nkeynes@103
   683
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   684
    uint32_t *banks[2];
nkeynes@103
   685
    uint32_t *dwdest;
nkeynes@103
   686
    int i;
nkeynes@103
   687
nkeynes@103
   688
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   689
    if( srcaddr + length > 0x800000 )
nkeynes@103
   690
	length = 0x800000 - srcaddr;
nkeynes@103
   691
nkeynes@108
   692
    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
nkeynes@103
   693
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   694
    if( bank_flag )
nkeynes@108
   695
	banks[0]++;
nkeynes@103
   696
    
nkeynes@103
   697
    /* Handle non-aligned start of source */
nkeynes@103
   698
    if( srcaddr & 0x03 ) {
nkeynes@103
   699
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   700
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   701
	    *dest++ = *src++;
nkeynes@103
   702
	}
nkeynes@103
   703
	bank_flag = !bank_flag;
nkeynes@103
   704
    }
nkeynes@103
   705
nkeynes@103
   706
    dwdest = (uint32_t *)dest;
nkeynes@103
   707
    while( length >= 4 ) {
nkeynes@103
   708
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   709
	bank_flag = !bank_flag;
nkeynes@103
   710
	length -= 4;
nkeynes@103
   711
    }
nkeynes@103
   712
    
nkeynes@103
   713
    /* Handle non-aligned end of source */
nkeynes@103
   714
    if( length ) {
nkeynes@103
   715
	dest = (char *)dwdest;
nkeynes@103
   716
	char *src = (char *)banks[bank_flag];
nkeynes@103
   717
	while( length-- > 0 ) {
nkeynes@103
   718
	    *dest++ = *src++;
nkeynes@103
   719
	}
nkeynes@103
   720
    }
nkeynes@103
   721
}
nkeynes@127
   722
nkeynes@127
   723
void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
nkeynes@127
   724
{
nkeynes@127
   725
    char tmp[length];
nkeynes@127
   726
    pvr2_vram64_read( tmp, addr, length );
nkeynes@127
   727
    fwrite_dump( tmp, length, f );
nkeynes@127
   728
}
.