Search
lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/pvr2/pvr2.c
changeset 107:e576dd36073a
prev106:9048bac046c3
next108:565de331ccec
author nkeynes
date Tue Mar 14 13:02:06 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Make sure subfunctions are initted
Fix stupid sign bug in texcache
file annotate diff log raw
nkeynes@31
     1
/**
nkeynes@107
     2
 * $Id: pvr2.c,v 1.19 2006-03-14 13:02:06 nkeynes Exp $
nkeynes@31
     3
 *
nkeynes@100
     4
 * PVR2 (Video) Core MMIO registers.
nkeynes@31
     5
 *
nkeynes@31
     6
 * Copyright (c) 2005 Nathan Keynes.
nkeynes@31
     7
 *
nkeynes@31
     8
 * This program is free software; you can redistribute it and/or modify
nkeynes@31
     9
 * it under the terms of the GNU General Public License as published by
nkeynes@31
    10
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@31
    11
 * (at your option) any later version.
nkeynes@31
    12
 *
nkeynes@31
    13
 * This program is distributed in the hope that it will be useful,
nkeynes@31
    14
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@31
    15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@31
    16
 * GNU General Public License for more details.
nkeynes@31
    17
 */
nkeynes@35
    18
#define MODULE pvr2_module
nkeynes@31
    19
nkeynes@1
    20
#include "dream.h"
nkeynes@1
    21
#include "video.h"
nkeynes@1
    22
#include "mem.h"
nkeynes@1
    23
#include "asic.h"
nkeynes@103
    24
#include "pvr2/pvr2.h"
nkeynes@56
    25
#include "sh4/sh4core.h"
nkeynes@1
    26
#define MMIO_IMPL
nkeynes@103
    27
#include "pvr2/pvr2mmio.h"
nkeynes@1
    28
nkeynes@1
    29
char *video_base;
nkeynes@1
    30
nkeynes@15
    31
void pvr2_init( void );
nkeynes@30
    32
uint32_t pvr2_run_slice( uint32_t );
nkeynes@94
    33
void pvr2_display_frame( void );
nkeynes@94
    34
nkeynes@103
    35
/**
nkeynes@103
    36
 * Current PVR2 ram address of the data (if any) currently held in the 
nkeynes@103
    37
 * OpenGL buffers.
nkeynes@103
    38
 */
nkeynes@103
    39
nkeynes@94
    40
video_driver_t video_driver = NULL;
nkeynes@94
    41
struct video_buffer video_buffer[2];
nkeynes@94
    42
int video_buffer_idx = 0;
nkeynes@15
    43
nkeynes@103
    44
struct video_timing {
nkeynes@103
    45
    int fields_per_second;
nkeynes@103
    46
    int total_lines;
nkeynes@103
    47
    int display_lines;
nkeynes@103
    48
    int line_time_ns;
nkeynes@103
    49
};
nkeynes@103
    50
nkeynes@103
    51
struct video_timing pal_timing = { 50, 625, 575, 32000 };
nkeynes@103
    52
struct video_timing ntsc_timing= { 60, 525, 480, 31746 };
nkeynes@103
    53
nkeynes@23
    54
struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
nkeynes@23
    55
					pvr2_run_slice, NULL,
nkeynes@15
    56
					NULL, NULL };
nkeynes@15
    57
nkeynes@1
    58
void pvr2_init( void )
nkeynes@1
    59
{
nkeynes@1
    60
    register_io_region( &mmio_region_PVR2 );
nkeynes@85
    61
    register_io_region( &mmio_region_PVR2PAL );
nkeynes@56
    62
    register_io_region( &mmio_region_PVR2TA );
nkeynes@1
    63
    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
nkeynes@107
    64
    pvr2_render_init();
nkeynes@107
    65
    texcache_init();
nkeynes@106
    66
}
nkeynes@106
    67
nkeynes@106
    68
void video_set_driver( video_driver_t driver )
nkeynes@106
    69
{
nkeynes@106
    70
    if( video_driver != NULL && video_driver->shutdown_driver != NULL )
nkeynes@106
    71
	video_driver->shutdown_driver();
nkeynes@106
    72
nkeynes@106
    73
    video_driver = driver;
nkeynes@106
    74
    if( driver->init_driver != NULL )
nkeynes@106
    75
	driver->init_driver();
nkeynes@106
    76
    driver->set_display_format( 640, 480, COLFMT_RGB32 );
nkeynes@1
    77
}
nkeynes@1
    78
nkeynes@103
    79
uint32_t pvr2_line_count = 0;
nkeynes@103
    80
uint32_t pvr2_line_remainder = 0;
nkeynes@103
    81
uint32_t pvr2_irq_vpos1 = 0;
nkeynes@103
    82
uint32_t pvr2_irq_vpos2 = 0;
nkeynes@103
    83
struct video_timing *pvr2_timing = &ntsc_timing;
nkeynes@23
    84
uint32_t pvr2_time_counter = 0;
nkeynes@94
    85
uint32_t pvr2_frame_counter = 0;
nkeynes@30
    86
uint32_t pvr2_time_per_frame = 20000000;
nkeynes@23
    87
nkeynes@30
    88
uint32_t pvr2_run_slice( uint32_t nanosecs ) 
nkeynes@23
    89
{
nkeynes@103
    90
    pvr2_line_remainder += nanosecs;
nkeynes@103
    91
    while( pvr2_line_remainder >= pvr2_timing->line_time_ns ) {
nkeynes@103
    92
	pvr2_line_remainder -= pvr2_timing->line_time_ns;
nkeynes@103
    93
	pvr2_line_count++;
nkeynes@103
    94
	if( pvr2_line_count == pvr2_irq_vpos1 ) {
nkeynes@103
    95
	    asic_event( EVENT_SCANLINE1 );
nkeynes@103
    96
	} 
nkeynes@103
    97
	if( pvr2_line_count == pvr2_irq_vpos2 ) {
nkeynes@103
    98
	    asic_event( EVENT_SCANLINE2 );
nkeynes@103
    99
	}
nkeynes@103
   100
	if( pvr2_line_count == pvr2_timing->display_lines ) {
nkeynes@103
   101
	    asic_event( EVENT_RETRACE );
nkeynes@103
   102
	} else if( pvr2_line_count == pvr2_timing->total_lines ) {
nkeynes@103
   103
	    pvr2_display_frame();
nkeynes@103
   104
	    pvr2_line_count = 0;
nkeynes@103
   105
	}
nkeynes@23
   106
    }
nkeynes@30
   107
    return nanosecs;
nkeynes@23
   108
}
nkeynes@23
   109
nkeynes@1
   110
uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
nkeynes@1
   111
int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
nkeynes@1
   112
char *frame_start; /* current video start address (in real memory) */
nkeynes@1
   113
nkeynes@103
   114
/**
nkeynes@1
   115
 * Display the next frame, copying the current contents of video ram to
nkeynes@1
   116
 * the window. If the video configuration has changed, first recompute the
nkeynes@1
   117
 * new frame size/depth.
nkeynes@1
   118
 */
nkeynes@94
   119
void pvr2_display_frame( void )
nkeynes@1
   120
{
nkeynes@103
   121
    uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
nkeynes@103
   122
    
nkeynes@94
   123
    int dispsize = MMIO_READ( PVR2, DISPSIZE );
nkeynes@94
   124
    int dispmode = MMIO_READ( PVR2, DISPMODE );
nkeynes@103
   125
    int vidcfg = MMIO_READ( PVR2, DISPCFG );
nkeynes@94
   126
    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
nkeynes@94
   127
    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
nkeynes@94
   128
    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
nkeynes@103
   129
    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
nkeynes@103
   130
    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
nkeynes@1
   131
    if( bEnabled ) {
nkeynes@94
   132
	video_buffer_t buffer = &video_buffer[video_buffer_idx];
nkeynes@94
   133
	video_buffer_idx = !video_buffer_idx;
nkeynes@94
   134
	video_buffer_t last = &video_buffer[video_buffer_idx];
nkeynes@94
   135
	buffer->rowstride = (vid_ppl + vid_stride) << 2;
nkeynes@94
   136
	buffer->data = frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 );
nkeynes@94
   137
	buffer->vres = vid_lpf;
nkeynes@94
   138
	if( interlaced ) buffer->vres <<= 1;
nkeynes@103
   139
	switch( (dispmode & DISPMODE_COL) >> 2 ) {
nkeynes@103
   140
	case 0: 
nkeynes@103
   141
	    buffer->colour_format = COLFMT_ARGB1555;
nkeynes@103
   142
	    buffer->hres = vid_ppl << 1; 
nkeynes@103
   143
	    break;
nkeynes@103
   144
	case 1: 
nkeynes@103
   145
	    buffer->colour_format = COLFMT_RGB565;
nkeynes@103
   146
	    buffer->hres = vid_ppl << 1; 
nkeynes@103
   147
	    break;
nkeynes@103
   148
	case 2:
nkeynes@103
   149
	    buffer->colour_format = COLFMT_RGB888;
nkeynes@103
   150
	    buffer->hres = (vid_ppl << 2) / 3; 
nkeynes@103
   151
	    break;
nkeynes@103
   152
	case 3: 
nkeynes@103
   153
	    buffer->colour_format = COLFMT_ARGB8888;
nkeynes@103
   154
	    buffer->hres = vid_ppl; 
nkeynes@103
   155
	    break;
nkeynes@94
   156
	}
nkeynes@94
   157
	
nkeynes@94
   158
	if( video_driver != NULL ) {
nkeynes@94
   159
	    if( buffer->hres != last->hres ||
nkeynes@94
   160
		buffer->vres != last->vres ||
nkeynes@94
   161
		buffer->colour_format != last->colour_format) {
nkeynes@103
   162
		video_driver->set_display_format( buffer->hres, buffer->vres,
nkeynes@103
   163
						  buffer->colour_format );
nkeynes@94
   164
	    }
nkeynes@103
   165
	    if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
nkeynes@100
   166
		uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
nkeynes@94
   167
		video_driver->display_blank_frame( colour );
nkeynes@103
   168
	    } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
nkeynes@94
   169
		video_driver->display_frame( buffer );
nkeynes@94
   170
	    }
nkeynes@65
   171
	}
nkeynes@1
   172
    } else {
nkeynes@94
   173
	video_buffer_idx = 0;
nkeynes@94
   174
	video_buffer[0].hres = video_buffer[0].vres = 0;
nkeynes@1
   175
    }
nkeynes@94
   176
    pvr2_frame_counter++;
nkeynes@1
   177
    asic_event( EVENT_SCANLINE1 );
nkeynes@1
   178
    asic_event( EVENT_SCANLINE2 );
nkeynes@1
   179
    asic_event( EVENT_RETRACE );
nkeynes@1
   180
}
nkeynes@1
   181
nkeynes@1
   182
void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
nkeynes@1
   183
{
nkeynes@1
   184
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   185
        MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   186
        /* I don't want to hear about these */
nkeynes@1
   187
        return;
nkeynes@1
   188
    }
nkeynes@1
   189
    
nkeynes@1
   190
    INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, 
nkeynes@1
   191
          MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) );
nkeynes@1
   192
   
nkeynes@1
   193
    switch(reg) {
nkeynes@103
   194
    case VPOS_IRQ:
nkeynes@103
   195
	pvr2_irq_vpos1 = (val >> 16) & 0x03FF;
nkeynes@103
   196
	pvr2_irq_vpos2 = val & 0x03FF;
nkeynes@103
   197
	break;
nkeynes@100
   198
    case TAINIT:
nkeynes@100
   199
	if( val & 0x80000000 )
nkeynes@100
   200
	    pvr2_ta_init();
nkeynes@100
   201
	break;
nkeynes@65
   202
    case RENDSTART:
nkeynes@65
   203
	if( val == 0xFFFFFFFF )
nkeynes@65
   204
	    pvr2_render_scene();
nkeynes@65
   205
	break;
nkeynes@1
   206
    }
nkeynes@1
   207
    MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   208
}
nkeynes@1
   209
nkeynes@1
   210
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   211
{
nkeynes@1
   212
    switch( reg ) {
nkeynes@1
   213
        case BEAMPOS:
nkeynes@2
   214
            return sh4r.icount&0x20 ? 0x2000 : 1;
nkeynes@1
   215
        default:
nkeynes@1
   216
            return MMIO_READ( PVR2, reg );
nkeynes@1
   217
    }
nkeynes@1
   218
}
nkeynes@19
   219
nkeynes@85
   220
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   221
nkeynes@19
   222
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   223
{
nkeynes@19
   224
    mmio_region_PVR2_write( DISPADDR1, base );
nkeynes@19
   225
}
nkeynes@56
   226
nkeynes@56
   227
nkeynes@65
   228
nkeynes@98
   229
nkeynes@56
   230
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   231
{
nkeynes@56
   232
    return 0xFFFFFFFF;
nkeynes@56
   233
}
nkeynes@56
   234
nkeynes@56
   235
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   236
{
nkeynes@100
   237
    pvr2_ta_write( &val, sizeof(uint32_t) );
nkeynes@56
   238
}
nkeynes@56
   239
nkeynes@85
   240
nkeynes@103
   241
void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
nkeynes@103
   242
{
nkeynes@103
   243
    int bank_flag = (destaddr & 0x04) >> 2;
nkeynes@103
   244
    uint32_t *banks[2];
nkeynes@103
   245
    uint32_t *dwsrc;
nkeynes@103
   246
    int i;
nkeynes@65
   247
nkeynes@103
   248
    destaddr = destaddr & 0x7FFFFF;
nkeynes@103
   249
    if( destaddr + length > 0x800000 ) {
nkeynes@103
   250
	length = 0x800000 - destaddr;
nkeynes@103
   251
    }
nkeynes@103
   252
nkeynes@103
   253
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
nkeynes@103
   254
	texcache_invalidate_page( i );
nkeynes@103
   255
    }
nkeynes@103
   256
nkeynes@103
   257
    banks[0] = ((uint32_t *)(video_base + (destaddr>>3)));
nkeynes@103
   258
    banks[1] = banks[0] + 0x100000;
nkeynes@103
   259
    
nkeynes@103
   260
    /* Handle non-aligned start of source */
nkeynes@103
   261
    if( destaddr & 0x03 ) {
nkeynes@103
   262
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
nkeynes@103
   263
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   264
	    *dest++ = *src++;
nkeynes@103
   265
	}
nkeynes@103
   266
	bank_flag = !bank_flag;
nkeynes@103
   267
    }
nkeynes@103
   268
nkeynes@103
   269
    dwsrc = (uint32_t *)src;
nkeynes@103
   270
    while( length >= 4 ) {
nkeynes@103
   271
	*banks[bank_flag]++ = *dwsrc++;
nkeynes@103
   272
	bank_flag = !bank_flag;
nkeynes@103
   273
	length -= 4;
nkeynes@103
   274
    }
nkeynes@103
   275
    
nkeynes@103
   276
    /* Handle non-aligned end of source */
nkeynes@103
   277
    if( length ) {
nkeynes@103
   278
	src = (char *)dwsrc;
nkeynes@103
   279
	char *dest = (char *)banks[bank_flag];
nkeynes@103
   280
	while( length-- > 0 ) {
nkeynes@103
   281
	    *dest++ = *src++;
nkeynes@103
   282
	}
nkeynes@103
   283
    }  
nkeynes@103
   284
nkeynes@103
   285
}
nkeynes@103
   286
nkeynes@103
   287
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   288
{
nkeynes@103
   289
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   290
    uint32_t *banks[2];
nkeynes@103
   291
    uint32_t *dwdest;
nkeynes@103
   292
    int i;
nkeynes@103
   293
nkeynes@103
   294
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   295
    if( srcaddr + length > 0x800000 )
nkeynes@103
   296
	length = 0x800000 - srcaddr;
nkeynes@103
   297
nkeynes@103
   298
    banks[0] = ((uint32_t *)(video_base + (srcaddr>>3)));
nkeynes@103
   299
    banks[1] = banks[0] + 0x100000;
nkeynes@103
   300
    
nkeynes@103
   301
    /* Handle non-aligned start of source */
nkeynes@103
   302
    if( srcaddr & 0x03 ) {
nkeynes@103
   303
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   304
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   305
	    *dest++ = *src++;
nkeynes@103
   306
	}
nkeynes@103
   307
	bank_flag = !bank_flag;
nkeynes@103
   308
    }
nkeynes@103
   309
nkeynes@103
   310
    dwdest = (uint32_t *)dest;
nkeynes@103
   311
    while( length >= 4 ) {
nkeynes@103
   312
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   313
	bank_flag = !bank_flag;
nkeynes@103
   314
	length -= 4;
nkeynes@103
   315
    }
nkeynes@103
   316
    
nkeynes@103
   317
    /* Handle non-aligned end of source */
nkeynes@103
   318
    if( length ) {
nkeynes@103
   319
	dest = (char *)dwdest;
nkeynes@103
   320
	char *src = (char *)banks[bank_flag];
nkeynes@103
   321
	while( length-- > 0 ) {
nkeynes@103
   322
	    *dest++ = *src++;
nkeynes@103
   323
	}
nkeynes@103
   324
    }
nkeynes@103
   325
}
.