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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 817:e9d2d9be7cb6
prev810:833cc4960556
next818:2e08d8237d33
author nkeynes
date Tue Aug 19 08:38:10 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix CCR register mask
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "mem.h"
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/* The MMU (practically unique in the system) is allowed to raise exceptions
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 * directly, with a return code indicating that one was raised and the caller
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 * had better behave appropriately.
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 */
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#define RAISE_TLB_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_tlb_exception(code);
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_OTHER_ERROR(code) \
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    sh4_raise_exception(code);
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/**
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 * Abort with a non-MMU address error. Caused by user-mode code attempting
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 * to access privileged regions, or alignment faults.
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 */
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#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
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#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
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#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
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#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
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#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
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#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
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#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
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#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
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#define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
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#define OCRAM_END   (0x20000000>>LXDREAM_PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    default: return 0; /* Unreachable */
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    }
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}
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int32_t mmio_region_MMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case MMUCR:
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    uint32_t tmp;
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    switch(reg) {
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_asid = val&0xFF;
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & MMUCR_AT ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_flush_icache();
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        }
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        break;
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    case CCR:
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        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
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        val &= 0x81A7;
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        break;
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    default:
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        break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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        return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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    case MEM_OC_INDEX0: /* OIX=0 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
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        break;
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    case MEM_OC_INDEX1: /* OIX=1 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
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        break;
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    default: /* disabled */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = NULL;
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        break;
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    }
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}
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/* TLB maintanence */
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
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}
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static void mmu_invalidate_tlb()
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{
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    int i;
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    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
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        mmu_itlb[i].flags &= (~TLB_VALID);
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    }
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    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
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        mmu_utlb[i].flags &= (~TLB_VALID);
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    }
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}
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#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
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int32_t mmu_itlb_addr_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
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}
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int32_t mmu_itlb_data_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->ppn | ent->flags;
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}
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void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->vpn = val & 0xFFFFFC00;
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    ent->asid = val & 0x000000FF;
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    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
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}
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void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->ppn = val & 0x1FFFFC00;
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    ent->flags = val & 0x00001DA;
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    ent->mask = get_mask_for_flags(val);
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}
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#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
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#define UTLB_ASSOC(addr) (addr&0x80)
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#define UTLB_DATA2(addr) (addr&0x00800000)
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int32_t mmu_utlb_addr_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
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    ((ent->flags & TLB_DIRTY)<<7);
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}
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int32_t mmu_utlb_data_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    if( UTLB_DATA2(addr) ) {
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        return ent->pcmcia;
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    } else {
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        return ent->ppn | ent->flags;
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    }
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}
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/**
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 * Find a UTLB entry for the associative TLB write - same as the normal
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 * lookup but ignores the valid bit.
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 */
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static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
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   334
{
nkeynes@586
   335
    int result = -1;
nkeynes@586
   336
    unsigned int i;
nkeynes@586
   337
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   338
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   339
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
nkeynes@736
   340
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   341
            if( result != -1 ) {
nkeynes@736
   342
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@736
   343
                return -2;
nkeynes@736
   344
            }
nkeynes@736
   345
            result = i;
nkeynes@736
   346
        }
nkeynes@586
   347
    }
nkeynes@586
   348
    return result;
nkeynes@586
   349
}
nkeynes@586
   350
nkeynes@586
   351
/**
nkeynes@586
   352
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@586
   353
 * lookup but ignores the valid bit.
nkeynes@586
   354
 */
nkeynes@669
   355
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   356
{
nkeynes@586
   357
    int result = -1;
nkeynes@586
   358
    unsigned int i;
nkeynes@586
   359
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   360
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   361
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
nkeynes@736
   362
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   363
            if( result != -1 ) {
nkeynes@736
   364
                return -2;
nkeynes@736
   365
            }
nkeynes@736
   366
            result = i;
nkeynes@736
   367
        }
nkeynes@586
   368
    }
nkeynes@586
   369
    return result;
nkeynes@586
   370
}
nkeynes@586
   371
nkeynes@550
   372
void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   373
{
nkeynes@550
   374
    if( UTLB_ASSOC(addr) ) {
nkeynes@736
   375
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   376
        if( utlb >= 0 ) {
nkeynes@736
   377
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@736
   378
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@736
   379
            ent->flags |= (val & TLB_VALID);
nkeynes@736
   380
            ent->flags |= ((val & 0x200)>>7);
nkeynes@736
   381
        }
nkeynes@586
   382
nkeynes@736
   383
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   384
        if( itlb >= 0 ) {
nkeynes@736
   385
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@736
   386
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@736
   387
        }
nkeynes@586
   388
nkeynes@736
   389
        if( itlb == -2 || utlb == -2 ) {
nkeynes@736
   390
            MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   391
            return;
nkeynes@736
   392
        }
nkeynes@550
   393
    } else {
nkeynes@736
   394
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@736
   395
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@736
   396
        ent->asid = (val & 0xFF);
nkeynes@736
   397
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@736
   398
        ent->flags |= (val & TLB_VALID);
nkeynes@736
   399
        ent->flags |= ((val & 0x200)>>7);
nkeynes@550
   400
    }
nkeynes@550
   401
}
nkeynes@550
   402
nkeynes@550
   403
void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   404
{
nkeynes@550
   405
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   406
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   407
        ent->pcmcia = val & 0x0000000F;
nkeynes@550
   408
    } else {
nkeynes@736
   409
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@736
   410
        ent->flags = (val & 0x000001FF);
nkeynes@736
   411
        ent->mask = get_mask_for_flags(val);
nkeynes@550
   412
    }
nkeynes@550
   413
}
nkeynes@550
   414
nkeynes@550
   415
/* Cache access - not implemented */
nkeynes@550
   416
nkeynes@550
   417
int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550
   418
{
nkeynes@550
   419
    return 0; // not implemented
nkeynes@550
   420
}
nkeynes@550
   421
int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@550
   422
{
nkeynes@550
   423
    return 0; // not implemented
nkeynes@550
   424
}
nkeynes@550
   425
int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550
   426
{
nkeynes@550
   427
    return 0; // not implemented
nkeynes@550
   428
}
nkeynes@550
   429
int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550
   430
{
nkeynes@550
   431
    return 0; // not implemented
nkeynes@550
   432
}
nkeynes@550
   433
nkeynes@550
   434
void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   435
{
nkeynes@550
   436
}
nkeynes@550
   437
nkeynes@550
   438
void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   439
{
nkeynes@550
   440
}
nkeynes@550
   441
nkeynes@550
   442
void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   443
{
nkeynes@550
   444
}
nkeynes@550
   445
nkeynes@550
   446
void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   447
{
nkeynes@550
   448
}
nkeynes@586
   449
nkeynes@586
   450
/******************************************************************************/
nkeynes@586
   451
/*                        MMU TLB address translation                         */
nkeynes@586
   452
/******************************************************************************/
nkeynes@586
   453
nkeynes@586
   454
/**
nkeynes@586
   455
 * The translations are excessively complicated, but unfortunately it's a 
nkeynes@586
   456
 * complicated system. TODO: make this not be painfully slow.
nkeynes@586
   457
 */
nkeynes@586
   458
nkeynes@586
   459
/**
nkeynes@586
   460
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   461
 * Possible utcomes are:
nkeynes@586
   462
 *   0..63 Single match - good, return entry found
nkeynes@586
   463
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   464
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   465
 * @param vpn virtual address to resolve
nkeynes@586
   466
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   467
 */
nkeynes@586
   468
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   469
{
nkeynes@586
   470
    int result = -1;
nkeynes@586
   471
    unsigned int i;
nkeynes@586
   472
nkeynes@586
   473
    mmu_urc++;
nkeynes@586
   474
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   475
        mmu_urc = 0;
nkeynes@586
   476
    }
nkeynes@586
   477
nkeynes@586
   478
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   479
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   480
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) && 
nkeynes@736
   481
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   482
            if( result != -1 ) {
nkeynes@736
   483
                return -2;
nkeynes@736
   484
            }
nkeynes@736
   485
            result = i;
nkeynes@736
   486
        }
nkeynes@586
   487
    }
nkeynes@586
   488
    return result;
nkeynes@586
   489
}
nkeynes@586
   490
nkeynes@586
   491
/**
nkeynes@586
   492
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   493
 * Possible utcomes are:
nkeynes@586
   494
 *   0..63 Single match - good, return entry found
nkeynes@586
   495
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   496
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   497
 * @param vpn virtual address to resolve
nkeynes@586
   498
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   499
 */
nkeynes@586
   500
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   501
{
nkeynes@586
   502
    int result = -1;
nkeynes@586
   503
    unsigned int i;
nkeynes@586
   504
nkeynes@586
   505
    mmu_urc++;
nkeynes@586
   506
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   507
        mmu_urc = 0;
nkeynes@586
   508
    }
nkeynes@586
   509
nkeynes@586
   510
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   511
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   512
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   513
            if( result != -1 ) {
nkeynes@736
   514
                return -2;
nkeynes@736
   515
            }
nkeynes@736
   516
            result = i;
nkeynes@736
   517
        }
nkeynes@586
   518
    }
nkeynes@586
   519
nkeynes@586
   520
    return result;
nkeynes@586
   521
}
nkeynes@586
   522
nkeynes@586
   523
/**
nkeynes@586
   524
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   525
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   526
 */
nkeynes@586
   527
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   528
{
nkeynes@586
   529
    int replace;
nkeynes@586
   530
    /* Determine entry to replace based on lrui */
nkeynes@586
   531
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   532
        replace = 0;
nkeynes@736
   533
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   534
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   535
        replace = 1;
nkeynes@736
   536
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   537
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   538
        replace = 2;
nkeynes@736
   539
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   540
    } else { // Note - gets invalid entries too
nkeynes@736
   541
        replace = 3;
nkeynes@736
   542
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@586
   543
    } 
nkeynes@586
   544
nkeynes@586
   545
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   546
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   547
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   548
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   549
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   550
    return replace;
nkeynes@586
   551
}
nkeynes@586
   552
nkeynes@586
   553
/**
nkeynes@586
   554
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   555
 * Possible utcomes are:
nkeynes@586
   556
 *   0..63 Single match - good, return entry found
nkeynes@586
   557
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   558
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   559
 * @param vpn virtual address to resolve
nkeynes@586
   560
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   561
 */
nkeynes@586
   562
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   563
{
nkeynes@586
   564
    int result = -1;
nkeynes@586
   565
    unsigned int i;
nkeynes@586
   566
nkeynes@586
   567
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   568
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   569
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) && 
nkeynes@736
   570
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   571
            if( result != -1 ) {
nkeynes@736
   572
                return -2;
nkeynes@736
   573
            }
nkeynes@736
   574
            result = i;
nkeynes@736
   575
        }
nkeynes@586
   576
    }
nkeynes@586
   577
nkeynes@586
   578
    if( result == -1 ) {
nkeynes@736
   579
        int utlbEntry = mmu_utlb_lookup_vpn_asid( vpn );
nkeynes@736
   580
        if( utlbEntry < 0 ) {
nkeynes@736
   581
            return utlbEntry;
nkeynes@736
   582
        } else {
nkeynes@736
   583
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   584
        }
nkeynes@586
   585
    }
nkeynes@586
   586
nkeynes@586
   587
    switch( result ) {
nkeynes@586
   588
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   589
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   590
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   591
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   592
    }
nkeynes@736
   593
nkeynes@586
   594
    return result;
nkeynes@586
   595
}
nkeynes@586
   596
nkeynes@586
   597
/**
nkeynes@586
   598
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   599
 * Possible utcomes are:
nkeynes@586
   600
 *   0..63 Single match - good, return entry found
nkeynes@586
   601
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   602
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   603
 * @param vpn virtual address to resolve
nkeynes@586
   604
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   605
 */
nkeynes@586
   606
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   607
{
nkeynes@586
   608
    int result = -1;
nkeynes@586
   609
    unsigned int i;
nkeynes@586
   610
nkeynes@586
   611
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   612
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   613
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   614
            if( result != -1 ) {
nkeynes@736
   615
                return -2;
nkeynes@736
   616
            }
nkeynes@736
   617
            result = i;
nkeynes@736
   618
        }
nkeynes@586
   619
    }
nkeynes@586
   620
nkeynes@586
   621
    if( result == -1 ) {
nkeynes@736
   622
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
   623
        if( utlbEntry < 0 ) {
nkeynes@736
   624
            return utlbEntry;
nkeynes@736
   625
        } else {
nkeynes@736
   626
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   627
        }
nkeynes@586
   628
    }
nkeynes@586
   629
nkeynes@586
   630
    switch( result ) {
nkeynes@586
   631
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   632
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   633
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   634
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   635
    }
nkeynes@736
   636
nkeynes@586
   637
    return result;
nkeynes@586
   638
}
nkeynes@586
   639
nkeynes@586
   640
sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr )
nkeynes@586
   641
{
nkeynes@586
   642
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   643
    if( addr & 0x80000000 ) {
nkeynes@736
   644
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   645
            if( addr >= 0xE0000000 ) {
nkeynes@736
   646
                return addr; /* P4 - passthrough */
nkeynes@736
   647
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   648
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   649
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   650
            }
nkeynes@736
   651
        } else {
nkeynes@736
   652
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   653
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   654
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   655
                return addr;
nkeynes@736
   656
            }
nkeynes@736
   657
            MMU_READ_ADDR_ERROR();
nkeynes@736
   658
            return MMU_VMA_ERROR;
nkeynes@736
   659
        }
nkeynes@586
   660
    }
nkeynes@736
   661
nkeynes@586
   662
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   663
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   664
    }
nkeynes@586
   665
nkeynes@586
   666
    /* If we get this far, translation is required */
nkeynes@586
   667
    int entryNo;
nkeynes@586
   668
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   669
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   670
    } else {
nkeynes@736
   671
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   672
    }
nkeynes@586
   673
nkeynes@586
   674
    switch(entryNo) {
nkeynes@586
   675
    case -1:
nkeynes@736
   676
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   677
    return MMU_VMA_ERROR;
nkeynes@586
   678
    case -2:
nkeynes@736
   679
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   680
    return MMU_VMA_ERROR;
nkeynes@586
   681
    default:
nkeynes@736
   682
        if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@736
   683
                !IS_SH4_PRIVMODE() ) {
nkeynes@736
   684
            /* protection violation */
nkeynes@736
   685
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   686
            return MMU_VMA_ERROR;
nkeynes@736
   687
        }
nkeynes@586
   688
nkeynes@736
   689
        /* finally generate the target address */
nkeynes@810
   690
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@810
   691
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   692
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4 
nkeynes@810
   693
        	pma |= 0xE0000000;
nkeynes@810
   694
        return pma;
nkeynes@586
   695
    }
nkeynes@586
   696
}
nkeynes@586
   697
nkeynes@586
   698
sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr )
nkeynes@586
   699
{
nkeynes@586
   700
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   701
    if( addr & 0x80000000 ) {
nkeynes@736
   702
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   703
            if( addr >= 0xE0000000 ) {
nkeynes@736
   704
                return addr; /* P4 - passthrough */
nkeynes@736
   705
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   706
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   707
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   708
            }
nkeynes@736
   709
        } else {
nkeynes@736
   710
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   711
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   712
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   713
                return addr;
nkeynes@736
   714
            }
nkeynes@736
   715
            MMU_WRITE_ADDR_ERROR();
nkeynes@736
   716
            return MMU_VMA_ERROR;
nkeynes@736
   717
        }
nkeynes@586
   718
    }
nkeynes@736
   719
nkeynes@586
   720
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   721
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   722
    }
nkeynes@586
   723
nkeynes@586
   724
    /* If we get this far, translation is required */
nkeynes@586
   725
    int entryNo;
nkeynes@586
   726
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   727
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   728
    } else {
nkeynes@736
   729
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   730
    }
nkeynes@586
   731
nkeynes@586
   732
    switch(entryNo) {
nkeynes@586
   733
    case -1:
nkeynes@736
   734
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   735
    return MMU_VMA_ERROR;
nkeynes@586
   736
    case -2:
nkeynes@736
   737
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   738
    return MMU_VMA_ERROR;
nkeynes@586
   739
    default:
nkeynes@736
   740
        if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   741
                : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   742
            /* protection violation */
nkeynes@736
   743
            MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   744
            return MMU_VMA_ERROR;
nkeynes@736
   745
        }
nkeynes@586
   746
nkeynes@736
   747
        if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   748
            MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   749
            return MMU_VMA_ERROR;
nkeynes@736
   750
        }
nkeynes@586
   751
nkeynes@736
   752
        /* finally generate the target address */
nkeynes@810
   753
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@810
   754
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   755
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4 
nkeynes@810
   756
        	pma |= 0xE0000000;
nkeynes@810
   757
        return pma;
nkeynes@586
   758
    }
nkeynes@586
   759
}
nkeynes@586
   760
nkeynes@586
   761
/**
nkeynes@586
   762
 * Update the icache for an untranslated address
nkeynes@586
   763
 */
nkeynes@586
   764
void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
   765
{
nkeynes@586
   766
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
   767
        /* Main ram */
nkeynes@736
   768
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
   769
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
   770
        sh4_icache.mask = 0xFF000000;
nkeynes@736
   771
        sh4_icache.page = sh4_main_ram;
nkeynes@586
   772
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
   773
        /* BIOS ROM */
nkeynes@736
   774
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
   775
        sh4_icache.page_ppa = 0;
nkeynes@736
   776
        sh4_icache.mask = 0xFFE00000;
nkeynes@736
   777
        sh4_icache.page = mem_get_region(0);
nkeynes@586
   778
    } else {
nkeynes@736
   779
        /* not supported */
nkeynes@736
   780
        sh4_icache.page_vma = -1;
nkeynes@586
   781
    }
nkeynes@586
   782
}
nkeynes@586
   783
nkeynes@586
   784
/**
nkeynes@586
   785
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
   786
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
   787
 * will be invalidated instead.
nkeynes@586
   788
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
   789
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
   790
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
   791
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
   792
 * the icache.
nkeynes@586
   793
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
   794
 * if an exception was raised.
nkeynes@586
   795
 */
nkeynes@586
   796
gboolean mmu_update_icache( sh4vma_t addr )
nkeynes@586
   797
{
nkeynes@586
   798
    int entryNo;
nkeynes@586
   799
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
   800
        if( addr & 0x80000000 ) {
nkeynes@736
   801
            if( addr < 0xC0000000 ) {
nkeynes@736
   802
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   803
                mmu_update_icache_phys(addr);
nkeynes@736
   804
                return TRUE;
nkeynes@736
   805
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@736
   806
                MMU_READ_ADDR_ERROR();
nkeynes@736
   807
                return FALSE;
nkeynes@736
   808
            }
nkeynes@736
   809
        }
nkeynes@586
   810
nkeynes@736
   811
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   812
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   813
            mmu_update_icache_phys(addr);
nkeynes@736
   814
            return TRUE;
nkeynes@736
   815
        }
nkeynes@736
   816
nkeynes@807
   817
        if( (mmucr & MMUCR_SV) == 0 ) 
nkeynes@807
   818
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   819
        else
nkeynes@807
   820
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
   821
    } else {
nkeynes@736
   822
        if( addr & 0x80000000 ) {
nkeynes@736
   823
            MMU_READ_ADDR_ERROR();
nkeynes@736
   824
            return FALSE;
nkeynes@736
   825
        }
nkeynes@586
   826
nkeynes@736
   827
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   828
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   829
            mmu_update_icache_phys(addr);
nkeynes@736
   830
            return TRUE;
nkeynes@736
   831
        }
nkeynes@736
   832
nkeynes@807
   833
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   834
nkeynes@736
   835
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@736
   836
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   837
            return FALSE;
nkeynes@736
   838
        }
nkeynes@586
   839
    }
nkeynes@586
   840
nkeynes@586
   841
    switch(entryNo) {
nkeynes@586
   842
    case -1:
nkeynes@736
   843
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   844
    return FALSE;
nkeynes@586
   845
    case -2:
nkeynes@736
   846
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   847
    return FALSE;
nkeynes@586
   848
    default:
nkeynes@736
   849
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
   850
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
   851
        if( sh4_icache.page == NULL ) {
nkeynes@736
   852
            sh4_icache.page_vma = -1;
nkeynes@736
   853
        } else {
nkeynes@736
   854
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
   855
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
   856
        }
nkeynes@736
   857
        return TRUE;
nkeynes@586
   858
    }
nkeynes@586
   859
}
nkeynes@586
   860
nkeynes@597
   861
/**
nkeynes@597
   862
 * Translate address for disassembly purposes (ie performs an instruction 
nkeynes@597
   863
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
   864
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@597
   865
 * on translation failure. 
nkeynes@597
   866
 */
nkeynes@597
   867
sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
   868
{
nkeynes@597
   869
    if( vma & 0x80000000 ) {
nkeynes@736
   870
        if( vma < 0xC0000000 ) {
nkeynes@736
   871
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   872
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
   873
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
   874
            /* Not translatable */
nkeynes@736
   875
            return MMU_VMA_ERROR;
nkeynes@736
   876
        }
nkeynes@597
   877
    }
nkeynes@597
   878
nkeynes@597
   879
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
   880
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   881
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
   882
    }
nkeynes@736
   883
nkeynes@597
   884
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
   885
    if( entryNo == -2 ) {
nkeynes@736
   886
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
   887
    }
nkeynes@597
   888
    if( entryNo < 0 ) {
nkeynes@736
   889
        return MMU_VMA_ERROR;
nkeynes@597
   890
    } else {
nkeynes@736
   891
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) | 
nkeynes@736
   892
        (vma & (~mmu_itlb[entryNo].mask));	
nkeynes@597
   893
    }
nkeynes@597
   894
}
nkeynes@597
   895
nkeynes@586
   896
gboolean sh4_flush_store_queue( sh4addr_t addr )
nkeynes@586
   897
{
nkeynes@586
   898
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   899
    int queue = (addr&0x20)>>2;
nkeynes@586
   900
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@586
   901
    sh4addr_t target;
nkeynes@586
   902
    /* Store queue operation */
nkeynes@586
   903
    if( mmucr & MMUCR_AT ) {
nkeynes@736
   904
        int entryNo;
nkeynes@736
   905
        if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   906
            entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@736
   907
        } else {
nkeynes@736
   908
            entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@736
   909
        }
nkeynes@736
   910
        switch(entryNo) {
nkeynes@736
   911
        case -1:
nkeynes@736
   912
        MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   913
        return FALSE;
nkeynes@736
   914
        case -2:
nkeynes@736
   915
        MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   916
        return FALSE;
nkeynes@736
   917
        default:
nkeynes@736
   918
            if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   919
                    : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   920
                /* protection violation */
nkeynes@736
   921
                MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   922
                return FALSE;
nkeynes@736
   923
            }
nkeynes@736
   924
nkeynes@736
   925
            if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   926
                MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   927
                return FALSE;
nkeynes@736
   928
            }
nkeynes@736
   929
nkeynes@736
   930
            /* finally generate the target address */
nkeynes@736
   931
            target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@736
   932
                    (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
nkeynes@736
   933
        }
nkeynes@586
   934
    } else {
nkeynes@736
   935
        uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@736
   936
        target = (addr&0x03FFFFE0) | hi;
nkeynes@586
   937
    }
nkeynes@586
   938
    mem_copy_to_sh4( target, src, 32 );
nkeynes@586
   939
    return TRUE;
nkeynes@586
   940
}
nkeynes@586
   941
.