nkeynes@11 | 1 | /**
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nkeynes@61 | 2 | * $Id: aica.c,v 1.10 2006-01-02 14:50:12 nkeynes Exp $
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nkeynes@11 | 3 | *
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nkeynes@11 | 4 | * This is the core sound system (ie the bit which does the actual work)
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nkeynes@11 | 5 | *
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nkeynes@11 | 6 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@11 | 7 | *
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nkeynes@11 | 8 | * This program is free software; you can redistribute it and/or modify
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nkeynes@11 | 9 | * it under the terms of the GNU General Public License as published by
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nkeynes@11 | 10 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@11 | 11 | * (at your option) any later version.
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nkeynes@11 | 12 | *
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nkeynes@11 | 13 | * This program is distributed in the hope that it will be useful,
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nkeynes@11 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@11 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@11 | 16 | * GNU General Public License for more details.
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nkeynes@11 | 17 | */
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nkeynes@11 | 18 |
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nkeynes@35 | 19 | #define MODULE aica_module
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nkeynes@35 | 20 |
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nkeynes@11 | 21 | #include "dream.h"
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nkeynes@15 | 22 | #include "mem.h"
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nkeynes@11 | 23 | #include "aica.h"
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nkeynes@61 | 24 | #include "armcore.h"
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nkeynes@11 | 25 | #define MMIO_IMPL
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nkeynes@11 | 26 | #include "aica.h"
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nkeynes@11 | 27 |
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nkeynes@11 | 28 | MMIO_REGION_READ_DEFFN( AICA0 )
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nkeynes@11 | 29 | MMIO_REGION_READ_DEFFN( AICA1 )
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nkeynes@11 | 30 | MMIO_REGION_READ_DEFFN( AICA2 )
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nkeynes@11 | 31 |
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nkeynes@23 | 32 | void aica_init( void );
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nkeynes@23 | 33 | void aica_reset( void );
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nkeynes@23 | 34 | void aica_start( void );
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nkeynes@23 | 35 | void aica_stop( void );
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nkeynes@35 | 36 | void aica_save_state( FILE *f );
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nkeynes@35 | 37 | int aica_load_state( FILE *f );
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nkeynes@30 | 38 | uint32_t aica_run_slice( uint32_t );
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nkeynes@23 | 39 |
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nkeynes@23 | 40 |
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nkeynes@23 | 41 | struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset,
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nkeynes@23 | 42 | aica_start, aica_run_slice, aica_stop,
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nkeynes@35 | 43 | aica_save_state, aica_load_state };
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nkeynes@15 | 44 |
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nkeynes@11 | 45 | /**
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nkeynes@11 | 46 | * Initialize the AICA subsystem. Note requires that
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nkeynes@11 | 47 | */
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nkeynes@11 | 48 | void aica_init( void )
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nkeynes@11 | 49 | {
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nkeynes@11 | 50 | register_io_regions( mmio_list_spu );
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nkeynes@11 | 51 | MMIO_NOTRACE(AICA0);
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nkeynes@11 | 52 | MMIO_NOTRACE(AICA1);
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nkeynes@11 | 53 | arm_mem_init();
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nkeynes@37 | 54 | arm_reset();
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nkeynes@11 | 55 | }
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nkeynes@11 | 56 |
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nkeynes@11 | 57 | void aica_reset( void )
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nkeynes@11 | 58 | {
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nkeynes@35 | 59 | arm_reset();
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nkeynes@11 | 60 | }
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nkeynes@11 | 61 |
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nkeynes@23 | 62 | void aica_start( void )
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nkeynes@23 | 63 | {
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nkeynes@23 | 64 |
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nkeynes@23 | 65 | }
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nkeynes@23 | 66 |
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nkeynes@30 | 67 | uint32_t aica_run_slice( uint32_t nanosecs )
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nkeynes@23 | 68 | {
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nkeynes@23 | 69 | /* Run arm instructions */
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nkeynes@35 | 70 | int reset = MMIO_READ( AICA2, AICA_RESET );
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nkeynes@44 | 71 | if( (reset & 1) == 0 ) {
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nkeynes@35 | 72 | /* Running */
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nkeynes@43 | 73 | nanosecs = arm_run_slice( nanosecs );
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nkeynes@35 | 74 | }
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nkeynes@23 | 75 | /* Generate audio buffer */
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nkeynes@43 | 76 | return nanosecs;
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nkeynes@23 | 77 | }
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nkeynes@23 | 78 |
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nkeynes@23 | 79 | void aica_stop( void )
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nkeynes@23 | 80 | {
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nkeynes@23 | 81 |
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nkeynes@23 | 82 | }
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nkeynes@23 | 83 |
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nkeynes@35 | 84 | void aica_save_state( FILE *f )
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nkeynes@35 | 85 | {
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nkeynes@35 | 86 | arm_save_state( f );
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nkeynes@35 | 87 | }
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nkeynes@35 | 88 |
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nkeynes@35 | 89 | int aica_load_state( FILE *f )
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nkeynes@35 | 90 | {
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nkeynes@35 | 91 | return arm_load_state( f );
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nkeynes@35 | 92 | }
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nkeynes@35 | 93 |
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nkeynes@61 | 94 | int aica_event_pending = 0;
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nkeynes@61 | 95 | int aica_clear_count = 0;
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nkeynes@61 | 96 |
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nkeynes@61 | 97 | /* Note: This is probably not necessarily technically correct but it should
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nkeynes@61 | 98 | * work in the meantime.
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nkeynes@61 | 99 | */
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nkeynes@61 | 100 |
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nkeynes@61 | 101 | void aica_event( int event )
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nkeynes@61 | 102 | {
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nkeynes@61 | 103 | if( aica_event_pending == 0 )
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nkeynes@61 | 104 | armr.int_pending |= CPSR_F;
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nkeynes@61 | 105 | aica_event_pending |= (1<<event);
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nkeynes@61 | 106 |
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nkeynes@61 | 107 | int pending = MMIO_READ( AICA2, AICA_IRQ );
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nkeynes@61 | 108 | if( pending == 0 || event < pending )
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nkeynes@61 | 109 | MMIO_WRITE( AICA2, AICA_IRQ, event );
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nkeynes@61 | 110 | }
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nkeynes@61 | 111 |
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nkeynes@61 | 112 | void aica_clear_event( )
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nkeynes@61 | 113 | {
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nkeynes@61 | 114 | aica_clear_count++;
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nkeynes@61 | 115 | if( aica_clear_count == 4 ) {
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nkeynes@61 | 116 | int i;
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nkeynes@61 | 117 | aica_clear_count = 0;
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nkeynes@61 | 118 |
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nkeynes@61 | 119 | for( i=0; i<8; i++ ) {
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nkeynes@61 | 120 | if( aica_event_pending & (1<<i) ) {
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nkeynes@61 | 121 | aica_event_pending &= ~(1<<i);
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nkeynes@61 | 122 | break;
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nkeynes@61 | 123 | }
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nkeynes@61 | 124 | }
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nkeynes@61 | 125 | for( ;i<8; i++ ) {
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nkeynes@61 | 126 | if( aica_event_pending & (1<<i) ) {
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nkeynes@61 | 127 | MMIO_WRITE( AICA2, AICA_IRQ, i );
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nkeynes@61 | 128 | break;
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nkeynes@61 | 129 | }
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nkeynes@61 | 130 | }
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nkeynes@61 | 131 | if( aica_event_pending == 0 )
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nkeynes@61 | 132 | armr.int_pending &= ~CPSR_F;
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nkeynes@61 | 133 | }
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nkeynes@61 | 134 | }
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nkeynes@11 | 135 | /** Channel register structure:
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nkeynes@43 | 136 | * 00 4 Channel config
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nkeynes@43 | 137 | * 04 4 Waveform address lo (16 bits)
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nkeynes@11 | 138 | * 08 4 Loop start address
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nkeynes@11 | 139 | * 0C 4 Loop end address
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nkeynes@11 | 140 | * 10 4 Volume envelope
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nkeynes@43 | 141 | * 14 4 Init to 0x1F
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nkeynes@43 | 142 | * 18 4 Frequency (floating point)
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nkeynes@43 | 143 | * 1C 4 ??
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nkeynes@43 | 144 | * 20 4 ??
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nkeynes@11 | 145 | * 24 1 Pan
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nkeynes@11 | 146 | * 25 1 ??
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nkeynes@11 | 147 | * 26
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nkeynes@11 | 148 | * 27
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nkeynes@11 | 149 | * 28 1 ??
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nkeynes@11 | 150 | * 29 1 Volume
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nkeynes@11 | 151 | * 2C
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nkeynes@11 | 152 | * 30
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nkeynes@11 | 153 | *
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nkeynes@11 | 154 |
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nkeynes@11 | 155 | /* Write to channels 0-31 */
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nkeynes@11 | 156 | void mmio_region_AICA0_write( uint32_t reg, uint32_t val )
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nkeynes@11 | 157 | {
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nkeynes@11 | 158 | // aica_write_channel( reg >> 7, reg % 128, val );
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nkeynes@35 | 159 | MMIO_WRITE( AICA0, reg, val );
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nkeynes@37 | 160 | // DEBUG( "AICA0 Write %08X => %08X", val, reg );
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nkeynes@11 | 161 | }
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nkeynes@11 | 162 |
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nkeynes@11 | 163 | /* Write to channels 32-64 */
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nkeynes@11 | 164 | void mmio_region_AICA1_write( uint32_t reg, uint32_t val )
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nkeynes@11 | 165 | {
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nkeynes@11 | 166 | // aica_write_channel( (reg >> 7) + 32, reg % 128, val );
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nkeynes@35 | 167 | MMIO_WRITE( AICA1, reg, val );
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nkeynes@37 | 168 | // DEBUG( "AICA1 Write %08X => %08X", val, reg );
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nkeynes@11 | 169 | }
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nkeynes@11 | 170 |
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nkeynes@11 | 171 | /* General registers */
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nkeynes@11 | 172 | void mmio_region_AICA2_write( uint32_t reg, uint32_t val )
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nkeynes@11 | 173 | {
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nkeynes@35 | 174 | uint32_t tmp;
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nkeynes@35 | 175 | switch( reg ) {
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nkeynes@35 | 176 | case AICA_RESET:
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nkeynes@35 | 177 | tmp = MMIO_READ( AICA2, AICA_RESET );
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nkeynes@37 | 178 | if( (tmp & 1) == 1 && (val & 1) == 0 ) {
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nkeynes@35 | 179 | /* ARM enabled - execute a core reset */
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nkeynes@37 | 180 | DEBUG( "ARM enabled" );
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nkeynes@35 | 181 | arm_reset();
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nkeynes@37 | 182 | } else if( (tmp&1) == 0 && (val&1) == 1 ) {
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nkeynes@37 | 183 | DEBUG( "ARM disabled" );
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nkeynes@35 | 184 | }
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nkeynes@35 | 185 | MMIO_WRITE( AICA2, AICA_RESET, val );
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nkeynes@35 | 186 | break;
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nkeynes@61 | 187 | case AICA_IRQCLEAR:
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nkeynes@61 | 188 | aica_clear_event();
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nkeynes@61 | 189 | break;
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nkeynes@35 | 190 | default:
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nkeynes@35 | 191 | MMIO_WRITE( AICA2, reg, val );
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nkeynes@35 | 192 | break;
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nkeynes@35 | 193 | }
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nkeynes@11 | 194 | }
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