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lxdream.org :: lxdream/src/aica/aica.c
lxdream 0.9.1
released Jun 29
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filename src/aica/aica.c
changeset 61:eb7a73c9bcae
prev44:8da2cbcffe24
next66:2ec5b6eb75e5
author nkeynes
date Mon Jan 02 14:50:12 2006 +0000 (15 years ago)
permissions -rw-r--r--
last change AICA IRQ event work in progress
file annotate diff log raw
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/**
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 * $Id: aica.c,v 1.10 2006-01-02 14:50:12 nkeynes Exp $
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 * 
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 * This is the core sound system (ie the bit which does the actual work)
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE aica_module
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#include "dream.h"
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#include "mem.h"
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#include "aica.h"
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#include "armcore.h"
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#define MMIO_IMPL
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#include "aica.h"
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MMIO_REGION_READ_DEFFN( AICA0 )
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MMIO_REGION_READ_DEFFN( AICA1 )
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MMIO_REGION_READ_DEFFN( AICA2 )
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void aica_init( void );
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void aica_reset( void );
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void aica_start( void );
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void aica_stop( void );
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void aica_save_state( FILE *f );
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int aica_load_state( FILE *f );
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uint32_t aica_run_slice( uint32_t );
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struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset, 
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					aica_start, aica_run_slice, aica_stop,
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					aica_save_state, aica_load_state };
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/**
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 * Initialize the AICA subsystem. Note requires that 
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 */
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void aica_init( void )
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{
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    register_io_regions( mmio_list_spu );
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    MMIO_NOTRACE(AICA0);
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    MMIO_NOTRACE(AICA1);
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    arm_mem_init();
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    arm_reset();
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}
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void aica_reset( void )
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{
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    arm_reset();
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}
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void aica_start( void )
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{
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}
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uint32_t aica_run_slice( uint32_t nanosecs )
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{
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    /* Run arm instructions */
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    int reset = MMIO_READ( AICA2, AICA_RESET );
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    if( (reset & 1) == 0 ) { 
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	/* Running */
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        nanosecs = arm_run_slice( nanosecs );
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    }
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    /* Generate audio buffer */
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    return nanosecs;
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}
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void aica_stop( void )
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{
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}
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void aica_save_state( FILE *f )
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{
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    arm_save_state( f );
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}
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int aica_load_state( FILE *f )
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{
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    return arm_load_state( f );
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}
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int aica_event_pending = 0;
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int aica_clear_count = 0;
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/* Note: This is probably not necessarily technically correct but it should
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 * work in the meantime.
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 */
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void aica_event( int event )
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{
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    if( aica_event_pending == 0 )
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	armr.int_pending |= CPSR_F;
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    aica_event_pending |= (1<<event);
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    int pending = MMIO_READ( AICA2, AICA_IRQ );
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    if( pending == 0 || event < pending )
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	MMIO_WRITE( AICA2, AICA_IRQ, event );
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}
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void aica_clear_event( )
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{
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    aica_clear_count++;
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    if( aica_clear_count == 4 ) {
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	int i;
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	aica_clear_count = 0;
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	for( i=0; i<8; i++ ) {
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	    if( aica_event_pending & (1<<i) ) {
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		aica_event_pending &= ~(1<<i);
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		break;
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	    }
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	}
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	for( ;i<8; i++ ) {
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	    if( aica_event_pending & (1<<i) ) {
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		MMIO_WRITE( AICA2, AICA_IRQ, i );
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		break;
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	    }
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	}
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	if( aica_event_pending == 0 )
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	    armr.int_pending &= ~CPSR_F;
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    }
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}
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/** Channel register structure:
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 * 00  4  Channel config
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 * 04  4  Waveform address lo (16 bits)
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 * 08  4  Loop start address
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 * 0C  4  Loop end address
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 * 10  4  Volume envelope
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 * 14  4  Init to 0x1F
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 * 18  4  Frequency (floating point)
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 * 1C  4  ?? 
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 * 20  4  ??
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 * 24  1  Pan
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 * 25  1  ??
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 * 26  
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 * 27  
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 * 28  1  ??
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 * 29  1  Volume
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 * 2C
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 * 30
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 * 
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/* Write to channels 0-31 */
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void mmio_region_AICA0_write( uint32_t reg, uint32_t val )
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{
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    //    aica_write_channel( reg >> 7, reg % 128, val );
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    MMIO_WRITE( AICA0, reg, val );
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    //    DEBUG( "AICA0 Write %08X => %08X", val, reg );
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}
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/* Write to channels 32-64 */
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void mmio_region_AICA1_write( uint32_t reg, uint32_t val )
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{
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    //    aica_write_channel( (reg >> 7) + 32, reg % 128, val );
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    MMIO_WRITE( AICA1, reg, val );
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    // DEBUG( "AICA1 Write %08X => %08X", val, reg );
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}
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/* General registers */
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void mmio_region_AICA2_write( uint32_t reg, uint32_t val )
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{
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    uint32_t tmp;
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    switch( reg ) {
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    case AICA_RESET:
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	tmp = MMIO_READ( AICA2, AICA_RESET );
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	if( (tmp & 1) == 1 && (val & 1) == 0 ) {
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	    /* ARM enabled - execute a core reset */
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	    DEBUG( "ARM enabled" );
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	    arm_reset();
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	} else if( (tmp&1) == 0 && (val&1) == 1 ) {
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	    DEBUG( "ARM disabled" );
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	}
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	MMIO_WRITE( AICA2, AICA_RESET, val );
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	break;
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    case AICA_IRQCLEAR:
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	aica_clear_event();
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	break;
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    default:
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	MMIO_WRITE( AICA2, reg, val );
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	break;
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    }
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}
.