lxdream.org :: lxdream/src/aica/armcore.c r51:ed6c27067502 (annotated)

tree revision 51:ed6c27067502

filename	src/aica/armcore.c
changeset	51:ed6c27067502
prev	49:6290c467cfbd
next	52:429b7fc6b843
author	nkeynes
date	Wed Dec 28 22:49:26 2005 +0000 (18 years ago)
permissions	-rw-r--r--
last change	Add several missing M instructions Add SWI instruction Fix disasm of LDM Accept interrupts

file

annotate

diff

log

raw

nkeynes@30	1	/**
nkeynes@51	2	* $Id: armcore.c,v 1.12 2005-12-28 22:49:26 nkeynes Exp $
nkeynes@30	3	*
nkeynes@30	4	* ARM7TDMI CPU emulation core.
nkeynes@30	5	*
nkeynes@30	6	* Copyright (c) 2005 Nathan Keynes.
nkeynes@30	7	*
nkeynes@30	8	* This program is free software; you can redistribute it and/or modify
nkeynes@30	9	* it under the terms of the GNU General Public License as published by
nkeynes@30	10	* the Free Software Foundation; either version 2 of the License, or
nkeynes@30	11	* (at your option) any later version.
nkeynes@30	12	*
nkeynes@30	13	* This program is distributed in the hope that it will be useful,
nkeynes@30	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@30	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
nkeynes@30	16	* GNU General Public License for more details.
nkeynes@30	17	*/
nkeynes@2	18
nkeynes@37	19	#define MODULE aica_module
nkeynes@37	20	#include "dream.h"
nkeynes@7	21	#include "aica/armcore.h"
nkeynes@43	22	#include "mem.h"
nkeynes@2	23
nkeynes@51	24	#define STM_R15_OFFSET 12
nkeynes@51	25
nkeynes@2	26	struct arm_registers armr;
nkeynes@2	27
nkeynes@35	28	void arm_set_mode( int mode );
nkeynes@35	29
nkeynes@35	30	uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 },
nkeynes@35	31	{ MODE_UND, 0x00000004 },
nkeynes@35	32	{ MODE_SVC, 0x00000008 },
nkeynes@35	33	{ MODE_ABT, 0x0000000C },
nkeynes@35	34	{ MODE_ABT, 0x00000010 },
nkeynes@35	35	{ MODE_IRQ, 0x00000018 },
nkeynes@35	36	{ MODE_FIQ, 0x0000001C } };
nkeynes@35	37
nkeynes@35	38	#define EXC_RESET 0
nkeynes@35	39	#define EXC_UNDEFINED 1
nkeynes@35	40	#define EXC_SOFTWARE 2
nkeynes@35	41	#define EXC_PREFETCH_ABORT 3
nkeynes@35	42	#define EXC_DATA_ABORT 4
nkeynes@35	43	#define EXC_IRQ 5
nkeynes@35	44	#define EXC_FAST_IRQ 6
nkeynes@35	45
nkeynes@35	46	uint32_t arm_cpu_freq = ARM_BASE_RATE;
nkeynes@35	47	uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;
nkeynes@35	48
nkeynes@43	49
nkeynes@43	50	static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];
nkeynes@43	51	static int arm_breakpoint_count = 0;
nkeynes@43	52
nkeynes@43	53	void arm_set_breakpoint( uint32_t pc, int type )
nkeynes@43	54	{
nkeynes@43	55	arm_breakpoints[arm_breakpoint_count].address = pc;
nkeynes@43	56	arm_breakpoints[arm_breakpoint_count].type = type;
nkeynes@43	57	arm_breakpoint_count++;
nkeynes@43	58	}
nkeynes@43	59
nkeynes@43	60	gboolean arm_clear_breakpoint( uint32_t pc, int type )
nkeynes@43	61	{
nkeynes@43	62	int i;
nkeynes@43	63
nkeynes@43	64	for( i=0; i<arm_breakpoint_count; i++ ) {
nkeynes@43	65	if( arm_breakpoints[i].address == pc &&
nkeynes@43	66	arm_breakpoints[i].type == type ) {
nkeynes@43	67	while( ++i < arm_breakpoint_count ) {
nkeynes@43	68	arm_breakpoints[i-1].address = arm_breakpoints[i].address;
nkeynes@43	69	arm_breakpoints[i-1].type = arm_breakpoints[i].type;
nkeynes@43	70	}
nkeynes@43	71	arm_breakpoint_count--;
nkeynes@43	72	return TRUE;
nkeynes@43	73	}
nkeynes@43	74	}
nkeynes@43	75	return FALSE;
nkeynes@43	76	}
nkeynes@43	77
nkeynes@43	78	int arm_get_breakpoint( uint32_t pc )
nkeynes@43	79	{
nkeynes@43	80	int i;
nkeynes@43	81	for( i=0; i<arm_breakpoint_count; i++ ) {
nkeynes@43	82	if( arm_breakpoints[i].address == pc )
nkeynes@43	83	return arm_breakpoints[i].type;
nkeynes@43	84	}
nkeynes@43	85	return 0;
nkeynes@43	86	}
nkeynes@43	87
nkeynes@35	88	uint32_t arm_run_slice( uint32_t nanosecs )
nkeynes@35	89	{
nkeynes@43	90	int i;
nkeynes@35	91	uint32_t target = armr.icount + nanosecs / arm_cpu_period;
nkeynes@35	92	uint32_t start = armr.icount;
nkeynes@35	93	while( armr.icount < target ) {
nkeynes@35	94	armr.icount++;
nkeynes@35	95	if( !arm_execute_instruction() )
nkeynes@35	96	break;
nkeynes@43	97	#ifdef ENABLE_DEBUG_MODE
nkeynes@43	98	for( i=0; i<arm_breakpoint_count; i++ ) {
nkeynes@43	99	if( arm_breakpoints[i].address == armr.r[15] ) {
nkeynes@43	100	break;
nkeynes@43	101	}
nkeynes@43	102	}
nkeynes@43	103	if( i != arm_breakpoint_count ) {
nkeynes@43	104	dreamcast_stop();
nkeynes@43	105	if( arm_breakpoints[i].type == BREAK_ONESHOT )
nkeynes@43	106	arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
nkeynes@43	107	break;
nkeynes@43	108	}
nkeynes@43	109	#endif
nkeynes@35	110	}
nkeynes@35	111
nkeynes@35	112	if( target != armr.icount ) {
nkeynes@35	113	/* Halted - compute time actually executed */
nkeynes@35	114	nanosecs = (armr.icount - start) * arm_cpu_period;
nkeynes@35	115	}
nkeynes@35	116	return nanosecs;
nkeynes@35	117	}
nkeynes@35	118
nkeynes@35	119	void arm_save_state( FILE *f )
nkeynes@35	120	{
nkeynes@35	121	fwrite( &armr, sizeof(armr), 1, f );
nkeynes@35	122	}
nkeynes@35	123
nkeynes@35	124	int arm_load_state( FILE *f )
nkeynes@35	125	{
nkeynes@35	126	fread( &armr, sizeof(armr), 1, f );
nkeynes@35	127	return 0;
nkeynes@35	128	}
nkeynes@35	129
nkeynes@35	130	/* Exceptions */
nkeynes@35	131	void arm_reset( void )
nkeynes@35	132	{
nkeynes@35	133	/* Wipe all processor state */
nkeynes@35	134	memset( &armr, 0, sizeof(armr) );
nkeynes@35	135
nkeynes@35	136	armr.cpsr = MODE_SVC \| CPSR_I \| CPSR_F;
nkeynes@35	137	armr.r[15] = 0x00000000;
nkeynes@35	138	}
nkeynes@35	139
nkeynes@37	140	#define SET_CPSR_CONTROL 0x00010000
nkeynes@37	141	#define SET_CPSR_EXTENSION 0x00020000
nkeynes@37	142	#define SET_CPSR_STATUS 0x00040000
nkeynes@37	143	#define SET_CPSR_FLAGS 0x00080000
nkeynes@37	144
nkeynes@37	145	uint32_t arm_get_cpsr( void )
nkeynes@37	146	{
nkeynes@37	147	/* write back all flags to the cpsr */
nkeynes@37	148	armr.cpsr = armr.cpsr & CPSR_COMPACT_MASK;
nkeynes@37	149	if( armr.n ) armr.cpsr \|= CPSR_N;
nkeynes@37	150	if( armr.z ) armr.cpsr \|= CPSR_Z;
nkeynes@37	151	if( armr.c ) armr.cpsr \|= CPSR_C;
nkeynes@37	152	if( armr.v ) armr.cpsr \|= CPSR_V;
nkeynes@37	153	if( armr.t ) armr.cpsr \|= CPSR_T;
nkeynes@37	154	return armr.cpsr;
nkeynes@37	155	}
nkeynes@37	156
nkeynes@37	157	/**
nkeynes@37	158	* Set the CPSR to the specified value.
nkeynes@37	159	*
nkeynes@37	160	* @param value values to set in CPSR
nkeynes@37	161	* @param fields set of mask values to define which sections of the
nkeynes@37	162	* CPSR to set (one of the SET_CPSR_* values above)
nkeynes@37	163	*/
nkeynes@37	164	void arm_set_cpsr( uint32_t value, uint32_t fields )
nkeynes@37	165	{
nkeynes@37	166	if( IS_PRIVILEGED_MODE() ) {
nkeynes@37	167	if( fields & SET_CPSR_CONTROL ) {
nkeynes@37	168	int mode = value & CPSR_MODE;
nkeynes@37	169	arm_set_mode( mode );
nkeynes@37	170	armr.t = ( value & CPSR_T ); /* Technically illegal to change */
nkeynes@37	171	armr.cpsr = (armr.cpsr & 0xFFFFFF00) \| (value & 0x000000FF);
nkeynes@37	172	}
nkeynes@37	173
nkeynes@37	174	/* Middle 16 bits not currently defined */
nkeynes@37	175	}
nkeynes@37	176	if( fields & SET_CPSR_FLAGS ) {
nkeynes@37	177	/* Break flags directly out of given value - don't bother writing
nkeynes@37	178	* back to CPSR
nkeynes@37	179	*/
nkeynes@37	180	armr.n = ( value & CPSR_N );
nkeynes@37	181	armr.z = ( value & CPSR_Z );
nkeynes@37	182	armr.c = ( value & CPSR_C );
nkeynes@37	183	armr.v = ( value & CPSR_V );
nkeynes@37	184	}
nkeynes@37	185	}
nkeynes@37	186
nkeynes@37	187	void arm_set_spsr( uint32_t value, uint32_t fields )
nkeynes@37	188	{
nkeynes@37	189	/* Only defined if we actually have an SPSR register */
nkeynes@37	190	if( IS_EXCEPTION_MODE() ) {
nkeynes@37	191	if( fields & SET_CPSR_CONTROL ) {
nkeynes@37	192	armr.spsr = (armr.spsr & 0xFFFFFF00) \| (value & 0x000000FF);
nkeynes@37	193	}
nkeynes@37	194
nkeynes@37	195	/* Middle 16 bits not currently defined */
nkeynes@37	196
nkeynes@37	197	if( fields & SET_CPSR_FLAGS ) {
nkeynes@37	198	armr.spsr = (armr.spsr & 0x00FFFFFF) \| (value & 0xFF000000);
nkeynes@37	199	}
nkeynes@37	200	}
nkeynes@37	201	}
nkeynes@37	202
nkeynes@35	203	/**
nkeynes@35	204	* Raise an ARM exception (other than reset, which uses arm_reset().
nkeynes@35	205	* @param exception one of the EXC_* exception codes defined above.
nkeynes@35	206	*/
nkeynes@35	207	void arm_raise_exception( int exception )
nkeynes@35	208	{
nkeynes@35	209	int mode = arm_exceptions[exception][0];
nkeynes@37	210	uint32_t spsr = arm_get_cpsr();
nkeynes@35	211	arm_set_mode( mode );
nkeynes@37	212	armr.spsr = spsr;
nkeynes@35	213	armr.r[14] = armr.r[15];
nkeynes@37	214	armr.cpsr = (spsr & (~CPSR_T)) \| CPSR_I;
nkeynes@35	215	if( mode == MODE_FIQ )
nkeynes@35	216	armr.cpsr \|= CPSR_F;
nkeynes@35	217	armr.r[15] = arm_exceptions[exception][1];
nkeynes@35	218	}
nkeynes@35	219
nkeynes@37	220	void arm_restore_cpsr( void )
nkeynes@35	221	{
nkeynes@35	222	int spsr = armr.spsr;
nkeynes@35	223	int mode = spsr & CPSR_MODE;
nkeynes@35	224	arm_set_mode( mode );
nkeynes@35	225	armr.cpsr = spsr;
nkeynes@37	226	armr.n = ( spsr & CPSR_N );
nkeynes@37	227	armr.z = ( spsr & CPSR_Z );
nkeynes@37	228	armr.c = ( spsr & CPSR_C );
nkeynes@37	229	armr.v = ( spsr & CPSR_V );
nkeynes@37	230	armr.t = ( spsr & CPSR_T );
nkeynes@35	231	}
nkeynes@35	232
nkeynes@35	233
nkeynes@35	234
nkeynes@35	235	/**
nkeynes@35	236	* Change the current executing ARM mode to the requested mode.
nkeynes@35	237	* Saves any required registers to banks and restores those for the
nkeynes@35	238	* correct mode. (Note does not actually update CPSR at the moment).
nkeynes@35	239	*/
nkeynes@35	240	void arm_set_mode( int targetMode )
nkeynes@35	241	{
nkeynes@35	242	int currentMode = armr.cpsr & CPSR_MODE;
nkeynes@35	243	if( currentMode == targetMode )
nkeynes@35	244	return;
nkeynes@35	245
nkeynes@35	246	switch( currentMode ) {
nkeynes@35	247	case MODE_USER:
nkeynes@35	248	case MODE_SYS:
nkeynes@35	249	armr.user_r[5] = armr.r[13];
nkeynes@35	250	armr.user_r[6] = armr.r[14];
nkeynes@35	251	break;
nkeynes@35	252	case MODE_SVC:
nkeynes@35	253	armr.svc_r[0] = armr.r[13];
nkeynes@35	254	armr.svc_r[1] = armr.r[14];
nkeynes@35	255	armr.svc_r[2] = armr.spsr;
nkeynes@35	256	break;
nkeynes@35	257	case MODE_ABT:
nkeynes@35	258	armr.abt_r[0] = armr.r[13];
nkeynes@35	259	armr.abt_r[1] = armr.r[14];
nkeynes@35	260	armr.abt_r[2] = armr.spsr;
nkeynes@35	261	break;
nkeynes@35	262	case MODE_UND:
nkeynes@35	263	armr.und_r[0] = armr.r[13];
nkeynes@35	264	armr.und_r[1] = armr.r[14];
nkeynes@35	265	armr.und_r[2] = armr.spsr;
nkeynes@35	266	break;
nkeynes@35	267	case MODE_IRQ:
nkeynes@35	268	armr.irq_r[0] = armr.r[13];
nkeynes@35	269	armr.irq_r[1] = armr.r[14];
nkeynes@35	270	armr.irq_r[2] = armr.spsr;
nkeynes@35	271	break;
nkeynes@35	272	case MODE_FIQ:
nkeynes@35	273	armr.fiq_r[0] = armr.r[8];
nkeynes@35	274	armr.fiq_r[1] = armr.r[9];
nkeynes@35	275	armr.fiq_r[2] = armr.r[10];
nkeynes@35	276	armr.fiq_r[3] = armr.r[11];
nkeynes@35	277	armr.fiq_r[4] = armr.r[12];
nkeynes@35	278	armr.fiq_r[5] = armr.r[13];
nkeynes@35	279	armr.fiq_r[6] = armr.r[14];
nkeynes@35	280	armr.fiq_r[7] = armr.spsr;
nkeynes@35	281	armr.r[8] = armr.user_r[0];
nkeynes@35	282	armr.r[9] = armr.user_r[1];
nkeynes@35	283	armr.r[10] = armr.user_r[2];
nkeynes@35	284	armr.r[11] = armr.user_r[3];
nkeynes@35	285	armr.r[12] = armr.user_r[4];
nkeynes@35	286	break;
nkeynes@35	287	}
nkeynes@35	288
nkeynes@35	289	switch( targetMode ) {
nkeynes@35	290	case MODE_USER:
nkeynes@35	291	case MODE_SYS:
nkeynes@35	292	armr.r[13] = armr.user_r[5];
nkeynes@35	293	armr.r[14] = armr.user_r[6];
nkeynes@35	294	break;
nkeynes@35	295	case MODE_SVC:
nkeynes@35	296	armr.r[13] = armr.svc_r[0];
nkeynes@35	297	armr.r[14] = armr.svc_r[1];
nkeynes@35	298	armr.spsr = armr.svc_r[2];
nkeynes@35	299	break;
nkeynes@35	300	case MODE_ABT:
nkeynes@35	301	armr.r[13] = armr.abt_r[0];
nkeynes@35	302	armr.r[14] = armr.abt_r[1];
nkeynes@35	303	armr.spsr = armr.abt_r[2];
nkeynes@35	304	break;
nkeynes@35	305	case MODE_UND:
nkeynes@35	306	armr.r[13] = armr.und_r[0];
nkeynes@35	307	armr.r[14] = armr.und_r[1];
nkeynes@35	308	armr.spsr = armr.und_r[2];
nkeynes@35	309	break;
nkeynes@35	310	case MODE_IRQ:
nkeynes@35	311	armr.r[13] = armr.irq_r[0];
nkeynes@35	312	armr.r[14] = armr.irq_r[1];
nkeynes@35	313	armr.spsr = armr.irq_r[2];
nkeynes@35	314	break;
nkeynes@35	315	case MODE_FIQ:
nkeynes@35	316	armr.user_r[0] = armr.r[8];
nkeynes@35	317	armr.user_r[1] = armr.r[9];
nkeynes@35	318	armr.user_r[2] = armr.r[10];
nkeynes@35	319	armr.user_r[3] = armr.r[11];
nkeynes@35	320	armr.user_r[4] = armr.r[12];
nkeynes@35	321	armr.r[8] = armr.fiq_r[0];
nkeynes@35	322	armr.r[9] = armr.fiq_r[1];
nkeynes@35	323	armr.r[10] = armr.fiq_r[2];
nkeynes@35	324	armr.r[11] = armr.fiq_r[3];
nkeynes@35	325	armr.r[12] = armr.fiq_r[4];
nkeynes@35	326	armr.r[13] = armr.fiq_r[5];
nkeynes@35	327	armr.r[14] = armr.fiq_r[6];
nkeynes@35	328	armr.spsr = armr.fiq_r[7];
nkeynes@35	329	break;
nkeynes@35	330	}
nkeynes@35	331	}
nkeynes@35	332
nkeynes@5	333	/* Page references are as per ARM DDI 0100E (June 2000) */
nkeynes@2	334
nkeynes@11	335	#define MEM_READ_BYTE( addr ) arm_read_byte(addr)
nkeynes@11	336	#define MEM_READ_WORD( addr ) arm_read_word(addr)
nkeynes@11	337	#define MEM_READ_LONG( addr ) arm_read_long(addr)
nkeynes@11	338	#define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val)
nkeynes@11	339	#define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val)
nkeynes@11	340	#define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val)
nkeynes@2	341
nkeynes@5	342
nkeynes@5	343	#define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1)
nkeynes@5	344	#define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0)
nkeynes@5	345	#define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31)
nkeynes@5	346	#define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31)
nkeynes@5	347
nkeynes@7	348	#define PC armr.r[15]
nkeynes@2	349
nkeynes@5	350	/* Instruction fields */
nkeynes@5	351	#define COND(ir) (ir>>28)
nkeynes@5	352	#define GRP(ir) ((ir>>26)&0x03)
nkeynes@5	353	#define OPCODE(ir) ((ir>>20)&0x1F)
nkeynes@5	354	#define IFLAG(ir) (ir&0x02000000)
nkeynes@5	355	#define SFLAG(ir) (ir&0x00100000)
nkeynes@5	356	#define PFLAG(ir) (ir&0x01000000)
nkeynes@5	357	#define UFLAG(ir) (ir&0x00800000)
nkeynes@5	358	#define BFLAG(ir) (ir&0x00400000)
nkeynes@46	359	#define WFLAG(ir) (ir&0x00200000)
nkeynes@5	360	#define LFLAG(ir) SFLAG(ir)
nkeynes@5	361	#define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0))
nkeynes@37	362	#define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>12)&0x0F) == 0x0F ? 4 : 0))
nkeynes@5	363	#define RDn(ir) ((ir>>12)&0x0F)
nkeynes@37	364	#define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>8)&0x0F) == 0x0F ? 4 : 0))
nkeynes@37	365	#define RM(ir) (armr.r[(ir&0x0F)] + (((ir&0x0F) == 0x0F ? 4 : 0)) )
nkeynes@5	366	#define LRN(ir) armr.r[((ir>>16)&0x0F)]
nkeynes@5	367	#define LRD(ir) armr.r[((ir>>12)&0x0F)]
nkeynes@5	368	#define LRS(ir) armr.r[((ir>>8)&0x0F)]
nkeynes@5	369	#define LRM(ir) armr.r[(ir&0x0F)]
nkeynes@5	370
nkeynes@5	371	#define IMM8(ir) (ir&0xFF)
nkeynes@5	372	#define IMM12(ir) (ir&0xFFF)
nkeynes@7	373	#define SHIFTIMM(ir) ((ir>>7)&0x1F)
nkeynes@7	374	#define IMMROT(ir) ((ir>>7)&0x1E)
nkeynes@37	375	#define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
nkeynes@37	376	#define SIGNEXT24(n) ((n&0x00800000) ? (n\|0xFF000000) : (n&0x00FFFFFF))
nkeynes@5	377	#define SHIFT(ir) ((ir>>4)&0x07)
nkeynes@5	378	#define DISP24(ir) ((ir&0x00FFFFFF))
nkeynes@37	379	#define UNDEF(ir) do{ arm_raise_exception( EXC_UNDEFINED ); return TRUE; } while(0)
nkeynes@46	380	#define UNIMP(ir) do{ PC-=4; ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); dreamcast_stop(); return FALSE; }while(0)
nkeynes@7	381
nkeynes@37	382	/**
nkeynes@37	383	* Determine the value of the shift-operand for a data processing instruction,
nkeynes@37	384	* without determing a value for shift_C (optimized form for instructions that
nkeynes@37	385	* don't require shift_C ).
nkeynes@37	386	* @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
nkeynes@37	387	*/
nkeynes@5	388	static uint32_t arm_get_shift_operand( uint32_t ir )
nkeynes@5	389	{
nkeynes@5	390	uint32_t operand, tmp;
nkeynes@5	391	if( IFLAG(ir) == 0 ) {
nkeynes@5	392	operand = RM(ir);
nkeynes@5	393	switch(SHIFT(ir)) {
nkeynes@5	394	case 0: /* (Rm << imm) */
nkeynes@5	395	operand = operand << SHIFTIMM(ir);
nkeynes@5	396	break;
nkeynes@5	397	case 1: /* (Rm << Rs) */
nkeynes@5	398	tmp = RS(ir)&0xFF;
nkeynes@5	399	if( tmp > 31 ) operand = 0;
nkeynes@5	400	else operand = operand << tmp;
nkeynes@5	401	break;
nkeynes@5	402	case 2: /* (Rm >> imm) */
nkeynes@5	403	operand = operand >> SHIFTIMM(ir);
nkeynes@5	404	break;
nkeynes@5	405	case 3: /* (Rm >> Rs) */
nkeynes@5	406	tmp = RS(ir) & 0xFF;
nkeynes@5	407	if( tmp > 31 ) operand = 0;
nkeynes@5	408	else operand = operand >> ir;
nkeynes@5	409	break;
nkeynes@5	410	case 4: /* (Rm >>> imm) */
nkeynes@5	411	tmp = SHIFTIMM(ir);
nkeynes@5	412	if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
nkeynes@5	413	else operand = ((int32_t)operand) >> tmp;
nkeynes@5	414	break;
nkeynes@5	415	case 5: /* (Rm >>> Rs) */
nkeynes@5	416	tmp = RS(ir) & 0xFF;
nkeynes@5	417	if( tmp > 31 ) operand = ((int32_t)operand) >> 31;
nkeynes@5	418	else operand = ((int32_t)operand) >> tmp;
nkeynes@5	419	break;
nkeynes@5	420	case 6:
nkeynes@5	421	tmp = SHIFTIMM(ir);
nkeynes@5	422	if( tmp == 0 ) /* RRX aka rotate with carry */
nkeynes@7	423	operand = (operand >> 1) \| (armr.c<<31);
nkeynes@5	424	else
nkeynes@5	425	operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@5	426	break;
nkeynes@5	427	case 7:
nkeynes@5	428	tmp = RS(ir)&0x1F;
nkeynes@5	429	operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@5	430	break;
nkeynes@5	431	}
nkeynes@5	432	} else {
nkeynes@5	433	operand = IMM8(ir);
nkeynes@5	434	tmp = IMMROT(ir);
nkeynes@5	435	operand = ROTATE_RIGHT_LONG(operand, tmp);
nkeynes@5	436	}
nkeynes@5	437	return operand;
nkeynes@5	438	}
nkeynes@5	439
nkeynes@5	440	/**
nkeynes@37	441	* Determine the value of the shift-operand for a data processing instruction,
nkeynes@37	442	* and set armr.shift_c accordingly.
nkeynes@37	443	* @see s5.1 Addressing Mode 1 - Data-processing operands (p A5-2, 218)
nkeynes@5	444	*/
nkeynes@5	445	static uint32_t arm_get_shift_operand_s( uint32_t ir )
nkeynes@5	446	{
nkeynes@5	447	uint32_t operand, tmp;
nkeynes@5	448	if( IFLAG(ir) == 0 ) {
nkeynes@5	449	operand = RM(ir);
nkeynes@5	450	switch(SHIFT(ir)) {
nkeynes@5	451	case 0: /* (Rm << imm) */
nkeynes@5	452	tmp = SHIFTIMM(ir);
nkeynes@5	453	if( tmp == 0 ) { /* Rm */
nkeynes@5	454	armr.shift_c = armr.c;
nkeynes@5	455	} else { /* Rm << imm */
nkeynes@5	456	armr.shift_c = (operand >> (32-tmp)) & 0x01;
nkeynes@5	457	operand = operand << tmp;
nkeynes@5	458	}
nkeynes@5	459	break;
nkeynes@5	460	case 1: /* (Rm << Rs) */
nkeynes@5	461	tmp = RS(ir)&0xFF;
nkeynes@5	462	if( tmp == 0 ) {
nkeynes@5	463	armr.shift_c = armr.c;
nkeynes@5	464	} else {
nkeynes@5	465	if( tmp <= 32 )
nkeynes@5	466	armr.shift_c = (operand >> (32-tmp)) & 0x01;
nkeynes@5	467	else armr.shift_c = 0;
nkeynes@5	468	if( tmp < 32 )
nkeynes@5	469	operand = operand << tmp;
nkeynes@5	470	else operand = 0;
nkeynes@5	471	}
nkeynes@5	472	break;
nkeynes@5	473	case 2: /* (Rm >> imm) */
nkeynes@5	474	tmp = SHIFTIMM(ir);
nkeynes@5	475	if( tmp == 0 ) {
nkeynes@5	476	armr.shift_c = operand >> 31;
nkeynes@5	477	operand = 0;
nkeynes@5	478	} else {
nkeynes@5	479	armr.shift_c = (operand >> (tmp-1)) & 0x01;
nkeynes@5	480	operand = RM(ir) >> tmp;
nkeynes@5	481	}
nkeynes@5	482	break;
nkeynes@5	483	case 3: /* (Rm >> Rs) */
nkeynes@5	484	tmp = RS(ir) & 0xFF;
nkeynes@5	485	if( tmp == 0 ) {
nkeynes@5	486	armr.shift_c = armr.c;
nkeynes@5	487	} else {
nkeynes@5	488	if( tmp <= 32 )
nkeynes@5	489	armr.shift_c = (operand >> (tmp-1))&0x01;
nkeynes@5	490	else armr.shift_c = 0;
nkeynes@5	491	if( tmp < 32 )
nkeynes@5	492	operand = operand >> tmp;
nkeynes@5	493	else operand = 0;
nkeynes@5	494	}
nkeynes@5	495	break;
nkeynes@5	496	case 4: /* (Rm >>> imm) */
nkeynes@5	497	tmp = SHIFTIMM(ir);
nkeynes@5	498	if( tmp == 0 ) {
nkeynes@5	499	armr.shift_c = operand >> 31;
nkeynes@5	500	operand = -armr.shift_c;
nkeynes@5	501	} else {
nkeynes@5	502	armr.shift_c = (operand >> (tmp-1)) & 0x01;
nkeynes@5	503	operand = ((int32_t)operand) >> tmp;
nkeynes@5	504	}
nkeynes@5	505	break;
nkeynes@5	506	case 5: /* (Rm >>> Rs) */
nkeynes@5	507	tmp = RS(ir) & 0xFF;
nkeynes@5	508	if( tmp == 0 ) {
nkeynes@5	509	armr.shift_c = armr.c;
nkeynes@5	510	} else {
nkeynes@5	511	if( tmp < 32 ) {
nkeynes@5	512	armr.shift_c = (operand >> (tmp-1))&0x01;
nkeynes@5	513	operand = ((int32_t)operand) >> tmp;
nkeynes@5	514	} else {
nkeynes@5	515	armr.shift_c = operand >> 31;
nkeynes@5	516	operand = ((int32_t)operand) >> 31;
nkeynes@5	517	}
nkeynes@5	518	}
nkeynes@5	519	break;
nkeynes@5	520	case 6:
nkeynes@5	521	tmp = SHIFTIMM(ir);
nkeynes@5	522	if( tmp == 0 ) { /* RRX aka rotate with carry */
nkeynes@5	523	armr.shift_c = operand&0x01;
nkeynes@7	524	operand = (operand >> 1) \| (armr.c<<31);
nkeynes@5	525	} else {
nkeynes@5	526	armr.shift_c = operand>>(tmp-1);
nkeynes@5	527	operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@5	528	}
nkeynes@5	529	break;
nkeynes@5	530	case 7:
nkeynes@5	531	tmp = RS(ir)&0xFF;
nkeynes@5	532	if( tmp == 0 ) {
nkeynes@5	533	armr.shift_c = armr.c;
nkeynes@5	534	} else {
nkeynes@5	535	tmp &= 0x1F;
nkeynes@5	536	if( tmp == 0 ) {
nkeynes@5	537	armr.shift_c = operand>>31;
nkeynes@5	538	} else {
nkeynes@5	539	armr.shift_c = (operand>>(tmp-1))&0x1;
nkeynes@5	540	operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@5	541	}
nkeynes@5	542	}
nkeynes@5	543	break;
nkeynes@5	544	}
nkeynes@5	545	} else {
nkeynes@5	546	operand = IMM8(ir);
nkeynes@5	547	tmp = IMMROT(ir);
nkeynes@5	548	if( tmp == 0 ) {
nkeynes@5	549	armr.shift_c = armr.c;
nkeynes@5	550	} else {
nkeynes@5	551	operand = ROTATE_RIGHT_LONG(operand, tmp);
nkeynes@5	552	armr.shift_c = operand>>31;
nkeynes@5	553	}
nkeynes@5	554	}
nkeynes@5	555	return operand;
nkeynes@5	556	}
nkeynes@5	557
nkeynes@5	558	/**
nkeynes@5	559	* Another variant of the shifter code for index-based memory addressing.
nkeynes@5	560	* Distinguished by the fact that it doesn't support register shifts, and
nkeynes@5	561	* ignores the I flag (WTF do the load/store instructions use the I flag to
nkeynes@5	562	* mean the _exact opposite_ of what it means for the data processing
nkeynes@5	563	* instructions ???)
nkeynes@5	564	*/
nkeynes@5	565	static uint32_t arm_get_address_index( uint32_t ir )
nkeynes@5	566	{
nkeynes@5	567	uint32_t operand = RM(ir);
nkeynes@7	568	uint32_t tmp;
nkeynes@7	569
nkeynes@5	570	switch(SHIFT(ir)) {
nkeynes@5	571	case 0: /* (Rm << imm) */
nkeynes@5	572	operand = operand << SHIFTIMM(ir);
nkeynes@5	573	break;
nkeynes@5	574	case 2: /* (Rm >> imm) */
nkeynes@5	575	operand = operand >> SHIFTIMM(ir);
nkeynes@5	576	break;
nkeynes@5	577	case 4: /* (Rm >>> imm) */
nkeynes@5	578	tmp = SHIFTIMM(ir);
nkeynes@5	579	if( tmp == 0 ) operand = ((int32_t)operand) >> 31;
nkeynes@5	580	else operand = ((int32_t)operand) >> tmp;
nkeynes@5	581	break;
nkeynes@5	582	case 6:
nkeynes@5	583	tmp = SHIFTIMM(ir);
nkeynes@5	584	if( tmp == 0 ) /* RRX aka rotate with carry */
nkeynes@7	585	operand = (operand >> 1) \| (armr.c<<31);
nkeynes@5	586	else
nkeynes@5	587	operand = ROTATE_RIGHT_LONG(operand,tmp);
nkeynes@5	588	break;
nkeynes@5	589	default: UNIMP(ir);
nkeynes@5	590	}
nkeynes@5	591	return operand;
nkeynes@5	592	}
nkeynes@5	593
nkeynes@37	594	/**
nkeynes@37	595	* Determine the address operand of a load/store instruction, including
nkeynes@37	596	* applying any pre/post adjustments to the address registers.
nkeynes@37	597	* @see s5.2 Addressing Mode 2 - Load and Store Word or Unsigned Byte
nkeynes@37	598	* @param The instruction word.
nkeynes@37	599	* @return The calculated address
nkeynes@37	600	*/
nkeynes@5	601	static uint32_t arm_get_address_operand( uint32_t ir )
nkeynes@5	602	{
nkeynes@5	603	uint32_t addr;
nkeynes@5	604
nkeynes@5	605	/* I P U . W */
nkeynes@5	606	switch( (ir>>21)&0x1D ) {
nkeynes@5	607	case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */
nkeynes@5	608	case 1:
nkeynes@5	609	addr = RN(ir);
nkeynes@7	610	LRN(ir) = addr - IMM12(ir);
nkeynes@5	611	break;
nkeynes@5	612	case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */
nkeynes@5	613	case 5:
nkeynes@5	614	addr = RN(ir);
nkeynes@7	615	LRN(ir) = addr + IMM12(ir);
nkeynes@5	616	break;
nkeynes@5	617	case 8: /* Rn - imm offset [5.2.2 A5-20] */
nkeynes@5	618	addr = RN(ir) - IMM12(ir);
nkeynes@5	619	break;
nkeynes@5	620	case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */
nkeynes@5	621	addr = RN(ir) - IMM12(ir);
nkeynes@7	622	LRN(ir) = addr;
nkeynes@5	623	break;
nkeynes@5	624	case 12: /* Rn + imm offset [5.2.2 A5-20] */
nkeynes@5	625	addr = RN(ir) + IMM12(ir);
nkeynes@5	626	break;
nkeynes@5	627	case 13: /* Rn += imm offset [5.2.5 A5-24 ] */
nkeynes@5	628	addr = RN(ir) + IMM12(ir);
nkeynes@7	629	LRN(ir) = addr;
nkeynes@5	630	break;
nkeynes@5	631	case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */
nkeynes@5	632	case 17:
nkeynes@5	633	addr = RN(ir);
nkeynes@7	634	LRN(ir) = addr - arm_get_address_index(ir);
nkeynes@5	635	break;
nkeynes@5	636	case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */
nkeynes@5	637	case 21:
nkeynes@5	638	addr = RN(ir);
nkeynes@7	639	LRN(ir) = addr - arm_get_address_index(ir);
nkeynes@5	640	break;
nkeynes@5	641	case 24: /* Rn - Rm [5.2.4 A5-23] */
nkeynes@5	642	addr = RN(ir) - arm_get_address_index(ir);
nkeynes@5	643	break;
nkeynes@5	644	case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */
nkeynes@5	645	addr = RN(ir) - arm_get_address_index(ir);
nkeynes@7	646	LRN(ir) = addr;
nkeynes@5	647	break;
nkeynes@5	648	case 28: /* Rn + Rm [5.2.4 A5-23] */
nkeynes@5	649	addr = RN(ir) + arm_get_address_index(ir);
nkeynes@5	650	break;
nkeynes@5	651	case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */
nkeynes@5	652	addr = RN(ir) + arm_get_address_index(ir);
nkeynes@7	653	LRN(ir) = addr;
nkeynes@5	654	break;
nkeynes@5	655	}
nkeynes@5	656	return addr;
nkeynes@5	657	}
nkeynes@5	658
nkeynes@30	659	gboolean arm_execute_instruction( void )
nkeynes@2	660	{
nkeynes@37	661	uint32_t pc = PC;
nkeynes@37	662	uint32_t ir = MEM_READ_LONG(pc);
nkeynes@49	663	uint32_t operand, operand2, tmp, tmp2, cond;
nkeynes@2	664
nkeynes@51	665	tmp = armr.int_pending & armr.cpsr;
nkeynes@51	666	if( tmp ) {
nkeynes@51	667	if( tmp & CPSR_F ) {
nkeynes@51	668	arm_raise_exception( EXC_FAST_IRQ );
nkeynes@51	669	} else {
nkeynes@51	670	arm_raise_exception( EXC_IRQ );
nkeynes@51	671	}
nkeynes@51	672	}
nkeynes@51	673
nkeynes@37	674	pc += 4;
nkeynes@37	675	PC = pc;
nkeynes@2	676
nkeynes@37	677	/**
nkeynes@37	678	* Check the condition bits first - if the condition fails return
nkeynes@37	679	* immediately without actually looking at the rest of the instruction.
nkeynes@37	680	*/
nkeynes@37	681	switch( COND(ir) ) {
nkeynes@37	682	case 0: /* EQ */
nkeynes@37	683	cond = armr.z;
nkeynes@37	684	break;
nkeynes@37	685	case 1: /* NE */
nkeynes@37	686	cond = !armr.z;
nkeynes@37	687	break;
nkeynes@37	688	case 2: /* CS/HS */
nkeynes@37	689	cond = armr.c;
nkeynes@37	690	break;
nkeynes@37	691	case 3: /* CC/LO */
nkeynes@37	692	cond = !armr.c;
nkeynes@37	693	break;
nkeynes@37	694	case 4: /* MI */
nkeynes@37	695	cond = armr.n;
nkeynes@37	696	break;
nkeynes@37	697	case 5: /* PL */
nkeynes@37	698	cond = !armr.n;
nkeynes@37	699	break;
nkeynes@37	700	case 6: /* VS */
nkeynes@37	701	cond = armr.v;
nkeynes@37	702	break;
nkeynes@37	703	case 7: /* VC */
nkeynes@37	704	cond = !armr.v;
nkeynes@37	705	break;
nkeynes@37	706	case 8: /* HI */
nkeynes@37	707	cond = armr.c && !armr.z;
nkeynes@37	708	break;
nkeynes@37	709	case 9: /* LS */
nkeynes@37	710	cond = (!armr.c) \|\| armr.z;
nkeynes@37	711	break;
nkeynes@37	712	case 10: /* GE */
nkeynes@37	713	cond = (armr.n == armr.v);
nkeynes@37	714	break;
nkeynes@37	715	case 11: /* LT */
nkeynes@37	716	cond = (armr.n != armr.v);
nkeynes@37	717	break;
nkeynes@37	718	case 12: /* GT */
nkeynes@37	719	cond = (!armr.z) && (armr.n == armr.v);
nkeynes@37	720	break;
nkeynes@37	721	case 13: /* LE */
nkeynes@37	722	cond = armr.z \|\| (armr.n != armr.v);
nkeynes@37	723	break;
nkeynes@37	724	case 14: /* AL */
nkeynes@37	725	cond = 1;
nkeynes@37	726	break;
nkeynes@37	727	case 15: /* (NV) */
nkeynes@37	728	cond = 0;
nkeynes@37	729	UNDEF(ir);
nkeynes@37	730	}
nkeynes@37	731	if( !cond )
nkeynes@37	732	return TRUE;
nkeynes@5	733
nkeynes@37	734	/**
nkeynes@37	735	* Condition passed, now for the actual instructions...
nkeynes@37	736	*/
nkeynes@37	737	switch( GRP(ir) ) {
nkeynes@37	738	case 0:
nkeynes@37	739	if( (ir & 0x0D900000) == 0x01000000 ) {
nkeynes@37	740	/* Instructions that aren't actual data processing even though
nkeynes@37	741	* they sit in the DP instruction block.
nkeynes@37	742	*/
nkeynes@37	743	switch( ir & 0x0FF000F0 ) {
nkeynes@37	744	case 0x01200010: /* BX Rd */
nkeynes@37	745	armr.t = ir & 0x01;
nkeynes@37	746	armr.r[15] = RM(ir) & 0xFFFFFFFE;
nkeynes@37	747	break;
nkeynes@37	748	case 0x01000000: /* MRS Rd, CPSR */
nkeynes@37	749	LRD(ir) = arm_get_cpsr();
nkeynes@37	750	break;
nkeynes@37	751	case 0x01400000: /* MRS Rd, SPSR */
nkeynes@37	752	LRD(ir) = armr.spsr;
nkeynes@37	753	break;
nkeynes@37	754	case 0x01200000: /* MSR CPSR, Rd */
nkeynes@37	755	arm_set_cpsr( RM(ir), ir );
nkeynes@37	756	break;
nkeynes@37	757	case 0x01600000: /* MSR SPSR, Rd */
nkeynes@37	758	arm_set_spsr( RM(ir), ir );
nkeynes@37	759	break;
nkeynes@37	760	case 0x03200000: /* MSR CPSR, imm */
nkeynes@37	761	arm_set_cpsr( ROTIMM12(ir), ir );
nkeynes@37	762	break;
nkeynes@37	763	case 0x03600000: /* MSR SPSR, imm */
nkeynes@37	764	arm_set_spsr( ROTIMM12(ir), ir );
nkeynes@37	765	break;
nkeynes@37	766	default:
nkeynes@37	767	UNIMP(ir);
nkeynes@37	768	}
nkeynes@37	769	} else if( (ir & 0x0E000090) == 0x00000090 ) {
nkeynes@37	770	/* Neither are these */
nkeynes@49	771	UNIMP(ir);
nkeynes@37	772	switch( (ir>>5)&0x03 ) {
nkeynes@37	773	case 0:
nkeynes@37	774	/* Arithmetic extension area */
nkeynes@37	775	switch(OPCODE(ir)) {
nkeynes@37	776	case 0: /* MUL */
nkeynes@51	777	LRN(ir) = RM(ir) * RS(ir);
nkeynes@37	778	break;
nkeynes@37	779	case 1: /* MULS */
nkeynes@51	780	tmp = RM(ir) * RS(ir);
nkeynes@51	781	LRN(ir) = tmp;
nkeynes@51	782	armr.n = tmp>>31;
nkeynes@51	783	armr.z = (tmp == 0);
nkeynes@37	784	break;
nkeynes@37	785	case 2: /* MLA */
nkeynes@51	786	LRN(ir) = RM(ir) * RS(ir) + RD(ir);
nkeynes@37	787	break;
nkeynes@37	788	case 3: /* MLAS */
nkeynes@51	789	tmp = RM(ir) * RS(ir) + RD(ir);
nkeynes@51	790	LRN(ir) = tmp;
nkeynes@51	791	armr.n = tmp>>31;
nkeynes@51	792	armr.z = (tmp == 0);
nkeynes@37	793	break;
nkeynes@37	794	case 8: /* UMULL */
nkeynes@37	795	break;
nkeynes@37	796	case 9: /* UMULLS */
nkeynes@37	797	break;
nkeynes@37	798	case 10: /* UMLAL */
nkeynes@37	799	break;
nkeynes@37	800	case 11: /* UMLALS */
nkeynes@37	801	break;
nkeynes@37	802	case 12: /* SMULL */
nkeynes@37	803	break;
nkeynes@37	804	case 13: /* SMULLS */
nkeynes@37	805	break;
nkeynes@37	806	case 14: /* SMLAL */
nkeynes@37	807	break;
nkeynes@37	808	case 15: /* SMLALS */
nkeynes@37	809	break;
nkeynes@37	810	case 16: /* SWP */
nkeynes@51	811	tmp = arm_read_long( RN(ir) );
nkeynes@51	812	switch( RN(ir) & 0x03 ) {
nkeynes@51	813	case 1:
nkeynes@51	814	tmp = ROTATE_RIGHT_LONG(tmp, 8);
nkeynes@51	815	break;
nkeynes@51	816	case 2:
nkeynes@51	817	tmp = ROTATE_RIGHT_LONG(tmp, 16);
nkeynes@51	818	break;
nkeynes@51	819	case 3:
nkeynes@51	820	tmp = ROTATE_RIGHT_LONG(tmp, 24);
nkeynes@51	821	break;
nkeynes@51	822	}
nkeynes@51	823	arm_write_long( RN(ir), RM(ir) );
nkeynes@51	824	LRD(ir) = tmp;
nkeynes@37	825	break;
nkeynes@37	826	case 20: /* SWPB */
nkeynes@51	827	tmp = arm_read_byte( RN(ir) );
nkeynes@51	828	arm_write_byte( RN(ir), RM(ir) );
nkeynes@51	829	LRD(ir) = tmp;
nkeynes@37	830	break;
nkeynes@37	831	default:
nkeynes@37	832	UNIMP(ir);
nkeynes@5	833	}
nkeynes@5	834	break;
nkeynes@37	835	case 1:
nkeynes@37	836	if( LFLAG(ir) ) {
nkeynes@37	837	/* LDRH */
nkeynes@37	838	} else {
nkeynes@37	839	/* STRH */
nkeynes@37	840	}
nkeynes@49	841	UNIMP(ir);
nkeynes@5	842	break;
nkeynes@37	843	case 2:
nkeynes@37	844	if( LFLAG(ir) ) {
nkeynes@37	845	/* LDRSB */
nkeynes@37	846	} else {
nkeynes@37	847	}
nkeynes@49	848	UNIMP(ir);
nkeynes@5	849	break;
nkeynes@37	850	case 3:
nkeynes@37	851	if( LFLAG(ir) ) {
nkeynes@37	852	/* LDRSH */
nkeynes@37	853	} else {
nkeynes@37	854	}
nkeynes@49	855	UNIMP(ir);
nkeynes@5	856	break;
nkeynes@37	857	}
nkeynes@37	858	} else {
nkeynes@37	859	/* Data processing */
nkeynes@37	860
nkeynes@37	861	switch(OPCODE(ir)) {
nkeynes@37	862	case 0: /* AND Rd, Rn, operand */
nkeynes@37	863	LRD(ir) = RN(ir) & arm_get_shift_operand(ir);
nkeynes@37	864	break;
nkeynes@37	865	case 1: /* ANDS Rd, Rn, operand */
nkeynes@37	866	operand = arm_get_shift_operand_s(ir) & RN(ir);
nkeynes@37	867	LRD(ir) = operand;
nkeynes@37	868	if( RDn(ir) == 15 ) {
nkeynes@37	869	arm_restore_cpsr();
nkeynes@37	870	} else {
nkeynes@37	871	armr.n = operand>>31;
nkeynes@37	872	armr.z = (operand == 0);
nkeynes@37	873	armr.c = armr.shift_c;
nkeynes@37	874	}
nkeynes@37	875	break;
nkeynes@37	876	case 2: /* EOR Rd, Rn, operand */
nkeynes@37	877	LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir);
nkeynes@37	878	break;
nkeynes@37	879	case 3: /* EORS Rd, Rn, operand */
nkeynes@37	880	operand = arm_get_shift_operand_s(ir) ^ RN(ir);
nkeynes@37	881	LRD(ir) = operand;
nkeynes@37	882	if( RDn(ir) == 15 ) {
nkeynes@37	883	arm_restore_cpsr();
nkeynes@37	884	} else {
nkeynes@37	885	armr.n = operand>>31;
nkeynes@37	886	armr.z = (operand == 0);
nkeynes@37	887	armr.c = armr.shift_c;
nkeynes@37	888	}
nkeynes@37	889	break;
nkeynes@37	890	case 4: /* SUB Rd, Rn, operand */
nkeynes@37	891	LRD(ir) = RN(ir) - arm_get_shift_operand(ir);
nkeynes@37	892	break;
nkeynes@37	893	case 5: /* SUBS Rd, Rn, operand */
nkeynes@37	894	operand = RN(ir);
nkeynes@37	895	operand2 = arm_get_shift_operand(ir);
nkeynes@37	896	tmp = operand - operand2;
nkeynes@37	897	LRD(ir) = tmp;
nkeynes@37	898	if( RDn(ir) == 15 ) {
nkeynes@37	899	arm_restore_cpsr();
nkeynes@37	900	} else {
nkeynes@37	901	armr.n = tmp>>31;
nkeynes@37	902	armr.z = (tmp == 0);
nkeynes@37	903	armr.c = IS_NOTBORROW(tmp,operand,operand2);
nkeynes@37	904	armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
nkeynes@37	905	}
nkeynes@37	906	break;
nkeynes@37	907	case 6: /* RSB Rd, operand, Rn */
nkeynes@37	908	LRD(ir) = arm_get_shift_operand(ir) - RN(ir);
nkeynes@37	909	break;
nkeynes@37	910	case 7: /* RSBS Rd, operand, Rn */
nkeynes@37	911	operand = arm_get_shift_operand(ir);
nkeynes@37	912	operand2 = RN(ir);
nkeynes@37	913	tmp = operand - operand2;
nkeynes@37	914	LRD(ir) = tmp;
nkeynes@37	915	if( RDn(ir) == 15 ) {
nkeynes@37	916	arm_restore_cpsr();
nkeynes@37	917	} else {
nkeynes@37	918	armr.n = tmp>>31;
nkeynes@37	919	armr.z = (tmp == 0);
nkeynes@37	920	armr.c = IS_NOTBORROW(tmp,operand,operand2);
nkeynes@37	921	armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
nkeynes@37	922	}
nkeynes@37	923	break;
nkeynes@37	924	case 8: /* ADD Rd, Rn, operand */
nkeynes@37	925	LRD(ir) = RN(ir) + arm_get_shift_operand(ir);
nkeynes@37	926	break;
nkeynes@37	927	case 9: /* ADDS Rd, Rn, operand */
nkeynes@37	928	operand = arm_get_shift_operand(ir);
nkeynes@37	929	operand2 = RN(ir);
nkeynes@37	930	tmp = operand + operand2;
nkeynes@37	931	LRD(ir) = tmp;
nkeynes@37	932	if( RDn(ir) == 15 ) {
nkeynes@37	933	arm_restore_cpsr();
nkeynes@37	934	} else {
nkeynes@37	935	armr.n = tmp>>31;
nkeynes@37	936	armr.z = (tmp == 0);
nkeynes@37	937	armr.c = IS_CARRY(tmp,operand,operand2);
nkeynes@37	938	armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
nkeynes@37	939	}
nkeynes@37	940	break;
nkeynes@37	941	case 10: /* ADC */
nkeynes@49	942	LRD(ir) = RN(ir) + arm_get_shift_operand(ir) +
nkeynes@49	943	(armr.c ? 1 : 0);
nkeynes@49	944	break;
nkeynes@37	945	case 11: /* ADCS */
nkeynes@49	946	operand = arm_get_shift_operand(ir);
nkeynes@49	947	operand2 = RN(ir);
nkeynes@49	948	tmp = operand + operand2;
nkeynes@49	949	tmp2 = tmp + armr.c ? 1 : 0;
nkeynes@49	950	LRD(ir) = tmp2;
nkeynes@49	951	if( RDn(ir) == 15 ) {
nkeynes@49	952	arm_restore_cpsr();
nkeynes@49	953	} else {
nkeynes@49	954	armr.n = tmp >> 31;
nkeynes@49	955	armr.z = (tmp == 0 );
nkeynes@49	956	armr.c = IS_CARRY(tmp,operand,operand2) \|\|
nkeynes@49	957	(tmp2 < tmp);
nkeynes@49	958	armr.v = IS_ADDOVERFLOW(tmp,operand, operand2) \|\|
nkeynes@49	959	((tmp&0x80000000) != (tmp2&0x80000000));
nkeynes@49	960	}
nkeynes@49	961	break;
nkeynes@37	962	case 12: /* SBC */
nkeynes@49	963	LRD(ir) = RN(ir) - arm_get_shift_operand(ir) -
nkeynes@49	964	(armr.c ? 0 : 1);
nkeynes@49	965	break;
nkeynes@37	966	case 13: /* SBCS */
nkeynes@49	967	operand = RN(ir);
nkeynes@49	968	operand2 = arm_get_shift_operand(ir);
nkeynes@49	969	tmp = operand - operand2;
nkeynes@49	970	tmp2 = tmp - (armr.c ? 0 : 1);
nkeynes@49	971	if( RDn(ir) == 15 ) {
nkeynes@49	972	arm_restore_cpsr();
nkeynes@49	973	} else {
nkeynes@49	974	armr.n = tmp >> 31;
nkeynes@49	975	armr.z = (tmp == 0 );
nkeynes@49	976	armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
nkeynes@49	977	(tmp2<tmp);
nkeynes@49	978	armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) \|\|
nkeynes@49	979	((tmp&0x80000000) != (tmp2&0x80000000));
nkeynes@49	980	}
nkeynes@49	981	break;
nkeynes@37	982	case 14: /* RSC */
nkeynes@49	983	LRD(ir) = arm_get_shift_operand(ir) - RN(ir) -
nkeynes@49	984	(armr.c ? 0 : 1);
nkeynes@49	985	break;
nkeynes@37	986	case 15: /* RSCS */
nkeynes@49	987	operand = arm_get_shift_operand(ir);
nkeynes@49	988	operand2 = RN(ir);
nkeynes@49	989	tmp = operand - operand2;
nkeynes@49	990	tmp2 = tmp - (armr.c ? 0 : 1);
nkeynes@49	991	if( RDn(ir) == 15 ) {
nkeynes@49	992	arm_restore_cpsr();
nkeynes@49	993	} else {
nkeynes@49	994	armr.n = tmp >> 31;
nkeynes@49	995	armr.z = (tmp == 0 );
nkeynes@49	996	armr.c = IS_NOTBORROW(tmp,operand,operand2) &&
nkeynes@49	997	(tmp2<tmp);
nkeynes@49	998	armr.v = IS_SUBOVERFLOW(tmp,operand,operand2) \|\|
nkeynes@49	999	((tmp&0x80000000) != (tmp2&0x80000000));
nkeynes@49	1000	}
nkeynes@37	1001	break;
nkeynes@37	1002	case 17: /* TST Rn, operand */
nkeynes@37	1003	operand = arm_get_shift_operand_s(ir) & RN(ir);
nkeynes@37	1004	armr.n = operand>>31;
nkeynes@37	1005	armr.z = (operand == 0);
nkeynes@37	1006	armr.c = armr.shift_c;
nkeynes@37	1007	break;
nkeynes@37	1008	case 19: /* TEQ Rn, operand */
nkeynes@37	1009	operand = arm_get_shift_operand_s(ir) ^ RN(ir);
nkeynes@37	1010	armr.n = operand>>31;
nkeynes@37	1011	armr.z = (operand == 0);
nkeynes@37	1012	armr.c = armr.shift_c;
nkeynes@37	1013	break;
nkeynes@37	1014	case 21: /* CMP Rn, operand */
nkeynes@37	1015	operand = RN(ir);
nkeynes@37	1016	operand2 = arm_get_shift_operand(ir);
nkeynes@37	1017	tmp = operand - operand2;
nkeynes@37	1018	armr.n = tmp>>31;
nkeynes@37	1019	armr.z = (tmp == 0);
nkeynes@37	1020	armr.c = IS_NOTBORROW(tmp,operand,operand2);
nkeynes@37	1021	armr.v = IS_SUBOVERFLOW(tmp,operand,operand2);
nkeynes@37	1022	break;
nkeynes@37	1023	case 23: /* CMN Rn, operand */
nkeynes@37	1024	operand = RN(ir);
nkeynes@37	1025	operand2 = arm_get_shift_operand(ir);
nkeynes@37	1026	tmp = operand + operand2;
nkeynes@37	1027	armr.n = tmp>>31;
nkeynes@37	1028	armr.z = (tmp == 0);
nkeynes@37	1029	armr.c = IS_CARRY(tmp,operand,operand2);
nkeynes@37	1030	armr.v = IS_ADDOVERFLOW(tmp,operand,operand2);
nkeynes@37	1031	break;
nkeynes@37	1032	case 24: /* ORR Rd, Rn, operand */
nkeynes@37	1033	LRD(ir) = RN(ir) \| arm_get_shift_operand(ir);
nkeynes@37	1034	break;
nkeynes@37	1035	case 25: /* ORRS Rd, Rn, operand */
nkeynes@37	1036	operand = arm_get_shift_operand_s(ir) \| RN(ir);
nkeynes@37	1037	LRD(ir) = operand;
nkeynes@37	1038	if( RDn(ir) == 15 ) {
nkeynes@37	1039	arm_restore_cpsr();
nkeynes@37	1040	} else {
nkeynes@37	1041	armr.n = operand>>31;
nkeynes@37	1042	armr.z = (operand == 0);
nkeynes@37	1043	armr.c = armr.shift_c;
nkeynes@37	1044	}
nkeynes@37	1045	break;
nkeynes@37	1046	case 26: /* MOV Rd, operand */
nkeynes@37	1047	LRD(ir) = arm_get_shift_operand(ir);
nkeynes@37	1048	break;
nkeynes@37	1049	case 27: /* MOVS Rd, operand */
nkeynes@37	1050	operand = arm_get_shift_operand_s(ir);
nkeynes@37	1051	LRD(ir) = operand;
nkeynes@37	1052	if( RDn(ir) == 15 ) {
nkeynes@37	1053	arm_restore_cpsr();
nkeynes@37	1054	} else {
nkeynes@37	1055	armr.n = operand>>31;
nkeynes@37	1056	armr.z = (operand == 0);
nkeynes@37	1057	armr.c = armr.shift_c;
nkeynes@37	1058	}
nkeynes@37	1059	break;
nkeynes@37	1060	case 28: /* BIC Rd, Rn, operand */
nkeynes@37	1061	LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir));
nkeynes@37	1062	break;
nkeynes@37	1063	case 29: /* BICS Rd, Rn, operand */
nkeynes@37	1064	operand = RN(ir) & (~arm_get_shift_operand_s(ir));
nkeynes@37	1065	LRD(ir) = operand;
nkeynes@37	1066	if( RDn(ir) == 15 ) {
nkeynes@37	1067	arm_restore_cpsr();
nkeynes@37	1068	} else {
nkeynes@37	1069	armr.n = operand>>31;
nkeynes@37	1070	armr.z = (operand == 0);
nkeynes@37	1071	armr.c = armr.shift_c;
nkeynes@37	1072	}
nkeynes@37	1073	break;
nkeynes@37	1074	case 30: /* MVN Rd, operand */
nkeynes@37	1075	LRD(ir) = ~arm_get_shift_operand(ir);
nkeynes@37	1076	break;
nkeynes@37	1077	case 31: /* MVNS Rd, operand */
nkeynes@37	1078	operand = ~arm_get_shift_operand_s(ir);
nkeynes@37	1079	LRD(ir) = operand;
nkeynes@37	1080	if( RDn(ir) == 15 ) {
nkeynes@37	1081	arm_restore_cpsr();
nkeynes@37	1082	} else {
nkeynes@37	1083	armr.n = operand>>31;
nkeynes@37	1084	armr.z = (operand == 0);
nkeynes@37	1085	armr.c = armr.shift_c;
nkeynes@37	1086	}
nkeynes@37	1087	break;
nkeynes@37	1088	default:
nkeynes@37	1089	UNIMP(ir);
nkeynes@37	1090	}
nkeynes@5	1091	}
nkeynes@37	1092	break;
nkeynes@37	1093	case 1: /* Load/store */
nkeynes@37	1094	operand = arm_get_address_operand(ir);
nkeynes@37	1095	switch( (ir>>20)&0x17 ) {
nkeynes@37	1096	case 0: case 16: case 18: /* STR Rd, address */
nkeynes@37	1097	arm_write_long( operand, RD(ir) );
nkeynes@37	1098	break;
nkeynes@37	1099	case 1: case 17: case 19: /* LDR Rd, address */
nkeynes@37	1100	LRD(ir) = arm_read_long(operand);
nkeynes@37	1101	break;
nkeynes@37	1102	case 2: /* STRT Rd, address */
nkeynes@37	1103	arm_write_long_user( operand, RD(ir) );
nkeynes@37	1104	break;
nkeynes@37	1105	case 3: /* LDRT Rd, address */
nkeynes@37	1106	LRD(ir) = arm_read_long_user( operand );
nkeynes@37	1107	break;
nkeynes@37	1108	case 4: case 20: case 22: /* STRB Rd, address */
nkeynes@37	1109	arm_write_byte( operand, RD(ir) );
nkeynes@37	1110	break;
nkeynes@37	1111	case 5: case 21: case 23: /* LDRB Rd, address */
nkeynes@37	1112	LRD(ir) = arm_read_byte( operand );
nkeynes@37	1113	break;
nkeynes@37	1114	case 6: /* STRBT Rd, address */
nkeynes@37	1115	arm_write_byte_user( operand, RD(ir) );
nkeynes@37	1116	break;
nkeynes@37	1117	case 7: /* LDRBT Rd, address */
nkeynes@37	1118	LRD(ir) = arm_read_byte_user( operand );
nkeynes@37	1119	break;
nkeynes@37	1120	}
nkeynes@37	1121	break;
nkeynes@37	1122	case 2: /* Load/store multiple, branch*/
nkeynes@37	1123	if( (ir & 0x02000000) == 0x02000000 ) { /* B[L] imm24 */
nkeynes@37	1124	operand = (SIGNEXT24(ir&0x00FFFFFF) << 2);
nkeynes@37	1125	if( (ir & 0x01000000) == 0x01000000 ) {
nkeynes@37	1126	armr.r[14] = pc; /* BL */
nkeynes@37	1127	}
nkeynes@37	1128	armr.r[15] = pc + 4 + operand;
nkeynes@37	1129	} else { /* Load/store multiple */
nkeynes@46	1130	int prestep, poststep;
nkeynes@46	1131	if( PFLAG(ir) ) {
nkeynes@46	1132	prestep = 0;
nkeynes@46	1133	poststep = UFLAG(ir) ? 4 : -4;
nkeynes@46	1134	} else {
nkeynes@46	1135	prestep = UFLAG(ir) ? 4 : -4;
nkeynes@46	1136	poststep = 0 ;
nkeynes@46	1137	}
nkeynes@46	1138	operand = RN(ir);
nkeynes@46	1139	if( BFLAG(ir) ) {
nkeynes@46	1140	/* Actually S - bit 22. Means "make massively complicated" */
nkeynes@46	1141	if( LFLAG(ir) && (ir&0x00008000) ) {
nkeynes@46	1142	/* LDM (3). Much like normal LDM but also copies SPSR
nkeynes@46	1143	* back to CPSR */
nkeynes@46	1144	for( tmp=0; tmp < 16; tmp++ ) {
nkeynes@46	1145	if( (ir & (1<<tmp)) ) {
nkeynes@46	1146	operand += prestep;
nkeynes@46	1147	armr.r[tmp] = arm_read_long(operand);
nkeynes@46	1148	operand += poststep;
nkeynes@46	1149	}
nkeynes@46	1150	}
nkeynes@46	1151	arm_restore_cpsr();
nkeynes@46	1152	if( armr.t ) PC &= 0xFFFFFFFE;
nkeynes@46	1153	else PC &= 0xFFFFFFFC;
nkeynes@46	1154	} else {
nkeynes@46	1155	/* LDM/STM (2). As normal LDM but accesses the User banks
nkeynes@46	1156	* instead of the active ones. Aka the truly evil case
nkeynes@46	1157	*/
nkeynes@46	1158	int bank_start;
nkeynes@46	1159	if( IS_FIQ_MODE() )
nkeynes@46	1160	bank_start = 8;
nkeynes@46	1161	else if( IS_EXCEPTION_MODE() )
nkeynes@46	1162	bank_start = 13;
nkeynes@46	1163	else bank_start = 15;
nkeynes@46	1164	for( tmp=0; tmp<bank_start; tmp++ ) {
nkeynes@46	1165	if( (ir & (1<<tmp)) ) {
nkeynes@46	1166	operand += prestep;
nkeynes@46	1167	if( LFLAG(ir) ) {
nkeynes@46	1168	armr.r[tmp] = arm_read_long(operand);
nkeynes@46	1169	} else {
nkeynes@46	1170	arm_write_long( operand, armr.r[tmp] );
nkeynes@46	1171	}
nkeynes@46	1172	operand += poststep;
nkeynes@46	1173	}
nkeynes@46	1174	}
nkeynes@46	1175	for( ; tmp < 15; tmp ++ ) {
nkeynes@46	1176	if( (ir & (1<<tmp)) ) {
nkeynes@46	1177	operand += prestep;
nkeynes@46	1178	if( LFLAG(ir) ) {
nkeynes@46	1179	armr.user_r[tmp-8] = arm_read_long(operand);
nkeynes@46	1180	} else {
nkeynes@46	1181	arm_write_long( operand, armr.user_r[tmp-8] );
nkeynes@46	1182	}
nkeynes@46	1183	operand += poststep;
nkeynes@46	1184	}
nkeynes@46	1185	}
nkeynes@46	1186	if( ir & 0x8000 ) {
nkeynes@46	1187	operand += prestep;
nkeynes@46	1188	if( LFLAG(ir) ) {
nkeynes@46	1189	/* Actually can't happen, but anyway... */
nkeynes@46	1190	armr.r[15] = arm_read_long(operand);
nkeynes@46	1191	} else {
nkeynes@51	1192	arm_write_long( operand, armr.r[15]+ STM_R15_OFFSET - 4 );
nkeynes@46	1193	}
nkeynes@46	1194	operand += poststep;
nkeynes@46	1195	}
nkeynes@46	1196	}
nkeynes@46	1197	} else {
nkeynes@46	1198	/* Normal LDM/STM */
nkeynes@46	1199	for( tmp=0; tmp < 16; tmp++ ) {
nkeynes@46	1200	if( (ir & (1<<tmp)) ) {
nkeynes@46	1201	operand += prestep;
nkeynes@46	1202	if( LFLAG(ir) ) {
nkeynes@46	1203	armr.r[tmp] = arm_read_long(operand);
nkeynes@46	1204	} else {
nkeynes@51	1205	if( tmp == 15 )
nkeynes@51	1206	arm_write_long( operand,
nkeynes@51	1207	armr.r[15] + STM_R15_OFFSET - 4 );
nkeynes@51	1208	else
nkeynes@51	1209	arm_write_long( operand, armr.r[tmp] );
nkeynes@46	1210	}
nkeynes@46	1211	operand += poststep;
nkeynes@46	1212	}
nkeynes@46	1213	}
nkeynes@46	1214	}
nkeynes@46	1215	if( WFLAG(ir) )
nkeynes@46	1216	LRN(ir) = operand;
nkeynes@37	1217	}
nkeynes@37	1218	break;
nkeynes@37	1219	case 3: /* Copro */
nkeynes@51	1220	if( (ir & 0x0F000000) == 0x0F000000 ) { /* SWI */
nkeynes@51	1221	arm_raise_exception( EXC_SOFTWARE );
nkeynes@51	1222	} else {
nkeynes@51	1223	UNIMP(ir);
nkeynes@51	1224	}
nkeynes@37	1225	break;
nkeynes@37	1226	}
nkeynes@37	1227	return TRUE;
nkeynes@2	1228	}