nkeynes@1 | 1 | #include <assert.h>
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nkeynes@1 | 2 | #include "dream.h"
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nkeynes@1 | 3 | #include "mem.h"
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nkeynes@1 | 4 | #include "sh4/intc.h"
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nkeynes@1 | 5 | #include "asic.h"
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nkeynes@1 | 6 | #include "maple.h"
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nkeynes@1 | 7 | #define MMIO_IMPL
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nkeynes@1 | 8 | #include "asic.h"
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nkeynes@1 | 9 | /*
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nkeynes@1 | 10 | * Open questions:
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nkeynes@1 | 11 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 12 | * interrupt being delivered immediately?
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nkeynes@1 | 13 | * 2) If the pending register is not cleared after an interrupt, does
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nkeynes@1 | 14 | * the interrupt line remain high? (ie does the IRQ reoccur?)
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nkeynes@1 | 15 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 16 | *
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nkeynes@1 | 17 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 18 | * practically nothing is publicly known...
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nkeynes@1 | 19 | */
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nkeynes@1 | 20 |
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nkeynes@1 | 21 | void asic_init( void )
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nkeynes@1 | 22 | {
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nkeynes@1 | 23 | register_io_region( &mmio_region_ASIC );
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nkeynes@1 | 24 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@1 | 25 | mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
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nkeynes@1 | 26 | asic_event( EVENT_GDROM_CMD );
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nkeynes@1 | 27 | }
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nkeynes@1 | 28 |
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nkeynes@1 | 29 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 30 | {
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nkeynes@1 | 31 | switch( reg ) {
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nkeynes@1 | 32 | case PIRQ0:
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nkeynes@1 | 33 | case PIRQ1:
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nkeynes@1 | 34 | case PIRQ2:
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nkeynes@1 | 35 | /* Clear any interrupts */
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nkeynes@1 | 36 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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nkeynes@1 | 37 | break;
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nkeynes@1 | 38 | case MAPLE_STATE:
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nkeynes@1 | 39 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 40 | if( val & 1 ) {
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nkeynes@1 | 41 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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nkeynes@1 | 42 | // maple_handle_buffer( maple_addr );
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nkeynes@1 | 43 | WARN( "Maple request initiated, halting" );
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nkeynes@1 | 44 | MMIO_WRITE( ASIC, reg, 0 );
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nkeynes@1 | 45 | sh4_stop();
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nkeynes@1 | 46 | }
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nkeynes@1 | 47 | break;
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nkeynes@1 | 48 | default:
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nkeynes@1 | 49 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 50 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
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nkeynes@1 | 51 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 52 | }
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nkeynes@1 | 53 | }
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nkeynes@1 | 54 |
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nkeynes@1 | 55 | int32_t mmio_region_ASIC_read( uint32_t reg )
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nkeynes@1 | 56 | {
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nkeynes@1 | 57 | int32_t val;
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nkeynes@1 | 58 | switch( reg ) {
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nkeynes@1 | 59 | case PIRQ0:
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nkeynes@1 | 60 | case PIRQ1:
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nkeynes@1 | 61 | case PIRQ2:
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nkeynes@1 | 62 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 63 | // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 64 | // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 65 | return val;
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nkeynes@1 | 66 | case G2STATUS:
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nkeynes@1 | 67 | return 0; /* find out later if there's any cases we actually need to care about */
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nkeynes@1 | 68 | default:
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nkeynes@1 | 69 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 70 | WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 71 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 72 | return val;
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nkeynes@1 | 73 | }
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nkeynes@1 | 74 |
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nkeynes@1 | 75 | }
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nkeynes@1 | 76 |
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nkeynes@1 | 77 | void asic_event( int event )
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nkeynes@1 | 78 | {
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nkeynes@1 | 79 | int offset = ((event&0x60)>>3);
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nkeynes@1 | 80 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@1 | 81 |
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nkeynes@1 | 82 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@1 | 83 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@1 | 84 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@1 | 85 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@1 | 86 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@1 | 87 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@1 | 88 | }
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nkeynes@1 | 89 |
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nkeynes@1 | 90 |
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nkeynes@1 | 91 |
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nkeynes@1 | 92 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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nkeynes@1 | 93 | {
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nkeynes@1 | 94 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@1 | 95 | }
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nkeynes@1 | 96 |
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nkeynes@1 | 97 | MMIO_REGION_READ_FN( EXTDMA, reg )
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nkeynes@1 | 98 | {
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nkeynes@1 | 99 | switch( reg ) {
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nkeynes@1 | 100 | case GDBUSY: return 0;
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nkeynes@1 | 101 | default:
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nkeynes@1 | 102 | return MMIO_READ( EXTDMA, reg );
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nkeynes@1 | 103 | }
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nkeynes@1 | 104 | }
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nkeynes@1 | 105 |
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