nkeynes@1 | 1 | /*
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nkeynes@1 | 2 | * Header for the basic sh4 emulator core
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nkeynes@1 | 3 | */
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nkeynes@1 | 4 | #ifndef sh4core_H
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nkeynes@1 | 5 | #define sh4core_H 1
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nkeynes@1 | 6 |
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nkeynes@1 | 7 | #include <stdint.h>
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nkeynes@1 | 8 |
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nkeynes@1 | 9 | #ifdef __cplusplus
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nkeynes@1 | 10 | extern "C" {
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nkeynes@1 | 11 | #if 0
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nkeynes@1 | 12 | }
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nkeynes@1 | 13 | #endif
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nkeynes@1 | 14 | #endif
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nkeynes@1 | 15 |
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nkeynes@1 | 16 | struct sh4_registers {
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nkeynes@1 | 17 | uint32_t r[16];
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nkeynes@1 | 18 | uint32_t r_bank[8]; /* hidden banked registers */
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nkeynes@1 | 19 | uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
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nkeynes@1 | 20 | uint32_t pr, pc, fpul, fpscr;
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nkeynes@1 | 21 | uint64_t mac;
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nkeynes@1 | 22 | uint32_t m, q, s, t; /* really boolean - 0 or 1 */
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nkeynes@1 | 23 | float fr[2][16];
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nkeynes@1 | 24 |
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nkeynes@1 | 25 | uint32_t new_pc; /* Not a real register, but used to handle delay slots */
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nkeynes@1 | 26 | uint32_t icount; /* Also not a real register, instruction counter */
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nkeynes@1 | 27 | uint32_t int_pending; /* flag set by the INTC = pending priority level */
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nkeynes@1 | 28 | };
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nkeynes@1 | 29 |
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nkeynes@1 | 30 | extern struct sh4_registers sh4r;
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nkeynes@1 | 31 |
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nkeynes@1 | 32 | /* Public functions */
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nkeynes@1 | 33 |
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nkeynes@1 | 34 | void sh4_init( void );
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nkeynes@1 | 35 | void sh4_reset( void );
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nkeynes@1 | 36 | void sh4_run( void );
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nkeynes@1 | 37 | void sh4_runto( uint32_t pc, uint32_t count );
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nkeynes@1 | 38 | void sh4_runfor( uint32_t count );
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nkeynes@1 | 39 | int sh4_isrunning( void );
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nkeynes@1 | 40 | void sh4_stop( void );
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nkeynes@1 | 41 | void sh4_set_pc( int );
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nkeynes@1 | 42 | void sh4_execute_instruction( void );
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nkeynes@1 | 43 | void sh4_raise_exception( int, int );
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nkeynes@1 | 44 |
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nkeynes@1 | 45 | void run_timers( int );
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nkeynes@1 | 46 |
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nkeynes@1 | 47 | #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
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nkeynes@1 | 48 | #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
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nkeynes@1 | 49 | #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
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nkeynes@1 | 50 | #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
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nkeynes@1 | 51 | #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
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nkeynes@1 | 52 | #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
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nkeynes@1 | 53 |
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nkeynes@1 | 54 | /* Status Register (SR) bits */
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nkeynes@1 | 55 | #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
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nkeynes@1 | 56 | #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
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nkeynes@1 | 57 | #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
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nkeynes@1 | 58 | #define SR_FD 0x00008000 /* FPU disable */
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nkeynes@1 | 59 | #define SR_M 0x00000200
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nkeynes@1 | 60 | #define SR_Q 0x00000100
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nkeynes@1 | 61 | #define SR_IMASK 0x000000F0 /* Interrupt mask level */
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nkeynes@1 | 62 | #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
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nkeynes@1 | 63 | #define SR_T 0x00000001 /* True/false or carry/borrow */
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nkeynes@1 | 64 | #define SR_MASK 0x700083F3
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nkeynes@1 | 65 | #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
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nkeynes@1 | 66 |
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nkeynes@1 | 67 | #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
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nkeynes@1 | 68 | #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
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nkeynes@1 | 69 | #define SH4_INT_PENDING() (sh4r.int_pending)
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nkeynes@1 | 70 |
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nkeynes@1 | 71 | #define FPSCR_FR 0x00200000 /* FPU register bank */
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nkeynes@1 | 72 | #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
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nkeynes@1 | 73 | #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
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nkeynes@1 | 74 | #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
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nkeynes@1 | 75 | #define FPSCR_CAUSE 0x0003F000
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nkeynes@1 | 76 | #define FPSCR_ENABLE 0x00000F80
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nkeynes@1 | 77 | #define FPSCR_FLAG 0x0000007C
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nkeynes@1 | 78 | #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
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nkeynes@1 | 79 |
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nkeynes@1 | 80 | #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
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nkeynes@1 | 81 | #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
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nkeynes@1 | 82 | #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
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nkeynes@1 | 83 |
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nkeynes@1 | 84 | #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
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nkeynes@1 | 85 |
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nkeynes@1 | 86 | /* Exceptions (for use with sh4_raise_exception) */
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nkeynes@1 | 87 |
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nkeynes@1 | 88 | #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
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nkeynes@1 | 89 | #define EX_SLOT_ILLEGAL 0x1A0, 0x100
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nkeynes@1 | 90 | #define EX_TLB_MISS_READ 0x040, 0x400
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nkeynes@1 | 91 | #define EX_TLB_MISS_WRITE 0x060, 0x400
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nkeynes@1 | 92 | #define EX_INIT_PAGE_WRITE 0x080, 0x100
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nkeynes@1 | 93 | #define EX_TLB_PROT_READ 0x0A0, 0x100
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nkeynes@1 | 94 | #define EX_TLB_PROT_WRITE 0x0C0, 0x100
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nkeynes@1 | 95 | #define EX_DATA_ADDR_READ 0x0E0, 0x100
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nkeynes@1 | 96 | #define EX_DATA_ADDR_WRITE 0x100, 0x100
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nkeynes@1 | 97 | #define EX_FPU_EXCEPTION 0x120, 0x100
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nkeynes@1 | 98 | #define EX_TRAPA 0x160, 0x100
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nkeynes@1 | 99 | #define EX_BREAKPOINT 0x1E0, 0x100
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nkeynes@1 | 100 | #define EX_FPU_DISABLED 0x800, 0x100
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nkeynes@1 | 101 | #define EX_SLOT_FPU_DISABLED 0x820, 0x100
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nkeynes@1 | 102 |
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nkeynes@1 | 103 |
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nkeynes@1 | 104 |
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nkeynes@1 | 105 | #ifdef __cplusplus
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nkeynes@1 | 106 | }
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nkeynes@1 | 107 | #endif
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nkeynes@1 | 108 | #endif
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