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lxdream.org :: lxdream/src/sh4/sh4mmio.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.c
changeset 1:eea311cfd33e
next10:c898b37506e0
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (17 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
file annotate diff log raw
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#include "dream.h"
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#include "mem.h"
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#include "sh4core.h"
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#include "sh4mmio.h"
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#define MMIO_IMPL
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#include "sh4mmio.h"
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/********************************* MMU *************************************/
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MMIO_REGION_READ_STUBFN( MMU )
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    switch(reg) {
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        case CCR:
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            mem_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
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            INFO( "Cache mode set to %08X", val );
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            break;
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        default:
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            break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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/********************************* BSC *************************************/
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uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
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uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
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uint32_t bsc_output = 0, bsc_input = 0x0300;
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void bsc_out( int output, int mask )
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{
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    /* Go figure... The BIOS won't start without this mess though */
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    if( ((output | (~mask)) & 0x03) == 3 ) {
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        bsc_output |= 0x03;
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    } else {
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        bsc_output &= ~0x03;
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    }
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}
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void mmio_region_BSC_write( uint32_t reg, uint32_t val )
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{
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    int i;
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    switch( reg ) {
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        case PCTRA:
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            bsc_input_mask_lo = bsc_output_mask_lo = 0;
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            for( i=0; i<16; i++ ) {
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                int bits = (val >> (i<<1)) & 0x03;
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                if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
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                else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
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            }
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            bsc_output = (bsc_output&0x000F0000) |
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                (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
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            bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
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                     bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
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            break;
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        case PCTRB:
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            bsc_input_mask_hi = bsc_output_mask_hi = 0;
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            for( i=0; i<4; i++ ) {
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                int bits = (val >> (i>>1)) & 0x03;
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                if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
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                else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
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            }
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            bsc_output = (bsc_output&0xFFFF) |
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                ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
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            break;
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        case PDTRA:
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            bsc_output = (bsc_output&0x000F0000) |
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                (val & bsc_output_mask_lo );
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            bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
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                     bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
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            break;
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        case PDTRB:
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            bsc_output = (bsc_output&0xFFFF) |
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                ( (val & bsc_output_mask_hi)<<16 );
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            break;
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    }
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    WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
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          reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
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    MMIO_WRITE( BSC, reg, val );
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}
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int32_t mmio_region_BSC_read( uint32_t reg )
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{
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    int32_t val;
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    switch( reg ) {
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        case PDTRA:
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            val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
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            break;
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        case PDTRB:
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            val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
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            break;
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        default:
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            val = MMIO_READ( BSC, reg );
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    }
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    WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
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          reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
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    return val;
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}
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/********************************* UBC *************************************/
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MMIO_REGION_STUBFNS( UBC )
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/********************************* CPG *************************************/
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MMIO_REGION_STUBFNS( CPG )
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/********************************* DMAC *************************************/
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MMIO_REGION_STUBFNS( DMAC )
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/********************************** RTC *************************************/
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MMIO_REGION_STUBFNS( RTC )
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/********************************** TMU *************************************/
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int timer_divider[3] = {16,16,16};
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MMIO_REGION_READ_DEFFN( TMU )
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int get_timer_div( int val )
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{
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    switch( val & 0x07 ) {
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        case 0: return 16; /* assume peripheral clock is IC/4 */
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        case 1: return 64;
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        case 2: return 256;
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        case 3: return 1024;
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        case 4: return 4096;
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    }
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    return 1;
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}
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void mmio_region_TMU_write( uint32_t reg, uint32_t val )
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{
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    switch( reg ) {
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        case TCR0:
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            timer_divider[0] = get_timer_div(val);
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            break;
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        case TCR1:
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            timer_divider[1] = get_timer_div(val);
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            break;
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        case TCR2:
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            timer_divider[2] = get_timer_div(val);
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            break;
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    }
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    MMIO_WRITE( TMU, reg, val );
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}
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void run_timers( int cycles )
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{
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    int tcr = MMIO_READ( TMU, TSTR );
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    cycles *= 16;
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    if( tcr & 1 ) {
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        int count = cycles / timer_divider[0];
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        int *val = MMIO_REG( TMU, TCNT0 );
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        if( *val < count ) {
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            MMIO_READ( TMU, TCR0 ) |= 0x100;
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            /* interrupt goes here */
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            count -= *val;
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            *val = MMIO_READ( TMU, TCOR0 ) - count;
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        } else {
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            *val -= count;
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        }
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    }
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}
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/********************************** SCI *************************************/
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MMIO_REGION_STUBFNS( SCI )
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/********************************* SCIF *************************************/
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MMIO_REGION_STUBFNS( SCIF )
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.