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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 819:ef4fec10a63a
prev818:2e08d8237d33
next826:69f2c9f1e608
author nkeynes
date Tue Aug 19 22:58:05 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Add stubs for the (undocumented) SH4 performance counter registers
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "mem.h"
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/* The MMU (practically unique in the system) is allowed to raise exceptions
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 * directly, with a return code indicating that one was raised and the caller
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 * had better behave appropriately.
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 */
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#define RAISE_TLB_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_tlb_exception(code);
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_OTHER_ERROR(code) \
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    sh4_raise_exception(code);
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/**
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 * Abort with a non-MMU address error. Caused by user-mode code attempting
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 * to access privileged regions, or alignment faults.
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 */
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#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
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#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
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#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
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#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
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#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
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#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
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#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
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#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
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#define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
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#define OCRAM_END   (0x20000000>>LXDREAM_PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    default: return 0; /* Unreachable */
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    }
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}
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int32_t mmio_region_MMU_read( uint32_t reg )
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{
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    switch( reg ) {
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    case MMUCR:
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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{
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    uint32_t tmp;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_asid = val&0xFF;
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & MMUCR_AT ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_flush_icache();
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        }
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        break;
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    case CCR:
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        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
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        val &= 0x81A7;
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        break;
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    case PMCR1:
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    case PMCR2:
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        if( val != 0 ) {
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            WARN( "Performance counters not implemented" );
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        }
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        break;
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    default:
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        break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init() 
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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        return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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    }
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    return 0;
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}
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void mmu_set_cache_mode( int mode )
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{
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    uint32_t i;
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    switch( mode ) {
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    case MEM_OC_INDEX0: /* OIX=0 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
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        break;
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    case MEM_OC_INDEX1: /* OIX=1 */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
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        break;
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    default: /* disabled */
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        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = NULL;
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        break;
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    }
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}
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/* TLB maintanence */
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/**
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 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
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 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
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 */
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void MMU_ldtlb()
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{
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    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
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    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
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    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
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    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
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    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
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    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
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}
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static void mmu_invalidate_tlb()
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{
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    int i;
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    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
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        mmu_itlb[i].flags &= (~TLB_VALID);
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    }
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    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
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        mmu_utlb[i].flags &= (~TLB_VALID);
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    }
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}
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#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
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int32_t mmu_itlb_addr_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
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}
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int32_t mmu_itlb_data_read( sh4addr_t addr )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    return ent->ppn | ent->flags;
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}
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   300
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void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->vpn = val & 0xFFFFFC00;
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    ent->asid = val & 0x000000FF;
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    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
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}
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   308
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void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
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{
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    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
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    ent->ppn = val & 0x1FFFFC00;
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    ent->flags = val & 0x00001DA;
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    ent->mask = get_mask_for_flags(val);
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}
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#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
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#define UTLB_ASSOC(addr) (addr&0x80)
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#define UTLB_DATA2(addr) (addr&0x00800000)
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int32_t mmu_utlb_addr_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
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    ((ent->flags & TLB_DIRTY)<<7);
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}
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int32_t mmu_utlb_data_read( sh4addr_t addr )
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{
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    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
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    if( UTLB_DATA2(addr) ) {
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        return ent->pcmcia;
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    } else {
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        return ent->ppn | ent->flags;
nkeynes@550
   334
    }
nkeynes@550
   335
}
nkeynes@550
   336
nkeynes@586
   337
/**
nkeynes@586
   338
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@586
   339
 * lookup but ignores the valid bit.
nkeynes@586
   340
 */
nkeynes@669
   341
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   342
{
nkeynes@586
   343
    int result = -1;
nkeynes@586
   344
    unsigned int i;
nkeynes@586
   345
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   346
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   347
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) && 
nkeynes@736
   348
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   349
            if( result != -1 ) {
nkeynes@736
   350
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@736
   351
                return -2;
nkeynes@736
   352
            }
nkeynes@736
   353
            result = i;
nkeynes@736
   354
        }
nkeynes@586
   355
    }
nkeynes@586
   356
    return result;
nkeynes@586
   357
}
nkeynes@586
   358
nkeynes@586
   359
/**
nkeynes@586
   360
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@586
   361
 * lookup but ignores the valid bit.
nkeynes@586
   362
 */
nkeynes@669
   363
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   364
{
nkeynes@586
   365
    int result = -1;
nkeynes@586
   366
    unsigned int i;
nkeynes@586
   367
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   368
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   369
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) && 
nkeynes@736
   370
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   371
            if( result != -1 ) {
nkeynes@736
   372
                return -2;
nkeynes@736
   373
            }
nkeynes@736
   374
            result = i;
nkeynes@736
   375
        }
nkeynes@586
   376
    }
nkeynes@586
   377
    return result;
nkeynes@586
   378
}
nkeynes@586
   379
nkeynes@550
   380
void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   381
{
nkeynes@550
   382
    if( UTLB_ASSOC(addr) ) {
nkeynes@736
   383
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   384
        if( utlb >= 0 ) {
nkeynes@736
   385
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@736
   386
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@736
   387
            ent->flags |= (val & TLB_VALID);
nkeynes@736
   388
            ent->flags |= ((val & 0x200)>>7);
nkeynes@736
   389
        }
nkeynes@586
   390
nkeynes@736
   391
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   392
        if( itlb >= 0 ) {
nkeynes@736
   393
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@736
   394
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@736
   395
        }
nkeynes@586
   396
nkeynes@736
   397
        if( itlb == -2 || utlb == -2 ) {
nkeynes@736
   398
            MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   399
            return;
nkeynes@736
   400
        }
nkeynes@550
   401
    } else {
nkeynes@736
   402
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@736
   403
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@736
   404
        ent->asid = (val & 0xFF);
nkeynes@736
   405
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@736
   406
        ent->flags |= (val & TLB_VALID);
nkeynes@736
   407
        ent->flags |= ((val & 0x200)>>7);
nkeynes@550
   408
    }
nkeynes@550
   409
}
nkeynes@550
   410
nkeynes@550
   411
void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   412
{
nkeynes@550
   413
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   414
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   415
        ent->pcmcia = val & 0x0000000F;
nkeynes@550
   416
    } else {
nkeynes@736
   417
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@736
   418
        ent->flags = (val & 0x000001FF);
nkeynes@736
   419
        ent->mask = get_mask_for_flags(val);
nkeynes@550
   420
    }
nkeynes@550
   421
}
nkeynes@550
   422
nkeynes@550
   423
/* Cache access - not implemented */
nkeynes@550
   424
nkeynes@550
   425
int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550
   426
{
nkeynes@550
   427
    return 0; // not implemented
nkeynes@550
   428
}
nkeynes@550
   429
int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@550
   430
{
nkeynes@550
   431
    return 0; // not implemented
nkeynes@550
   432
}
nkeynes@550
   433
int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550
   434
{
nkeynes@550
   435
    return 0; // not implemented
nkeynes@550
   436
}
nkeynes@550
   437
int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550
   438
{
nkeynes@550
   439
    return 0; // not implemented
nkeynes@550
   440
}
nkeynes@550
   441
nkeynes@550
   442
void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   443
{
nkeynes@550
   444
}
nkeynes@550
   445
nkeynes@550
   446
void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   447
{
nkeynes@550
   448
}
nkeynes@550
   449
nkeynes@550
   450
void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   451
{
nkeynes@550
   452
}
nkeynes@550
   453
nkeynes@550
   454
void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   455
{
nkeynes@550
   456
}
nkeynes@586
   457
nkeynes@586
   458
/******************************************************************************/
nkeynes@586
   459
/*                        MMU TLB address translation                         */
nkeynes@586
   460
/******************************************************************************/
nkeynes@586
   461
nkeynes@586
   462
/**
nkeynes@586
   463
 * The translations are excessively complicated, but unfortunately it's a 
nkeynes@586
   464
 * complicated system. TODO: make this not be painfully slow.
nkeynes@586
   465
 */
nkeynes@586
   466
nkeynes@586
   467
/**
nkeynes@586
   468
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   469
 * Possible utcomes are:
nkeynes@586
   470
 *   0..63 Single match - good, return entry found
nkeynes@586
   471
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   472
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   473
 * @param vpn virtual address to resolve
nkeynes@586
   474
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   475
 */
nkeynes@586
   476
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   477
{
nkeynes@586
   478
    int result = -1;
nkeynes@586
   479
    unsigned int i;
nkeynes@586
   480
nkeynes@586
   481
    mmu_urc++;
nkeynes@586
   482
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   483
        mmu_urc = 0;
nkeynes@586
   484
    }
nkeynes@586
   485
nkeynes@586
   486
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   487
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   488
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) && 
nkeynes@736
   489
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   490
            if( result != -1 ) {
nkeynes@736
   491
                return -2;
nkeynes@736
   492
            }
nkeynes@736
   493
            result = i;
nkeynes@736
   494
        }
nkeynes@586
   495
    }
nkeynes@586
   496
    return result;
nkeynes@586
   497
}
nkeynes@586
   498
nkeynes@586
   499
/**
nkeynes@586
   500
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   501
 * Possible utcomes are:
nkeynes@586
   502
 *   0..63 Single match - good, return entry found
nkeynes@586
   503
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   504
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   505
 * @param vpn virtual address to resolve
nkeynes@586
   506
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   507
 */
nkeynes@586
   508
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   509
{
nkeynes@586
   510
    int result = -1;
nkeynes@586
   511
    unsigned int i;
nkeynes@586
   512
nkeynes@586
   513
    mmu_urc++;
nkeynes@586
   514
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   515
        mmu_urc = 0;
nkeynes@586
   516
    }
nkeynes@586
   517
nkeynes@586
   518
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   519
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   520
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   521
            if( result != -1 ) {
nkeynes@736
   522
                return -2;
nkeynes@736
   523
            }
nkeynes@736
   524
            result = i;
nkeynes@736
   525
        }
nkeynes@586
   526
    }
nkeynes@586
   527
nkeynes@586
   528
    return result;
nkeynes@586
   529
}
nkeynes@586
   530
nkeynes@586
   531
/**
nkeynes@586
   532
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   533
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   534
 */
nkeynes@586
   535
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   536
{
nkeynes@586
   537
    int replace;
nkeynes@586
   538
    /* Determine entry to replace based on lrui */
nkeynes@586
   539
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   540
        replace = 0;
nkeynes@736
   541
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   542
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   543
        replace = 1;
nkeynes@736
   544
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   545
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   546
        replace = 2;
nkeynes@736
   547
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   548
    } else { // Note - gets invalid entries too
nkeynes@736
   549
        replace = 3;
nkeynes@736
   550
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@586
   551
    } 
nkeynes@586
   552
nkeynes@586
   553
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   554
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   555
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   556
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   557
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   558
    return replace;
nkeynes@586
   559
}
nkeynes@586
   560
nkeynes@586
   561
/**
nkeynes@586
   562
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   563
 * Possible utcomes are:
nkeynes@586
   564
 *   0..63 Single match - good, return entry found
nkeynes@586
   565
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   566
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   567
 * @param vpn virtual address to resolve
nkeynes@586
   568
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   569
 */
nkeynes@586
   570
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   571
{
nkeynes@586
   572
    int result = -1;
nkeynes@586
   573
    unsigned int i;
nkeynes@586
   574
nkeynes@586
   575
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   576
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   577
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) && 
nkeynes@736
   578
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   579
            if( result != -1 ) {
nkeynes@736
   580
                return -2;
nkeynes@736
   581
            }
nkeynes@736
   582
            result = i;
nkeynes@736
   583
        }
nkeynes@586
   584
    }
nkeynes@586
   585
nkeynes@586
   586
    if( result == -1 ) {
nkeynes@736
   587
        int utlbEntry = mmu_utlb_lookup_vpn_asid( vpn );
nkeynes@736
   588
        if( utlbEntry < 0 ) {
nkeynes@736
   589
            return utlbEntry;
nkeynes@736
   590
        } else {
nkeynes@736
   591
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   592
        }
nkeynes@586
   593
    }
nkeynes@586
   594
nkeynes@586
   595
    switch( result ) {
nkeynes@586
   596
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   597
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   598
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   599
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   600
    }
nkeynes@736
   601
nkeynes@586
   602
    return result;
nkeynes@586
   603
}
nkeynes@586
   604
nkeynes@586
   605
/**
nkeynes@586
   606
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   607
 * Possible utcomes are:
nkeynes@586
   608
 *   0..63 Single match - good, return entry found
nkeynes@586
   609
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   610
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   611
 * @param vpn virtual address to resolve
nkeynes@586
   612
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   613
 */
nkeynes@586
   614
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   615
{
nkeynes@586
   616
    int result = -1;
nkeynes@586
   617
    unsigned int i;
nkeynes@586
   618
nkeynes@586
   619
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   620
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   621
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   622
            if( result != -1 ) {
nkeynes@736
   623
                return -2;
nkeynes@736
   624
            }
nkeynes@736
   625
            result = i;
nkeynes@736
   626
        }
nkeynes@586
   627
    }
nkeynes@586
   628
nkeynes@586
   629
    if( result == -1 ) {
nkeynes@736
   630
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
   631
        if( utlbEntry < 0 ) {
nkeynes@736
   632
            return utlbEntry;
nkeynes@736
   633
        } else {
nkeynes@736
   634
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   635
        }
nkeynes@586
   636
    }
nkeynes@586
   637
nkeynes@586
   638
    switch( result ) {
nkeynes@586
   639
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   640
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   641
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   642
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   643
    }
nkeynes@736
   644
nkeynes@586
   645
    return result;
nkeynes@586
   646
}
nkeynes@586
   647
nkeynes@586
   648
sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr )
nkeynes@586
   649
{
nkeynes@586
   650
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   651
    if( addr & 0x80000000 ) {
nkeynes@736
   652
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   653
            if( addr >= 0xE0000000 ) {
nkeynes@736
   654
                return addr; /* P4 - passthrough */
nkeynes@736
   655
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   656
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   657
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   658
            }
nkeynes@736
   659
        } else {
nkeynes@736
   660
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   661
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   662
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   663
                return addr;
nkeynes@736
   664
            }
nkeynes@736
   665
            MMU_READ_ADDR_ERROR();
nkeynes@736
   666
            return MMU_VMA_ERROR;
nkeynes@736
   667
        }
nkeynes@586
   668
    }
nkeynes@736
   669
nkeynes@586
   670
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   671
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   672
    }
nkeynes@586
   673
nkeynes@586
   674
    /* If we get this far, translation is required */
nkeynes@586
   675
    int entryNo;
nkeynes@586
   676
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   677
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   678
    } else {
nkeynes@736
   679
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   680
    }
nkeynes@586
   681
nkeynes@586
   682
    switch(entryNo) {
nkeynes@586
   683
    case -1:
nkeynes@736
   684
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   685
    return MMU_VMA_ERROR;
nkeynes@586
   686
    case -2:
nkeynes@736
   687
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   688
    return MMU_VMA_ERROR;
nkeynes@586
   689
    default:
nkeynes@736
   690
        if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@736
   691
                !IS_SH4_PRIVMODE() ) {
nkeynes@736
   692
            /* protection violation */
nkeynes@736
   693
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   694
            return MMU_VMA_ERROR;
nkeynes@736
   695
        }
nkeynes@586
   696
nkeynes@736
   697
        /* finally generate the target address */
nkeynes@810
   698
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@810
   699
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   700
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4 
nkeynes@810
   701
        	pma |= 0xE0000000;
nkeynes@810
   702
        return pma;
nkeynes@586
   703
    }
nkeynes@586
   704
}
nkeynes@586
   705
nkeynes@586
   706
sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr )
nkeynes@586
   707
{
nkeynes@586
   708
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   709
    if( addr & 0x80000000 ) {
nkeynes@736
   710
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   711
            if( addr >= 0xE0000000 ) {
nkeynes@736
   712
                return addr; /* P4 - passthrough */
nkeynes@736
   713
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   714
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   715
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   716
            }
nkeynes@736
   717
        } else {
nkeynes@736
   718
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   719
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   720
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   721
                return addr;
nkeynes@736
   722
            }
nkeynes@736
   723
            MMU_WRITE_ADDR_ERROR();
nkeynes@736
   724
            return MMU_VMA_ERROR;
nkeynes@736
   725
        }
nkeynes@586
   726
    }
nkeynes@736
   727
nkeynes@586
   728
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   729
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   730
    }
nkeynes@586
   731
nkeynes@586
   732
    /* If we get this far, translation is required */
nkeynes@586
   733
    int entryNo;
nkeynes@586
   734
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   735
        entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@586
   736
    } else {
nkeynes@736
   737
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   738
    }
nkeynes@586
   739
nkeynes@586
   740
    switch(entryNo) {
nkeynes@586
   741
    case -1:
nkeynes@736
   742
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   743
    return MMU_VMA_ERROR;
nkeynes@586
   744
    case -2:
nkeynes@736
   745
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   746
    return MMU_VMA_ERROR;
nkeynes@586
   747
    default:
nkeynes@736
   748
        if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   749
                : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   750
            /* protection violation */
nkeynes@736
   751
            MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   752
            return MMU_VMA_ERROR;
nkeynes@736
   753
        }
nkeynes@586
   754
nkeynes@736
   755
        if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   756
            MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   757
            return MMU_VMA_ERROR;
nkeynes@736
   758
        }
nkeynes@586
   759
nkeynes@736
   760
        /* finally generate the target address */
nkeynes@810
   761
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@810
   762
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   763
        if( pma > 0x1C000000 ) // Remap 1Cxx .. 1Fxx region to P4 
nkeynes@810
   764
        	pma |= 0xE0000000;
nkeynes@810
   765
        return pma;
nkeynes@586
   766
    }
nkeynes@586
   767
}
nkeynes@586
   768
nkeynes@586
   769
/**
nkeynes@586
   770
 * Update the icache for an untranslated address
nkeynes@586
   771
 */
nkeynes@586
   772
void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
   773
{
nkeynes@586
   774
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
   775
        /* Main ram */
nkeynes@736
   776
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
   777
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
   778
        sh4_icache.mask = 0xFF000000;
nkeynes@736
   779
        sh4_icache.page = sh4_main_ram;
nkeynes@586
   780
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
   781
        /* BIOS ROM */
nkeynes@736
   782
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
   783
        sh4_icache.page_ppa = 0;
nkeynes@736
   784
        sh4_icache.mask = 0xFFE00000;
nkeynes@736
   785
        sh4_icache.page = mem_get_region(0);
nkeynes@586
   786
    } else {
nkeynes@736
   787
        /* not supported */
nkeynes@736
   788
        sh4_icache.page_vma = -1;
nkeynes@586
   789
    }
nkeynes@586
   790
}
nkeynes@586
   791
nkeynes@586
   792
/**
nkeynes@586
   793
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
   794
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
   795
 * will be invalidated instead.
nkeynes@586
   796
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
   797
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
   798
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
   799
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
   800
 * the icache.
nkeynes@586
   801
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
   802
 * if an exception was raised.
nkeynes@586
   803
 */
nkeynes@586
   804
gboolean mmu_update_icache( sh4vma_t addr )
nkeynes@586
   805
{
nkeynes@586
   806
    int entryNo;
nkeynes@586
   807
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
   808
        if( addr & 0x80000000 ) {
nkeynes@736
   809
            if( addr < 0xC0000000 ) {
nkeynes@736
   810
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   811
                mmu_update_icache_phys(addr);
nkeynes@736
   812
                return TRUE;
nkeynes@736
   813
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@736
   814
                MMU_READ_ADDR_ERROR();
nkeynes@736
   815
                return FALSE;
nkeynes@736
   816
            }
nkeynes@736
   817
        }
nkeynes@586
   818
nkeynes@736
   819
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   820
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   821
            mmu_update_icache_phys(addr);
nkeynes@736
   822
            return TRUE;
nkeynes@736
   823
        }
nkeynes@736
   824
nkeynes@807
   825
        if( (mmucr & MMUCR_SV) == 0 ) 
nkeynes@807
   826
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   827
        else
nkeynes@807
   828
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
   829
    } else {
nkeynes@736
   830
        if( addr & 0x80000000 ) {
nkeynes@736
   831
            MMU_READ_ADDR_ERROR();
nkeynes@736
   832
            return FALSE;
nkeynes@736
   833
        }
nkeynes@586
   834
nkeynes@736
   835
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
   836
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   837
            mmu_update_icache_phys(addr);
nkeynes@736
   838
            return TRUE;
nkeynes@736
   839
        }
nkeynes@736
   840
nkeynes@807
   841
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
   842
nkeynes@736
   843
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@736
   844
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
   845
            return FALSE;
nkeynes@736
   846
        }
nkeynes@586
   847
    }
nkeynes@586
   848
nkeynes@586
   849
    switch(entryNo) {
nkeynes@586
   850
    case -1:
nkeynes@736
   851
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
   852
    return FALSE;
nkeynes@586
   853
    case -2:
nkeynes@736
   854
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   855
    return FALSE;
nkeynes@586
   856
    default:
nkeynes@736
   857
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
   858
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
   859
        if( sh4_icache.page == NULL ) {
nkeynes@736
   860
            sh4_icache.page_vma = -1;
nkeynes@736
   861
        } else {
nkeynes@736
   862
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
   863
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
   864
        }
nkeynes@736
   865
        return TRUE;
nkeynes@586
   866
    }
nkeynes@586
   867
}
nkeynes@586
   868
nkeynes@597
   869
/**
nkeynes@597
   870
 * Translate address for disassembly purposes (ie performs an instruction 
nkeynes@597
   871
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
   872
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@597
   873
 * on translation failure. 
nkeynes@597
   874
 */
nkeynes@597
   875
sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
   876
{
nkeynes@597
   877
    if( vma & 0x80000000 ) {
nkeynes@736
   878
        if( vma < 0xC0000000 ) {
nkeynes@736
   879
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   880
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
   881
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
   882
            /* Not translatable */
nkeynes@736
   883
            return MMU_VMA_ERROR;
nkeynes@736
   884
        }
nkeynes@597
   885
    }
nkeynes@597
   886
nkeynes@597
   887
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
   888
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   889
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
   890
    }
nkeynes@736
   891
nkeynes@597
   892
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
   893
    if( entryNo == -2 ) {
nkeynes@736
   894
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
   895
    }
nkeynes@597
   896
    if( entryNo < 0 ) {
nkeynes@736
   897
        return MMU_VMA_ERROR;
nkeynes@597
   898
    } else {
nkeynes@736
   899
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) | 
nkeynes@736
   900
        (vma & (~mmu_itlb[entryNo].mask));	
nkeynes@597
   901
    }
nkeynes@597
   902
}
nkeynes@597
   903
nkeynes@586
   904
gboolean sh4_flush_store_queue( sh4addr_t addr )
nkeynes@586
   905
{
nkeynes@586
   906
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   907
    int queue = (addr&0x20)>>2;
nkeynes@586
   908
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@586
   909
    sh4addr_t target;
nkeynes@586
   910
    /* Store queue operation */
nkeynes@586
   911
    if( mmucr & MMUCR_AT ) {
nkeynes@736
   912
        int entryNo;
nkeynes@736
   913
        if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@736
   914
            entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@736
   915
        } else {
nkeynes@736
   916
            entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@736
   917
        }
nkeynes@736
   918
        switch(entryNo) {
nkeynes@736
   919
        case -1:
nkeynes@736
   920
        MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@736
   921
        return FALSE;
nkeynes@736
   922
        case -2:
nkeynes@736
   923
        MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   924
        return FALSE;
nkeynes@736
   925
        default:
nkeynes@736
   926
            if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   927
                    : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   928
                /* protection violation */
nkeynes@736
   929
                MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@736
   930
                return FALSE;
nkeynes@736
   931
            }
nkeynes@736
   932
nkeynes@736
   933
            if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   934
                MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@736
   935
                return FALSE;
nkeynes@736
   936
            }
nkeynes@736
   937
nkeynes@736
   938
            /* finally generate the target address */
nkeynes@736
   939
            target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) | 
nkeynes@736
   940
                    (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
nkeynes@736
   941
        }
nkeynes@586
   942
    } else {
nkeynes@736
   943
        uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
nkeynes@736
   944
        target = (addr&0x03FFFFE0) | hi;
nkeynes@586
   945
    }
nkeynes@586
   946
    mem_copy_to_sh4( target, src, 32 );
nkeynes@586
   947
    return TRUE;
nkeynes@586
   948
}
nkeynes@586
   949
nkeynes@819
   950
/********************************* PMM *************************************/
nkeynes@819
   951
nkeynes@819
   952
/**
nkeynes@819
   953
 * Side note - this is here (rather than in sh4mmio.c) as the control registers
nkeynes@819
   954
 * are part of the MMU block, and it seems simplest to keep it all together.
nkeynes@819
   955
 */
nkeynes@819
   956
nkeynes@819
   957
int32_t mmio_region_PMM_read( uint32_t reg )
nkeynes@819
   958
{
nkeynes@819
   959
    return MMIO_READ( PMM, reg );
nkeynes@819
   960
}
nkeynes@819
   961
nkeynes@819
   962
void mmio_region_PMM_write( uint32_t reg, uint32_t val )
nkeynes@819
   963
{
nkeynes@819
   964
    /* Read-only */
nkeynes@819
   965
}
.