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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 732:f05753bbe723
prev675:b97020f9af1c
next733:633ee022f52e
author nkeynes
date Thu Jul 10 01:46:00 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Fix alignment check for 64-bit FMOVs
Add missing MMU code etc to FMOV emu implementation
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SIZEOF_VOID_P == 8
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#include "sh4/ia64abi.h"
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#else /* 32-bit system */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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   309
#else
nkeynes@539
   310
#include "sh4/ia32abi.h"
nkeynes@539
   311
#endif
nkeynes@539
   312
#endif
nkeynes@539
   313
nkeynes@593
   314
uint32_t sh4_translate_end_block_size()
nkeynes@593
   315
{
nkeynes@596
   316
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   317
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   318
    } else {
nkeynes@596
   319
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   320
    }
nkeynes@593
   321
}
nkeynes@593
   322
nkeynes@593
   323
nkeynes@590
   324
/**
nkeynes@590
   325
 * Embed a breakpoint into the generated code
nkeynes@590
   326
 */
nkeynes@586
   327
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   328
{
nkeynes@591
   329
    load_imm32( R_EAX, pc );
nkeynes@591
   330
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   331
}
nkeynes@590
   332
nkeynes@601
   333
nkeynes@601
   334
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   335
nkeynes@590
   336
/**
nkeynes@590
   337
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   338
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   339
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   340
 *
nkeynes@601
   341
 * Performs:
nkeynes@601
   342
 *   Set PC = endpc
nkeynes@601
   343
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   344
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   345
 *   Call sh4_execute_instruction
nkeynes@601
   346
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   347
 */
nkeynes@601
   348
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   349
{
nkeynes@590
   350
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   351
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   352
    
nkeynes@601
   353
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   354
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   355
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   356
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   357
nkeynes@590
   358
    call_func0( sh4_execute_instruction );    
nkeynes@601
   359
    load_spreg( R_EAX, R_PC );
nkeynes@590
   360
    if( sh4_x86.tlb_on ) {
nkeynes@590
   361
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   362
    } else {
nkeynes@590
   363
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   364
    }
nkeynes@601
   365
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   366
    POP_r32(R_EBP);
nkeynes@590
   367
    RET();
nkeynes@590
   368
} 
nkeynes@539
   369
nkeynes@359
   370
/**
nkeynes@359
   371
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   372
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   373
 * 
nkeynes@586
   374
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   375
 *
nkeynes@359
   376
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   377
 * (eg a branch or 
nkeynes@359
   378
 */
nkeynes@590
   379
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   380
{
nkeynes@388
   381
    uint32_t ir;
nkeynes@586
   382
    /* Read instruction from icache */
nkeynes@586
   383
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   384
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   385
    
nkeynes@586
   386
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   387
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   388
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   389
	 * almost certainly in a delay slot.
nkeynes@586
   390
	 *
nkeynes@586
   391
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   392
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   393
	 * small repairs to cope with the different environment).
nkeynes@586
   394
	 */
nkeynes@586
   395
nkeynes@586
   396
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   397
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   398
    }
nkeynes@359
   399
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   400
            case 0x0:
nkeynes@359
   401
                switch( ir&0xF ) {
nkeynes@359
   402
                    case 0x2:
nkeynes@359
   403
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   404
                            case 0x0:
nkeynes@359
   405
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   406
                                    case 0x0:
nkeynes@359
   407
                                        { /* STC SR, Rn */
nkeynes@359
   408
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   409
                                        COUNT_INST(I_STCSR);
nkeynes@386
   410
                                        check_priv();
nkeynes@374
   411
                                        call_func0(sh4_read_sr);
nkeynes@368
   412
                                        store_reg( R_EAX, Rn );
nkeynes@417
   413
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   414
                                        }
nkeynes@359
   415
                                        break;
nkeynes@359
   416
                                    case 0x1:
nkeynes@359
   417
                                        { /* STC GBR, Rn */
nkeynes@359
   418
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   419
                                        COUNT_INST(I_STC);
nkeynes@359
   420
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   421
                                        store_reg( R_EAX, Rn );
nkeynes@359
   422
                                        }
nkeynes@359
   423
                                        break;
nkeynes@359
   424
                                    case 0x2:
nkeynes@359
   425
                                        { /* STC VBR, Rn */
nkeynes@359
   426
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   427
                                        COUNT_INST(I_STC);
nkeynes@386
   428
                                        check_priv();
nkeynes@359
   429
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   430
                                        store_reg( R_EAX, Rn );
nkeynes@417
   431
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   432
                                        }
nkeynes@359
   433
                                        break;
nkeynes@359
   434
                                    case 0x3:
nkeynes@359
   435
                                        { /* STC SSR, Rn */
nkeynes@359
   436
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   437
                                        COUNT_INST(I_STC);
nkeynes@386
   438
                                        check_priv();
nkeynes@359
   439
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   440
                                        store_reg( R_EAX, Rn );
nkeynes@417
   441
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   442
                                        }
nkeynes@359
   443
                                        break;
nkeynes@359
   444
                                    case 0x4:
nkeynes@359
   445
                                        { /* STC SPC, Rn */
nkeynes@359
   446
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   447
                                        COUNT_INST(I_STC);
nkeynes@386
   448
                                        check_priv();
nkeynes@359
   449
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   450
                                        store_reg( R_EAX, Rn );
nkeynes@417
   451
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   452
                                        }
nkeynes@359
   453
                                        break;
nkeynes@359
   454
                                    default:
nkeynes@359
   455
                                        UNDEF();
nkeynes@359
   456
                                        break;
nkeynes@359
   457
                                }
nkeynes@359
   458
                                break;
nkeynes@359
   459
                            case 0x1:
nkeynes@359
   460
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   461
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@671
   462
                                COUNT_INST(I_STC);
nkeynes@386
   463
                                check_priv();
nkeynes@374
   464
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   465
                                store_reg( R_EAX, Rn );
nkeynes@417
   466
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   467
                                }
nkeynes@359
   468
                                break;
nkeynes@359
   469
                        }
nkeynes@359
   470
                        break;
nkeynes@359
   471
                    case 0x3:
nkeynes@359
   472
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   473
                            case 0x0:
nkeynes@359
   474
                                { /* BSRF Rn */
nkeynes@359
   475
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   476
                                COUNT_INST(I_BSRF);
nkeynes@374
   477
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   478
                            	SLOTILLEGAL();
nkeynes@374
   479
                                } else {
nkeynes@590
   480
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   481
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   482
                            	store_spreg( R_EAX, R_PR );
nkeynes@590
   483
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   484
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   485
                            
nkeynes@601
   486
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   487
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   488
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   489
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   490
                            	    exit_block_emu(pc+2);
nkeynes@601
   491
                            	    return 2;
nkeynes@601
   492
                            	} else {
nkeynes@601
   493
                            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
   494
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   495
                            	    return 4;
nkeynes@601
   496
                            	}
nkeynes@374
   497
                                }
nkeynes@359
   498
                                }
nkeynes@359
   499
                                break;
nkeynes@359
   500
                            case 0x2:
nkeynes@359
   501
                                { /* BRAF Rn */
nkeynes@359
   502
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   503
                                COUNT_INST(I_BRAF);
nkeynes@374
   504
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   505
                            	SLOTILLEGAL();
nkeynes@374
   506
                                } else {
nkeynes@590
   507
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
   508
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
   509
                            	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
   510
                            	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
   511
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
   512
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   513
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   514
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   515
                            	    exit_block_emu(pc+2);
nkeynes@601
   516
                            	    return 2;
nkeynes@601
   517
                            	} else {
nkeynes@601
   518
                            	    sh4_translate_instruction( pc + 2 );
nkeynes@601
   519
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   520
                            	    return 4;
nkeynes@601
   521
                            	}
nkeynes@374
   522
                                }
nkeynes@359
   523
                                }
nkeynes@359
   524
                                break;
nkeynes@359
   525
                            case 0x8:
nkeynes@359
   526
                                { /* PREF @Rn */
nkeynes@359
   527
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   528
                                COUNT_INST(I_PREF);
nkeynes@374
   529
                                load_reg( R_EAX, Rn );
nkeynes@532
   530
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
   531
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   532
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
   533
                                JNE_rel8(end);
nkeynes@532
   534
                                call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
   535
                                TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
   536
                                JE_exc(-1);
nkeynes@380
   537
                                JMP_TARGET(end);
nkeynes@417
   538
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   539
                                }
nkeynes@359
   540
                                break;
nkeynes@359
   541
                            case 0x9:
nkeynes@359
   542
                                { /* OCBI @Rn */
nkeynes@359
   543
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   544
                                COUNT_INST(I_OCBI);
nkeynes@359
   545
                                }
nkeynes@359
   546
                                break;
nkeynes@359
   547
                            case 0xA:
nkeynes@359
   548
                                { /* OCBP @Rn */
nkeynes@359
   549
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   550
                                COUNT_INST(I_OCBP);
nkeynes@359
   551
                                }
nkeynes@359
   552
                                break;
nkeynes@359
   553
                            case 0xB:
nkeynes@359
   554
                                { /* OCBWB @Rn */
nkeynes@359
   555
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   556
                                COUNT_INST(I_OCBWB);
nkeynes@359
   557
                                }
nkeynes@359
   558
                                break;
nkeynes@359
   559
                            case 0xC:
nkeynes@359
   560
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   561
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   562
                                COUNT_INST(I_MOVCA);
nkeynes@586
   563
                                load_reg( R_EAX, Rn );
nkeynes@586
   564
                                check_walign32( R_EAX );
nkeynes@586
   565
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   566
                                load_reg( R_EDX, 0 );
nkeynes@586
   567
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   568
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   569
                                }
nkeynes@359
   570
                                break;
nkeynes@359
   571
                            default:
nkeynes@359
   572
                                UNDEF();
nkeynes@359
   573
                                break;
nkeynes@359
   574
                        }
nkeynes@359
   575
                        break;
nkeynes@359
   576
                    case 0x4:
nkeynes@359
   577
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   578
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   579
                        COUNT_INST(I_MOVB);
nkeynes@359
   580
                        load_reg( R_EAX, 0 );
nkeynes@359
   581
                        load_reg( R_ECX, Rn );
nkeynes@586
   582
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   583
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   584
                        load_reg( R_EDX, Rm );
nkeynes@586
   585
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   586
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   587
                        }
nkeynes@359
   588
                        break;
nkeynes@359
   589
                    case 0x5:
nkeynes@359
   590
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   591
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   592
                        COUNT_INST(I_MOVW);
nkeynes@361
   593
                        load_reg( R_EAX, 0 );
nkeynes@361
   594
                        load_reg( R_ECX, Rn );
nkeynes@586
   595
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   596
                        check_walign16( R_EAX );
nkeynes@586
   597
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   598
                        load_reg( R_EDX, Rm );
nkeynes@586
   599
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   600
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   601
                        }
nkeynes@359
   602
                        break;
nkeynes@359
   603
                    case 0x6:
nkeynes@359
   604
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   605
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   606
                        COUNT_INST(I_MOVL);
nkeynes@361
   607
                        load_reg( R_EAX, 0 );
nkeynes@361
   608
                        load_reg( R_ECX, Rn );
nkeynes@586
   609
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   610
                        check_walign32( R_EAX );
nkeynes@586
   611
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   612
                        load_reg( R_EDX, Rm );
nkeynes@586
   613
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   614
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   615
                        }
nkeynes@359
   616
                        break;
nkeynes@359
   617
                    case 0x7:
nkeynes@359
   618
                        { /* MUL.L Rm, Rn */
nkeynes@359
   619
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   620
                        COUNT_INST(I_MULL);
nkeynes@361
   621
                        load_reg( R_EAX, Rm );
nkeynes@361
   622
                        load_reg( R_ECX, Rn );
nkeynes@361
   623
                        MUL_r32( R_ECX );
nkeynes@361
   624
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
   625
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   626
                        }
nkeynes@359
   627
                        break;
nkeynes@359
   628
                    case 0x8:
nkeynes@359
   629
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   630
                            case 0x0:
nkeynes@359
   631
                                { /* CLRT */
nkeynes@671
   632
                                COUNT_INST(I_CLRT);
nkeynes@374
   633
                                CLC();
nkeynes@374
   634
                                SETC_t();
nkeynes@417
   635
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   636
                                }
nkeynes@359
   637
                                break;
nkeynes@359
   638
                            case 0x1:
nkeynes@359
   639
                                { /* SETT */
nkeynes@671
   640
                                COUNT_INST(I_SETT);
nkeynes@374
   641
                                STC();
nkeynes@374
   642
                                SETC_t();
nkeynes@417
   643
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   644
                                }
nkeynes@359
   645
                                break;
nkeynes@359
   646
                            case 0x2:
nkeynes@359
   647
                                { /* CLRMAC */
nkeynes@671
   648
                                COUNT_INST(I_CLRMAC);
nkeynes@374
   649
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   650
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   651
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
   652
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   653
                                }
nkeynes@359
   654
                                break;
nkeynes@359
   655
                            case 0x3:
nkeynes@359
   656
                                { /* LDTLB */
nkeynes@671
   657
                                COUNT_INST(I_LDTLB);
nkeynes@553
   658
                                call_func0( MMU_ldtlb );
nkeynes@359
   659
                                }
nkeynes@359
   660
                                break;
nkeynes@359
   661
                            case 0x4:
nkeynes@359
   662
                                { /* CLRS */
nkeynes@671
   663
                                COUNT_INST(I_CLRS);
nkeynes@374
   664
                                CLC();
nkeynes@374
   665
                                SETC_sh4r(R_S);
nkeynes@417
   666
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   667
                                }
nkeynes@359
   668
                                break;
nkeynes@359
   669
                            case 0x5:
nkeynes@359
   670
                                { /* SETS */
nkeynes@671
   671
                                COUNT_INST(I_SETS);
nkeynes@374
   672
                                STC();
nkeynes@374
   673
                                SETC_sh4r(R_S);
nkeynes@417
   674
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
   675
                                }
nkeynes@359
   676
                                break;
nkeynes@359
   677
                            default:
nkeynes@359
   678
                                UNDEF();
nkeynes@359
   679
                                break;
nkeynes@359
   680
                        }
nkeynes@359
   681
                        break;
nkeynes@359
   682
                    case 0x9:
nkeynes@359
   683
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   684
                            case 0x0:
nkeynes@359
   685
                                { /* NOP */
nkeynes@671
   686
                                COUNT_INST(I_NOP);
nkeynes@359
   687
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   688
                                }
nkeynes@359
   689
                                break;
nkeynes@359
   690
                            case 0x1:
nkeynes@359
   691
                                { /* DIV0U */
nkeynes@671
   692
                                COUNT_INST(I_DIV0U);
nkeynes@361
   693
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   694
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   695
                                store_spreg( R_EAX, R_M );
nkeynes@361
   696
                                store_spreg( R_EAX, R_T );
nkeynes@417
   697
                                sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@359
   698
                                }
nkeynes@359
   699
                                break;
nkeynes@359
   700
                            case 0x2:
nkeynes@359
   701
                                { /* MOVT Rn */
nkeynes@359
   702
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   703
                                COUNT_INST(I_MOVT);
nkeynes@359
   704
                                load_spreg( R_EAX, R_T );
nkeynes@359
   705
                                store_reg( R_EAX, Rn );
nkeynes@359
   706
                                }
nkeynes@359
   707
                                break;
nkeynes@359
   708
                            default:
nkeynes@359
   709
                                UNDEF();
nkeynes@359
   710
                                break;
nkeynes@359
   711
                        }
nkeynes@359
   712
                        break;
nkeynes@359
   713
                    case 0xA:
nkeynes@359
   714
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   715
                            case 0x0:
nkeynes@359
   716
                                { /* STS MACH, Rn */
nkeynes@359
   717
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   718
                                COUNT_INST(I_STS);
nkeynes@359
   719
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   720
                                store_reg( R_EAX, Rn );
nkeynes@359
   721
                                }
nkeynes@359
   722
                                break;
nkeynes@359
   723
                            case 0x1:
nkeynes@359
   724
                                { /* STS MACL, Rn */
nkeynes@359
   725
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   726
                                COUNT_INST(I_STS);
nkeynes@359
   727
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   728
                                store_reg( R_EAX, Rn );
nkeynes@359
   729
                                }
nkeynes@359
   730
                                break;
nkeynes@359
   731
                            case 0x2:
nkeynes@359
   732
                                { /* STS PR, Rn */
nkeynes@359
   733
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   734
                                COUNT_INST(I_STS);
nkeynes@359
   735
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   736
                                store_reg( R_EAX, Rn );
nkeynes@359
   737
                                }
nkeynes@359
   738
                                break;
nkeynes@359
   739
                            case 0x3:
nkeynes@359
   740
                                { /* STC SGR, Rn */
nkeynes@359
   741
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   742
                                COUNT_INST(I_STC);
nkeynes@386
   743
                                check_priv();
nkeynes@359
   744
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   745
                                store_reg( R_EAX, Rn );
nkeynes@417
   746
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   747
                                }
nkeynes@359
   748
                                break;
nkeynes@359
   749
                            case 0x5:
nkeynes@359
   750
                                { /* STS FPUL, Rn */
nkeynes@359
   751
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   752
                                COUNT_INST(I_STS);
nkeynes@626
   753
                                check_fpuen();
nkeynes@359
   754
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   755
                                store_reg( R_EAX, Rn );
nkeynes@359
   756
                                }
nkeynes@359
   757
                                break;
nkeynes@359
   758
                            case 0x6:
nkeynes@359
   759
                                { /* STS FPSCR, Rn */
nkeynes@359
   760
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@673
   761
                                COUNT_INST(I_STSFPSCR);
nkeynes@626
   762
                                check_fpuen();
nkeynes@359
   763
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   764
                                store_reg( R_EAX, Rn );
nkeynes@359
   765
                                }
nkeynes@359
   766
                                break;
nkeynes@359
   767
                            case 0xF:
nkeynes@359
   768
                                { /* STC DBR, Rn */
nkeynes@359
   769
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
   770
                                COUNT_INST(I_STC);
nkeynes@386
   771
                                check_priv();
nkeynes@359
   772
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   773
                                store_reg( R_EAX, Rn );
nkeynes@417
   774
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   775
                                }
nkeynes@359
   776
                                break;
nkeynes@359
   777
                            default:
nkeynes@359
   778
                                UNDEF();
nkeynes@359
   779
                                break;
nkeynes@359
   780
                        }
nkeynes@359
   781
                        break;
nkeynes@359
   782
                    case 0xB:
nkeynes@359
   783
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   784
                            case 0x0:
nkeynes@359
   785
                                { /* RTS */
nkeynes@671
   786
                                COUNT_INST(I_RTS);
nkeynes@374
   787
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   788
                            	SLOTILLEGAL();
nkeynes@374
   789
                                } else {
nkeynes@408
   790
                            	load_spreg( R_ECX, R_PR );
nkeynes@590
   791
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
   792
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
   793
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   794
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   795
                            	    exit_block_emu(pc+2);
nkeynes@601
   796
                            	    return 2;
nkeynes@601
   797
                            	} else {
nkeynes@601
   798
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
   799
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   800
                            	    return 4;
nkeynes@601
   801
                            	}
nkeynes@374
   802
                                }
nkeynes@359
   803
                                }
nkeynes@359
   804
                                break;
nkeynes@359
   805
                            case 0x1:
nkeynes@359
   806
                                { /* SLEEP */
nkeynes@671
   807
                                COUNT_INST(I_SLEEP);
nkeynes@388
   808
                                check_priv();
nkeynes@388
   809
                                call_func0( sh4_sleep );
nkeynes@417
   810
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
   811
                                sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
   812
                                return 2;
nkeynes@359
   813
                                }
nkeynes@359
   814
                                break;
nkeynes@359
   815
                            case 0x2:
nkeynes@359
   816
                                { /* RTE */
nkeynes@671
   817
                                COUNT_INST(I_RTE);
nkeynes@374
   818
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   819
                            	SLOTILLEGAL();
nkeynes@374
   820
                                } else {
nkeynes@408
   821
                            	check_priv();
nkeynes@408
   822
                            	load_spreg( R_ECX, R_SPC );
nkeynes@590
   823
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
   824
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   825
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
   826
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
   827
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   828
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
   829
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
   830
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
   831
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
   832
                            	    exit_block_emu(pc+2);
nkeynes@601
   833
                            	    return 2;
nkeynes@601
   834
                            	} else {
nkeynes@601
   835
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
   836
                            	    exit_block_newpcset(pc+2);
nkeynes@601
   837
                            	    return 4;
nkeynes@601
   838
                            	}
nkeynes@374
   839
                                }
nkeynes@359
   840
                                }
nkeynes@359
   841
                                break;
nkeynes@359
   842
                            default:
nkeynes@359
   843
                                UNDEF();
nkeynes@359
   844
                                break;
nkeynes@359
   845
                        }
nkeynes@359
   846
                        break;
nkeynes@359
   847
                    case 0xC:
nkeynes@359
   848
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   849
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   850
                        COUNT_INST(I_MOVB);
nkeynes@359
   851
                        load_reg( R_EAX, 0 );
nkeynes@359
   852
                        load_reg( R_ECX, Rm );
nkeynes@586
   853
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   854
                        MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
   855
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
   856
                        store_reg( R_EAX, Rn );
nkeynes@417
   857
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   858
                        }
nkeynes@359
   859
                        break;
nkeynes@359
   860
                    case 0xD:
nkeynes@359
   861
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   862
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   863
                        COUNT_INST(I_MOVW);
nkeynes@361
   864
                        load_reg( R_EAX, 0 );
nkeynes@361
   865
                        load_reg( R_ECX, Rm );
nkeynes@586
   866
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   867
                        check_ralign16( R_EAX );
nkeynes@586
   868
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   869
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
   870
                        store_reg( R_EAX, Rn );
nkeynes@417
   871
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   872
                        }
nkeynes@359
   873
                        break;
nkeynes@359
   874
                    case 0xE:
nkeynes@359
   875
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   876
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   877
                        COUNT_INST(I_MOVL);
nkeynes@361
   878
                        load_reg( R_EAX, 0 );
nkeynes@361
   879
                        load_reg( R_ECX, Rm );
nkeynes@586
   880
                        ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   881
                        check_ralign32( R_EAX );
nkeynes@586
   882
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   883
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
   884
                        store_reg( R_EAX, Rn );
nkeynes@417
   885
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   886
                        }
nkeynes@359
   887
                        break;
nkeynes@359
   888
                    case 0xF:
nkeynes@359
   889
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   890
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   891
                        COUNT_INST(I_MACL);
nkeynes@586
   892
                        if( Rm == Rn ) {
nkeynes@586
   893
                    	load_reg( R_EAX, Rm );
nkeynes@586
   894
                    	check_ralign32( R_EAX );
nkeynes@586
   895
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   896
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
   897
                    	load_reg( R_EAX, Rn );
nkeynes@586
   898
                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   899
                    	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   900
                    	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   901
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   902
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
   903
                        } else {
nkeynes@586
   904
                    	load_reg( R_EAX, Rm );
nkeynes@586
   905
                    	check_ralign32( R_EAX );
nkeynes@586
   906
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   907
                    	load_reg( R_ECX, Rn );
nkeynes@596
   908
                    	check_ralign32( R_ECX );
nkeynes@586
   909
                    	PUSH_realigned_r32( R_EAX );
nkeynes@596
   910
                    	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   911
                    	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   912
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   913
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   914
                        }
nkeynes@586
   915
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   916
                        POP_r32( R_ECX );
nkeynes@586
   917
                        PUSH_r32( R_EAX );
nkeynes@386
   918
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   919
                        POP_realigned_r32( R_ECX );
nkeynes@586
   920
                    
nkeynes@386
   921
                        IMUL_r32( R_ECX );
nkeynes@386
   922
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   923
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   924
                    
nkeynes@386
   925
                        load_spreg( R_ECX, R_S );
nkeynes@386
   926
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   927
                        JE_rel8( nosat );
nkeynes@386
   928
                        call_func0( signsat48 );
nkeynes@386
   929
                        JMP_TARGET( nosat );
nkeynes@417
   930
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   931
                        }
nkeynes@359
   932
                        break;
nkeynes@359
   933
                    default:
nkeynes@359
   934
                        UNDEF();
nkeynes@359
   935
                        break;
nkeynes@359
   936
                }
nkeynes@359
   937
                break;
nkeynes@359
   938
            case 0x1:
nkeynes@359
   939
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   940
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@671
   941
                COUNT_INST(I_MOVL);
nkeynes@586
   942
                load_reg( R_EAX, Rn );
nkeynes@586
   943
                ADD_imm32_r32( disp, R_EAX );
nkeynes@586
   944
                check_walign32( R_EAX );
nkeynes@586
   945
                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   946
                load_reg( R_EDX, Rm );
nkeynes@586
   947
                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   948
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   949
                }
nkeynes@359
   950
                break;
nkeynes@359
   951
            case 0x2:
nkeynes@359
   952
                switch( ir&0xF ) {
nkeynes@359
   953
                    case 0x0:
nkeynes@359
   954
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   955
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   956
                        COUNT_INST(I_MOVB);
nkeynes@586
   957
                        load_reg( R_EAX, Rn );
nkeynes@586
   958
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   959
                        load_reg( R_EDX, Rm );
nkeynes@586
   960
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   961
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   962
                        }
nkeynes@359
   963
                        break;
nkeynes@359
   964
                    case 0x1:
nkeynes@359
   965
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   966
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   967
                        COUNT_INST(I_MOVW);
nkeynes@586
   968
                        load_reg( R_EAX, Rn );
nkeynes@586
   969
                        check_walign16( R_EAX );
nkeynes@586
   970
                        MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
   971
                        load_reg( R_EDX, Rm );
nkeynes@586
   972
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
   973
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   974
                        }
nkeynes@359
   975
                        break;
nkeynes@359
   976
                    case 0x2:
nkeynes@359
   977
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   978
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   979
                        COUNT_INST(I_MOVL);
nkeynes@586
   980
                        load_reg( R_EAX, Rn );
nkeynes@586
   981
                        check_walign32(R_EAX);
nkeynes@586
   982
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   983
                        load_reg( R_EDX, Rm );
nkeynes@586
   984
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
   985
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   986
                        }
nkeynes@359
   987
                        break;
nkeynes@359
   988
                    case 0x4:
nkeynes@359
   989
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   990
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
   991
                        COUNT_INST(I_MOVB);
nkeynes@586
   992
                        load_reg( R_EAX, Rn );
nkeynes@586
   993
                        ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
   994
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   995
                        load_reg( R_EDX, Rm );
nkeynes@586
   996
                        ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
   997
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   998
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   999
                        }
nkeynes@359
  1000
                        break;
nkeynes@359
  1001
                    case 0x5:
nkeynes@359
  1002
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
  1003
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1004
                        COUNT_INST(I_MOVW);
nkeynes@586
  1005
                        load_reg( R_EAX, Rn );
nkeynes@586
  1006
                        ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1007
                        check_walign16( R_EAX );
nkeynes@586
  1008
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1009
                        load_reg( R_EDX, Rm );
nkeynes@586
  1010
                        ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1011
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1012
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1013
                        }
nkeynes@359
  1014
                        break;
nkeynes@359
  1015
                    case 0x6:
nkeynes@359
  1016
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
  1017
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1018
                        COUNT_INST(I_MOVL);
nkeynes@586
  1019
                        load_reg( R_EAX, Rn );
nkeynes@586
  1020
                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1021
                        check_walign32( R_EAX );
nkeynes@586
  1022
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1023
                        load_reg( R_EDX, Rm );
nkeynes@586
  1024
                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1025
                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1026
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1027
                        }
nkeynes@359
  1028
                        break;
nkeynes@359
  1029
                    case 0x7:
nkeynes@359
  1030
                        { /* DIV0S Rm, Rn */
nkeynes@359
  1031
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1032
                        COUNT_INST(I_DIV0S);
nkeynes@361
  1033
                        load_reg( R_EAX, Rm );
nkeynes@386
  1034
                        load_reg( R_ECX, Rn );
nkeynes@361
  1035
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
  1036
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
  1037
                        store_spreg( R_EAX, R_M );
nkeynes@361
  1038
                        store_spreg( R_ECX, R_Q );
nkeynes@361
  1039
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1040
                        SETNE_t();
nkeynes@417
  1041
                        sh4_x86.tstate = TSTATE_NE;
nkeynes@359
  1042
                        }
nkeynes@359
  1043
                        break;
nkeynes@359
  1044
                    case 0x8:
nkeynes@359
  1045
                        { /* TST Rm, Rn */
nkeynes@359
  1046
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1047
                        COUNT_INST(I_TST);
nkeynes@361
  1048
                        load_reg( R_EAX, Rm );
nkeynes@361
  1049
                        load_reg( R_ECX, Rn );
nkeynes@361
  1050
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1051
                        SETE_t();
nkeynes@417
  1052
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1053
                        }
nkeynes@359
  1054
                        break;
nkeynes@359
  1055
                    case 0x9:
nkeynes@359
  1056
                        { /* AND Rm, Rn */
nkeynes@359
  1057
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1058
                        COUNT_INST(I_AND);
nkeynes@359
  1059
                        load_reg( R_EAX, Rm );
nkeynes@359
  1060
                        load_reg( R_ECX, Rn );
nkeynes@359
  1061
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1062
                        store_reg( R_ECX, Rn );
nkeynes@417
  1063
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1064
                        }
nkeynes@359
  1065
                        break;
nkeynes@359
  1066
                    case 0xA:
nkeynes@359
  1067
                        { /* XOR Rm, Rn */
nkeynes@359
  1068
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1069
                        COUNT_INST(I_XOR);
nkeynes@359
  1070
                        load_reg( R_EAX, Rm );
nkeynes@359
  1071
                        load_reg( R_ECX, Rn );
nkeynes@359
  1072
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1073
                        store_reg( R_ECX, Rn );
nkeynes@417
  1074
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1075
                        }
nkeynes@359
  1076
                        break;
nkeynes@359
  1077
                    case 0xB:
nkeynes@359
  1078
                        { /* OR Rm, Rn */
nkeynes@359
  1079
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1080
                        COUNT_INST(I_OR);
nkeynes@359
  1081
                        load_reg( R_EAX, Rm );
nkeynes@359
  1082
                        load_reg( R_ECX, Rn );
nkeynes@359
  1083
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1084
                        store_reg( R_ECX, Rn );
nkeynes@417
  1085
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1086
                        }
nkeynes@359
  1087
                        break;
nkeynes@359
  1088
                    case 0xC:
nkeynes@359
  1089
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1090
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1091
                        COUNT_INST(I_CMPSTR);
nkeynes@368
  1092
                        load_reg( R_EAX, Rm );
nkeynes@368
  1093
                        load_reg( R_ECX, Rn );
nkeynes@368
  1094
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1095
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@669
  1096
                        JE_rel8(target1);
nkeynes@669
  1097
                        TEST_r8_r8( R_AH, R_AH );
nkeynes@669
  1098
                        JE_rel8(target2);
nkeynes@669
  1099
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@669
  1100
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@669
  1101
                        JE_rel8(target3);
nkeynes@669
  1102
                        TEST_r8_r8( R_AH, R_AH );
nkeynes@380
  1103
                        JMP_TARGET(target1);
nkeynes@380
  1104
                        JMP_TARGET(target2);
nkeynes@380
  1105
                        JMP_TARGET(target3);
nkeynes@368
  1106
                        SETE_t();
nkeynes@417
  1107
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1108
                        }
nkeynes@359
  1109
                        break;
nkeynes@359
  1110
                    case 0xD:
nkeynes@359
  1111
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1112
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1113
                        COUNT_INST(I_XTRCT);
nkeynes@361
  1114
                        load_reg( R_EAX, Rm );
nkeynes@394
  1115
                        load_reg( R_ECX, Rn );
nkeynes@394
  1116
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1117
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1118
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1119
                        store_reg( R_ECX, Rn );
nkeynes@417
  1120
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1121
                        }
nkeynes@359
  1122
                        break;
nkeynes@359
  1123
                    case 0xE:
nkeynes@359
  1124
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1125
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1126
                        COUNT_INST(I_MULUW);
nkeynes@374
  1127
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1128
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1129
                        MUL_r32( R_ECX );
nkeynes@374
  1130
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1131
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1132
                        }
nkeynes@359
  1133
                        break;
nkeynes@359
  1134
                    case 0xF:
nkeynes@359
  1135
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1136
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1137
                        COUNT_INST(I_MULSW);
nkeynes@374
  1138
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1139
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1140
                        MUL_r32( R_ECX );
nkeynes@374
  1141
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1142
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1143
                        }
nkeynes@359
  1144
                        break;
nkeynes@359
  1145
                    default:
nkeynes@359
  1146
                        UNDEF();
nkeynes@359
  1147
                        break;
nkeynes@359
  1148
                }
nkeynes@359
  1149
                break;
nkeynes@359
  1150
            case 0x3:
nkeynes@359
  1151
                switch( ir&0xF ) {
nkeynes@359
  1152
                    case 0x0:
nkeynes@359
  1153
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1154
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1155
                        COUNT_INST(I_CMPEQ);
nkeynes@359
  1156
                        load_reg( R_EAX, Rm );
nkeynes@359
  1157
                        load_reg( R_ECX, Rn );
nkeynes@359
  1158
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1159
                        SETE_t();
nkeynes@417
  1160
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1161
                        }
nkeynes@359
  1162
                        break;
nkeynes@359
  1163
                    case 0x2:
nkeynes@359
  1164
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1165
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1166
                        COUNT_INST(I_CMPHS);
nkeynes@359
  1167
                        load_reg( R_EAX, Rm );
nkeynes@359
  1168
                        load_reg( R_ECX, Rn );
nkeynes@359
  1169
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1170
                        SETAE_t();
nkeynes@417
  1171
                        sh4_x86.tstate = TSTATE_AE;
nkeynes@359
  1172
                        }
nkeynes@359
  1173
                        break;
nkeynes@359
  1174
                    case 0x3:
nkeynes@359
  1175
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1176
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1177
                        COUNT_INST(I_CMPGE);
nkeynes@359
  1178
                        load_reg( R_EAX, Rm );
nkeynes@359
  1179
                        load_reg( R_ECX, Rn );
nkeynes@359
  1180
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1181
                        SETGE_t();
nkeynes@417
  1182
                        sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1183
                        }
nkeynes@359
  1184
                        break;
nkeynes@359
  1185
                    case 0x4:
nkeynes@359
  1186
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1187
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1188
                        COUNT_INST(I_DIV1);
nkeynes@386
  1189
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1190
                        load_reg( R_EAX, Rn );
nkeynes@417
  1191
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1192
                    	LDC_t();
nkeynes@417
  1193
                        }
nkeynes@386
  1194
                        RCL1_r32( R_EAX );
nkeynes@386
  1195
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1196
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
  1197
                        JE_rel8(mqequal);
nkeynes@386
  1198
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
  1199
                        JMP_rel8(end);
nkeynes@380
  1200
                        JMP_TARGET(mqequal);
nkeynes@386
  1201
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1202
                        JMP_TARGET(end);
nkeynes@386
  1203
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1204
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1205
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1206
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1207
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1208
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1209
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1210
                        store_spreg( R_EAX, R_T );
nkeynes@417
  1211
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1212
                        }
nkeynes@359
  1213
                        break;
nkeynes@359
  1214
                    case 0x5:
nkeynes@359
  1215
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1216
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1217
                        COUNT_INST(I_DMULU);
nkeynes@361
  1218
                        load_reg( R_EAX, Rm );
nkeynes@361
  1219
                        load_reg( R_ECX, Rn );
nkeynes@361
  1220
                        MUL_r32(R_ECX);
nkeynes@361
  1221
                        store_spreg( R_EDX, R_MACH );
nkeynes@417
  1222
                        store_spreg( R_EAX, R_MACL );    
nkeynes@417
  1223
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1224
                        }
nkeynes@359
  1225
                        break;
nkeynes@359
  1226
                    case 0x6:
nkeynes@359
  1227
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1228
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1229
                        COUNT_INST(I_CMPHI);
nkeynes@359
  1230
                        load_reg( R_EAX, Rm );
nkeynes@359
  1231
                        load_reg( R_ECX, Rn );
nkeynes@359
  1232
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1233
                        SETA_t();
nkeynes@417
  1234
                        sh4_x86.tstate = TSTATE_A;
nkeynes@359
  1235
                        }
nkeynes@359
  1236
                        break;
nkeynes@359
  1237
                    case 0x7:
nkeynes@359
  1238
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1239
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1240
                        COUNT_INST(I_CMPGT);
nkeynes@359
  1241
                        load_reg( R_EAX, Rm );
nkeynes@359
  1242
                        load_reg( R_ECX, Rn );
nkeynes@359
  1243
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1244
                        SETG_t();
nkeynes@417
  1245
                        sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1246
                        }
nkeynes@359
  1247
                        break;
nkeynes@359
  1248
                    case 0x8:
nkeynes@359
  1249
                        { /* SUB Rm, Rn */
nkeynes@359
  1250
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1251
                        COUNT_INST(I_SUB);
nkeynes@359
  1252
                        load_reg( R_EAX, Rm );
nkeynes@359
  1253
                        load_reg( R_ECX, Rn );
nkeynes@359
  1254
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1255
                        store_reg( R_ECX, Rn );
nkeynes@417
  1256
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1257
                        }
nkeynes@359
  1258
                        break;
nkeynes@359
  1259
                    case 0xA:
nkeynes@359
  1260
                        { /* SUBC Rm, Rn */
nkeynes@359
  1261
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1262
                        COUNT_INST(I_SUBC);
nkeynes@359
  1263
                        load_reg( R_EAX, Rm );
nkeynes@359
  1264
                        load_reg( R_ECX, Rn );
nkeynes@417
  1265
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1266
                    	LDC_t();
nkeynes@417
  1267
                        }
nkeynes@359
  1268
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1269
                        store_reg( R_ECX, Rn );
nkeynes@394
  1270
                        SETC_t();
nkeynes@417
  1271
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1272
                        }
nkeynes@359
  1273
                        break;
nkeynes@359
  1274
                    case 0xB:
nkeynes@359
  1275
                        { /* SUBV Rm, Rn */
nkeynes@359
  1276
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1277
                        COUNT_INST(I_SUBV);
nkeynes@359
  1278
                        load_reg( R_EAX, Rm );
nkeynes@359
  1279
                        load_reg( R_ECX, Rn );
nkeynes@359
  1280
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1281
                        store_reg( R_ECX, Rn );
nkeynes@359
  1282
                        SETO_t();
nkeynes@417
  1283
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1284
                        }
nkeynes@359
  1285
                        break;
nkeynes@359
  1286
                    case 0xC:
nkeynes@359
  1287
                        { /* ADD Rm, Rn */
nkeynes@359
  1288
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1289
                        COUNT_INST(I_ADD);
nkeynes@359
  1290
                        load_reg( R_EAX, Rm );
nkeynes@359
  1291
                        load_reg( R_ECX, Rn );
nkeynes@359
  1292
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1293
                        store_reg( R_ECX, Rn );
nkeynes@417
  1294
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1295
                        }
nkeynes@359
  1296
                        break;
nkeynes@359
  1297
                    case 0xD:
nkeynes@359
  1298
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1299
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1300
                        COUNT_INST(I_DMULS);
nkeynes@361
  1301
                        load_reg( R_EAX, Rm );
nkeynes@361
  1302
                        load_reg( R_ECX, Rn );
nkeynes@361
  1303
                        IMUL_r32(R_ECX);
nkeynes@361
  1304
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1305
                        store_spreg( R_EAX, R_MACL );
nkeynes@417
  1306
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1307
                        }
nkeynes@359
  1308
                        break;
nkeynes@359
  1309
                    case 0xE:
nkeynes@359
  1310
                        { /* ADDC Rm, Rn */
nkeynes@359
  1311
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1312
                        COUNT_INST(I_ADDC);
nkeynes@417
  1313
                        if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1314
                    	LDC_t();
nkeynes@417
  1315
                        }
nkeynes@359
  1316
                        load_reg( R_EAX, Rm );
nkeynes@359
  1317
                        load_reg( R_ECX, Rn );
nkeynes@359
  1318
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1319
                        store_reg( R_ECX, Rn );
nkeynes@359
  1320
                        SETC_t();
nkeynes@417
  1321
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1322
                        }
nkeynes@359
  1323
                        break;
nkeynes@359
  1324
                    case 0xF:
nkeynes@359
  1325
                        { /* ADDV Rm, Rn */
nkeynes@359
  1326
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  1327
                        COUNT_INST(I_ADDV);
nkeynes@359
  1328
                        load_reg( R_EAX, Rm );
nkeynes@359
  1329
                        load_reg( R_ECX, Rn );
nkeynes@359
  1330
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1331
                        store_reg( R_ECX, Rn );
nkeynes@359
  1332
                        SETO_t();
nkeynes@417
  1333
                        sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1334
                        }
nkeynes@359
  1335
                        break;
nkeynes@359
  1336
                    default:
nkeynes@359
  1337
                        UNDEF();
nkeynes@359
  1338
                        break;
nkeynes@359
  1339
                }
nkeynes@359
  1340
                break;
nkeynes@359
  1341
            case 0x4:
nkeynes@359
  1342
                switch( ir&0xF ) {
nkeynes@359
  1343
                    case 0x0:
nkeynes@359
  1344
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1345
                            case 0x0:
nkeynes@359
  1346
                                { /* SHLL Rn */
nkeynes@359
  1347
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1348
                                COUNT_INST(I_SHLL);
nkeynes@359
  1349
                                load_reg( R_EAX, Rn );
nkeynes@359
  1350
                                SHL1_r32( R_EAX );
nkeynes@397
  1351
                                SETC_t();
nkeynes@359
  1352
                                store_reg( R_EAX, Rn );
nkeynes@417
  1353
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1354
                                }
nkeynes@359
  1355
                                break;
nkeynes@359
  1356
                            case 0x1:
nkeynes@359
  1357
                                { /* DT Rn */
nkeynes@359
  1358
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1359
                                COUNT_INST(I_DT);
nkeynes@359
  1360
                                load_reg( R_EAX, Rn );
nkeynes@386
  1361
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1362
                                store_reg( R_EAX, Rn );
nkeynes@359
  1363
                                SETE_t();
nkeynes@417
  1364
                                sh4_x86.tstate = TSTATE_E;
nkeynes@359
  1365
                                }
nkeynes@359
  1366
                                break;
nkeynes@359
  1367
                            case 0x2:
nkeynes@359
  1368
                                { /* SHAL Rn */
nkeynes@359
  1369
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1370
                                COUNT_INST(I_SHAL);
nkeynes@359
  1371
                                load_reg( R_EAX, Rn );
nkeynes@359
  1372
                                SHL1_r32( R_EAX );
nkeynes@397
  1373
                                SETC_t();
nkeynes@359
  1374
                                store_reg( R_EAX, Rn );
nkeynes@417
  1375
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1376
                                }
nkeynes@359
  1377
                                break;
nkeynes@359
  1378
                            default:
nkeynes@359
  1379
                                UNDEF();
nkeynes@359
  1380
                                break;
nkeynes@359
  1381
                        }
nkeynes@359
  1382
                        break;
nkeynes@359
  1383
                    case 0x1:
nkeynes@359
  1384
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1385
                            case 0x0:
nkeynes@359
  1386
                                { /* SHLR Rn */
nkeynes@359
  1387
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1388
                                COUNT_INST(I_SHLR);
nkeynes@359
  1389
                                load_reg( R_EAX, Rn );
nkeynes@359
  1390
                                SHR1_r32( R_EAX );
nkeynes@397
  1391
                                SETC_t();
nkeynes@359
  1392
                                store_reg( R_EAX, Rn );
nkeynes@417
  1393
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1394
                                }
nkeynes@359
  1395
                                break;
nkeynes@359
  1396
                            case 0x1:
nkeynes@359
  1397
                                { /* CMP/PZ Rn */
nkeynes@359
  1398
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1399
                                COUNT_INST(I_CMPPZ);
nkeynes@359
  1400
                                load_reg( R_EAX, Rn );
nkeynes@359
  1401
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1402
                                SETGE_t();
nkeynes@417
  1403
                                sh4_x86.tstate = TSTATE_GE;
nkeynes@359
  1404
                                }
nkeynes@359
  1405
                                break;
nkeynes@359
  1406
                            case 0x2:
nkeynes@359
  1407
                                { /* SHAR Rn */
nkeynes@359
  1408
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1409
                                COUNT_INST(I_SHAR);
nkeynes@359
  1410
                                load_reg( R_EAX, Rn );
nkeynes@359
  1411
                                SAR1_r32( R_EAX );
nkeynes@397
  1412
                                SETC_t();
nkeynes@359
  1413
                                store_reg( R_EAX, Rn );
nkeynes@417
  1414
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1415
                                }
nkeynes@359
  1416
                                break;
nkeynes@359
  1417
                            default:
nkeynes@359
  1418
                                UNDEF();
nkeynes@359
  1419
                                break;
nkeynes@359
  1420
                        }
nkeynes@359
  1421
                        break;
nkeynes@359
  1422
                    case 0x2:
nkeynes@359
  1423
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1424
                            case 0x0:
nkeynes@359
  1425
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1426
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1427
                                COUNT_INST(I_STSM);
nkeynes@586
  1428
                                load_reg( R_EAX, Rn );
nkeynes@586
  1429
                                check_walign32( R_EAX );
nkeynes@586
  1430
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1431
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1432
                                load_spreg( R_EDX, R_MACH );
nkeynes@586
  1433
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1434
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1435
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1436
                                }
nkeynes@359
  1437
                                break;
nkeynes@359
  1438
                            case 0x1:
nkeynes@359
  1439
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1440
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1441
                                COUNT_INST(I_STSM);
nkeynes@586
  1442
                                load_reg( R_EAX, Rn );
nkeynes@586
  1443
                                check_walign32( R_EAX );
nkeynes@586
  1444
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1445
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1446
                                load_spreg( R_EDX, R_MACL );
nkeynes@586
  1447
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1448
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1449
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1450
                                }
nkeynes@359
  1451
                                break;
nkeynes@359
  1452
                            case 0x2:
nkeynes@359
  1453
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1454
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1455
                                COUNT_INST(I_STSM);
nkeynes@586
  1456
                                load_reg( R_EAX, Rn );
nkeynes@586
  1457
                                check_walign32( R_EAX );
nkeynes@586
  1458
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1459
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1460
                                load_spreg( R_EDX, R_PR );
nkeynes@586
  1461
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1462
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1463
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1464
                                }
nkeynes@359
  1465
                                break;
nkeynes@359
  1466
                            case 0x3:
nkeynes@359
  1467
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1468
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1469
                                COUNT_INST(I_STCM);
nkeynes@586
  1470
                                check_priv();
nkeynes@586
  1471
                                load_reg( R_EAX, Rn );
nkeynes@586
  1472
                                check_walign32( R_EAX );
nkeynes@586
  1473
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1474
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1475
                                load_spreg( R_EDX, R_SGR );
nkeynes@586
  1476
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1477
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1478
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1479
                                }
nkeynes@359
  1480
                                break;
nkeynes@359
  1481
                            case 0x5:
nkeynes@359
  1482
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1483
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1484
                                COUNT_INST(I_STSM);
nkeynes@626
  1485
                                check_fpuen();
nkeynes@586
  1486
                                load_reg( R_EAX, Rn );
nkeynes@586
  1487
                                check_walign32( R_EAX );
nkeynes@586
  1488
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1489
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1490
                                load_spreg( R_EDX, R_FPUL );
nkeynes@586
  1491
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1492
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1493
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1494
                                }
nkeynes@359
  1495
                                break;
nkeynes@359
  1496
                            case 0x6:
nkeynes@359
  1497
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1498
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@673
  1499
                                COUNT_INST(I_STSFPSCRM);
nkeynes@626
  1500
                                check_fpuen();
nkeynes@586
  1501
                                load_reg( R_EAX, Rn );
nkeynes@586
  1502
                                check_walign32( R_EAX );
nkeynes@586
  1503
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1504
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1505
                                load_spreg( R_EDX, R_FPSCR );
nkeynes@586
  1506
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1507
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1508
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1509
                                }
nkeynes@359
  1510
                                break;
nkeynes@359
  1511
                            case 0xF:
nkeynes@359
  1512
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1513
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1514
                                COUNT_INST(I_STCM);
nkeynes@586
  1515
                                check_priv();
nkeynes@586
  1516
                                load_reg( R_EAX, Rn );
nkeynes@586
  1517
                                check_walign32( R_EAX );
nkeynes@586
  1518
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1519
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1520
                                load_spreg( R_EDX, R_DBR );
nkeynes@586
  1521
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1522
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1523
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1524
                                }
nkeynes@359
  1525
                                break;
nkeynes@359
  1526
                            default:
nkeynes@359
  1527
                                UNDEF();
nkeynes@359
  1528
                                break;
nkeynes@359
  1529
                        }
nkeynes@359
  1530
                        break;
nkeynes@359
  1531
                    case 0x3:
nkeynes@359
  1532
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1533
                            case 0x0:
nkeynes@359
  1534
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1535
                                    case 0x0:
nkeynes@359
  1536
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1537
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1538
                                        COUNT_INST(I_STCSRM);
nkeynes@586
  1539
                                        check_priv();
nkeynes@586
  1540
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1541
                                        check_walign32( R_EAX );
nkeynes@586
  1542
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1543
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1544
                                        PUSH_realigned_r32( R_EAX );
nkeynes@395
  1545
                                        call_func0( sh4_read_sr );
nkeynes@586
  1546
                                        POP_realigned_r32( R_ECX );
nkeynes@586
  1547
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@374
  1548
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  1549
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1550
                                        }
nkeynes@359
  1551
                                        break;
nkeynes@359
  1552
                                    case 0x1:
nkeynes@359
  1553
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1554
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1555
                                        COUNT_INST(I_STCM);
nkeynes@586
  1556
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1557
                                        check_walign32( R_EAX );
nkeynes@586
  1558
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1559
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1560
                                        load_spreg( R_EDX, R_GBR );
nkeynes@586
  1561
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1562
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1563
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1564
                                        }
nkeynes@359
  1565
                                        break;
nkeynes@359
  1566
                                    case 0x2:
nkeynes@359
  1567
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1568
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1569
                                        COUNT_INST(I_STCM);
nkeynes@586
  1570
                                        check_priv();
nkeynes@586
  1571
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1572
                                        check_walign32( R_EAX );
nkeynes@586
  1573
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1574
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1575
                                        load_spreg( R_EDX, R_VBR );
nkeynes@586
  1576
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1577
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1578
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1579
                                        }
nkeynes@359
  1580
                                        break;
nkeynes@359
  1581
                                    case 0x3:
nkeynes@359
  1582
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1583
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1584
                                        COUNT_INST(I_STCM);
nkeynes@586
  1585
                                        check_priv();
nkeynes@586
  1586
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1587
                                        check_walign32( R_EAX );
nkeynes@586
  1588
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1589
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1590
                                        load_spreg( R_EDX, R_SSR );
nkeynes@586
  1591
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1592
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1593
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1594
                                        }
nkeynes@359
  1595
                                        break;
nkeynes@359
  1596
                                    case 0x4:
nkeynes@359
  1597
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1598
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1599
                                        COUNT_INST(I_STCM);
nkeynes@586
  1600
                                        check_priv();
nkeynes@586
  1601
                                        load_reg( R_EAX, Rn );
nkeynes@586
  1602
                                        check_walign32( R_EAX );
nkeynes@586
  1603
                                        ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1604
                                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1605
                                        load_spreg( R_EDX, R_SPC );
nkeynes@586
  1606
                                        ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1607
                                        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1608
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1609
                                        }
nkeynes@359
  1610
                                        break;
nkeynes@359
  1611
                                    default:
nkeynes@359
  1612
                                        UNDEF();
nkeynes@359
  1613
                                        break;
nkeynes@359
  1614
                                }
nkeynes@359
  1615
                                break;
nkeynes@359
  1616
                            case 0x1:
nkeynes@359
  1617
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1618
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@671
  1619
                                COUNT_INST(I_STCM);
nkeynes@586
  1620
                                check_priv();
nkeynes@586
  1621
                                load_reg( R_EAX, Rn );
nkeynes@586
  1622
                                check_walign32( R_EAX );
nkeynes@586
  1623
                                ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1624
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1625
                                load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  1626
                                ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1627
                                MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1628
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1629
                                }
nkeynes@359
  1630
                                break;
nkeynes@359
  1631
                        }
nkeynes@359
  1632
                        break;
nkeynes@359
  1633
                    case 0x4:
nkeynes@359
  1634
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1635
                            case 0x0:
nkeynes@359
  1636
                                { /* ROTL Rn */
nkeynes@359
  1637
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1638
                                COUNT_INST(I_ROTL);
nkeynes@359
  1639
                                load_reg( R_EAX, Rn );
nkeynes@359
  1640
                                ROL1_r32( R_EAX );
nkeynes@359
  1641
                                store_reg( R_EAX, Rn );
nkeynes@359
  1642
                                SETC_t();
nkeynes@417
  1643
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1644
                                }
nkeynes@359
  1645
                                break;
nkeynes@359
  1646
                            case 0x2:
nkeynes@359
  1647
                                { /* ROTCL Rn */
nkeynes@359
  1648
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1649
                                COUNT_INST(I_ROTCL);
nkeynes@359
  1650
                                load_reg( R_EAX, Rn );
nkeynes@417
  1651
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1652
                            	LDC_t();
nkeynes@417
  1653
                                }
nkeynes@359
  1654
                                RCL1_r32( R_EAX );
nkeynes@359
  1655
                                store_reg( R_EAX, Rn );
nkeynes@359
  1656
                                SETC_t();
nkeynes@417
  1657
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1658
                                }
nkeynes@359
  1659
                                break;
nkeynes@359
  1660
                            default:
nkeynes@359
  1661
                                UNDEF();
nkeynes@359
  1662
                                break;
nkeynes@359
  1663
                        }
nkeynes@359
  1664
                        break;
nkeynes@359
  1665
                    case 0x5:
nkeynes@359
  1666
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1667
                            case 0x0:
nkeynes@359
  1668
                                { /* ROTR Rn */
nkeynes@359
  1669
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1670
                                COUNT_INST(I_ROTR);
nkeynes@359
  1671
                                load_reg( R_EAX, Rn );
nkeynes@359
  1672
                                ROR1_r32( R_EAX );
nkeynes@359
  1673
                                store_reg( R_EAX, Rn );
nkeynes@359
  1674
                                SETC_t();
nkeynes@417
  1675
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1676
                                }
nkeynes@359
  1677
                                break;
nkeynes@359
  1678
                            case 0x1:
nkeynes@359
  1679
                                { /* CMP/PL Rn */
nkeynes@359
  1680
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1681
                                COUNT_INST(I_CMPPL);
nkeynes@359
  1682
                                load_reg( R_EAX, Rn );
nkeynes@359
  1683
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1684
                                SETG_t();
nkeynes@417
  1685
                                sh4_x86.tstate = TSTATE_G;
nkeynes@359
  1686
                                }
nkeynes@359
  1687
                                break;
nkeynes@359
  1688
                            case 0x2:
nkeynes@359
  1689
                                { /* ROTCR Rn */
nkeynes@359
  1690
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1691
                                COUNT_INST(I_ROTCR);
nkeynes@359
  1692
                                load_reg( R_EAX, Rn );
nkeynes@417
  1693
                                if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1694
                            	LDC_t();
nkeynes@417
  1695
                                }
nkeynes@359
  1696
                                RCR1_r32( R_EAX );
nkeynes@359
  1697
                                store_reg( R_EAX, Rn );
nkeynes@359
  1698
                                SETC_t();
nkeynes@417
  1699
                                sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1700
                                }
nkeynes@359
  1701
                                break;
nkeynes@359
  1702
                            default:
nkeynes@359
  1703
                                UNDEF();
nkeynes@359
  1704
                                break;
nkeynes@359
  1705
                        }
nkeynes@359
  1706
                        break;
nkeynes@359
  1707
                    case 0x6:
nkeynes@359
  1708
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1709
                            case 0x0:
nkeynes@359
  1710
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1711
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1712
                                COUNT_INST(I_LDSM);
nkeynes@359
  1713
                                load_reg( R_EAX, Rm );
nkeynes@395
  1714
                                check_ralign32( R_EAX );
nkeynes@586
  1715
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1716
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1717
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1718
                                store_spreg( R_EAX, R_MACH );
nkeynes@417
  1719
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1720
                                }
nkeynes@359
  1721
                                break;
nkeynes@359
  1722
                            case 0x1:
nkeynes@359
  1723
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1724
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1725
                                COUNT_INST(I_LDSM);
nkeynes@359
  1726
                                load_reg( R_EAX, Rm );
nkeynes@395
  1727
                                check_ralign32( R_EAX );
nkeynes@586
  1728
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1729
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1730
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1731
                                store_spreg( R_EAX, R_MACL );
nkeynes@417
  1732
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1733
                                }
nkeynes@359
  1734
                                break;
nkeynes@359
  1735
                            case 0x2:
nkeynes@359
  1736
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1737
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1738
                                COUNT_INST(I_LDSM);
nkeynes@359
  1739
                                load_reg( R_EAX, Rm );
nkeynes@395
  1740
                                check_ralign32( R_EAX );
nkeynes@586
  1741
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1742
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1743
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1744
                                store_spreg( R_EAX, R_PR );
nkeynes@417
  1745
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1746
                                }
nkeynes@359
  1747
                                break;
nkeynes@359
  1748
                            case 0x3:
nkeynes@359
  1749
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1750
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1751
                                COUNT_INST(I_LDCM);
nkeynes@586
  1752
                                check_priv();
nkeynes@359
  1753
                                load_reg( R_EAX, Rm );
nkeynes@395
  1754
                                check_ralign32( R_EAX );
nkeynes@586
  1755
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1756
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1757
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1758
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  1759
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1760
                                }
nkeynes@359
  1761
                                break;
nkeynes@359
  1762
                            case 0x5:
nkeynes@359
  1763
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1764
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1765
                                COUNT_INST(I_LDSM);
nkeynes@626
  1766
                                check_fpuen();
nkeynes@359
  1767
                                load_reg( R_EAX, Rm );
nkeynes@395
  1768
                                check_ralign32( R_EAX );
nkeynes@586
  1769
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1770
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1771
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1772
                                store_spreg( R_EAX, R_FPUL );
nkeynes@417
  1773
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1774
                                }
nkeynes@359
  1775
                                break;
nkeynes@359
  1776
                            case 0x6:
nkeynes@359
  1777
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1778
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@673
  1779
                                COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  1780
                                check_fpuen();
nkeynes@359
  1781
                                load_reg( R_EAX, Rm );
nkeynes@395
  1782
                                check_ralign32( R_EAX );
nkeynes@586
  1783
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1784
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1785
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1786
                                call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  1787
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1788
                                }
nkeynes@359
  1789
                                break;
nkeynes@359
  1790
                            case 0xF:
nkeynes@359
  1791
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1792
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1793
                                COUNT_INST(I_LDCM);
nkeynes@586
  1794
                                check_priv();
nkeynes@359
  1795
                                load_reg( R_EAX, Rm );
nkeynes@395
  1796
                                check_ralign32( R_EAX );
nkeynes@586
  1797
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1798
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1799
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1800
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  1801
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1802
                                }
nkeynes@359
  1803
                                break;
nkeynes@359
  1804
                            default:
nkeynes@359
  1805
                                UNDEF();
nkeynes@359
  1806
                                break;
nkeynes@359
  1807
                        }
nkeynes@359
  1808
                        break;
nkeynes@359
  1809
                    case 0x7:
nkeynes@359
  1810
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1811
                            case 0x0:
nkeynes@359
  1812
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1813
                                    case 0x0:
nkeynes@359
  1814
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1815
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1816
                                        COUNT_INST(I_LDCSRM);
nkeynes@386
  1817
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1818
                                    	SLOTILLEGAL();
nkeynes@386
  1819
                                        } else {
nkeynes@586
  1820
                                    	check_priv();
nkeynes@386
  1821
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1822
                                    	check_ralign32( R_EAX );
nkeynes@586
  1823
                                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1824
                                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1825
                                    	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  1826
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1827
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1828
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1829
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  1830
                                        }
nkeynes@359
  1831
                                        }
nkeynes@359
  1832
                                        break;
nkeynes@359
  1833
                                    case 0x1:
nkeynes@359
  1834
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1835
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1836
                                        COUNT_INST(I_LDCM);
nkeynes@359
  1837
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1838
                                        check_ralign32( R_EAX );
nkeynes@586
  1839
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1840
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1841
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1842
                                        store_spreg( R_EAX, R_GBR );
nkeynes@417
  1843
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1844
                                        }
nkeynes@359
  1845
                                        break;
nkeynes@359
  1846
                                    case 0x2:
nkeynes@359
  1847
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1848
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1849
                                        COUNT_INST(I_LDCM);
nkeynes@586
  1850
                                        check_priv();
nkeynes@359
  1851
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1852
                                        check_ralign32( R_EAX );
nkeynes@586
  1853
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1854
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1855
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1856
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  1857
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1858
                                        }
nkeynes@359
  1859
                                        break;
nkeynes@359
  1860
                                    case 0x3:
nkeynes@359
  1861
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1862
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1863
                                        COUNT_INST(I_LDCM);
nkeynes@586
  1864
                                        check_priv();
nkeynes@359
  1865
                                        load_reg( R_EAX, Rm );
nkeynes@416
  1866
                                        check_ralign32( R_EAX );
nkeynes@586
  1867
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1868
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1869
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1870
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  1871
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1872
                                        }
nkeynes@359
  1873
                                        break;
nkeynes@359
  1874
                                    case 0x4:
nkeynes@359
  1875
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1876
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1877
                                        COUNT_INST(I_LDCM);
nkeynes@586
  1878
                                        check_priv();
nkeynes@359
  1879
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1880
                                        check_ralign32( R_EAX );
nkeynes@586
  1881
                                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1882
                                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1883
                                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  1884
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  1885
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1886
                                        }
nkeynes@359
  1887
                                        break;
nkeynes@359
  1888
                                    default:
nkeynes@359
  1889
                                        UNDEF();
nkeynes@359
  1890
                                        break;
nkeynes@359
  1891
                                }
nkeynes@359
  1892
                                break;
nkeynes@359
  1893
                            case 0x1:
nkeynes@359
  1894
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1895
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@671
  1896
                                COUNT_INST(I_LDCM);
nkeynes@586
  1897
                                check_priv();
nkeynes@374
  1898
                                load_reg( R_EAX, Rm );
nkeynes@395
  1899
                                check_ralign32( R_EAX );
nkeynes@586
  1900
                                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1901
                                ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1902
                                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  1903
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  1904
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1905
                                }
nkeynes@359
  1906
                                break;
nkeynes@359
  1907
                        }
nkeynes@359
  1908
                        break;
nkeynes@359
  1909
                    case 0x8:
nkeynes@359
  1910
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1911
                            case 0x0:
nkeynes@359
  1912
                                { /* SHLL2 Rn */
nkeynes@359
  1913
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1914
                                COUNT_INST(I_SHLL);
nkeynes@359
  1915
                                load_reg( R_EAX, Rn );
nkeynes@359
  1916
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1917
                                store_reg( R_EAX, Rn );
nkeynes@417
  1918
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1919
                                }
nkeynes@359
  1920
                                break;
nkeynes@359
  1921
                            case 0x1:
nkeynes@359
  1922
                                { /* SHLL8 Rn */
nkeynes@359
  1923
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1924
                                COUNT_INST(I_SHLL);
nkeynes@359
  1925
                                load_reg( R_EAX, Rn );
nkeynes@359
  1926
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1927
                                store_reg( R_EAX, Rn );
nkeynes@417
  1928
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1929
                                }
nkeynes@359
  1930
                                break;
nkeynes@359
  1931
                            case 0x2:
nkeynes@359
  1932
                                { /* SHLL16 Rn */
nkeynes@359
  1933
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1934
                                COUNT_INST(I_SHLL);
nkeynes@359
  1935
                                load_reg( R_EAX, Rn );
nkeynes@359
  1936
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1937
                                store_reg( R_EAX, Rn );
nkeynes@417
  1938
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1939
                                }
nkeynes@359
  1940
                                break;
nkeynes@359
  1941
                            default:
nkeynes@359
  1942
                                UNDEF();
nkeynes@359
  1943
                                break;
nkeynes@359
  1944
                        }
nkeynes@359
  1945
                        break;
nkeynes@359
  1946
                    case 0x9:
nkeynes@359
  1947
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1948
                            case 0x0:
nkeynes@359
  1949
                                { /* SHLR2 Rn */
nkeynes@359
  1950
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1951
                                COUNT_INST(I_SHLR);
nkeynes@359
  1952
                                load_reg( R_EAX, Rn );
nkeynes@359
  1953
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1954
                                store_reg( R_EAX, Rn );
nkeynes@417
  1955
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1956
                                }
nkeynes@359
  1957
                                break;
nkeynes@359
  1958
                            case 0x1:
nkeynes@359
  1959
                                { /* SHLR8 Rn */
nkeynes@359
  1960
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1961
                                COUNT_INST(I_SHLR);
nkeynes@359
  1962
                                load_reg( R_EAX, Rn );
nkeynes@359
  1963
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1964
                                store_reg( R_EAX, Rn );
nkeynes@417
  1965
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1966
                                }
nkeynes@359
  1967
                                break;
nkeynes@359
  1968
                            case 0x2:
nkeynes@359
  1969
                                { /* SHLR16 Rn */
nkeynes@359
  1970
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  1971
                                COUNT_INST(I_SHLR);
nkeynes@359
  1972
                                load_reg( R_EAX, Rn );
nkeynes@359
  1973
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1974
                                store_reg( R_EAX, Rn );
nkeynes@417
  1975
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1976
                                }
nkeynes@359
  1977
                                break;
nkeynes@359
  1978
                            default:
nkeynes@359
  1979
                                UNDEF();
nkeynes@359
  1980
                                break;
nkeynes@359
  1981
                        }
nkeynes@359
  1982
                        break;
nkeynes@359
  1983
                    case 0xA:
nkeynes@359
  1984
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1985
                            case 0x0:
nkeynes@359
  1986
                                { /* LDS Rm, MACH */
nkeynes@359
  1987
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1988
                                COUNT_INST(I_LDS);
nkeynes@359
  1989
                                load_reg( R_EAX, Rm );
nkeynes@359
  1990
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1991
                                }
nkeynes@359
  1992
                                break;
nkeynes@359
  1993
                            case 0x1:
nkeynes@359
  1994
                                { /* LDS Rm, MACL */
nkeynes@359
  1995
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  1996
                                COUNT_INST(I_LDS);
nkeynes@359
  1997
                                load_reg( R_EAX, Rm );
nkeynes@359
  1998
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1999
                                }
nkeynes@359
  2000
                                break;
nkeynes@359
  2001
                            case 0x2:
nkeynes@359
  2002
                                { /* LDS Rm, PR */
nkeynes@359
  2003
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2004
                                COUNT_INST(I_LDS);
nkeynes@359
  2005
                                load_reg( R_EAX, Rm );
nkeynes@359
  2006
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  2007
                                }
nkeynes@359
  2008
                                break;
nkeynes@359
  2009
                            case 0x3:
nkeynes@359
  2010
                                { /* LDC Rm, SGR */
nkeynes@359
  2011
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2012
                                COUNT_INST(I_LDC);
nkeynes@386
  2013
                                check_priv();
nkeynes@359
  2014
                                load_reg( R_EAX, Rm );
nkeynes@359
  2015
                                store_spreg( R_EAX, R_SGR );
nkeynes@417
  2016
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2017
                                }
nkeynes@359
  2018
                                break;
nkeynes@359
  2019
                            case 0x5:
nkeynes@359
  2020
                                { /* LDS Rm, FPUL */
nkeynes@359
  2021
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2022
                                COUNT_INST(I_LDS);
nkeynes@626
  2023
                                check_fpuen();
nkeynes@359
  2024
                                load_reg( R_EAX, Rm );
nkeynes@359
  2025
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2026
                                }
nkeynes@359
  2027
                                break;
nkeynes@359
  2028
                            case 0x6:
nkeynes@359
  2029
                                { /* LDS Rm, FPSCR */
nkeynes@359
  2030
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@673
  2031
                                COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2032
                                check_fpuen();
nkeynes@359
  2033
                                load_reg( R_EAX, Rm );
nkeynes@669
  2034
                                call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2035
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2036
                                }
nkeynes@359
  2037
                                break;
nkeynes@359
  2038
                            case 0xF:
nkeynes@359
  2039
                                { /* LDC Rm, DBR */
nkeynes@359
  2040
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2041
                                COUNT_INST(I_LDC);
nkeynes@386
  2042
                                check_priv();
nkeynes@359
  2043
                                load_reg( R_EAX, Rm );
nkeynes@359
  2044
                                store_spreg( R_EAX, R_DBR );
nkeynes@417
  2045
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2046
                                }
nkeynes@359
  2047
                                break;
nkeynes@359
  2048
                            default:
nkeynes@359
  2049
                                UNDEF();
nkeynes@359
  2050
                                break;
nkeynes@359
  2051
                        }
nkeynes@359
  2052
                        break;
nkeynes@359
  2053
                    case 0xB:
nkeynes@359
  2054
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2055
                            case 0x0:
nkeynes@359
  2056
                                { /* JSR @Rn */
nkeynes@359
  2057
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  2058
                                COUNT_INST(I_JSR);
nkeynes@374
  2059
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2060
                            	SLOTILLEGAL();
nkeynes@374
  2061
                                } else {
nkeynes@590
  2062
                            	load_spreg( R_EAX, R_PC );
nkeynes@590
  2063
                            	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  2064
                            	store_spreg( R_EAX, R_PR );
nkeynes@408
  2065
                            	load_reg( R_ECX, Rn );
nkeynes@590
  2066
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  2067
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2068
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2069
                            	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  2070
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2071
                            	    exit_block_emu(pc+2);
nkeynes@601
  2072
                            	    return 2;
nkeynes@601
  2073
                            	} else {
nkeynes@601
  2074
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
  2075
                            	    exit_block_newpcset(pc+2);
nkeynes@601
  2076
                            	    return 4;
nkeynes@601
  2077
                            	}
nkeynes@374
  2078
                                }
nkeynes@359
  2079
                                }
nkeynes@359
  2080
                                break;
nkeynes@359
  2081
                            case 0x1:
nkeynes@359
  2082
                                { /* TAS.B @Rn */
nkeynes@359
  2083
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  2084
                                COUNT_INST(I_TASB);
nkeynes@586
  2085
                                load_reg( R_EAX, Rn );
nkeynes@586
  2086
                                MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2087
                                PUSH_realigned_r32( R_EAX );
nkeynes@586
  2088
                                MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  2089
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  2090
                                SETE_t();
nkeynes@361
  2091
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  2092
                                POP_realigned_r32( R_ECX );
nkeynes@361
  2093
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  2094
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2095
                                }
nkeynes@359
  2096
                                break;
nkeynes@359
  2097
                            case 0x2:
nkeynes@359
  2098
                                { /* JMP @Rn */
nkeynes@359
  2099
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@671
  2100
                                COUNT_INST(I_JMP);
nkeynes@374
  2101
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2102
                            	SLOTILLEGAL();
nkeynes@374
  2103
                                } else {
nkeynes@408
  2104
                            	load_reg( R_ECX, Rn );
nkeynes@590
  2105
                            	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  2106
                            	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  2107
                            	sh4_x86.branch_taken = TRUE;
nkeynes@601
  2108
                            	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2109
                            	    exit_block_emu(pc+2);
nkeynes@601
  2110
                            	    return 2;
nkeynes@601
  2111
                            	} else {
nkeynes@601
  2112
                            	    sh4_translate_instruction(pc+2);
nkeynes@601
  2113
                            	    exit_block_newpcset(pc+2);
nkeynes@601
  2114
                            	    return 4;
nkeynes@601
  2115
                            	}
nkeynes@374
  2116
                                }
nkeynes@359
  2117
                                }
nkeynes@359
  2118
                                break;
nkeynes@359
  2119
                            default:
nkeynes@359
  2120
                                UNDEF();
nkeynes@359
  2121
                                break;
nkeynes@359
  2122
                        }
nkeynes@359
  2123
                        break;
nkeynes@359
  2124
                    case 0xC:
nkeynes@359
  2125
                        { /* SHAD Rm, Rn */
nkeynes@359
  2126
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2127
                        COUNT_INST(I_SHAD);
nkeynes@359
  2128
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  2129
                        load_reg( R_EAX, Rn );
nkeynes@361
  2130
                        load_reg( R_ECX, Rm );
nkeynes@361
  2131
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@669
  2132
                        JGE_rel8(doshl);
nkeynes@361
  2133
                                        
nkeynes@361
  2134
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  2135
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
  2136
                        JE_rel8(emptysar);     // 2
nkeynes@361
  2137
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@669
  2138
                        JMP_rel8(end);          // 2
nkeynes@386
  2139
                    
nkeynes@386
  2140
                        JMP_TARGET(emptysar);
nkeynes@386
  2141
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
  2142
                        JMP_rel8(end2);
nkeynes@386
  2143
                    
nkeynes@380
  2144
                        JMP_TARGET(doshl);
nkeynes@361
  2145
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  2146
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  2147
                        JMP_TARGET(end);
nkeynes@386
  2148
                        JMP_TARGET(end2);
nkeynes@361
  2149
                        store_reg( R_EAX, Rn );
nkeynes@417
  2150
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2151
                        }
nkeynes@359
  2152
                        break;
nkeynes@359
  2153
                    case 0xD:
nkeynes@359
  2154
                        { /* SHLD Rm, Rn */
nkeynes@359
  2155
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2156
                        COUNT_INST(I_SHLD);
nkeynes@368
  2157
                        load_reg( R_EAX, Rn );
nkeynes@368
  2158
                        load_reg( R_ECX, Rm );
nkeynes@386
  2159
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@669
  2160
                        JGE_rel8(doshl);
nkeynes@368
  2161
                    
nkeynes@386
  2162
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  2163
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
  2164
                        JE_rel8(emptyshr );
nkeynes@386
  2165
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@669
  2166
                        JMP_rel8(end);          // 2
nkeynes@386
  2167
                    
nkeynes@386
  2168
                        JMP_TARGET(emptyshr);
nkeynes@386
  2169
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  2170
                        JMP_rel8(end2);
nkeynes@386
  2171
                    
nkeynes@386
  2172
                        JMP_TARGET(doshl);
nkeynes@386
  2173
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  2174
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  2175
                        JMP_TARGET(end);
nkeynes@386
  2176
                        JMP_TARGET(end2);
nkeynes@368
  2177
                        store_reg( R_EAX, Rn );
nkeynes@417
  2178
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2179
                        }
nkeynes@359
  2180
                        break;
nkeynes@359
  2181
                    case 0xE:
nkeynes@359
  2182
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  2183
                            case 0x0:
nkeynes@359
  2184
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  2185
                                    case 0x0:
nkeynes@359
  2186
                                        { /* LDC Rm, SR */
nkeynes@359
  2187
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2188
                                        COUNT_INST(I_LDCSR);
nkeynes@386
  2189
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2190
                                    	SLOTILLEGAL();
nkeynes@386
  2191
                                        } else {
nkeynes@386
  2192
                                    	check_priv();
nkeynes@386
  2193
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  2194
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2195
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2196
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2197
                                    	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2198
                                        }
nkeynes@359
  2199
                                        }
nkeynes@359
  2200
                                        break;
nkeynes@359
  2201
                                    case 0x1:
nkeynes@359
  2202
                                        { /* LDC Rm, GBR */
nkeynes@359
  2203
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2204
                                        COUNT_INST(I_LDC);
nkeynes@359
  2205
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2206
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  2207
                                        }
nkeynes@359
  2208
                                        break;
nkeynes@359
  2209
                                    case 0x2:
nkeynes@359
  2210
                                        { /* LDC Rm, VBR */
nkeynes@359
  2211
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2212
                                        COUNT_INST(I_LDC);
nkeynes@386
  2213
                                        check_priv();
nkeynes@359
  2214
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2215
                                        store_spreg( R_EAX, R_VBR );
nkeynes@417
  2216
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2217
                                        }
nkeynes@359
  2218
                                        break;
nkeynes@359
  2219
                                    case 0x3:
nkeynes@359
  2220
                                        { /* LDC Rm, SSR */
nkeynes@359
  2221
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2222
                                        COUNT_INST(I_LDC);
nkeynes@386
  2223
                                        check_priv();
nkeynes@359
  2224
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2225
                                        store_spreg( R_EAX, R_SSR );
nkeynes@417
  2226
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2227
                                        }
nkeynes@359
  2228
                                        break;
nkeynes@359
  2229
                                    case 0x4:
nkeynes@359
  2230
                                        { /* LDC Rm, SPC */
nkeynes@359
  2231
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@671
  2232
                                        COUNT_INST(I_LDC);
nkeynes@386
  2233
                                        check_priv();
nkeynes@359
  2234
                                        load_reg( R_EAX, Rm );
nkeynes@359
  2235
                                        store_spreg( R_EAX, R_SPC );
nkeynes@417
  2236
                                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2237
                                        }
nkeynes@359
  2238
                                        break;
nkeynes@359
  2239
                                    default:
nkeynes@359
  2240
                                        UNDEF();
nkeynes@359
  2241
                                        break;
nkeynes@359
  2242
                                }
nkeynes@359
  2243
                                break;
nkeynes@359
  2244
                            case 0x1:
nkeynes@359
  2245
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  2246
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@671
  2247
                                COUNT_INST(I_LDC);
nkeynes@386
  2248
                                check_priv();
nkeynes@374
  2249
                                load_reg( R_EAX, Rm );
nkeynes@374
  2250
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2251
                                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2252
                                }
nkeynes@359
  2253
                                break;
nkeynes@359
  2254
                        }
nkeynes@359
  2255
                        break;
nkeynes@359
  2256
                    case 0xF:
nkeynes@359
  2257
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  2258
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2259
                        COUNT_INST(I_MACW);
nkeynes@586
  2260
                        if( Rm == Rn ) {
nkeynes@586
  2261
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2262
                    	check_ralign16( R_EAX );
nkeynes@586
  2263
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2264
                    	PUSH_realigned_r32( R_EAX );
nkeynes@586
  2265
                    	load_reg( R_EAX, Rn );
nkeynes@586
  2266
                    	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
  2267
                    	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
  2268
                    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2269
                    	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
  2270
                    	// adding a page-boundary check to skip the second translation
nkeynes@586
  2271
                        } else {
nkeynes@586
  2272
                    	load_reg( R_EAX, Rm );
nkeynes@586
  2273
                    	check_ralign16( R_EAX );
nkeynes@586
  2274
                    	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
  2275
                    	load_reg( R_ECX, Rn );
nkeynes@596
  2276
                    	check_ralign16( R_ECX );
nkeynes@586
  2277
                    	PUSH_realigned_r32( R_EAX );
nkeynes@596
  2278
                    	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
  2279
                    	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
  2280
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
  2281
                    	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2282
                        }
nkeynes@586
  2283
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  2284
                        POP_r32( R_ECX );
nkeynes@586
  2285
                        PUSH_r32( R_EAX );
nkeynes@386
  2286
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
  2287
                        POP_realigned_r32( R_ECX );
nkeynes@386
  2288
                        IMUL_r32( R_ECX );
nkeynes@386
  2289
                    
nkeynes@386
  2290
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2291
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
  2292
                        JE_rel8( nosat );
nkeynes@386
  2293
                    
nkeynes@386
  2294
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
  2295
                        JNO_rel8( end );            // 2
nkeynes@386
  2296
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2297
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
  2298
                        JS_rel8( positive );        // 2
nkeynes@386
  2299
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2300
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
  2301
                        JMP_rel8(end2);           // 2
nkeynes@386
  2302
                    
nkeynes@386
  2303
                        JMP_TARGET(positive);
nkeynes@386
  2304
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2305
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
  2306
                        JMP_rel8(end3);            // 2
nkeynes@386
  2307
                    
nkeynes@386
  2308
                        JMP_TARGET(nosat);
nkeynes@386
  2309
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2310
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2311
                        JMP_TARGET(end);
nkeynes@386
  2312
                        JMP_TARGET(end2);
nkeynes@386
  2313
                        JMP_TARGET(end3);
nkeynes@417
  2314
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2315
                        }
nkeynes@359
  2316
                        break;
nkeynes@359
  2317
                }
nkeynes@359
  2318
                break;
nkeynes@359
  2319
            case 0x5:
nkeynes@359
  2320
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2321
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@671
  2322
                COUNT_INST(I_MOVL);
nkeynes@586
  2323
                load_reg( R_EAX, Rm );
nkeynes@586
  2324
                ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  2325
                check_ralign32( R_EAX );
nkeynes@586
  2326
                MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2327
                MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2328
                store_reg( R_EAX, Rn );
nkeynes@417
  2329
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2330
                }
nkeynes@359
  2331
                break;
nkeynes@359
  2332
            case 0x6:
nkeynes@359
  2333
                switch( ir&0xF ) {
nkeynes@359
  2334
                    case 0x0:
nkeynes@359
  2335
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2336
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2337
                        COUNT_INST(I_MOVB);
nkeynes@586
  2338
                        load_reg( R_EAX, Rm );
nkeynes@586
  2339
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2340
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  2341
                        store_reg( R_EAX, Rn );
nkeynes@417
  2342
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2343
                        }
nkeynes@359
  2344
                        break;
nkeynes@359
  2345
                    case 0x1:
nkeynes@359
  2346
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2347
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2348
                        COUNT_INST(I_MOVW);
nkeynes@586
  2349
                        load_reg( R_EAX, Rm );
nkeynes@586
  2350
                        check_ralign16( R_EAX );
nkeynes@586
  2351
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2352
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2353
                        store_reg( R_EAX, Rn );
nkeynes@417
  2354
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2355
                        }
nkeynes@359
  2356
                        break;
nkeynes@359
  2357
                    case 0x2:
nkeynes@359
  2358
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2359
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2360
                        COUNT_INST(I_MOVL);
nkeynes@586
  2361
                        load_reg( R_EAX, Rm );
nkeynes@586
  2362
                        check_ralign32( R_EAX );
nkeynes@586
  2363
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2364
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2365
                        store_reg( R_EAX, Rn );
nkeynes@417
  2366
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2367
                        }
nkeynes@359
  2368
                        break;
nkeynes@359
  2369
                    case 0x3:
nkeynes@359
  2370
                        { /* MOV Rm, Rn */
nkeynes@359
  2371
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2372
                        COUNT_INST(I_MOV);
nkeynes@359
  2373
                        load_reg( R_EAX, Rm );
nkeynes@359
  2374
                        store_reg( R_EAX, Rn );
nkeynes@359
  2375
                        }
nkeynes@359
  2376
                        break;
nkeynes@359
  2377
                    case 0x4:
nkeynes@359
  2378
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2379
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2380
                        COUNT_INST(I_MOVB);
nkeynes@586
  2381
                        load_reg( R_EAX, Rm );
nkeynes@586
  2382
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2383
                        ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  2384
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2385
                        store_reg( R_EAX, Rn );
nkeynes@417
  2386
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2387
                        }
nkeynes@359
  2388
                        break;
nkeynes@359
  2389
                    case 0x5:
nkeynes@359
  2390
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2391
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2392
                        COUNT_INST(I_MOVW);
nkeynes@361
  2393
                        load_reg( R_EAX, Rm );
nkeynes@374
  2394
                        check_ralign16( R_EAX );
nkeynes@586
  2395
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2396
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  2397
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2398
                        store_reg( R_EAX, Rn );
nkeynes@417
  2399
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2400
                        }
nkeynes@359
  2401
                        break;
nkeynes@359
  2402
                    case 0x6:
nkeynes@359
  2403
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2404
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2405
                        COUNT_INST(I_MOVL);
nkeynes@361
  2406
                        load_reg( R_EAX, Rm );
nkeynes@386
  2407
                        check_ralign32( R_EAX );
nkeynes@586
  2408
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2409
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2410
                        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  2411
                        store_reg( R_EAX, Rn );
nkeynes@417
  2412
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2413
                        }
nkeynes@359
  2414
                        break;
nkeynes@359
  2415
                    case 0x7:
nkeynes@359
  2416
                        { /* NOT Rm, Rn */
nkeynes@359
  2417
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2418
                        COUNT_INST(I_NOT);
nkeynes@359
  2419
                        load_reg( R_EAX, Rm );
nkeynes@359
  2420
                        NOT_r32( R_EAX );
nkeynes@359
  2421
                        store_reg( R_EAX, Rn );
nkeynes@417
  2422
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2423
                        }
nkeynes@359
  2424
                        break;
nkeynes@359
  2425
                    case 0x8:
nkeynes@359
  2426
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2427
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2428
                        COUNT_INST(I_SWAPB);
nkeynes@359
  2429
                        load_reg( R_EAX, Rm );
nkeynes@601
  2430
                        XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  2431
                        store_reg( R_EAX, Rn );
nkeynes@359
  2432
                        }
nkeynes@359
  2433
                        break;
nkeynes@359
  2434
                    case 0x9:
nkeynes@359
  2435
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2436
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2437
                        COUNT_INST(I_SWAPB);
nkeynes@359
  2438
                        load_reg( R_EAX, Rm );
nkeynes@359
  2439
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2440
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2441
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2442
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2443
                        store_reg( R_ECX, Rn );
nkeynes@417
  2444
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2445
                        }
nkeynes@359
  2446
                        break;
nkeynes@359
  2447
                    case 0xA:
nkeynes@359
  2448
                        { /* NEGC Rm, Rn */
nkeynes@359
  2449
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2450
                        COUNT_INST(I_NEGC);
nkeynes@359
  2451
                        load_reg( R_EAX, Rm );
nkeynes@359
  2452
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2453
                        LDC_t();
nkeynes@359
  2454
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2455
                        store_reg( R_ECX, Rn );
nkeynes@359
  2456
                        SETC_t();
nkeynes@417
  2457
                        sh4_x86.tstate = TSTATE_C;
nkeynes@359
  2458
                        }
nkeynes@359
  2459
                        break;
nkeynes@359
  2460
                    case 0xB:
nkeynes@359
  2461
                        { /* NEG Rm, Rn */
nkeynes@359
  2462
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2463
                        COUNT_INST(I_NEG);
nkeynes@359
  2464
                        load_reg( R_EAX, Rm );
nkeynes@359
  2465
                        NEG_r32( R_EAX );
nkeynes@359
  2466
                        store_reg( R_EAX, Rn );
nkeynes@417
  2467
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2468
                        }
nkeynes@359
  2469
                        break;
nkeynes@359
  2470
                    case 0xC:
nkeynes@359
  2471
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2472
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2473
                        COUNT_INST(I_EXTUB);
nkeynes@361
  2474
                        load_reg( R_EAX, Rm );
nkeynes@361
  2475
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2476
                        store_reg( R_EAX, Rn );
nkeynes@359
  2477
                        }
nkeynes@359
  2478
                        break;
nkeynes@359
  2479
                    case 0xD:
nkeynes@359
  2480
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2481
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2482
                        COUNT_INST(I_EXTUW);
nkeynes@361
  2483
                        load_reg( R_EAX, Rm );
nkeynes@361
  2484
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2485
                        store_reg( R_EAX, Rn );
nkeynes@359
  2486
                        }
nkeynes@359
  2487
                        break;
nkeynes@359
  2488
                    case 0xE:
nkeynes@359
  2489
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2490
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2491
                        COUNT_INST(I_EXTSB);
nkeynes@359
  2492
                        load_reg( R_EAX, Rm );
nkeynes@359
  2493
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2494
                        store_reg( R_EAX, Rn );
nkeynes@359
  2495
                        }
nkeynes@359
  2496
                        break;
nkeynes@359
  2497
                    case 0xF:
nkeynes@359
  2498
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2499
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@671
  2500
                        COUNT_INST(I_EXTSW);
nkeynes@361
  2501
                        load_reg( R_EAX, Rm );
nkeynes@361
  2502
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2503
                        store_reg( R_EAX, Rn );
nkeynes@359
  2504
                        }
nkeynes@359
  2505
                        break;
nkeynes@359
  2506
                }
nkeynes@359
  2507
                break;
nkeynes@359
  2508
            case 0x7:
nkeynes@359
  2509
                { /* ADD #imm, Rn */
nkeynes@359
  2510
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@671
  2511
                COUNT_INST(I_ADDI);
nkeynes@359
  2512
                load_reg( R_EAX, Rn );
nkeynes@359
  2513
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2514
                store_reg( R_EAX, Rn );
nkeynes@417
  2515
                sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2516
                }
nkeynes@359
  2517
                break;
nkeynes@359
  2518
            case 0x8:
nkeynes@359
  2519
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2520
                    case 0x0:
nkeynes@359
  2521
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2522
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@671
  2523
                        COUNT_INST(I_MOVB);
nkeynes@586
  2524
                        load_reg( R_EAX, Rn );
nkeynes@586
  2525
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2526
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2527
                        load_reg( R_EDX, 0 );
nkeynes@586
  2528
                        MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  2529
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2530
                        }
nkeynes@359
  2531
                        break;
nkeynes@359
  2532
                    case 0x1:
nkeynes@359
  2533
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2534
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@671
  2535
                        COUNT_INST(I_MOVW);
nkeynes@586
  2536
                        load_reg( R_EAX, Rn );
nkeynes@586
  2537
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2538
                        check_walign16( R_EAX );
nkeynes@586
  2539
                        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2540
                        load_reg( R_EDX, 0 );
nkeynes@586
  2541
                        MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  2542
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2543
                        }
nkeynes@359
  2544
                        break;
nkeynes@359
  2545
                    case 0x4:
nkeynes@359
  2546
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2547
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@671
  2548
                        COUNT_INST(I_MOVB);
nkeynes@586
  2549
                        load_reg( R_EAX, Rm );
nkeynes@586
  2550
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2551
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2552
                        MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  2553
                        store_reg( R_EAX, 0 );
nkeynes@417
  2554
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2555
                        }
nkeynes@359
  2556
                        break;
nkeynes@359
  2557
                    case 0x5:
nkeynes@359
  2558
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2559
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@671
  2560
                        COUNT_INST(I_MOVW);
nkeynes@586
  2561
                        load_reg( R_EAX, Rm );
nkeynes@586
  2562
                        ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  2563
                        check_ralign16( R_EAX );
nkeynes@586
  2564
                        MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2565
                        MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  2566
                        store_reg( R_EAX, 0 );
nkeynes@417
  2567
                        sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2568
                        }
nkeynes@359
  2569
                        break;
nkeynes@359
  2570
                    case 0x8:
nkeynes@359
  2571
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2572
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@671
  2573
                        COUNT_INST(I_CMPEQI);
nkeynes@359
  2574
                        load_reg( R_EAX, 0 );
nkeynes@359
  2575
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2576
                        SETE_t();
nkeynes@417
  2577
                        sh4_x86.tstate = TSTATE_E;
nkeynes@359
  2578
                        }
nkeynes@359
  2579
                        break;
nkeynes@359
  2580
                    case 0x9:
nkeynes@359
  2581
                        { /* BT disp */
nkeynes@359
  2582
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@671
  2583
                        COUNT_INST(I_BT);
nkeynes@374
  2584
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2585
                    	SLOTILLEGAL();
nkeynes@374
  2586
                        } else {
nkeynes@586
  2587
                    	sh4vma_t target = disp + pc + 4;
nkeynes@669
  2588
                    	JF_rel8( nottaken );
nkeynes@586
  2589
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2590
                    	JMP_TARGET(nottaken);
nkeynes@408
  2591
                    	return 2;
nkeynes@374
  2592
                        }
nkeynes@359
  2593
                        }
nkeynes@359
  2594
                        break;
nkeynes@359
  2595
                    case 0xB:
nkeynes@359
  2596
                        { /* BF disp */
nkeynes@359
  2597
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@671
  2598
                        COUNT_INST(I_BF);
nkeynes@374
  2599
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2600
                    	SLOTILLEGAL();
nkeynes@374
  2601
                        } else {
nkeynes@586
  2602
                    	sh4vma_t target = disp + pc + 4;
nkeynes@669
  2603
                    	JT_rel8( nottaken );
nkeynes@586
  2604
                    	exit_block_rel(target, pc+2 );
nkeynes@380
  2605
                    	JMP_TARGET(nottaken);
nkeynes@408
  2606
                    	return 2;
nkeynes@374
  2607
                        }
nkeynes@359
  2608
                        }
nkeynes@359
  2609
                        break;
nkeynes@359
  2610
                    case 0xD:
nkeynes@359
  2611
                        { /* BT/S disp */
nkeynes@359
  2612
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@671
  2613
                        COUNT_INST(I_BTS);
nkeynes@374
  2614
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2615
                    	SLOTILLEGAL();
nkeynes@374
  2616
                        } else {
nkeynes@590
  2617
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2618
                    	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2619
                    	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  2620
                    	    JF_rel8(nottaken);
nkeynes@601
  2621
                    	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2622
                    	    JMP_TARGET(nottaken);
nkeynes@601
  2623
                    	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  2624
                    	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2625
                    	    exit_block_emu(pc+2);
nkeynes@601
  2626
                    	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2627
                    	    return 2;
nkeynes@601
  2628
                    	} else {
nkeynes@601
  2629
                    	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  2630
                    		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  2631
                    		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2632
                    	    }
nkeynes@601
  2633
                    	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  2634
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2635
                    	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  2636
                    	    // not taken
nkeynes@601
  2637
                    	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  2638
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2639
                    	    return 4;
nkeynes@417
  2640
                    	}
nkeynes@374
  2641
                        }
nkeynes@359
  2642
                        }
nkeynes@359
  2643
                        break;
nkeynes@359
  2644
                    case 0xF:
nkeynes@359
  2645
                        { /* BF/S disp */
nkeynes@359
  2646
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@671
  2647
                        COUNT_INST(I_BFS);
nkeynes@374
  2648
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2649
                    	SLOTILLEGAL();
nkeynes@374
  2650
                        } else {
nkeynes@590
  2651
                    	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  2652
                    	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  2653
                    	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  2654
                    	    JT_rel8(nottaken);
nkeynes@601
  2655
                    	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  2656
                    	    JMP_TARGET(nottaken);
nkeynes@601
  2657
                    	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  2658
                    	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  2659
                    	    exit_block_emu(pc+2);
nkeynes@601
  2660
                    	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  2661
                    	    return 2;
nkeynes@601
  2662
                    	} else {
nkeynes@601
  2663
                    	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  2664
                    		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  2665
                    		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  2666
                    	    }
nkeynes@601
  2667
                    	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  2668
                    	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  2669
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2670
                    	    exit_block_rel( target, pc+4 );
nkeynes@601
  2671
                    	    
nkeynes@601
  2672
                    	    // not taken
nkeynes@601
  2673
                    	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  2674
                    	    sh4_translate_instruction(pc+2);
nkeynes@601
  2675
                    	    return 4;
nkeynes@417
  2676
                    	}
nkeynes@374
  2677
                        }
nkeynes@359
  2678
                        }
nkeynes@359
  2679
                        break;
nkeynes@359
  2680
                    default:
nkeynes@359
  2681
                        UNDEF();
nkeynes@359
  2682
                        break;
nkeynes@359
  2683
                }
nkeynes@359
  2684
                break;
nkeynes@359
  2685
            case 0x9:
nkeynes@359
  2686
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2687
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;