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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 732:f05753bbe723
prev675:b97020f9af1c
next733:633ee022f52e
author nkeynes
date Thu Jul 10 01:46:00 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix alignment check for 64-bit FMOVs
Add missing MMU code etc to FMOV emu implementation
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define MAX_RECOVERY_SIZE 2048
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
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#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
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#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
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#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
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#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
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/****** Import appropriate calling conventions ******/
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#if SIZEOF_VOID_P == 8
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#include "sh4/ia64abi.h"
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#else /* 32-bit system */
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#ifdef APPLE_BUILD
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#include "sh4/ia32mac.h"
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   309
#else
nkeynes@539
   310
#include "sh4/ia32abi.h"
nkeynes@539
   311
#endif
nkeynes@539
   312
#endif
nkeynes@539
   313
nkeynes@593
   314
uint32_t sh4_translate_end_block_size()
nkeynes@593
   315
{
nkeynes@596
   316
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@596
   317
	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   318
    } else {
nkeynes@596
   319
	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   320
    }
nkeynes@593
   321
}
nkeynes@593
   322
nkeynes@593
   323
nkeynes@590
   324
/**
nkeynes@590
   325
 * Embed a breakpoint into the generated code
nkeynes@590
   326
 */
nkeynes@586
   327
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   328
{
nkeynes@591
   329
    load_imm32( R_EAX, pc );
nkeynes@591
   330
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@586
   331
}
nkeynes@590
   332
nkeynes@601
   333
nkeynes@601
   334
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   335
nkeynes@590
   336
/**
nkeynes@590
   337
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   338
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   339
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   340
 *
nkeynes@601
   341
 * Performs:
nkeynes@601
   342
 *   Set PC = endpc
nkeynes@601
   343
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   344
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   345
 *   Call sh4_execute_instruction
nkeynes@601
   346
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   347
 */
nkeynes@601
   348
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   349
{
nkeynes@590
   350
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   351
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   352
    
nkeynes@601
   353
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   354
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   355
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   356
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   357
nkeynes@590
   358
    call_func0( sh4_execute_instruction );    
nkeynes@601
   359
    load_spreg( R_EAX, R_PC );
nkeynes@590
   360
    if( sh4_x86.tlb_on ) {
nkeynes@590
   361
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   362
    } else {
nkeynes@590
   363
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   364
    }
nkeynes@601
   365
    AND_imm8s_rptr( 0xFC, R_EAX );
nkeynes@590
   366
    POP_r32(R_EBP);
nkeynes@590
   367
    RET();
nkeynes@590
   368
} 
nkeynes@539
   369
nkeynes@359
   370
/**
nkeynes@359
   371
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   372
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   373
 * 
nkeynes@586
   374
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   375
 *
nkeynes@359
   376
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   377
 * (eg a branch or 
nkeynes@359
   378
 */
nkeynes@590
   379
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   380
{
nkeynes@388
   381
    uint32_t ir;
nkeynes@586
   382
    /* Read instruction from icache */
nkeynes@586
   383
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   384
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   385
    
nkeynes@586
   386
	/* PC is not in the current icache - this usually means we're running
nkeynes@586
   387
	 * with MMU on, and we've gone past the end of the page. And since 
nkeynes@586
   388
	 * sh4_translate_block is pretty careful about this, it means we're
nkeynes@586
   389
	 * almost certainly in a delay slot.
nkeynes@586
   390
	 *
nkeynes@586
   391
	 * Since we can't assume the page is present (and we can't fault it in
nkeynes@586
   392
	 * at this point, inline a call to sh4_execute_instruction (with a few
nkeynes@586
   393
	 * small repairs to cope with the different environment).
nkeynes@586
   394
	 */
nkeynes@586
   395
nkeynes@586
   396
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   397
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   398
    }
nkeynes@359
   399
%%
nkeynes@359
   400
/* ALU operations */
nkeynes@359
   401
ADD Rm, Rn {:
nkeynes@671
   402
    COUNT_INST(I_ADD);
nkeynes@359
   403
    load_reg( R_EAX, Rm );
nkeynes@359
   404
    load_reg( R_ECX, Rn );
nkeynes@359
   405
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   406
    store_reg( R_ECX, Rn );
nkeynes@417
   407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   408
:}
nkeynes@359
   409
ADD #imm, Rn {:  
nkeynes@671
   410
    COUNT_INST(I_ADDI);
nkeynes@359
   411
    load_reg( R_EAX, Rn );
nkeynes@359
   412
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   413
    store_reg( R_EAX, Rn );
nkeynes@417
   414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   415
:}
nkeynes@359
   416
ADDC Rm, Rn {:
nkeynes@671
   417
    COUNT_INST(I_ADDC);
nkeynes@417
   418
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   419
	LDC_t();
nkeynes@417
   420
    }
nkeynes@359
   421
    load_reg( R_EAX, Rm );
nkeynes@359
   422
    load_reg( R_ECX, Rn );
nkeynes@359
   423
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   424
    store_reg( R_ECX, Rn );
nkeynes@359
   425
    SETC_t();
nkeynes@417
   426
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   427
:}
nkeynes@359
   428
ADDV Rm, Rn {:
nkeynes@671
   429
    COUNT_INST(I_ADDV);
nkeynes@359
   430
    load_reg( R_EAX, Rm );
nkeynes@359
   431
    load_reg( R_ECX, Rn );
nkeynes@359
   432
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   433
    store_reg( R_ECX, Rn );
nkeynes@359
   434
    SETO_t();
nkeynes@417
   435
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   436
:}
nkeynes@359
   437
AND Rm, Rn {:
nkeynes@671
   438
    COUNT_INST(I_AND);
nkeynes@359
   439
    load_reg( R_EAX, Rm );
nkeynes@359
   440
    load_reg( R_ECX, Rn );
nkeynes@359
   441
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   442
    store_reg( R_ECX, Rn );
nkeynes@417
   443
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   444
:}
nkeynes@359
   445
AND #imm, R0 {:  
nkeynes@671
   446
    COUNT_INST(I_ANDI);
nkeynes@359
   447
    load_reg( R_EAX, 0 );
nkeynes@359
   448
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   449
    store_reg( R_EAX, 0 );
nkeynes@417
   450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   451
:}
nkeynes@359
   452
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   453
    COUNT_INST(I_ANDB);
nkeynes@359
   454
    load_reg( R_EAX, 0 );
nkeynes@359
   455
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   456
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   457
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   458
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   459
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   460
    POP_realigned_r32(R_ECX);
nkeynes@386
   461
    AND_imm32_r32(imm, R_EAX );
nkeynes@359
   462
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   464
:}
nkeynes@359
   465
CMP/EQ Rm, Rn {:  
nkeynes@671
   466
    COUNT_INST(I_CMPEQ);
nkeynes@359
   467
    load_reg( R_EAX, Rm );
nkeynes@359
   468
    load_reg( R_ECX, Rn );
nkeynes@359
   469
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   470
    SETE_t();
nkeynes@417
   471
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   472
:}
nkeynes@359
   473
CMP/EQ #imm, R0 {:  
nkeynes@671
   474
    COUNT_INST(I_CMPEQI);
nkeynes@359
   475
    load_reg( R_EAX, 0 );
nkeynes@359
   476
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   477
    SETE_t();
nkeynes@417
   478
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   479
:}
nkeynes@359
   480
CMP/GE Rm, Rn {:  
nkeynes@671
   481
    COUNT_INST(I_CMPGE);
nkeynes@359
   482
    load_reg( R_EAX, Rm );
nkeynes@359
   483
    load_reg( R_ECX, Rn );
nkeynes@359
   484
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   485
    SETGE_t();
nkeynes@417
   486
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   487
:}
nkeynes@359
   488
CMP/GT Rm, Rn {: 
nkeynes@671
   489
    COUNT_INST(I_CMPGT);
nkeynes@359
   490
    load_reg( R_EAX, Rm );
nkeynes@359
   491
    load_reg( R_ECX, Rn );
nkeynes@359
   492
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   493
    SETG_t();
nkeynes@417
   494
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   495
:}
nkeynes@359
   496
CMP/HI Rm, Rn {:  
nkeynes@671
   497
    COUNT_INST(I_CMPHI);
nkeynes@359
   498
    load_reg( R_EAX, Rm );
nkeynes@359
   499
    load_reg( R_ECX, Rn );
nkeynes@359
   500
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   501
    SETA_t();
nkeynes@417
   502
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   503
:}
nkeynes@359
   504
CMP/HS Rm, Rn {: 
nkeynes@671
   505
    COUNT_INST(I_CMPHS);
nkeynes@359
   506
    load_reg( R_EAX, Rm );
nkeynes@359
   507
    load_reg( R_ECX, Rn );
nkeynes@359
   508
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   509
    SETAE_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   511
 :}
nkeynes@359
   512
CMP/PL Rn {: 
nkeynes@671
   513
    COUNT_INST(I_CMPPL);
nkeynes@359
   514
    load_reg( R_EAX, Rn );
nkeynes@359
   515
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   516
    SETG_t();
nkeynes@417
   517
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   518
:}
nkeynes@359
   519
CMP/PZ Rn {:  
nkeynes@671
   520
    COUNT_INST(I_CMPPZ);
nkeynes@359
   521
    load_reg( R_EAX, Rn );
nkeynes@359
   522
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   523
    SETGE_t();
nkeynes@417
   524
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   525
:}
nkeynes@361
   526
CMP/STR Rm, Rn {:  
nkeynes@671
   527
    COUNT_INST(I_CMPSTR);
nkeynes@368
   528
    load_reg( R_EAX, Rm );
nkeynes@368
   529
    load_reg( R_ECX, Rn );
nkeynes@368
   530
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   531
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   532
    JE_rel8(target1);
nkeynes@669
   533
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   534
    JE_rel8(target2);
nkeynes@669
   535
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   536
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   537
    JE_rel8(target3);
nkeynes@669
   538
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   539
    JMP_TARGET(target1);
nkeynes@380
   540
    JMP_TARGET(target2);
nkeynes@380
   541
    JMP_TARGET(target3);
nkeynes@368
   542
    SETE_t();
nkeynes@417
   543
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   544
:}
nkeynes@361
   545
DIV0S Rm, Rn {:
nkeynes@671
   546
    COUNT_INST(I_DIV0S);
nkeynes@361
   547
    load_reg( R_EAX, Rm );
nkeynes@386
   548
    load_reg( R_ECX, Rn );
nkeynes@361
   549
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   550
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   551
    store_spreg( R_EAX, R_M );
nkeynes@361
   552
    store_spreg( R_ECX, R_Q );
nkeynes@361
   553
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   554
    SETNE_t();
nkeynes@417
   555
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   556
:}
nkeynes@361
   557
DIV0U {:  
nkeynes@671
   558
    COUNT_INST(I_DIV0U);
nkeynes@361
   559
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   560
    store_spreg( R_EAX, R_Q );
nkeynes@361
   561
    store_spreg( R_EAX, R_M );
nkeynes@361
   562
    store_spreg( R_EAX, R_T );
nkeynes@417
   563
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   564
:}
nkeynes@386
   565
DIV1 Rm, Rn {:
nkeynes@671
   566
    COUNT_INST(I_DIV1);
nkeynes@386
   567
    load_spreg( R_ECX, R_M );
nkeynes@386
   568
    load_reg( R_EAX, Rn );
nkeynes@417
   569
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   570
	LDC_t();
nkeynes@417
   571
    }
nkeynes@386
   572
    RCL1_r32( R_EAX );
nkeynes@386
   573
    SETC_r8( R_DL ); // Q'
nkeynes@386
   574
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   575
    JE_rel8(mqequal);
nkeynes@386
   576
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   577
    JMP_rel8(end);
nkeynes@380
   578
    JMP_TARGET(mqequal);
nkeynes@386
   579
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   580
    JMP_TARGET(end);
nkeynes@386
   581
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   582
    SETC_r8(R_AL); // tmp1
nkeynes@386
   583
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   584
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   585
    store_spreg( R_ECX, R_Q );
nkeynes@386
   586
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   587
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   588
    store_spreg( R_EAX, R_T );
nkeynes@417
   589
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   590
:}
nkeynes@361
   591
DMULS.L Rm, Rn {:  
nkeynes@671
   592
    COUNT_INST(I_DMULS);
nkeynes@361
   593
    load_reg( R_EAX, Rm );
nkeynes@361
   594
    load_reg( R_ECX, Rn );
nkeynes@361
   595
    IMUL_r32(R_ECX);
nkeynes@361
   596
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   597
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   598
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   599
:}
nkeynes@361
   600
DMULU.L Rm, Rn {:  
nkeynes@671
   601
    COUNT_INST(I_DMULU);
nkeynes@361
   602
    load_reg( R_EAX, Rm );
nkeynes@361
   603
    load_reg( R_ECX, Rn );
nkeynes@361
   604
    MUL_r32(R_ECX);
nkeynes@361
   605
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   606
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   607
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   608
:}
nkeynes@359
   609
DT Rn {:  
nkeynes@671
   610
    COUNT_INST(I_DT);
nkeynes@359
   611
    load_reg( R_EAX, Rn );
nkeynes@382
   612
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   613
    store_reg( R_EAX, Rn );
nkeynes@359
   614
    SETE_t();
nkeynes@417
   615
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   616
:}
nkeynes@359
   617
EXTS.B Rm, Rn {:  
nkeynes@671
   618
    COUNT_INST(I_EXTSB);
nkeynes@359
   619
    load_reg( R_EAX, Rm );
nkeynes@359
   620
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   621
    store_reg( R_EAX, Rn );
nkeynes@359
   622
:}
nkeynes@361
   623
EXTS.W Rm, Rn {:  
nkeynes@671
   624
    COUNT_INST(I_EXTSW);
nkeynes@361
   625
    load_reg( R_EAX, Rm );
nkeynes@361
   626
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   627
    store_reg( R_EAX, Rn );
nkeynes@361
   628
:}
nkeynes@361
   629
EXTU.B Rm, Rn {:  
nkeynes@671
   630
    COUNT_INST(I_EXTUB);
nkeynes@361
   631
    load_reg( R_EAX, Rm );
nkeynes@361
   632
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   633
    store_reg( R_EAX, Rn );
nkeynes@361
   634
:}
nkeynes@361
   635
EXTU.W Rm, Rn {:  
nkeynes@671
   636
    COUNT_INST(I_EXTUW);
nkeynes@361
   637
    load_reg( R_EAX, Rm );
nkeynes@361
   638
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   639
    store_reg( R_EAX, Rn );
nkeynes@361
   640
:}
nkeynes@586
   641
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   642
    COUNT_INST(I_MACL);
nkeynes@586
   643
    if( Rm == Rn ) {
nkeynes@586
   644
	load_reg( R_EAX, Rm );
nkeynes@586
   645
	check_ralign32( R_EAX );
nkeynes@586
   646
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   647
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   648
	load_reg( R_EAX, Rn );
nkeynes@586
   649
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@596
   650
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   651
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   652
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   653
	// adding a page-boundary check to skip the second translation
nkeynes@586
   654
    } else {
nkeynes@586
   655
	load_reg( R_EAX, Rm );
nkeynes@586
   656
	check_ralign32( R_EAX );
nkeynes@586
   657
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   658
	load_reg( R_ECX, Rn );
nkeynes@596
   659
	check_ralign32( R_ECX );
nkeynes@586
   660
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   661
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   662
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   663
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   664
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   665
    }
nkeynes@586
   666
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   667
    POP_r32( R_ECX );
nkeynes@586
   668
    PUSH_r32( R_EAX );
nkeynes@386
   669
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@547
   670
    POP_realigned_r32( R_ECX );
nkeynes@586
   671
nkeynes@386
   672
    IMUL_r32( R_ECX );
nkeynes@386
   673
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   674
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   675
nkeynes@386
   676
    load_spreg( R_ECX, R_S );
nkeynes@386
   677
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   678
    JE_rel8( nosat );
nkeynes@386
   679
    call_func0( signsat48 );
nkeynes@386
   680
    JMP_TARGET( nosat );
nkeynes@417
   681
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   682
:}
nkeynes@386
   683
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   684
    COUNT_INST(I_MACW);
nkeynes@586
   685
    if( Rm == Rn ) {
nkeynes@586
   686
	load_reg( R_EAX, Rm );
nkeynes@586
   687
	check_ralign16( R_EAX );
nkeynes@586
   688
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   689
	PUSH_realigned_r32( R_EAX );
nkeynes@586
   690
	load_reg( R_EAX, Rn );
nkeynes@586
   691
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@596
   692
	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
nkeynes@586
   693
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   694
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   695
	// adding a page-boundary check to skip the second translation
nkeynes@586
   696
    } else {
nkeynes@586
   697
	load_reg( R_EAX, Rm );
nkeynes@586
   698
	check_ralign16( R_EAX );
nkeynes@586
   699
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@596
   700
	load_reg( R_ECX, Rn );
nkeynes@596
   701
	check_ralign16( R_ECX );
nkeynes@586
   702
	PUSH_realigned_r32( R_EAX );
nkeynes@596
   703
	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
nkeynes@596
   704
	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@586
   705
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   706
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   707
    }
nkeynes@586
   708
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   709
    POP_r32( R_ECX );
nkeynes@586
   710
    PUSH_r32( R_EAX );
nkeynes@386
   711
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@547
   712
    POP_realigned_r32( R_ECX );
nkeynes@386
   713
    IMUL_r32( R_ECX );
nkeynes@386
   714
nkeynes@386
   715
    load_spreg( R_ECX, R_S );
nkeynes@386
   716
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   717
    JE_rel8( nosat );
nkeynes@386
   718
nkeynes@386
   719
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   720
    JNO_rel8( end );            // 2
nkeynes@386
   721
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   722
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   723
    JS_rel8( positive );        // 2
nkeynes@386
   724
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   725
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   726
    JMP_rel8(end2);           // 2
nkeynes@386
   727
nkeynes@386
   728
    JMP_TARGET(positive);
nkeynes@386
   729
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   730
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   731
    JMP_rel8(end3);            // 2
nkeynes@386
   732
nkeynes@386
   733
    JMP_TARGET(nosat);
nkeynes@386
   734
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   735
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   736
    JMP_TARGET(end);
nkeynes@386
   737
    JMP_TARGET(end2);
nkeynes@386
   738
    JMP_TARGET(end3);
nkeynes@417
   739
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   740
:}
nkeynes@359
   741
MOVT Rn {:  
nkeynes@671
   742
    COUNT_INST(I_MOVT);
nkeynes@359
   743
    load_spreg( R_EAX, R_T );
nkeynes@359
   744
    store_reg( R_EAX, Rn );
nkeynes@359
   745
:}
nkeynes@361
   746
MUL.L Rm, Rn {:  
nkeynes@671
   747
    COUNT_INST(I_MULL);
nkeynes@361
   748
    load_reg( R_EAX, Rm );
nkeynes@361
   749
    load_reg( R_ECX, Rn );
nkeynes@361
   750
    MUL_r32( R_ECX );
nkeynes@361
   751
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   752
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   753
:}
nkeynes@374
   754
MULS.W Rm, Rn {:
nkeynes@671
   755
    COUNT_INST(I_MULSW);
nkeynes@374
   756
    load_reg16s( R_EAX, Rm );
nkeynes@374
   757
    load_reg16s( R_ECX, Rn );
nkeynes@374
   758
    MUL_r32( R_ECX );
nkeynes@374
   759
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   760
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   761
:}
nkeynes@374
   762
MULU.W Rm, Rn {:  
nkeynes@671
   763
    COUNT_INST(I_MULUW);
nkeynes@374
   764
    load_reg16u( R_EAX, Rm );
nkeynes@374
   765
    load_reg16u( R_ECX, Rn );
nkeynes@374
   766
    MUL_r32( R_ECX );
nkeynes@374
   767
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   768
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   769
:}
nkeynes@359
   770
NEG Rm, Rn {:
nkeynes@671
   771
    COUNT_INST(I_NEG);
nkeynes@359
   772
    load_reg( R_EAX, Rm );
nkeynes@359
   773
    NEG_r32( R_EAX );
nkeynes@359
   774
    store_reg( R_EAX, Rn );
nkeynes@417
   775
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   776
:}
nkeynes@359
   777
NEGC Rm, Rn {:  
nkeynes@671
   778
    COUNT_INST(I_NEGC);
nkeynes@359
   779
    load_reg( R_EAX, Rm );
nkeynes@359
   780
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   781
    LDC_t();
nkeynes@359
   782
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   783
    store_reg( R_ECX, Rn );
nkeynes@359
   784
    SETC_t();
nkeynes@417
   785
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   786
:}
nkeynes@359
   787
NOT Rm, Rn {:  
nkeynes@671
   788
    COUNT_INST(I_NOT);
nkeynes@359
   789
    load_reg( R_EAX, Rm );
nkeynes@359
   790
    NOT_r32( R_EAX );
nkeynes@359
   791
    store_reg( R_EAX, Rn );
nkeynes@417
   792
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   793
:}
nkeynes@359
   794
OR Rm, Rn {:  
nkeynes@671
   795
    COUNT_INST(I_OR);
nkeynes@359
   796
    load_reg( R_EAX, Rm );
nkeynes@359
   797
    load_reg( R_ECX, Rn );
nkeynes@359
   798
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   799
    store_reg( R_ECX, Rn );
nkeynes@417
   800
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   801
:}
nkeynes@359
   802
OR #imm, R0 {:
nkeynes@671
   803
    COUNT_INST(I_ORI);
nkeynes@359
   804
    load_reg( R_EAX, 0 );
nkeynes@359
   805
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   806
    store_reg( R_EAX, 0 );
nkeynes@417
   807
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   808
:}
nkeynes@374
   809
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   810
    COUNT_INST(I_ORB);
nkeynes@374
   811
    load_reg( R_EAX, 0 );
nkeynes@374
   812
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   813
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   814
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
   815
    PUSH_realigned_r32(R_EAX);
nkeynes@586
   816
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@547
   817
    POP_realigned_r32(R_ECX);
nkeynes@386
   818
    OR_imm32_r32(imm, R_EAX );
nkeynes@374
   819
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
   820
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   821
:}
nkeynes@359
   822
ROTCL Rn {:
nkeynes@671
   823
    COUNT_INST(I_ROTCL);
nkeynes@359
   824
    load_reg( R_EAX, Rn );
nkeynes@417
   825
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   826
	LDC_t();
nkeynes@417
   827
    }
nkeynes@359
   828
    RCL1_r32( R_EAX );
nkeynes@359
   829
    store_reg( R_EAX, Rn );
nkeynes@359
   830
    SETC_t();
nkeynes@417
   831
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   832
:}
nkeynes@359
   833
ROTCR Rn {:  
nkeynes@671
   834
    COUNT_INST(I_ROTCR);
nkeynes@359
   835
    load_reg( R_EAX, Rn );
nkeynes@417
   836
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   837
	LDC_t();
nkeynes@417
   838
    }
nkeynes@359
   839
    RCR1_r32( R_EAX );
nkeynes@359
   840
    store_reg( R_EAX, Rn );
nkeynes@359
   841
    SETC_t();
nkeynes@417
   842
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   843
:}
nkeynes@359
   844
ROTL Rn {:  
nkeynes@671
   845
    COUNT_INST(I_ROTL);
nkeynes@359
   846
    load_reg( R_EAX, Rn );
nkeynes@359
   847
    ROL1_r32( R_EAX );
nkeynes@359
   848
    store_reg( R_EAX, Rn );
nkeynes@359
   849
    SETC_t();
nkeynes@417
   850
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   851
:}
nkeynes@359
   852
ROTR Rn {:  
nkeynes@671
   853
    COUNT_INST(I_ROTR);
nkeynes@359
   854
    load_reg( R_EAX, Rn );
nkeynes@359
   855
    ROR1_r32( R_EAX );
nkeynes@359
   856
    store_reg( R_EAX, Rn );
nkeynes@359
   857
    SETC_t();
nkeynes@417
   858
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   859
:}
nkeynes@359
   860
SHAD Rm, Rn {:
nkeynes@671
   861
    COUNT_INST(I_SHAD);
nkeynes@359
   862
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   863
    load_reg( R_EAX, Rn );
nkeynes@361
   864
    load_reg( R_ECX, Rm );
nkeynes@361
   865
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   866
    JGE_rel8(doshl);
nkeynes@361
   867
                    
nkeynes@361
   868
    NEG_r32( R_ECX );      // 2
nkeynes@361
   869
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   870
    JE_rel8(emptysar);     // 2
nkeynes@361
   871
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   872
    JMP_rel8(end);          // 2
nkeynes@386
   873
nkeynes@386
   874
    JMP_TARGET(emptysar);
nkeynes@386
   875
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   876
    JMP_rel8(end2);
nkeynes@382
   877
nkeynes@380
   878
    JMP_TARGET(doshl);
nkeynes@361
   879
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   880
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   881
    JMP_TARGET(end);
nkeynes@386
   882
    JMP_TARGET(end2);
nkeynes@361
   883
    store_reg( R_EAX, Rn );
nkeynes@417
   884
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   885
:}
nkeynes@359
   886
SHLD Rm, Rn {:  
nkeynes@671
   887
    COUNT_INST(I_SHLD);
nkeynes@368
   888
    load_reg( R_EAX, Rn );
nkeynes@368
   889
    load_reg( R_ECX, Rm );
nkeynes@382
   890
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   891
    JGE_rel8(doshl);
nkeynes@368
   892
nkeynes@382
   893
    NEG_r32( R_ECX );      // 2
nkeynes@382
   894
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   895
    JE_rel8(emptyshr );
nkeynes@382
   896
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   897
    JMP_rel8(end);          // 2
nkeynes@386
   898
nkeynes@386
   899
    JMP_TARGET(emptyshr);
nkeynes@386
   900
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   901
    JMP_rel8(end2);
nkeynes@382
   902
nkeynes@382
   903
    JMP_TARGET(doshl);
nkeynes@382
   904
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   905
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   906
    JMP_TARGET(end);
nkeynes@386
   907
    JMP_TARGET(end2);
nkeynes@368
   908
    store_reg( R_EAX, Rn );
nkeynes@417
   909
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   910
:}
nkeynes@359
   911
SHAL Rn {: 
nkeynes@671
   912
    COUNT_INST(I_SHAL);
nkeynes@359
   913
    load_reg( R_EAX, Rn );
nkeynes@359
   914
    SHL1_r32( R_EAX );
nkeynes@397
   915
    SETC_t();
nkeynes@359
   916
    store_reg( R_EAX, Rn );
nkeynes@417
   917
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   918
:}
nkeynes@359
   919
SHAR Rn {:  
nkeynes@671
   920
    COUNT_INST(I_SHAR);
nkeynes@359
   921
    load_reg( R_EAX, Rn );
nkeynes@359
   922
    SAR1_r32( R_EAX );
nkeynes@397
   923
    SETC_t();
nkeynes@359
   924
    store_reg( R_EAX, Rn );
nkeynes@417
   925
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   926
:}
nkeynes@359
   927
SHLL Rn {:  
nkeynes@671
   928
    COUNT_INST(I_SHLL);
nkeynes@359
   929
    load_reg( R_EAX, Rn );
nkeynes@359
   930
    SHL1_r32( R_EAX );
nkeynes@397
   931
    SETC_t();
nkeynes@359
   932
    store_reg( R_EAX, Rn );
nkeynes@417
   933
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   934
:}
nkeynes@359
   935
SHLL2 Rn {:
nkeynes@671
   936
    COUNT_INST(I_SHLL);
nkeynes@359
   937
    load_reg( R_EAX, Rn );
nkeynes@359
   938
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   939
    store_reg( R_EAX, Rn );
nkeynes@417
   940
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   941
:}
nkeynes@359
   942
SHLL8 Rn {:  
nkeynes@671
   943
    COUNT_INST(I_SHLL);
nkeynes@359
   944
    load_reg( R_EAX, Rn );
nkeynes@359
   945
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   946
    store_reg( R_EAX, Rn );
nkeynes@417
   947
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   948
:}
nkeynes@359
   949
SHLL16 Rn {:  
nkeynes@671
   950
    COUNT_INST(I_SHLL);
nkeynes@359
   951
    load_reg( R_EAX, Rn );
nkeynes@359
   952
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   953
    store_reg( R_EAX, Rn );
nkeynes@417
   954
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   955
:}
nkeynes@359
   956
SHLR Rn {:  
nkeynes@671
   957
    COUNT_INST(I_SHLR);
nkeynes@359
   958
    load_reg( R_EAX, Rn );
nkeynes@359
   959
    SHR1_r32( R_EAX );
nkeynes@397
   960
    SETC_t();
nkeynes@359
   961
    store_reg( R_EAX, Rn );
nkeynes@417
   962
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   963
:}
nkeynes@359
   964
SHLR2 Rn {:  
nkeynes@671
   965
    COUNT_INST(I_SHLR);
nkeynes@359
   966
    load_reg( R_EAX, Rn );
nkeynes@359
   967
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   968
    store_reg( R_EAX, Rn );
nkeynes@417
   969
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   970
:}
nkeynes@359
   971
SHLR8 Rn {:  
nkeynes@671
   972
    COUNT_INST(I_SHLR);
nkeynes@359
   973
    load_reg( R_EAX, Rn );
nkeynes@359
   974
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   975
    store_reg( R_EAX, Rn );
nkeynes@417
   976
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   977
:}
nkeynes@359
   978
SHLR16 Rn {:  
nkeynes@671
   979
    COUNT_INST(I_SHLR);
nkeynes@359
   980
    load_reg( R_EAX, Rn );
nkeynes@359
   981
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   982
    store_reg( R_EAX, Rn );
nkeynes@417
   983
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   984
:}
nkeynes@359
   985
SUB Rm, Rn {:  
nkeynes@671
   986
    COUNT_INST(I_SUB);
nkeynes@359
   987
    load_reg( R_EAX, Rm );
nkeynes@359
   988
    load_reg( R_ECX, Rn );
nkeynes@359
   989
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   990
    store_reg( R_ECX, Rn );
nkeynes@417
   991
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   992
:}
nkeynes@359
   993
SUBC Rm, Rn {:  
nkeynes@671
   994
    COUNT_INST(I_SUBC);
nkeynes@359
   995
    load_reg( R_EAX, Rm );
nkeynes@359
   996
    load_reg( R_ECX, Rn );
nkeynes@417
   997
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   998
	LDC_t();
nkeynes@417
   999
    }
nkeynes@359
  1000
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1001
    store_reg( R_ECX, Rn );
nkeynes@394
  1002
    SETC_t();
nkeynes@417
  1003
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1004
:}
nkeynes@359
  1005
SUBV Rm, Rn {:  
nkeynes@671
  1006
    COUNT_INST(I_SUBV);
nkeynes@359
  1007
    load_reg( R_EAX, Rm );
nkeynes@359
  1008
    load_reg( R_ECX, Rn );
nkeynes@359
  1009
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1010
    store_reg( R_ECX, Rn );
nkeynes@359
  1011
    SETO_t();
nkeynes@417
  1012
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1013
:}
nkeynes@359
  1014
SWAP.B Rm, Rn {:  
nkeynes@671
  1015
    COUNT_INST(I_SWAPB);
nkeynes@359
  1016
    load_reg( R_EAX, Rm );
nkeynes@601
  1017
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1018
    store_reg( R_EAX, Rn );
nkeynes@359
  1019
:}
nkeynes@359
  1020
SWAP.W Rm, Rn {:  
nkeynes@671
  1021
    COUNT_INST(I_SWAPB);
nkeynes@359
  1022
    load_reg( R_EAX, Rm );
nkeynes@359
  1023
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1024
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1025
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1026
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1027
    store_reg( R_ECX, Rn );
nkeynes@417
  1028
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1029
:}
nkeynes@361
  1030
TAS.B @Rn {:  
nkeynes@671
  1031
    COUNT_INST(I_TASB);
nkeynes@586
  1032
    load_reg( R_EAX, Rn );
nkeynes@586
  1033
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1034
    PUSH_realigned_r32( R_EAX );
nkeynes@586
  1035
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@361
  1036
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1037
    SETE_t();
nkeynes@361
  1038
    OR_imm8_r8( 0x80, R_AL );
nkeynes@586
  1039
    POP_realigned_r32( R_ECX );
nkeynes@361
  1040
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1041
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1042
:}
nkeynes@361
  1043
TST Rm, Rn {:  
nkeynes@671
  1044
    COUNT_INST(I_TST);
nkeynes@361
  1045
    load_reg( R_EAX, Rm );
nkeynes@361
  1046
    load_reg( R_ECX, Rn );
nkeynes@361
  1047
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1048
    SETE_t();
nkeynes@417
  1049
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1050
:}
nkeynes@368
  1051
TST #imm, R0 {:  
nkeynes@671
  1052
    COUNT_INST(I_TSTI);
nkeynes@368
  1053
    load_reg( R_EAX, 0 );
nkeynes@368
  1054
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1055
    SETE_t();
nkeynes@417
  1056
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1057
:}
nkeynes@368
  1058
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1059
    COUNT_INST(I_TSTB);
nkeynes@368
  1060
    load_reg( R_EAX, 0);
nkeynes@368
  1061
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1062
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1063
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1064
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1065
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1066
    SETE_t();
nkeynes@417
  1067
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1068
:}
nkeynes@359
  1069
XOR Rm, Rn {:  
nkeynes@671
  1070
    COUNT_INST(I_XOR);
nkeynes@359
  1071
    load_reg( R_EAX, Rm );
nkeynes@359
  1072
    load_reg( R_ECX, Rn );
nkeynes@359
  1073
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1074
    store_reg( R_ECX, Rn );
nkeynes@417
  1075
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1076
:}
nkeynes@359
  1077
XOR #imm, R0 {:  
nkeynes@671
  1078
    COUNT_INST(I_XORI);
nkeynes@359
  1079
    load_reg( R_EAX, 0 );
nkeynes@359
  1080
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1081
    store_reg( R_EAX, 0 );
nkeynes@417
  1082
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1083
:}
nkeynes@359
  1084
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1085
    COUNT_INST(I_XORB);
nkeynes@359
  1086
    load_reg( R_EAX, 0 );
nkeynes@359
  1087
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1088
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1089
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1090
    PUSH_realigned_r32(R_EAX);
nkeynes@586
  1091
    MEM_READ_BYTE(R_EAX, R_EAX);
nkeynes@547
  1092
    POP_realigned_r32(R_ECX);
nkeynes@359
  1093
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1094
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@417
  1095
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1096
:}
nkeynes@361
  1097
XTRCT Rm, Rn {:
nkeynes@671
  1098
    COUNT_INST(I_XTRCT);
nkeynes@361
  1099
    load_reg( R_EAX, Rm );
nkeynes@394
  1100
    load_reg( R_ECX, Rn );
nkeynes@394
  1101
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1102
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1103
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1104
    store_reg( R_ECX, Rn );
nkeynes@417
  1105
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1106
:}
nkeynes@359
  1107
nkeynes@359
  1108
/* Data move instructions */
nkeynes@359
  1109
MOV Rm, Rn {:  
nkeynes@671
  1110
    COUNT_INST(I_MOV);
nkeynes@359
  1111
    load_reg( R_EAX, Rm );
nkeynes@359
  1112
    store_reg( R_EAX, Rn );
nkeynes@359
  1113
:}
nkeynes@359
  1114
MOV #imm, Rn {:  
nkeynes@671
  1115
    COUNT_INST(I_MOVI);
nkeynes@359
  1116
    load_imm32( R_EAX, imm );
nkeynes@359
  1117
    store_reg( R_EAX, Rn );
nkeynes@359
  1118
:}
nkeynes@359
  1119
MOV.B Rm, @Rn {:  
nkeynes@671
  1120
    COUNT_INST(I_MOVB);
nkeynes@586
  1121
    load_reg( R_EAX, Rn );
nkeynes@586
  1122
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1123
    load_reg( R_EDX, Rm );
nkeynes@586
  1124
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1125
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1126
:}
nkeynes@359
  1127
MOV.B Rm, @-Rn {:  
nkeynes@671
  1128
    COUNT_INST(I_MOVB);
nkeynes@586
  1129
    load_reg( R_EAX, Rn );
nkeynes@586
  1130
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1131
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1132
    load_reg( R_EDX, Rm );
nkeynes@586
  1133
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1134
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1135
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1136
:}
nkeynes@359
  1137
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1138
    COUNT_INST(I_MOVB);
nkeynes@359
  1139
    load_reg( R_EAX, 0 );
nkeynes@359
  1140
    load_reg( R_ECX, Rn );
nkeynes@586
  1141
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1142
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1143
    load_reg( R_EDX, Rm );
nkeynes@586
  1144
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1145
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1146
:}
nkeynes@359
  1147
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1148
    COUNT_INST(I_MOVB);
nkeynes@586
  1149
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1150
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1151
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1152
    load_reg( R_EDX, 0 );
nkeynes@586
  1153
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1154
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1155
:}
nkeynes@359
  1156
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1157
    COUNT_INST(I_MOVB);
nkeynes@586
  1158
    load_reg( R_EAX, Rn );
nkeynes@586
  1159
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1160
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1161
    load_reg( R_EDX, 0 );
nkeynes@586
  1162
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1164
:}
nkeynes@359
  1165
MOV.B @Rm, Rn {:  
nkeynes@671
  1166
    COUNT_INST(I_MOVB);
nkeynes@586
  1167
    load_reg( R_EAX, Rm );
nkeynes@586
  1168
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1169
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1170
    store_reg( R_EAX, Rn );
nkeynes@417
  1171
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1172
:}
nkeynes@359
  1173
MOV.B @Rm+, Rn {:  
nkeynes@671
  1174
    COUNT_INST(I_MOVB);
nkeynes@586
  1175
    load_reg( R_EAX, Rm );
nkeynes@586
  1176
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1177
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1178
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1179
    store_reg( R_EAX, Rn );
nkeynes@417
  1180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1181
:}
nkeynes@359
  1182
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1183
    COUNT_INST(I_MOVB);
nkeynes@359
  1184
    load_reg( R_EAX, 0 );
nkeynes@359
  1185
    load_reg( R_ECX, Rm );
nkeynes@586
  1186
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1187
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1188
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1189
    store_reg( R_EAX, Rn );
nkeynes@417
  1190
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1191
:}
nkeynes@359
  1192
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1193
    COUNT_INST(I_MOVB);
nkeynes@586
  1194
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1195
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1196
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1197
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1198
    store_reg( R_EAX, 0 );
nkeynes@417
  1199
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1200
:}
nkeynes@359
  1201
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1202
    COUNT_INST(I_MOVB);
nkeynes@586
  1203
    load_reg( R_EAX, Rm );
nkeynes@586
  1204
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1205
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1206
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1207
    store_reg( R_EAX, 0 );
nkeynes@417
  1208
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1209
:}
nkeynes@374
  1210
MOV.L Rm, @Rn {:
nkeynes@671
  1211
    COUNT_INST(I_MOVL);
nkeynes@586
  1212
    load_reg( R_EAX, Rn );
nkeynes@586
  1213
    check_walign32(R_EAX);
nkeynes@586
  1214
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1215
    load_reg( R_EDX, Rm );
nkeynes@586
  1216
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1217
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1218
:}
nkeynes@361
  1219
MOV.L Rm, @-Rn {:  
nkeynes@671
  1220
    COUNT_INST(I_MOVL);
nkeynes@586
  1221
    load_reg( R_EAX, Rn );
nkeynes@586
  1222
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1223
    check_walign32( R_EAX );
nkeynes@586
  1224
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1225
    load_reg( R_EDX, Rm );
nkeynes@586
  1226
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1227
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1229
:}
nkeynes@361
  1230
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1231
    COUNT_INST(I_MOVL);
nkeynes@361
  1232
    load_reg( R_EAX, 0 );
nkeynes@361
  1233
    load_reg( R_ECX, Rn );
nkeynes@586
  1234
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1235
    check_walign32( R_EAX );
nkeynes@586
  1236
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1237
    load_reg( R_EDX, Rm );
nkeynes@586
  1238
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1239
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1240
:}
nkeynes@361
  1241
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1242
    COUNT_INST(I_MOVL);
nkeynes@586
  1243
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1244
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1245
    check_walign32( R_EAX );
nkeynes@586
  1246
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1247
    load_reg( R_EDX, 0 );
nkeynes@586
  1248
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1249
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1250
:}
nkeynes@361
  1251
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1252
    COUNT_INST(I_MOVL);
nkeynes@586
  1253
    load_reg( R_EAX, Rn );
nkeynes@586
  1254
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1255
    check_walign32( R_EAX );
nkeynes@586
  1256
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1257
    load_reg( R_EDX, Rm );
nkeynes@586
  1258
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1259
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1260
:}
nkeynes@361
  1261
MOV.L @Rm, Rn {:  
nkeynes@671
  1262
    COUNT_INST(I_MOVL);
nkeynes@586
  1263
    load_reg( R_EAX, Rm );
nkeynes@586
  1264
    check_ralign32( R_EAX );
nkeynes@586
  1265
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1266
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1267
    store_reg( R_EAX, Rn );
nkeynes@417
  1268
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1269
:}
nkeynes@361
  1270
MOV.L @Rm+, Rn {:  
nkeynes@671
  1271
    COUNT_INST(I_MOVL);
nkeynes@361
  1272
    load_reg( R_EAX, Rm );
nkeynes@382
  1273
    check_ralign32( R_EAX );
nkeynes@586
  1274
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1275
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1276
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1277
    store_reg( R_EAX, Rn );
nkeynes@417
  1278
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1279
:}
nkeynes@361
  1280
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1281
    COUNT_INST(I_MOVL);
nkeynes@361
  1282
    load_reg( R_EAX, 0 );
nkeynes@361
  1283
    load_reg( R_ECX, Rm );
nkeynes@586
  1284
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1285
    check_ralign32( R_EAX );
nkeynes@586
  1286
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1287
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1288
    store_reg( R_EAX, Rn );
nkeynes@417
  1289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1290
:}
nkeynes@361
  1291
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1292
    COUNT_INST(I_MOVL);
nkeynes@586
  1293
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1294
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1295
    check_ralign32( R_EAX );
nkeynes@586
  1296
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1297
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1298
    store_reg( R_EAX, 0 );
nkeynes@417
  1299
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1300
:}
nkeynes@361
  1301
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1302
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1303
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1304
	SLOTILLEGAL();
nkeynes@374
  1305
    } else {
nkeynes@388
  1306
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1307
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1308
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1309
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1310
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1311
nkeynes@586
  1312
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1313
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1314
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1315
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1316
	    // behaviour though.
nkeynes@586
  1317
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1318
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1319
	} else {
nkeynes@586
  1320
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1321
	    // different virtual address than the translation was done with,
nkeynes@586
  1322
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1323
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1324
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1325
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1326
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1327
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1328
	}
nkeynes@382
  1329
	store_reg( R_EAX, Rn );
nkeynes@374
  1330
    }
nkeynes@361
  1331
:}
nkeynes@361
  1332
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1333
    COUNT_INST(I_MOVL);
nkeynes@586
  1334
    load_reg( R_EAX, Rm );
nkeynes@586
  1335
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1336
    check_ralign32( R_EAX );
nkeynes@586
  1337
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1338
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1339
    store_reg( R_EAX, Rn );
nkeynes@417
  1340
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1341
:}
nkeynes@361
  1342
MOV.W Rm, @Rn {:  
nkeynes@671
  1343
    COUNT_INST(I_MOVW);
nkeynes@586
  1344
    load_reg( R_EAX, Rn );
nkeynes@586
  1345
    check_walign16( R_EAX );
nkeynes@586
  1346
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1347
    load_reg( R_EDX, Rm );
nkeynes@586
  1348
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1349
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1350
:}
nkeynes@361
  1351
MOV.W Rm, @-Rn {:  
nkeynes@671
  1352
    COUNT_INST(I_MOVW);
nkeynes@586
  1353
    load_reg( R_EAX, Rn );
nkeynes@586
  1354
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1355
    check_walign16( R_EAX );
nkeynes@586
  1356
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1357
    load_reg( R_EDX, Rm );
nkeynes@586
  1358
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1359
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1360
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1361
:}
nkeynes@361
  1362
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1363
    COUNT_INST(I_MOVW);
nkeynes@361
  1364
    load_reg( R_EAX, 0 );
nkeynes@361
  1365
    load_reg( R_ECX, Rn );
nkeynes@586
  1366
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1367
    check_walign16( R_EAX );
nkeynes@586
  1368
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1369
    load_reg( R_EDX, Rm );
nkeynes@586
  1370
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1371
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1372
:}
nkeynes@361
  1373
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1374
    COUNT_INST(I_MOVW);
nkeynes@586
  1375
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1376
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1377
    check_walign16( R_EAX );
nkeynes@586
  1378
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1379
    load_reg( R_EDX, 0 );
nkeynes@586
  1380
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1381
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1382
:}
nkeynes@361
  1383
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1384
    COUNT_INST(I_MOVW);
nkeynes@586
  1385
    load_reg( R_EAX, Rn );
nkeynes@586
  1386
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1387
    check_walign16( R_EAX );
nkeynes@586
  1388
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1389
    load_reg( R_EDX, 0 );
nkeynes@586
  1390
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1392
:}
nkeynes@361
  1393
MOV.W @Rm, Rn {:  
nkeynes@671
  1394
    COUNT_INST(I_MOVW);
nkeynes@586
  1395
    load_reg( R_EAX, Rm );
nkeynes@586
  1396
    check_ralign16( R_EAX );
nkeynes@586
  1397
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1398
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1399
    store_reg( R_EAX, Rn );
nkeynes@417
  1400
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1401
:}
nkeynes@361
  1402
MOV.W @Rm+, Rn {:  
nkeynes@671
  1403
    COUNT_INST(I_MOVW);
nkeynes@361
  1404
    load_reg( R_EAX, Rm );
nkeynes@374
  1405
    check_ralign16( R_EAX );
nkeynes@586
  1406
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1407
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1408
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1409
    store_reg( R_EAX, Rn );
nkeynes@417
  1410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1411
:}
nkeynes@361
  1412
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1413
    COUNT_INST(I_MOVW);
nkeynes@361
  1414
    load_reg( R_EAX, 0 );
nkeynes@361
  1415
    load_reg( R_ECX, Rm );
nkeynes@586
  1416
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1417
    check_ralign16( R_EAX );
nkeynes@586
  1418
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1419
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1420
    store_reg( R_EAX, Rn );
nkeynes@417
  1421
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1422
:}
nkeynes@361
  1423
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1424
    COUNT_INST(I_MOVW);
nkeynes@586
  1425
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1426
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1427
    check_ralign16( R_EAX );
nkeynes@586
  1428
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1429
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1430
    store_reg( R_EAX, 0 );
nkeynes@417
  1431
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1432
:}
nkeynes@361
  1433
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1434
    COUNT_INST(I_MOVW);
nkeynes@374
  1435
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1436
	SLOTILLEGAL();
nkeynes@374
  1437
    } else {
nkeynes@586
  1438
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1439
	uint32_t target = pc + disp + 4;
nkeynes@586
  1440
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1441
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1442
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1443
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1444
	} else {
nkeynes@586
  1445
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1446
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1447
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1448
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1449
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1450
	}
nkeynes@374
  1451
	store_reg( R_EAX, Rn );
nkeynes@374
  1452
    }
nkeynes@361
  1453
:}
nkeynes@361
  1454
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1455
    COUNT_INST(I_MOVW);
nkeynes@586
  1456
    load_reg( R_EAX, Rm );
nkeynes@586
  1457
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1458
    check_ralign16( R_EAX );
nkeynes@586
  1459
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1460
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1461
    store_reg( R_EAX, 0 );
nkeynes@417
  1462
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1463
:}
nkeynes@361
  1464
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1465
    COUNT_INST(I_MOVA);
nkeynes@374
  1466
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1467
	SLOTILLEGAL();
nkeynes@374
  1468
    } else {
nkeynes@586
  1469
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1470
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1471
	store_reg( R_ECX, 0 );
nkeynes@586
  1472
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1473
    }
nkeynes@361
  1474
:}
nkeynes@361
  1475
MOVCA.L R0, @Rn {:  
nkeynes@671
  1476
    COUNT_INST(I_MOVCA);
nkeynes@586
  1477
    load_reg( R_EAX, Rn );
nkeynes@586
  1478
    check_walign32( R_EAX );
nkeynes@586
  1479
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1480
    load_reg( R_EDX, 0 );
nkeynes@586
  1481
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1482
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1483
:}
nkeynes@359
  1484
nkeynes@359
  1485
/* Control transfer instructions */
nkeynes@374
  1486
BF disp {:
nkeynes@671
  1487
    COUNT_INST(I_BF);
nkeynes@374
  1488
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1489
	SLOTILLEGAL();
nkeynes@374
  1490
    } else {
nkeynes@586
  1491
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1492
	JT_rel8( nottaken );
nkeynes@586
  1493
	exit_block_rel(target, pc+2 );
nkeynes@380
  1494
	JMP_TARGET(nottaken);
nkeynes@408
  1495
	return 2;
nkeynes@374
  1496
    }
nkeynes@374
  1497
:}
nkeynes@374
  1498
BF/S disp {:
nkeynes@671
  1499
    COUNT_INST(I_BFS);
nkeynes@374
  1500
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1501
	SLOTILLEGAL();
nkeynes@374
  1502
    } else {
nkeynes@590
  1503
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1504
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1505
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1506
	    JT_rel8(nottaken);
nkeynes@601
  1507
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1508
	    JMP_TARGET(nottaken);
nkeynes@601
  1509
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1510
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1511
	    exit_block_emu(pc+2);
nkeynes@601
  1512
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1513
	    return 2;
nkeynes@601
  1514
	} else {
nkeynes@601
  1515
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1516
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1517
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1518
	    }
nkeynes@601
  1519
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1520
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@601
  1521
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1522
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1523
	    
nkeynes@601
  1524
	    // not taken
nkeynes@601
  1525
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1526
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1527
	    return 4;
nkeynes@417
  1528
	}
nkeynes@374
  1529
    }
nkeynes@374
  1530
:}
nkeynes@374
  1531
BRA disp {:  
nkeynes@671
  1532
    COUNT_INST(I_BRA);
nkeynes@374
  1533
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1534
	SLOTILLEGAL();
nkeynes@374
  1535
    } else {
nkeynes@590
  1536
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1537
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1538
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1539
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1540
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1541
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1542
	    exit_block_emu(pc+2);
nkeynes@601
  1543
	    return 2;
nkeynes@601
  1544
	} else {
nkeynes@601
  1545
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1546
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1547
	    return 4;
nkeynes@601
  1548
	}
nkeynes@374
  1549
    }
nkeynes@374
  1550
:}
nkeynes@374
  1551
BRAF Rn {:  
nkeynes@671
  1552
    COUNT_INST(I_BRAF);
nkeynes@374
  1553
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1554
	SLOTILLEGAL();
nkeynes@374
  1555
    } else {
nkeynes@590
  1556
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1557
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1558
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1559
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1560
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1561
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1562
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1563
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1564
	    exit_block_emu(pc+2);
nkeynes@601
  1565
	    return 2;
nkeynes@601
  1566
	} else {
nkeynes@601
  1567
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1568
	    exit_block_newpcset(pc+2);
nkeynes@601
  1569
	    return 4;
nkeynes@601
  1570
	}
nkeynes@374
  1571
    }
nkeynes@374
  1572
:}
nkeynes@374
  1573
BSR disp {:  
nkeynes@671
  1574
    COUNT_INST(I_BSR);
nkeynes@374
  1575
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1576
	SLOTILLEGAL();
nkeynes@374
  1577
    } else {
nkeynes@590
  1578
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1579
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1580
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1581
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1582
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1583
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1584
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1585
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1586
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1587
	    exit_block_emu(pc+2);
nkeynes@601
  1588
	    return 2;
nkeynes@601
  1589
	} else {
nkeynes@601
  1590
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1591
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1592
	    return 4;
nkeynes@601
  1593
	}
nkeynes@374
  1594
    }
nkeynes@374
  1595
:}
nkeynes@374
  1596
BSRF Rn {:  
nkeynes@671
  1597
    COUNT_INST(I_BSRF);
nkeynes@374
  1598
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1599
	SLOTILLEGAL();
nkeynes@374
  1600
    } else {
nkeynes@590
  1601
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1602
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1603
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1604
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1605
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1606
nkeynes@601
  1607
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1608
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1609
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1610
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1611
	    exit_block_emu(pc+2);
nkeynes@601
  1612
	    return 2;
nkeynes@601
  1613
	} else {
nkeynes@601
  1614
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1615
	    exit_block_newpcset(pc+2);
nkeynes@601
  1616
	    return 4;
nkeynes@601
  1617
	}
nkeynes@374
  1618
    }
nkeynes@374
  1619
:}
nkeynes@374
  1620
BT disp {:
nkeynes@671
  1621
    COUNT_INST(I_BT);
nkeynes@374
  1622
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1623
	SLOTILLEGAL();
nkeynes@374
  1624
    } else {
nkeynes@586
  1625
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1626
	JF_rel8( nottaken );
nkeynes@586
  1627
	exit_block_rel(target, pc+2 );
nkeynes@380
  1628
	JMP_TARGET(nottaken);
nkeynes@408
  1629
	return 2;
nkeynes@374
  1630
    }
nkeynes@374
  1631
:}
nkeynes@374
  1632
BT/S disp {:
nkeynes@671
  1633
    COUNT_INST(I_BTS);
nkeynes@374
  1634
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1635
	SLOTILLEGAL();
nkeynes@374
  1636
    } else {
nkeynes@590
  1637
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1638
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1639
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1640
	    JF_rel8(nottaken);
nkeynes@601
  1641
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1642
	    JMP_TARGET(nottaken);
nkeynes@601
  1643
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1644
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1645
	    exit_block_emu(pc+2);
nkeynes@601
  1646
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1647
	    return 2;
nkeynes@601
  1648
	} else {
nkeynes@601
  1649
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1650
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1651
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1652
	    }
nkeynes@601
  1653
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@601
  1654
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1655
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1656
	    // not taken
nkeynes@601
  1657
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@601
  1658
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1659
	    return 4;
nkeynes@417
  1660
	}
nkeynes@374
  1661
    }
nkeynes@374
  1662
:}
nkeynes@374
  1663
JMP @Rn {:  
nkeynes@671
  1664
    COUNT_INST(I_JMP);
nkeynes@374
  1665
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1666
	SLOTILLEGAL();
nkeynes@374
  1667
    } else {
nkeynes@408
  1668
	load_reg( R_ECX, Rn );
nkeynes@590
  1669
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1670
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1671
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1672
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1673
	    exit_block_emu(pc+2);
nkeynes@601
  1674
	    return 2;
nkeynes@601
  1675
	} else {
nkeynes@601
  1676
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1677
	    exit_block_newpcset(pc+2);
nkeynes@601
  1678
	    return 4;
nkeynes@601
  1679
	}
nkeynes@374
  1680
    }
nkeynes@374
  1681
:}
nkeynes@374
  1682
JSR @Rn {:  
nkeynes@671
  1683
    COUNT_INST(I_JSR);
nkeynes@374
  1684
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1685
	SLOTILLEGAL();
nkeynes@374
  1686
    } else {
nkeynes@590
  1687
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1688
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1689
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1690
	load_reg( R_ECX, Rn );
nkeynes@590
  1691
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1692
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1693
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1694
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1695
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1696
	    exit_block_emu(pc+2);
nkeynes@601
  1697
	    return 2;
nkeynes@601
  1698
	} else {
nkeynes@601
  1699
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1700
	    exit_block_newpcset(pc+2);
nkeynes@601
  1701
	    return 4;
nkeynes@601
  1702
	}
nkeynes@374
  1703
    }
nkeynes@374
  1704
:}
nkeynes@374
  1705
RTE {:  
nkeynes@671
  1706
    COUNT_INST(I_RTE);
nkeynes@374
  1707
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1708
	SLOTILLEGAL();
nkeynes@374
  1709
    } else {
nkeynes@408
  1710
	check_priv();
nkeynes@408
  1711
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1712
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1713
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1714
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1715
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1716
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1717
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1718
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1719
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1720
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1721
	    exit_block_emu(pc+2);
nkeynes@601
  1722
	    return 2;
nkeynes@601
  1723
	} else {
nkeynes@601
  1724
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1725
	    exit_block_newpcset(pc+2);
nkeynes@601
  1726
	    return 4;
nkeynes@601
  1727
	}
nkeynes@374
  1728
    }
nkeynes@374
  1729
:}
nkeynes@374
  1730
RTS {:  
nkeynes@671
  1731
    COUNT_INST(I_RTS);
nkeynes@374
  1732
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1733
	SLOTILLEGAL();
nkeynes@374
  1734
    } else {
nkeynes@408
  1735
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1736
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1737
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1738
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1739
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1740
	    exit_block_emu(pc+2);
nkeynes@601
  1741
	    return 2;
nkeynes@601
  1742
	} else {
nkeynes@601
  1743
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1744
	    exit_block_newpcset(pc+2);
nkeynes@601
  1745
	    return 4;
nkeynes@601
  1746
	}
nkeynes@374
  1747
    }
nkeynes@374
  1748
:}
nkeynes@374
  1749
TRAPA #imm {:  
nkeynes@671
  1750
    COUNT_INST(I_TRAPA);
nkeynes@374
  1751
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1752
	SLOTILLEGAL();
nkeynes@374
  1753
    } else {
nkeynes@590
  1754
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1755
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1756
	load_imm32( R_EAX, imm );
nkeynes@527
  1757
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1758
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1759
	exit_block_pcset(pc);
nkeynes@409
  1760
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1761
	return 2;
nkeynes@374
  1762
    }
nkeynes@374
  1763
:}
nkeynes@374
  1764
UNDEF {:  
nkeynes@671
  1765
    COUNT_INST(I_UNDEF);
nkeynes@374
  1766
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1767
	SLOTILLEGAL();
nkeynes@374
  1768
    } else {
nkeynes@586
  1769
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1770
	return 2;
nkeynes@374
  1771
    }
nkeynes@368
  1772
:}
nkeynes@374
  1773
nkeynes@374
  1774
CLRMAC {:  
nkeynes@671
  1775
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1776
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1777
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1778
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1779
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1780
:}
nkeynes@374
  1781
CLRS {:
nkeynes@671
  1782
    COUNT_INST(I_CLRS);
nkeynes@374
  1783
    CLC();
nkeynes@374
  1784
    SETC_sh4r(R_S);
nkeynes@417
  1785
    sh4_x86.tstate = TSTATE_C;
nkeynes@368
  1786
:}
nkeynes@374
  1787
CLRT {:  
nkeynes@671
  1788
    COUNT_INST(I_CLRT);
nkeynes@374
  1789
    CLC();
nkeynes@374
  1790
    SETC_t();
nkeynes@417
  1791
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1792
:}
nkeynes@374
  1793
SETS {:  
nkeynes@671
  1794
    COUNT_INST(I_SETS);
nkeynes@374
  1795
    STC();
nkeynes@374
  1796
    SETC_sh4r(R_S);
nkeynes@417
  1797
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1798
:}
nkeynes@374
  1799
SETT {:  
nkeynes@671
  1800
    COUNT_INST(I_SETT);
nkeynes@374
  1801
    STC();
nkeynes@374
  1802
    SETC_t();
nkeynes@417
  1803
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1804
:}
nkeynes@359
  1805
nkeynes@375
  1806
/* Floating point moves */
nkeynes@375
  1807
FMOV FRm, FRn {:  
nkeynes@671
  1808
    COUNT_INST(I_FMOV1);
nkeynes@377
  1809
    check_fpuen();
nkeynes@375
  1810
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1811
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@669
  1812
    JNE_rel8(doublesize);
nkeynes@673
  1813
    load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@669
  1814
    store_fr( R_EAX, FRn );
nkeynes@669
  1815
    JMP_rel8(end);
nkeynes@669
  1816
    JMP_TARGET(doublesize);
nkeynes@669
  1817
    load_dr0( R_EAX, FRm );
nkeynes@669
  1818
    load_dr1( R_ECX, FRm );
nkeynes@669
  1819
    store_dr0( R_EAX, FRn );
nkeynes@669
  1820
    store_dr1( R_ECX, FRn );
nkeynes@669
  1821
    JMP_TARGET(end);
nkeynes@417
  1822
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1823
:}
nkeynes@416
  1824
FMOV FRm, @Rn {: 
nkeynes@671
  1825
    COUNT_INST(I_FMOV2);
nkeynes@586
  1826
    check_fpuen();
nkeynes@586
  1827
    load_reg( R_EAX, Rn );
nkeynes@416
  1828
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1829
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1830
    JNE_rel8(doublesize);
nkeynes@669
  1831
nkeynes@732
  1832
    check_walign32( R_EAX );
nkeynes@732
  1833
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1834
    load_fr( R_ECX, FRm );
nkeynes@586
  1835
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1836
    JMP_rel8(end);
nkeynes@669
  1837
nkeynes@669
  1838
    JMP_TARGET(doublesize);
nkeynes@732
  1839
    check_walign64( R_EAX );
nkeynes@732
  1840
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1841
    load_dr0( R_ECX, FRm );
nkeynes@669
  1842
    load_dr1( R_EDX, FRm );
nkeynes@669
  1843
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1844
    JMP_TARGET(end);
nkeynes@417
  1845
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1846
:}
nkeynes@375
  1847
FMOV @Rm, FRn {:  
nkeynes@671
  1848
    COUNT_INST(I_FMOV5);
nkeynes@586
  1849
    check_fpuen();
nkeynes@586
  1850
    load_reg( R_EAX, Rm );
nkeynes@416
  1851
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1852
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1853
    JNE_rel8(doublesize);
nkeynes@669
  1854
nkeynes@732
  1855
    check_ralign32( R_EAX );
nkeynes@732
  1856
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1857
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1858
    store_fr( R_EAX, FRn );
nkeynes@669
  1859
    JMP_rel8(end);
nkeynes@669
  1860
nkeynes@669
  1861
    JMP_TARGET(doublesize);
nkeynes@732
  1862
    check_ralign64( R_EAX );
nkeynes@732
  1863
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1864
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1865
    store_dr0( R_ECX, FRn );
nkeynes@669
  1866
    store_dr1( R_EAX, FRn );
nkeynes@669
  1867
    JMP_TARGET(end);
nkeynes@417
  1868
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1869
:}
nkeynes@377
  1870
FMOV FRm, @-Rn {:  
nkeynes@671
  1871
    COUNT_INST(I_FMOV3);
nkeynes@586
  1872
    check_fpuen();
nkeynes@586
  1873
    load_reg( R_EAX, Rn );
nkeynes@416
  1874
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1875
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1876
    JNE_rel8(doublesize);
nkeynes@669
  1877
nkeynes@732
  1878
    check_walign32( R_EAX );
nkeynes@586
  1879
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1880
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1881
    load_fr( R_ECX, FRm );
nkeynes@586
  1882
    ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@669
  1883
    MEM_WRITE_LONG( R_EAX, R_ECX );
nkeynes@669
  1884
    JMP_rel8(end);
nkeynes@669
  1885
nkeynes@669
  1886
    JMP_TARGET(doublesize);
nkeynes@732
  1887
    check_walign64( R_EAX );
nkeynes@669
  1888
    ADD_imm8s_r32(-8,R_EAX);
nkeynes@669
  1889
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1890
    load_dr0( R_ECX, FRm );
nkeynes@669
  1891
    load_dr1( R_EDX, FRm );
nkeynes@669
  1892
    ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@669
  1893
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1894
    JMP_TARGET(end);
nkeynes@669
  1895
nkeynes@417
  1896
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1897
:}
nkeynes@416
  1898
FMOV @Rm+, FRn {:
nkeynes@671
  1899
    COUNT_INST(I_FMOV6);
nkeynes@586
  1900
    check_fpuen();
nkeynes@586
  1901
    load_reg( R_EAX, Rm );
nkeynes@416
  1902
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1903
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1904
    JNE_rel8(doublesize);
nkeynes@669
  1905
nkeynes@732
  1906
    check_ralign32( R_EAX );
nkeynes@732
  1907
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1908
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1909
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1910
    store_fr( R_EAX, FRn );
nkeynes@669
  1911
    JMP_rel8(end);
nkeynes@669
  1912
nkeynes@669
  1913
    JMP_TARGET(doublesize);
nkeynes@732
  1914
    check_ralign64( R_EAX );
nkeynes@732
  1915
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1916
    ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@669
  1917
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1918
    store_dr0( R_ECX, FRn );
nkeynes@669
  1919
    store_dr1( R_EAX, FRn );
nkeynes@669
  1920
    JMP_TARGET(end);
nkeynes@669
  1921
nkeynes@417
  1922
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1923
:}
nkeynes@377
  1924
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1925
    COUNT_INST(I_FMOV4);
nkeynes@586
  1926
    check_fpuen();
nkeynes@586
  1927
    load_reg( R_EAX, Rn );
nkeynes@586
  1928
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@416
  1929
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1930
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1931
    JNE_rel8(doublesize);
nkeynes@669
  1932
nkeynes@732
  1933
    check_walign32( R_EAX );
nkeynes@732
  1934
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1935
    load_fr( R_ECX, FRm );
nkeynes@586
  1936
    MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
nkeynes@669
  1937
    JMP_rel8(end);
nkeynes@669
  1938
nkeynes@669
  1939
    JMP_TARGET(doublesize);
nkeynes@732
  1940
    check_walign64( R_EAX );
nkeynes@732
  1941
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@669
  1942
    load_dr0( R_ECX, FRm );
nkeynes@669
  1943
    load_dr1( R_EDX, FRm );
nkeynes@669
  1944
    MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
nkeynes@669
  1945
    JMP_TARGET(end);
nkeynes@669
  1946
nkeynes@417
  1947
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1948
:}
nkeynes@377
  1949
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1950
    COUNT_INST(I_FMOV7);
nkeynes@586
  1951
    check_fpuen();
nkeynes@586
  1952
    load_reg( R_EAX, Rm );
nkeynes@586
  1953
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@416
  1954
    load_spreg( R_EDX, R_FPSCR );
nkeynes@416
  1955
    TEST_imm32_r32( FPSCR_SZ, R_EDX );
nkeynes@669
  1956
    JNE_rel8(doublesize);
nkeynes@669
  1957
nkeynes@732
  1958
    check_ralign32( R_EAX );
nkeynes@732
  1959
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1960
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  1961
    store_fr( R_EAX, FRn );
nkeynes@669
  1962
    JMP_rel8(end);
nkeynes@669
  1963
nkeynes@669
  1964
    JMP_TARGET(doublesize);
nkeynes@732
  1965
    check_ralign64( R_EAX );
nkeynes@732
  1966
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@669
  1967
    MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@669
  1968
    store_dr0( R_ECX, FRn );
nkeynes@669
  1969
    store_dr1( R_EAX, FRn );
nkeynes@669
  1970
    JMP_TARGET(end);
nkeynes@669
  1971
nkeynes@417
  1972
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1973
:}
nkeynes@377
  1974
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1975
    COUNT_INST(I_FLDI0);
nkeynes@377
  1976
    check_fpuen();
nkeynes@377
  1977
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1978
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1979
    JNE_rel8(end);
nkeynes@377
  1980
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  1981
    store_fr( R_EAX, FRn );
nkeynes@380
  1982
    JMP_TARGET(end);
nkeynes@417
  1983
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1984
:}
nkeynes@377
  1985
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1986
    COUNT_INST(I_FLDI1);
nkeynes@377
  1987
    check_fpuen();
nkeynes@377
  1988
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1989
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  1990
    JNE_rel8(end);
nkeynes@377
  1991
    load_imm32(R_EAX, 0x3F800000);
nkeynes@669
  1992
    store_fr( R_EAX, FRn );
nkeynes@380
  1993
    JMP_TARGET(end);
nkeynes@417
  1994
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1995
:}
nkeynes@377
  1996
nkeynes@377
  1997
FLOAT FPUL, FRn {:  
nkeynes@671
  1998
    COUNT_INST(I_FLOAT);
nkeynes@377
  1999
    check_fpuen();
nkeynes@377
  2000
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2001
    FILD_sh4r(R_FPUL);
nkeynes@377
  2002
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2003
    JNE_rel8(doubleprec);
nkeynes@669
  2004
    pop_fr( FRn );
nkeynes@669
  2005
    JMP_rel8(end);
nkeynes@380
  2006
    JMP_TARGET(doubleprec);
nkeynes@669
  2007
    pop_dr( FRn );
nkeynes@380
  2008
    JMP_TARGET(end);
nkeynes@417
  2009
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2010
:}
nkeynes@377
  2011
FTRC FRm, FPUL {:  
nkeynes@671
  2012
    COUNT_INST(I_FTRC);
nkeynes@377
  2013
    check_fpuen();
nkeynes@388
  2014
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2015
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2016
    JNE_rel8(doubleprec);
nkeynes@669
  2017
    push_fr( FRm );
nkeynes@669
  2018
    JMP_rel8(doop);
nkeynes@388
  2019
    JMP_TARGET(doubleprec);
nkeynes@669
  2020
    push_dr( FRm );
nkeynes@388
  2021
    JMP_TARGET( doop );
nkeynes@388
  2022
    load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388
  2023
    FILD_r32ind( R_ECX );
nkeynes@388
  2024
    FCOMIP_st(1);
nkeynes@669
  2025
    JNA_rel8( sat );
nkeynes@388
  2026
    load_imm32( R_ECX, (uint32_t)&min_int );  // 5
nkeynes@388
  2027
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2028
    FCOMIP_st(1);                   // 2
nkeynes@669
  2029
    JAE_rel8( sat2 );            // 2
nkeynes@394
  2030
    load_imm32( R_EAX, (uint32_t)&save_fcw );
nkeynes@394
  2031
    FNSTCW_r32ind( R_EAX );
nkeynes@394
  2032
    load_imm32( R_EDX, (uint32_t)&trunc_fcw );
nkeynes@394
  2033
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2034
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2035
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2036
    JMP_rel8(end);             // 2
nkeynes@388
  2037
nkeynes@388
  2038
    JMP_TARGET(sat);
nkeynes@388
  2039
    JMP_TARGET(sat2);
nkeynes@388
  2040
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2041
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2042
    FPOP_st();
nkeynes@388
  2043
    JMP_TARGET(end);
nkeynes@417
  2044
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2045
:}
nkeynes@377
  2046
FLDS FRm, FPUL {:  
nkeynes@671
  2047
    COUNT_INST(I_FLDS);
nkeynes@377
  2048
    check_fpuen();
nkeynes@669
  2049
    load_fr( R_EAX, FRm );
nkeynes@377
  2050
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2051
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2052
:}
nkeynes@377
  2053
FSTS FPUL, FRn {:  
nkeynes@671
  2054
    COUNT_INST(I_FSTS);
nkeynes@377
  2055
    check_fpuen();
nkeynes@377
  2056
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2057
    store_fr( R_EAX, FRn );
nkeynes@417
  2058
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2059
:}
nkeynes@377
  2060
FCNVDS FRm, FPUL {:  
nkeynes@671
  2061
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2062
    check_fpuen();
nkeynes@377
  2063
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2064
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2065
    JE_rel8(end); // only when PR=1
nkeynes@669
  2066
    push_dr( FRm );
nkeynes@377
  2067
    pop_fpul();
nkeynes@380
  2068
    JMP_TARGET(end);
nkeynes@417
  2069
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2070
:}
nkeynes@377
  2071
FCNVSD FPUL, FRn {:  
nkeynes@671
  2072
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2073
    check_fpuen();
nkeynes@377
  2074
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2075
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2076
    JE_rel8(end); // only when PR=1
nkeynes@377
  2077
    push_fpul();
nkeynes@669
  2078
    pop_dr( FRn );
nkeynes@380
  2079
    JMP_TARGET(end);
nkeynes@417
  2080
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2081
:}
nkeynes@375
  2082
nkeynes@359
  2083
/* Floating point instructions */
nkeynes@374
  2084
FABS FRn {:  
nkeynes@671
  2085
    COUNT_INST(I_FABS);
nkeynes@377
  2086
    check_fpuen();
nkeynes@374
  2087
    load_spreg( R_ECX, R_FPSCR );
nkeynes@374
  2088
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2089
    JNE_rel8(doubleprec);
nkeynes@669
  2090
    push_fr(FRn); // 6
nkeynes@374
  2091
    FABS_st0(); // 2
nkeynes@669
  2092
    pop_fr(FRn); //6
nkeynes@669
  2093
    JMP_rel8(end); // 2
nkeynes@380
  2094
    JMP_TARGET(doubleprec);
nkeynes@669
  2095
    push_dr(FRn);
nkeynes@374
  2096
    FABS_st0();
nkeynes@669
  2097
    pop_dr(FRn);
nkeynes@380
  2098
    JMP_TARGET(end);
nkeynes@417
  2099
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2100
:}
nkeynes@377
  2101
FADD FRm, FRn {:  
nkeynes@671
  2102
    COUNT_INST(I_FADD);
nkeynes@377
  2103
    check_fpuen();
nkeynes@375
  2104
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2105
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2106
    JNE_rel8(doubleprec);
nkeynes@669
  2107
    push_fr(FRm);
nkeynes@669
  2108
    push_fr(FRn);
nkeynes@377
  2109
    FADDP_st(1);
nkeynes@669
  2110
    pop_fr(FRn);
nkeynes@669
  2111
    JMP_rel8(end);
nkeynes@380
  2112
    JMP_TARGET(doubleprec);
nkeynes@669
  2113
    push_dr(FRm);
nkeynes@669
  2114
    push_dr(FRn);
nkeynes@377
  2115
    FADDP_st(1);
nkeynes@669
  2116
    pop_dr(FRn);
nkeynes@380
  2117
    JMP_TARGET(end);
nkeynes@417
  2118
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2119
:}
nkeynes@377
  2120
FDIV FRm, FRn {:  
nkeynes@671
  2121
    COUNT_INST(I_FDIV);
nkeynes@377
  2122
    check_fpuen();
nkeynes@375
  2123
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2124
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2125
    JNE_rel8(doubleprec);
nkeynes@669
  2126
    push_fr(FRn);
nkeynes@669
  2127
    push_fr(FRm);
nkeynes@377
  2128
    FDIVP_st(1);
nkeynes@669
  2129
    pop_fr(FRn);
nkeynes@669
  2130
    JMP_rel8(end);
nkeynes@380
  2131
    JMP_TARGET(doubleprec);
nkeynes@669
  2132
    push_dr(FRn);
nkeynes@669
  2133
    push_dr(FRm);
nkeynes@377
  2134
    FDIVP_st(1);
nkeynes@669
  2135
    pop_dr(FRn);
nkeynes@380
  2136
    JMP_TARGET(end);
nkeynes@417
  2137
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2138
:}
nkeynes@375
  2139
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2140
    COUNT_INST(I_FMAC);
nkeynes@377
  2141
    check_fpuen();
nkeynes@375
  2142
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2143
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2144
    JNE_rel8(doubleprec);
nkeynes@669
  2145
    push_fr( 0 );
nkeynes@669
  2146
    push_fr( FRm );
nkeynes@375
  2147
    FMULP_st(1);
nkeynes@669
  2148
    push_fr( FRn );
nkeynes@375
  2149
    FADDP_st(1);
nkeynes@669
  2150
    pop_fr( FRn );
nkeynes@669
  2151
    JMP_rel8(end);
nkeynes@380
  2152
    JMP_TARGET(doubleprec);
nkeynes@669
  2153
    push_dr( 0 );
nkeynes@669
  2154
    push_dr( FRm );
nkeynes@375
  2155
    FMULP_st(1);
nkeynes@669
  2156
    push_dr( FRn );
nkeynes@375
  2157
    FADDP_st(1);
nkeynes@669
  2158
    pop_dr( FRn );
nkeynes@380
  2159
    JMP_TARGET(end);
nkeynes@417
  2160
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  2161
:}
nkeynes@375
  2162
nkeynes@377
  2163
FMUL FRm, FRn {:  
nkeynes@671
  2164
    COUNT_INST(I_FMUL);
nkeynes@377
  2165
    check_fpuen();
nkeynes@377
  2166
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2167
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2168
    JNE_rel8(doubleprec);
nkeynes@669
  2169
    push_fr(FRm);
nkeynes@669
  2170
    push_fr(FRn);
nkeynes@377
  2171
    FMULP_st(1);
nkeynes@669
  2172
    pop_fr(FRn);
nkeynes@669
  2173
    JMP_rel8(end);
nkeynes@380
  2174
    JMP_TARGET(doubleprec);
nkeynes@669
  2175
    push_dr(FRm);
nkeynes@669
  2176
    push_dr(FRn);
nkeynes@377
  2177
    FMULP_st(1);
nkeynes@669
  2178
    pop_dr(FRn);
nkeynes@380
  2179
    JMP_TARGET(end);
nkeynes@417
  2180
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2181
:}
nkeynes@377
  2182
FNEG FRn {:  
nkeynes@671
  2183
    COUNT_INST(I_FNEG);
nkeynes@377
  2184
    check_fpuen();
nkeynes@377
  2185
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2186
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2187
    JNE_rel8(doubleprec);
nkeynes@669
  2188
    push_fr(FRn);
nkeynes@377
  2189
    FCHS_st0();
nkeynes@669
  2190
    pop_fr(FRn);
nkeynes@669
  2191
    JMP_rel8(end);
nkeynes@380
  2192
    JMP_TARGET(doubleprec);
nkeynes@669
  2193
    push_dr(FRn);
nkeynes@377
  2194
    FCHS_st0();
nkeynes@669
  2195
    pop_dr(FRn);
nkeynes@380
  2196
    JMP_TARGET(end);
nkeynes@417
  2197
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2198
:}
nkeynes@377
  2199
FSRRA FRn {:  
nkeynes@671
  2200
    COUNT_INST(I_FSRRA);
nkeynes@377
  2201
    check_fpuen();
nkeynes@377
  2202
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2203
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2204
    JNE_rel8(end); // PR=0 only
nkeynes@377
  2205
    FLD1_st0();
nkeynes@669
  2206
    push_fr(FRn);
nkeynes@377
  2207
    FSQRT_st0();
nkeynes@377
  2208
    FDIVP_st(1);
nkeynes@669
  2209
    pop_fr(FRn);
nkeynes@380
  2210
    JMP_TARGET(end);
nkeynes@417
  2211
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2212
:}
nkeynes@377
  2213
FSQRT FRn {:  
nkeynes@671
  2214
    COUNT_INST(I_FSQRT);
nkeynes@377
  2215
    check_fpuen();
nkeynes@377
  2216
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2217
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2218
    JNE_rel8(doubleprec);
nkeynes@669
  2219
    push_fr(FRn);
nkeynes@377
  2220
    FSQRT_st0();
nkeynes@669
  2221
    pop_fr(FRn);
nkeynes@669
  2222
    JMP_rel8(end);
nkeynes@380
  2223
    JMP_TARGET(doubleprec);
nkeynes@669
  2224
    push_dr(FRn);
nkeynes@377
  2225
    FSQRT_st0();
nkeynes@669
  2226
    pop_dr(FRn);
nkeynes@380
  2227
    JMP_TARGET(end);
nkeynes@417
  2228
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2229
:}
nkeynes@377
  2230
FSUB FRm, FRn {:  
nkeynes@671
  2231
    COUNT_INST(I_FSUB);
nkeynes@377
  2232
    check_fpuen();
nkeynes@377
  2233
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2234
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2235
    JNE_rel8(doubleprec);
nkeynes@669
  2236
    push_fr(FRn);
nkeynes@669
  2237
    push_fr(FRm);
nkeynes@388
  2238
    FSUBP_st(1);
nkeynes@669
  2239
    pop_fr(FRn);
nkeynes@669
  2240
    JMP_rel8(end);
nkeynes@380
  2241
    JMP_TARGET(doubleprec);
nkeynes@669
  2242
    push_dr(FRn);
nkeynes@669
  2243
    push_dr(FRm);
nkeynes@388
  2244
    FSUBP_st(1);
nkeynes@669
  2245
    pop_dr(FRn);
nkeynes@380
  2246
    JMP_TARGET(end);
nkeynes@417
  2247
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2248
:}
nkeynes@377
  2249
nkeynes@377
  2250
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2251
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2252
    check_fpuen();
nkeynes@377
  2253
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2254
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2255
    JNE_rel8(doubleprec);
nkeynes@669
  2256
    push_fr(FRm);
nkeynes@669
  2257
    push_fr(FRn);
nkeynes@669
  2258
    JMP_rel8(end);
nkeynes@380
  2259
    JMP_TARGET(doubleprec);
nkeynes@669
  2260
    push_dr(FRm);
nkeynes@669
  2261
    push_dr(FRn);
nkeynes@382
  2262
    JMP_TARGET(end);
nkeynes@377
  2263
    FCOMIP_st(1);
nkeynes@377
  2264
    SETE_t();
nkeynes@377
  2265
    FPOP_st();
nkeynes@417
  2266
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2267
:}
nkeynes@377
  2268
FCMP/GT FRm, FRn {:  
nkeynes@671
  2269
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2270
    check_fpuen();
nkeynes@377
  2271
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2272
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2273
    JNE_rel8(doubleprec);
nkeynes@669
  2274
    push_fr(FRm);
nkeynes@669
  2275
    push_fr(FRn);
nkeynes@669
  2276
    JMP_rel8(end);
nkeynes@380
  2277
    JMP_TARGET(doubleprec);
nkeynes@669
  2278
    push_dr(FRm);
nkeynes@669
  2279
    push_dr(FRn);
nkeynes@380
  2280
    JMP_TARGET(end);
nkeynes@377
  2281
    FCOMIP_st(1);
nkeynes@377
  2282
    SETA_t();
nkeynes@377
  2283
    FPOP_st();
nkeynes@417
  2284
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2285
:}
nkeynes@377
  2286
nkeynes@377
  2287
FSCA FPUL, FRn {:  
nkeynes@671
  2288
    COUNT_INST(I_FSCA);
nkeynes@377
  2289
    check_fpuen();
nkeynes@388
  2290
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2291
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2292
    JNE_rel8(doubleprec );
nkeynes@669
  2293
    LEA_sh4r_r32( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
nkeynes@388
  2294
    load_spreg( R_EDX, R_FPUL );
nkeynes@388
  2295
    call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388
  2296
    JMP_TARGET(doubleprec);
nkeynes@417
  2297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2298
:}
nkeynes@377
  2299
FIPR FVm, FVn {:  
nkeynes@671
  2300
    COUNT_INST(I_FIPR);
nkeynes@377
  2301
    check_fpuen();
nkeynes@388
  2302
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2303
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2304
    JNE_rel8( doubleprec);
nkeynes@388
  2305
    
nkeynes@669
  2306
    push_fr( FVm<<2 );
nkeynes@669
  2307
    push_fr( FVn<<2 );
nkeynes@388
  2308
    FMULP_st(1);
nkeynes@669
  2309
    push_fr( (FVm<<2)+1);
nkeynes@669
  2310
    push_fr( (FVn<<2)+1);
nkeynes@388
  2311
    FMULP_st(1);
nkeynes@388
  2312
    FADDP_st(1);
nkeynes@669
  2313
    push_fr( (FVm<<2)+2);
nkeynes@669
  2314
    push_fr( (FVn<<2)+2);
nkeynes@388
  2315
    FMULP_st(1);
nkeynes@388
  2316
    FADDP_st(1);
nkeynes@669
  2317
    push_fr( (FVm<<2)+3);
nkeynes@669
  2318
    push_fr( (FVn<<2)+3);
nkeynes@388
  2319
    FMULP_st(1);
nkeynes@388
  2320
    FADDP_st(1);
nkeynes@669
  2321
    pop_fr( (FVn<<2)+3);
nkeynes@388
  2322
    JMP_TARGET(doubleprec);
nkeynes@417
  2323
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2324
:}
nkeynes@377
  2325
FTRV XMTRX, FVn {:  
nkeynes@671
  2326
    COUNT_INST(I_FTRV);
nkeynes@377
  2327
    check_fpuen();
nkeynes@388
  2328
    load_spreg( R_ECX, R_FPSCR );
nkeynes@388
  2329
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@669
  2330
    JNE_rel8( doubleprec );
nkeynes@669
  2331
    LEA_sh4r_r32( REG_OFFSET(fr[0][FVn<<2]), R_EDX );
nkeynes@669
  2332
    call_func1( sh4_ftrv, R_EDX );  // 12
nkeynes@388
  2333
    JMP_TARGET(doubleprec);
nkeynes@417
  2334
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2335
:}
nkeynes@377
  2336
nkeynes@377
  2337
FRCHG {:  
nkeynes@671
  2338
    COUNT_INST(I_FRCHG);
nkeynes@377
  2339
    check_fpuen();
nkeynes@377
  2340
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2341
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2342
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2343
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2344
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2345
:}
nkeynes@377
  2346
FSCHG {:  
nkeynes@671
  2347
    COUNT_INST(I_FSCHG);
nkeynes@377
  2348
    check_fpuen();
nkeynes@377
  2349
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2350
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2351
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2352
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2353
:}
nkeynes@359
  2354
nkeynes@359
  2355
/* Processor control instructions */
nkeynes@368
  2356
LDC Rm, SR {:
nkeynes@671
  2357
    COUNT_INST(I_LDCSR);
nkeynes@386
  2358
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2359
	SLOTILLEGAL();
nkeynes@386
  2360
    } else {
nkeynes@386
  2361
	check_priv();
nkeynes@386
  2362
	load_reg( R_EAX, Rm );
nkeynes@386
  2363
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2364
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2365
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2366
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2367
    }
nkeynes@368
  2368
:}
nkeynes@359
  2369
LDC Rm, GBR {: 
nkeynes@671
  2370
    COUNT_INST(I_LDC);
nkeynes@359
  2371
    load_reg( R_EAX, Rm );
nkeynes@359
  2372
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2373
:}
nkeynes@359
  2374
LDC Rm, VBR {:  
nkeynes@671
  2375
    COUNT_INST(I_LDC);
nkeynes@386
  2376
    check_priv();
nkeynes@359
  2377
    load_reg( R_EAX, Rm );
nkeynes@359
  2378
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2380
:}
nkeynes@359
  2381
LDC Rm, SSR {:  
nkeynes@671
  2382
    COUNT_INST(I_LDC);
nkeynes@386
  2383
    check_priv();
nkeynes@359
  2384
    load_reg( R_EAX, Rm );
nkeynes@359
  2385
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2386
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2387
:}
nkeynes@359
  2388
LDC Rm, SGR {:  
nkeynes@671
  2389
    COUNT_INST(I_LDC);
nkeynes@386
  2390
    check_priv();
nkeynes@359
  2391
    load_reg( R_EAX, Rm );
nkeynes@359
  2392
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2393
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2394
:}
nkeynes@359
  2395
LDC Rm, SPC {:  
nkeynes@671
  2396
    COUNT_INST(I_LDC);
nkeynes@386
  2397
    check_priv();
nkeynes@359
  2398
    load_reg( R_EAX, Rm );
nkeynes@359
  2399
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2400
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2401
:}
nkeynes@359
  2402
LDC Rm, DBR {:  
nkeynes@671
  2403
    COUNT_INST(I_LDC);
nkeynes@386
  2404
    check_priv();
nkeynes@359
  2405
    load_reg( R_EAX, Rm );
nkeynes@359
  2406
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2408
:}
nkeynes@374
  2409
LDC Rm, Rn_BANK {:  
nkeynes@671
  2410
    COUNT_INST(I_LDC);
nkeynes@386
  2411
    check_priv();
nkeynes@374
  2412
    load_reg( R_EAX, Rm );
nkeynes@374
  2413
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2415
:}
nkeynes@359
  2416
LDC.L @Rm+, GBR {:  
nkeynes@671
  2417
    COUNT_INST(I_LDCM);
nkeynes@359
  2418
    load_reg( R_EAX, Rm );
nkeynes@395
  2419
    check_ralign32( R_EAX );
nkeynes@586
  2420
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2421
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2422
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2423
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2425
:}
nkeynes@368
  2426
LDC.L @Rm+, SR {:
nkeynes@671
  2427
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2428
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2429
	SLOTILLEGAL();
nkeynes@386
  2430
    } else {
nkeynes@586
  2431
	check_priv();
nkeynes@386
  2432
	load_reg( R_EAX, Rm );
nkeynes@395
  2433
	check_ralign32( R_EAX );
nkeynes@586
  2434
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2435
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2436
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2437
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2438
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2439
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2440
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2441
    }
nkeynes@359
  2442
:}
nkeynes@359
  2443
LDC.L @Rm+, VBR {:  
nkeynes@671
  2444
    COUNT_INST(I_LDCM);
nkeynes@586
  2445
    check_priv();
nkeynes@359
  2446
    load_reg( R_EAX, Rm );
nkeynes@395
  2447
    check_ralign32( R_EAX );
nkeynes@586
  2448
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2449
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2450
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2451
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2452
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2453
:}
nkeynes@359
  2454
LDC.L @Rm+, SSR {:
nkeynes@671
  2455
    COUNT_INST(I_LDCM);
nkeynes@586
  2456
    check_priv();
nkeynes@359
  2457
    load_reg( R_EAX, Rm );
nkeynes@416
  2458
    check_ralign32( R_EAX );
nkeynes@586
  2459
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2460
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2461
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2462
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2464
:}
nkeynes@359
  2465
LDC.L @Rm+, SGR {:  
nkeynes@671
  2466
    COUNT_INST(I_LDCM);
nkeynes@586
  2467
    check_priv();
nkeynes@359
  2468
    load_reg( R_EAX, Rm );
nkeynes@395
  2469
    check_ralign32( R_EAX );
nkeynes@586
  2470
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2471
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2472
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2473
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2474
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2475
:}
nkeynes@359
  2476
LDC.L @Rm+, SPC {:  
nkeynes@671
  2477
    COUNT_INST(I_LDCM);
nkeynes@586
  2478
    check_priv();
nkeynes@359
  2479
    load_reg( R_EAX, Rm );
nkeynes@395
  2480
    check_ralign32( R_EAX );
nkeynes@586
  2481
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2482
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2483
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2484
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2485
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2486
:}
nkeynes@359
  2487
LDC.L @Rm+, DBR {:  
nkeynes@671
  2488
    COUNT_INST(I_LDCM);
nkeynes@586
  2489
    check_priv();
nkeynes@359
  2490
    load_reg( R_EAX, Rm );
nkeynes@395
  2491
    check_ralign32( R_EAX );
nkeynes@586
  2492
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2493
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2494
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2495
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2496
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2497
:}
nkeynes@359
  2498
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2499
    COUNT_INST(I_LDCM);
nkeynes@586
  2500
    check_priv();
nkeynes@374
  2501
    load_reg( R_EAX, Rm );
nkeynes@395
  2502
    check_ralign32( R_EAX );
nkeynes@586
  2503
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2504
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2505
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2506
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2507
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2508
:}
nkeynes@626
  2509
LDS Rm, FPSCR {:
nkeynes@673
  2510
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2511
    check_fpuen();
nkeynes@359
  2512
    load_reg( R_EAX, Rm );
nkeynes@669
  2513
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2514
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2515
:}
nkeynes@359
  2516
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2517
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2518
    check_fpuen();
nkeynes@359
  2519
    load_reg( R_EAX, Rm );
nkeynes@395
  2520
    check_ralign32( R_EAX );
nkeynes@586
  2521
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2522
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2523
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2524
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2525
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2526
:}
nkeynes@359
  2527
LDS Rm, FPUL {:  
nkeynes@671
  2528
    COUNT_INST(I_LDS);
nkeynes@626
  2529
    check_fpuen();
nkeynes@359
  2530
    load_reg( R_EAX, Rm );
nkeynes@359
  2531
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2532
:}
nkeynes@359
  2533
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2534
    COUNT_INST(I_LDSM);
nkeynes@626
  2535
    check_fpuen();
nkeynes@359
  2536
    load_reg( R_EAX, Rm );
nkeynes@395
  2537
    check_ralign32( R_EAX );
nkeynes@586
  2538
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2539
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2540
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2541
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2542
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2543
:}
nkeynes@359
  2544
LDS Rm, MACH {: 
nkeynes@671
  2545
    COUNT_INST(I_LDS);
nkeynes@359
  2546
    load_reg( R_EAX, Rm );
nkeynes@359
  2547
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2548
:}
nkeynes@359
  2549
LDS.L @Rm+, MACH {:  
nkeynes@671
  2550
    COUNT_INST(I_LDSM);
nkeynes@359
  2551
    load_reg( R_EAX, Rm );
nkeynes@395
  2552
    check_ralign32( R_EAX );
nkeynes@586
  2553
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2554
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2555
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2556
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2557
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2558
:}
nkeynes@359
  2559
LDS Rm, MACL {:  
nkeynes@671
  2560
    COUNT_INST(I_LDS);
nkeynes@359
  2561
    load_reg( R_EAX, Rm );
nkeynes@359
  2562
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2563
:}
nkeynes@359
  2564
LDS.L @Rm+, MACL {:  
nkeynes@671
  2565
    COUNT_INST(I_LDSM);
nkeynes@359
  2566
    load_reg( R_EAX, Rm );
nkeynes@395
  2567
    check_ralign32( R_EAX );
nkeynes@586
  2568
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2569
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2570
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2571
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2572
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2573
:}
nkeynes@359
  2574
LDS Rm, PR {:  
nkeynes@671
  2575
    COUNT_INST(I_LDS);
nkeynes@359
  2576
    load_reg( R_EAX, Rm );
nkeynes@359
  2577
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2578
:}
nkeynes@359
  2579
LDS.L @Rm+, PR {:  
nkeynes@671
  2580
    COUNT_INST(I_LDSM);
nkeynes@359
  2581
    load_reg( R_EAX, Rm );
nkeynes@395
  2582
    check_ralign32( R_EAX );
nkeynes@586
  2583
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2584
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2585
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2586
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2587
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2588
:}
nkeynes@550
  2589
LDTLB {:  
nkeynes@671
  2590
    COUNT_INST(I_LDTLB);
nkeynes@553
  2591
    call_func0( MMU_ldtlb );
nkeynes@550
  2592
:}
nkeynes@671
  2593
OCBI @Rn {:
nkeynes@671
  2594
    COUNT_INST(I_OCBI);
nkeynes@671
  2595
:}
nkeynes@671
  2596
OCBP @Rn {:
nkeynes@671
  2597
    COUNT_INST(I_OCBP);
nkeynes@671
  2598
:}
nkeynes@671
  2599
OCBWB @Rn {:
nkeynes@671
  2600
    COUNT_INST(I_OCBWB);
nkeynes@671
  2601
:}
nkeynes@374
  2602
PREF @Rn {:
nkeynes@671
  2603
    COUNT_INST(I_PREF);
nkeynes@374
  2604
    load_reg( R_EAX, Rn );
nkeynes@532
  2605
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2606
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2607
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@669
  2608
    JNE_rel8(end);
nkeynes@532
  2609
    call_func1( sh4_flush_store_queue, R_ECX );
nkeynes@586
  2610
    TEST_r32_r32( R_EAX, R_EAX );
nkeynes@586
  2611
    JE_exc(-1);
nkeynes@380
  2612
    JMP_TARGET(end);
nkeynes@417
  2613
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2614
:}
nkeynes@388
  2615
SLEEP {: 
nkeynes@671
  2616
    COUNT_INST(I_SLEEP);
nkeynes@388
  2617
    check_priv();
nkeynes@388
  2618
    call_func0( sh4_sleep );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2620
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2621
    return 2;
nkeynes@388
  2622
:}
nkeynes@386
  2623
STC SR, Rn {:
nkeynes@671
  2624
    COUNT_INST(I_STCSR);
nkeynes@386
  2625
    check_priv();
nkeynes@386
  2626
    call_func0(sh4_read_sr);
nkeynes@386
  2627
    store_reg( R_EAX, Rn );
nkeynes@417
  2628
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2629
:}
nkeynes@359
  2630
STC GBR, Rn {:  
nkeynes@671
  2631
    COUNT_INST(I_STC);
nkeynes@359
  2632
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2633
    store_reg( R_EAX, Rn );
nkeynes@359
  2634
:}
nkeynes@359
  2635
STC VBR, Rn {:  
nkeynes@671
  2636
    COUNT_INST(I_STC);
nkeynes@386
  2637
    check_priv();
nkeynes@359
  2638
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2639
    store_reg( R_EAX, Rn );
nkeynes@417
  2640
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2641
:}
nkeynes@359
  2642
STC SSR, Rn {:  
nkeynes@671
  2643
    COUNT_INST(I_STC);
nkeynes@386
  2644
    check_priv();
nkeynes@359
  2645
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2646
    store_reg( R_EAX, Rn );
nkeynes@417
  2647
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2648
:}
nkeynes@359
  2649
STC SPC, Rn {:  
nkeynes@671
  2650
    COUNT_INST(I_STC);
nkeynes@386
  2651
    check_priv();
nkeynes@359
  2652
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2653
    store_reg( R_EAX, Rn );
nkeynes@417
  2654
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2655
:}
nkeynes@359
  2656
STC SGR, Rn {:  
nkeynes@671
  2657
    COUNT_INST(I_STC);
nkeynes@386
  2658
    check_priv();
nkeynes@359
  2659
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2660
    store_reg( R_EAX, Rn );
nkeynes@417
  2661
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2662
:}
nkeynes@359
  2663
STC DBR, Rn {:  
nkeynes@671
  2664
    COUNT_INST(I_STC);
nkeynes@386
  2665
    check_priv();
nkeynes@359
  2666
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2667
    store_reg( R_EAX, Rn );
nkeynes@417
  2668
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2669
:}
nkeynes@374
  2670
STC Rm_BANK, Rn {:
nkeynes@671
  2671
    COUNT_INST(I_STC);
nkeynes@386
  2672
    check_priv();
nkeynes@374
  2673
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2674
    store_reg( R_EAX, Rn );
nkeynes@417
  2675
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2676
:}
nkeynes@374
  2677
STC.L SR, @-Rn {:
nkeynes@671
  2678
    COUNT_INST(I_STCSRM);
nkeynes@586
  2679
    check_priv();
nkeynes@586
  2680
    load_reg( R_EAX, Rn );
nkeynes@586
  2681
    check_walign32( R_EAX );
nkeynes@586
  2682
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2683
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2684
    PUSH_realigned_r32( R_EAX );
nkeynes@395
  2685
    call_func0( sh4_read_sr );
nkeynes@586
  2686
    POP_realigned_r32( R_ECX );
nkeynes@586
  2687
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@368
  2688
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@417
  2689
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2690
:}
nkeynes@359
  2691
STC.L VBR, @-Rn {:  
nkeynes@671
  2692
    COUNT_INST(I_STCM);
nkeynes@586
  2693
    check_priv();
nkeynes@586
  2694
    load_reg( R_EAX, Rn );
nkeynes@586
  2695
    check_walign32( R_EAX );
nkeynes@586
  2696
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2697
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2698
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2699
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2700
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2702
:}
nkeynes@359
  2703
STC.L SSR, @-Rn {:  
nkeynes@671
  2704
    COUNT_INST(I_STCM);
nkeynes@586
  2705
    check_priv();
nkeynes@586
  2706
    load_reg( R_EAX, Rn );
nkeynes@586
  2707
    check_walign32( R_EAX );
nkeynes@586
  2708
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2709
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2710
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2711
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2712
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2714
:}
nkeynes@416
  2715
STC.L SPC, @-Rn {:
nkeynes@671
  2716
    COUNT_INST(I_STCM);
nkeynes@586
  2717
    check_priv();
nkeynes@586
  2718
    load_reg( R_EAX, Rn );
nkeynes@586
  2719
    check_walign32( R_EAX );
nkeynes@586
  2720
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2721
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2722
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2723
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2724
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2725
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2726
:}
nkeynes@359
  2727
STC.L SGR, @-Rn {:  
nkeynes@671
  2728
    COUNT_INST(I_STCM);
nkeynes@586
  2729
    check_priv();
nkeynes@586
  2730
    load_reg( R_EAX, Rn );
nkeynes@586
  2731
    check_walign32( R_EAX );
nkeynes@586
  2732
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2733
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2734
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2735
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2736
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2737
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2738
:}
nkeynes@359
  2739
STC.L DBR, @-Rn {:  
nkeynes@671
  2740
    COUNT_INST(I_STCM);
nkeynes@586
  2741
    check_priv();
nkeynes@586
  2742
    load_reg( R_EAX, Rn );
nkeynes@586
  2743
    check_walign32( R_EAX );
nkeynes@586
  2744
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2745
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2746
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2747
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2748
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2749
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2750
:}
nkeynes@374
  2751
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2752
    COUNT_INST(I_STCM);
nkeynes@586
  2753
    check_priv();
nkeynes@586
  2754
    load_reg( R_EAX, Rn );
nkeynes@586
  2755
    check_walign32( R_EAX );
nkeynes@586
  2756
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2757
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2758
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2759
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2760
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2761
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2762
:}
nkeynes@359
  2763
STC.L