filename | src/pvr2/pvr2.c |
changeset | 352:f0df7a6d4703 |
prev | 337:cdd757aa8e8c |
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author | nkeynes |
date | Sun Feb 11 10:09:32 2007 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Bug 27: Implement opengl framebuffer objects Rewrite much of the final video output stage. Now uses generic "render buffers", implemented on GL using framebuffer objects + textures. |
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nkeynes@31 | 1 | /** |
nkeynes@352 | 2 | * $Id: pvr2.c,v 1.44 2007-02-11 10:09:32 nkeynes Exp $ |
nkeynes@31 | 3 | * |
nkeynes@133 | 4 | * PVR2 (Video) Core module implementation and MMIO registers. |
nkeynes@31 | 5 | * |
nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@31 | 7 | * |
nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify |
nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by |
nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@31 | 11 | * (at your option) any later version. |
nkeynes@31 | 12 | * |
nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful, |
nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@31 | 16 | * GNU General Public License for more details. |
nkeynes@31 | 17 | */ |
nkeynes@35 | 18 | #define MODULE pvr2_module |
nkeynes@31 | 19 | |
nkeynes@1 | 20 | #include "dream.h" |
nkeynes@265 | 21 | #include "eventq.h" |
nkeynes@144 | 22 | #include "display.h" |
nkeynes@1 | 23 | #include "mem.h" |
nkeynes@1 | 24 | #include "asic.h" |
nkeynes@261 | 25 | #include "clock.h" |
nkeynes@103 | 26 | #include "pvr2/pvr2.h" |
nkeynes@56 | 27 | #include "sh4/sh4core.h" |
nkeynes@1 | 28 | #define MMIO_IMPL |
nkeynes@103 | 29 | #include "pvr2/pvr2mmio.h" |
nkeynes@1 | 30 | |
nkeynes@1 | 31 | char *video_base; |
nkeynes@1 | 32 | |
nkeynes@352 | 33 | #define MAX_RENDER_BUFFERS 4 |
nkeynes@352 | 34 | |
nkeynes@304 | 35 | #define HPOS_PER_FRAME 0 |
nkeynes@304 | 36 | #define HPOS_PER_LINECOUNT 1 |
nkeynes@304 | 37 | |
nkeynes@133 | 38 | static void pvr2_init( void ); |
nkeynes@133 | 39 | static void pvr2_reset( void ); |
nkeynes@133 | 40 | static uint32_t pvr2_run_slice( uint32_t ); |
nkeynes@133 | 41 | static void pvr2_save_state( FILE *f ); |
nkeynes@133 | 42 | static int pvr2_load_state( FILE *f ); |
nkeynes@265 | 43 | static void pvr2_update_raster_posn( uint32_t nanosecs ); |
nkeynes@304 | 44 | static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns ); |
nkeynes@352 | 45 | static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame ); |
nkeynes@352 | 46 | static render_buffer_t pvr2_next_render_buffer( ); |
nkeynes@265 | 47 | uint32_t pvr2_get_sync_status(); |
nkeynes@133 | 48 | |
nkeynes@94 | 49 | void pvr2_display_frame( void ); |
nkeynes@94 | 50 | |
nkeynes@352 | 51 | static int output_colour_formats[] = { COLFMT_ARGB1555, COLFMT_RGB565, COLFMT_RGB888, COLFMT_ARGB8888 }; |
nkeynes@161 | 52 | |
nkeynes@133 | 53 | struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, |
nkeynes@133 | 54 | pvr2_run_slice, NULL, |
nkeynes@133 | 55 | pvr2_save_state, pvr2_load_state }; |
nkeynes@133 | 56 | |
nkeynes@103 | 57 | |
nkeynes@144 | 58 | display_driver_t display_driver = NULL; |
nkeynes@15 | 59 | |
nkeynes@133 | 60 | struct pvr2_state { |
nkeynes@133 | 61 | uint32_t frame_count; |
nkeynes@133 | 62 | uint32_t line_count; |
nkeynes@133 | 63 | uint32_t line_remainder; |
nkeynes@265 | 64 | uint32_t cycles_run; /* Cycles already executed prior to main time slice */ |
nkeynes@304 | 65 | uint32_t irq_hpos_line; |
nkeynes@304 | 66 | uint32_t irq_hpos_line_count; |
nkeynes@304 | 67 | uint32_t irq_hpos_mode; |
nkeynes@304 | 68 | uint32_t irq_hpos_time_ns; /* Time within the line */ |
nkeynes@133 | 69 | uint32_t irq_vpos1; |
nkeynes@133 | 70 | uint32_t irq_vpos2; |
nkeynes@261 | 71 | uint32_t odd_even_field; /* 1 = odd, 0 = even */ |
nkeynes@337 | 72 | gboolean palette_changed; /* TRUE if palette has changed since last render */ |
nkeynes@295 | 73 | gchar *save_next_render_filename; |
nkeynes@261 | 74 | /* timing */ |
nkeynes@261 | 75 | uint32_t dot_clock; |
nkeynes@261 | 76 | uint32_t total_lines; |
nkeynes@261 | 77 | uint32_t line_size; |
nkeynes@261 | 78 | uint32_t line_time_ns; |
nkeynes@261 | 79 | uint32_t vsync_lines; |
nkeynes@261 | 80 | uint32_t hsync_width_ns; |
nkeynes@261 | 81 | uint32_t front_porch_ns; |
nkeynes@261 | 82 | uint32_t back_porch_ns; |
nkeynes@265 | 83 | uint32_t retrace_start_line; |
nkeynes@265 | 84 | uint32_t retrace_end_line; |
nkeynes@261 | 85 | gboolean interlaced; |
nkeynes@133 | 86 | } pvr2_state; |
nkeynes@15 | 87 | |
nkeynes@352 | 88 | render_buffer_t render_buffers[MAX_RENDER_BUFFERS]; |
nkeynes@352 | 89 | int render_buffer_count = 0; |
nkeynes@133 | 90 | |
nkeynes@265 | 91 | /** |
nkeynes@304 | 92 | * Event handler for the hpos callback |
nkeynes@265 | 93 | */ |
nkeynes@304 | 94 | static void pvr2_hpos_callback( int eventid ) { |
nkeynes@265 | 95 | asic_event( eventid ); |
nkeynes@265 | 96 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@304 | 97 | if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) { |
nkeynes@304 | 98 | pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count; |
nkeynes@304 | 99 | while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) { |
nkeynes@304 | 100 | pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1); |
nkeynes@304 | 101 | } |
nkeynes@304 | 102 | } |
nkeynes@304 | 103 | pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, |
nkeynes@304 | 104 | pvr2_state.irq_hpos_time_ns ); |
nkeynes@265 | 105 | } |
nkeynes@265 | 106 | |
nkeynes@265 | 107 | /** |
nkeynes@265 | 108 | * Event handler for the scanline callbacks. Fires the corresponding |
nkeynes@265 | 109 | * ASIC event, and resets the timer for the next field. |
nkeynes@265 | 110 | */ |
nkeynes@265 | 111 | static void pvr2_scanline_callback( int eventid ) { |
nkeynes@265 | 112 | asic_event( eventid ); |
nkeynes@265 | 113 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@265 | 114 | if( eventid == EVENT_SCANLINE1 ) { |
nkeynes@304 | 115 | pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 ); |
nkeynes@265 | 116 | } else { |
nkeynes@304 | 117 | pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 ); |
nkeynes@265 | 118 | } |
nkeynes@265 | 119 | } |
nkeynes@265 | 120 | |
nkeynes@133 | 121 | static void pvr2_init( void ) |
nkeynes@1 | 122 | { |
nkeynes@352 | 123 | int i; |
nkeynes@1 | 124 | register_io_region( &mmio_region_PVR2 ); |
nkeynes@85 | 125 | register_io_region( &mmio_region_PVR2PAL ); |
nkeynes@56 | 126 | register_io_region( &mmio_region_PVR2TA ); |
nkeynes@304 | 127 | register_event_callback( EVENT_HPOS, pvr2_hpos_callback ); |
nkeynes@265 | 128 | register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback ); |
nkeynes@265 | 129 | register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback ); |
nkeynes@1 | 130 | video_base = mem_get_region_by_name( MEM_REGION_VIDEO ); |
nkeynes@133 | 131 | texcache_init(); |
nkeynes@133 | 132 | pvr2_reset(); |
nkeynes@214 | 133 | pvr2_ta_reset(); |
nkeynes@295 | 134 | pvr2_state.save_next_render_filename = NULL; |
nkeynes@352 | 135 | for( i=0; i<MAX_RENDER_BUFFERS; i++ ) { |
nkeynes@352 | 136 | render_buffers[i] = NULL; |
nkeynes@352 | 137 | } |
nkeynes@352 | 138 | render_buffer_count = 0; |
nkeynes@133 | 139 | } |
nkeynes@133 | 140 | |
nkeynes@133 | 141 | static void pvr2_reset( void ) |
nkeynes@133 | 142 | { |
nkeynes@133 | 143 | pvr2_state.line_count = 0; |
nkeynes@133 | 144 | pvr2_state.line_remainder = 0; |
nkeynes@265 | 145 | pvr2_state.cycles_run = 0; |
nkeynes@133 | 146 | pvr2_state.irq_vpos1 = 0; |
nkeynes@133 | 147 | pvr2_state.irq_vpos2 = 0; |
nkeynes@265 | 148 | pvr2_state.dot_clock = PVR2_DOT_CLOCK; |
nkeynes@265 | 149 | pvr2_state.back_porch_ns = 4000; |
nkeynes@337 | 150 | pvr2_state.palette_changed = FALSE; |
nkeynes@265 | 151 | mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F ); |
nkeynes@265 | 152 | mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F ); |
nkeynes@284 | 153 | mmio_region_PVR2_write( YUV_ADDR, 0 ); |
nkeynes@284 | 154 | mmio_region_PVR2_write( YUV_CFG, 0 ); |
nkeynes@133 | 155 | |
nkeynes@133 | 156 | pvr2_ta_init(); |
nkeynes@133 | 157 | texcache_flush(); |
nkeynes@133 | 158 | } |
nkeynes@133 | 159 | |
nkeynes@133 | 160 | static void pvr2_save_state( FILE *f ) |
nkeynes@133 | 161 | { |
nkeynes@133 | 162 | fwrite( &pvr2_state, sizeof(pvr2_state), 1, f ); |
nkeynes@193 | 163 | pvr2_ta_save_state( f ); |
nkeynes@295 | 164 | pvr2_yuv_save_state( f ); |
nkeynes@133 | 165 | } |
nkeynes@133 | 166 | |
nkeynes@133 | 167 | static int pvr2_load_state( FILE *f ) |
nkeynes@133 | 168 | { |
nkeynes@153 | 169 | if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 ) |
nkeynes@153 | 170 | return 1; |
nkeynes@295 | 171 | if( pvr2_ta_load_state(f) ) { |
nkeynes@295 | 172 | return 1; |
nkeynes@295 | 173 | } |
nkeynes@295 | 174 | return pvr2_yuv_load_state(f); |
nkeynes@133 | 175 | } |
nkeynes@133 | 176 | |
nkeynes@265 | 177 | /** |
nkeynes@265 | 178 | * Update the current raster position to the given number of nanoseconds, |
nkeynes@265 | 179 | * relative to the last time slice. (ie the raster will be adjusted forward |
nkeynes@265 | 180 | * by nanosecs - nanosecs_already_run_this_timeslice) |
nkeynes@265 | 181 | */ |
nkeynes@265 | 182 | static void pvr2_update_raster_posn( uint32_t nanosecs ) |
nkeynes@265 | 183 | { |
nkeynes@265 | 184 | uint32_t old_line_count = pvr2_state.line_count; |
nkeynes@265 | 185 | if( pvr2_state.line_time_ns == 0 ) { |
nkeynes@265 | 186 | return; /* do nothing */ |
nkeynes@265 | 187 | } |
nkeynes@265 | 188 | pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run); |
nkeynes@265 | 189 | pvr2_state.cycles_run = nanosecs; |
nkeynes@265 | 190 | while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) { |
nkeynes@265 | 191 | pvr2_state.line_count ++; |
nkeynes@265 | 192 | pvr2_state.line_remainder -= pvr2_state.line_time_ns; |
nkeynes@265 | 193 | } |
nkeynes@265 | 194 | |
nkeynes@265 | 195 | if( pvr2_state.line_count >= pvr2_state.total_lines ) { |
nkeynes@265 | 196 | pvr2_state.line_count -= pvr2_state.total_lines; |
nkeynes@265 | 197 | if( pvr2_state.interlaced ) { |
nkeynes@265 | 198 | pvr2_state.odd_even_field = !pvr2_state.odd_even_field; |
nkeynes@265 | 199 | } |
nkeynes@265 | 200 | } |
nkeynes@265 | 201 | if( pvr2_state.line_count >= pvr2_state.retrace_end_line && |
nkeynes@265 | 202 | (old_line_count < pvr2_state.retrace_end_line || |
nkeynes@265 | 203 | old_line_count > pvr2_state.line_count) ) { |
nkeynes@337 | 204 | pvr2_state.frame_count++; |
nkeynes@265 | 205 | pvr2_display_frame(); |
nkeynes@265 | 206 | } |
nkeynes@265 | 207 | } |
nkeynes@265 | 208 | |
nkeynes@133 | 209 | static uint32_t pvr2_run_slice( uint32_t nanosecs ) |
nkeynes@133 | 210 | { |
nkeynes@265 | 211 | pvr2_update_raster_posn( nanosecs ); |
nkeynes@265 | 212 | pvr2_state.cycles_run = 0; |
nkeynes@133 | 213 | return nanosecs; |
nkeynes@133 | 214 | } |
nkeynes@133 | 215 | |
nkeynes@133 | 216 | int pvr2_get_frame_count() |
nkeynes@133 | 217 | { |
nkeynes@133 | 218 | return pvr2_state.frame_count; |
nkeynes@106 | 219 | } |
nkeynes@106 | 220 | |
nkeynes@295 | 221 | gboolean pvr2_save_next_scene( const gchar *filename ) |
nkeynes@295 | 222 | { |
nkeynes@295 | 223 | if( pvr2_state.save_next_render_filename != NULL ) { |
nkeynes@295 | 224 | g_free( pvr2_state.save_next_render_filename ); |
nkeynes@295 | 225 | } |
nkeynes@295 | 226 | pvr2_state.save_next_render_filename = g_strdup(filename); |
nkeynes@295 | 227 | return TRUE; |
nkeynes@295 | 228 | } |
nkeynes@295 | 229 | |
nkeynes@295 | 230 | |
nkeynes@295 | 231 | |
nkeynes@103 | 232 | /** |
nkeynes@1 | 233 | * Display the next frame, copying the current contents of video ram to |
nkeynes@1 | 234 | * the window. If the video configuration has changed, first recompute the |
nkeynes@1 | 235 | * new frame size/depth. |
nkeynes@1 | 236 | */ |
nkeynes@94 | 237 | void pvr2_display_frame( void ) |
nkeynes@1 | 238 | { |
nkeynes@197 | 239 | int dispmode = MMIO_READ( PVR2, DISP_MODE ); |
nkeynes@261 | 240 | int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG ); |
nkeynes@335 | 241 | gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE; |
nkeynes@352 | 242 | |
nkeynes@352 | 243 | if( display_driver == NULL ) { |
nkeynes@352 | 244 | return; /* can't really do anything much */ |
nkeynes@352 | 245 | } else if( !bEnabled ) { |
nkeynes@352 | 246 | /* Output disabled == black */ |
nkeynes@352 | 247 | display_driver->display_blank( 0 ); |
nkeynes@352 | 248 | } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { |
nkeynes@352 | 249 | /* Enabled but blanked - border colour */ |
nkeynes@352 | 250 | uint32_t colour = MMIO_READ( PVR2, DISP_BORDER ); |
nkeynes@352 | 251 | display_driver->display_blank( colour ); |
nkeynes@352 | 252 | } else { |
nkeynes@352 | 253 | /* Real output - determine dimensions etc */ |
nkeynes@352 | 254 | struct frame_buffer fbuf; |
nkeynes@352 | 255 | uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE ); |
nkeynes@352 | 256 | int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1); |
nkeynes@352 | 257 | int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1; |
nkeynes@352 | 258 | |
nkeynes@352 | 259 | fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2]; |
nkeynes@352 | 260 | fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp; |
nkeynes@352 | 261 | fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1; |
nkeynes@352 | 262 | fbuf.size = vid_ppl << 2 * fbuf.height; |
nkeynes@352 | 263 | fbuf.rowstride = (vid_ppl + vid_stride) << 2; |
nkeynes@352 | 264 | |
nkeynes@352 | 265 | /* Determine the field to display, and deinterlace if possible */ |
nkeynes@352 | 266 | if( pvr2_state.interlaced ) { |
nkeynes@352 | 267 | if( vid_ppl == vid_stride ) { /* Magic deinterlace */ |
nkeynes@352 | 268 | fbuf.height = fbuf.height << 1; |
nkeynes@352 | 269 | fbuf.rowstride = vid_ppl << 2; |
nkeynes@352 | 270 | fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 ); |
nkeynes@352 | 271 | } else { |
nkeynes@352 | 272 | /* Just display the field as is, folks. This is slightly tricky - |
nkeynes@352 | 273 | * we pick the field based on which frame is about to come through, |
nkeynes@352 | 274 | * which may not be the same as the odd_even_field. |
nkeynes@352 | 275 | */ |
nkeynes@352 | 276 | gboolean oddfield = pvr2_state.odd_even_field; |
nkeynes@352 | 277 | if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) { |
nkeynes@352 | 278 | oddfield = !oddfield; |
nkeynes@352 | 279 | } |
nkeynes@352 | 280 | if( oddfield ) { |
nkeynes@352 | 281 | fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 ); |
nkeynes@352 | 282 | } else { |
nkeynes@352 | 283 | fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 ); |
nkeynes@352 | 284 | } |
nkeynes@337 | 285 | } |
nkeynes@352 | 286 | } else { |
nkeynes@352 | 287 | fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 ); |
nkeynes@335 | 288 | } |
nkeynes@352 | 289 | fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE; |
nkeynes@352 | 290 | |
nkeynes@352 | 291 | render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf ); |
nkeynes@352 | 292 | if( rbuf != NULL ) { |
nkeynes@352 | 293 | display_driver->display_render_buffer( rbuf ); |
nkeynes@352 | 294 | } else { |
nkeynes@352 | 295 | fbuf.data = video_base + (fbuf.address&0x00FFFFFF); |
nkeynes@352 | 296 | display_driver->display_frame_buffer( &fbuf ); |
nkeynes@65 | 297 | } |
nkeynes@1 | 298 | } |
nkeynes@1 | 299 | } |
nkeynes@1 | 300 | |
nkeynes@197 | 301 | /** |
nkeynes@197 | 302 | * This has to handle every single register individually as they all get masked |
nkeynes@197 | 303 | * off differently (and its easier to do it at write time) |
nkeynes@197 | 304 | */ |
nkeynes@1 | 305 | void mmio_region_PVR2_write( uint32_t reg, uint32_t val ) |
nkeynes@1 | 306 | { |
nkeynes@1 | 307 | if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */ |
nkeynes@1 | 308 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@1 | 309 | return; |
nkeynes@1 | 310 | } |
nkeynes@1 | 311 | |
nkeynes@1 | 312 | switch(reg) { |
nkeynes@189 | 313 | case PVRID: |
nkeynes@189 | 314 | case PVRVER: |
nkeynes@261 | 315 | case GUNPOS: /* Read only registers */ |
nkeynes@189 | 316 | break; |
nkeynes@197 | 317 | case PVRRESET: |
nkeynes@197 | 318 | val &= 0x00000007; /* Do stuff? */ |
nkeynes@197 | 319 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@197 | 320 | break; |
nkeynes@295 | 321 | case RENDER_START: /* Don't really care what value */ |
nkeynes@295 | 322 | if( pvr2_state.save_next_render_filename != NULL ) { |
nkeynes@295 | 323 | if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) { |
nkeynes@295 | 324 | INFO( "Saved scene to %s", pvr2_state.save_next_render_filename); |
nkeynes@295 | 325 | } |
nkeynes@295 | 326 | g_free( pvr2_state.save_next_render_filename ); |
nkeynes@295 | 327 | pvr2_state.save_next_render_filename = NULL; |
nkeynes@295 | 328 | } |
nkeynes@352 | 329 | render_buffer_t buffer = pvr2_next_render_buffer(); |
nkeynes@352 | 330 | pvr2_render_scene( buffer ); |
nkeynes@352 | 331 | asic_event( EVENT_PVR_RENDER_DONE ); |
nkeynes@189 | 332 | break; |
nkeynes@191 | 333 | case RENDER_POLYBASE: |
nkeynes@191 | 334 | MMIO_WRITE( PVR2, reg, val&0x00F00000 ); |
nkeynes@191 | 335 | break; |
nkeynes@191 | 336 | case RENDER_TSPCFG: |
nkeynes@191 | 337 | MMIO_WRITE( PVR2, reg, val&0x00010101 ); |
nkeynes@191 | 338 | break; |
nkeynes@197 | 339 | case DISP_BORDER: |
nkeynes@191 | 340 | MMIO_WRITE( PVR2, reg, val&0x01FFFFFF ); |
nkeynes@191 | 341 | break; |
nkeynes@197 | 342 | case DISP_MODE: |
nkeynes@191 | 343 | MMIO_WRITE( PVR2, reg, val&0x00FFFF7F ); |
nkeynes@191 | 344 | break; |
nkeynes@191 | 345 | case RENDER_MODE: |
nkeynes@191 | 346 | MMIO_WRITE( PVR2, reg, val&0x00FFFF0F ); |
nkeynes@191 | 347 | break; |
nkeynes@191 | 348 | case RENDER_SIZE: |
nkeynes@191 | 349 | MMIO_WRITE( PVR2, reg, val&0x000001FF ); |
nkeynes@191 | 350 | break; |
nkeynes@197 | 351 | case DISP_ADDR1: |
nkeynes@189 | 352 | val &= 0x00FFFFFC; |
nkeynes@189 | 353 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@265 | 354 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@108 | 355 | break; |
nkeynes@197 | 356 | case DISP_ADDR2: |
nkeynes@191 | 357 | MMIO_WRITE( PVR2, reg, val&0x00FFFFFC ); |
nkeynes@337 | 358 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@191 | 359 | break; |
nkeynes@197 | 360 | case DISP_SIZE: |
nkeynes@191 | 361 | MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF ); |
nkeynes@191 | 362 | break; |
nkeynes@191 | 363 | case RENDER_ADDR1: |
nkeynes@191 | 364 | case RENDER_ADDR2: |
nkeynes@191 | 365 | MMIO_WRITE( PVR2, reg, val&0x01FFFFFC ); |
nkeynes@191 | 366 | break; |
nkeynes@191 | 367 | case RENDER_HCLIP: |
nkeynes@191 | 368 | MMIO_WRITE( PVR2, reg, val&0x07FF07FF ); |
nkeynes@189 | 369 | break; |
nkeynes@191 | 370 | case RENDER_VCLIP: |
nkeynes@191 | 371 | MMIO_WRITE( PVR2, reg, val&0x03FF03FF ); |
nkeynes@189 | 372 | break; |
nkeynes@197 | 373 | case DISP_HPOSIRQ: |
nkeynes@191 | 374 | MMIO_WRITE( PVR2, reg, val&0x03FF33FF ); |
nkeynes@304 | 375 | pvr2_state.irq_hpos_line = val & 0x03FF; |
nkeynes@304 | 376 | pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock; |
nkeynes@304 | 377 | pvr2_state.irq_hpos_mode = (val >> 12) & 0x03; |
nkeynes@304 | 378 | switch( pvr2_state.irq_hpos_mode ) { |
nkeynes@304 | 379 | case 3: /* Reserved - treat as 0 */ |
nkeynes@304 | 380 | case 0: /* Once per frame at specified line */ |
nkeynes@304 | 381 | pvr2_state.irq_hpos_mode = HPOS_PER_FRAME; |
nkeynes@304 | 382 | break; |
nkeynes@304 | 383 | case 2: /* Once per line - as per-line-count */ |
nkeynes@304 | 384 | pvr2_state.irq_hpos_line = 1; |
nkeynes@304 | 385 | pvr2_state.irq_hpos_mode = 1; |
nkeynes@304 | 386 | case 1: /* Once per N lines */ |
nkeynes@304 | 387 | pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line; |
nkeynes@304 | 388 | pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + |
nkeynes@304 | 389 | pvr2_state.irq_hpos_line_count; |
nkeynes@304 | 390 | while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) { |
nkeynes@304 | 391 | pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1); |
nkeynes@304 | 392 | } |
nkeynes@304 | 393 | pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT; |
nkeynes@304 | 394 | } |
nkeynes@304 | 395 | pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, |
nkeynes@304 | 396 | pvr2_state.irq_hpos_time_ns ); |
nkeynes@189 | 397 | break; |
nkeynes@197 | 398 | case DISP_VPOSIRQ: |
nkeynes@189 | 399 | val = val & 0x03FF03FF; |
nkeynes@189 | 400 | pvr2_state.irq_vpos1 = (val >> 16); |
nkeynes@133 | 401 | pvr2_state.irq_vpos2 = val & 0x03FF; |
nkeynes@265 | 402 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@304 | 403 | pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 ); |
nkeynes@304 | 404 | pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 ); |
nkeynes@189 | 405 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@103 | 406 | break; |
nkeynes@197 | 407 | case RENDER_NEARCLIP: |
nkeynes@197 | 408 | MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF ); |
nkeynes@197 | 409 | break; |
nkeynes@191 | 410 | case RENDER_SHADOW: |
nkeynes@191 | 411 | MMIO_WRITE( PVR2, reg, val&0x000001FF ); |
nkeynes@191 | 412 | break; |
nkeynes@191 | 413 | case RENDER_OBJCFG: |
nkeynes@191 | 414 | MMIO_WRITE( PVR2, reg, val&0x003FFFFF ); |
nkeynes@191 | 415 | break; |
nkeynes@191 | 416 | case RENDER_TSPCLIP: |
nkeynes@191 | 417 | MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF ); |
nkeynes@191 | 418 | break; |
nkeynes@197 | 419 | case RENDER_FARCLIP: |
nkeynes@197 | 420 | MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 ); |
nkeynes@197 | 421 | break; |
nkeynes@191 | 422 | case RENDER_BGPLANE: |
nkeynes@191 | 423 | MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF ); |
nkeynes@191 | 424 | break; |
nkeynes@191 | 425 | case RENDER_ISPCFG: |
nkeynes@191 | 426 | MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 ); |
nkeynes@191 | 427 | break; |
nkeynes@197 | 428 | case VRAM_CFG1: |
nkeynes@197 | 429 | MMIO_WRITE( PVR2, reg, val&0x000000FF ); |
nkeynes@197 | 430 | break; |
nkeynes@197 | 431 | case VRAM_CFG2: |
nkeynes@197 | 432 | MMIO_WRITE( PVR2, reg, val&0x003FFFFF ); |
nkeynes@197 | 433 | break; |
nkeynes@197 | 434 | case VRAM_CFG3: |
nkeynes@197 | 435 | MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF ); |
nkeynes@197 | 436 | break; |
nkeynes@197 | 437 | case RENDER_FOGTBLCOL: |
nkeynes@197 | 438 | case RENDER_FOGVRTCOL: |
nkeynes@197 | 439 | MMIO_WRITE( PVR2, reg, val&0x00FFFFFF ); |
nkeynes@197 | 440 | break; |
nkeynes@197 | 441 | case RENDER_FOGCOEFF: |
nkeynes@197 | 442 | MMIO_WRITE( PVR2, reg, val&0x0000FFFF ); |
nkeynes@197 | 443 | break; |
nkeynes@197 | 444 | case RENDER_CLAMPHI: |
nkeynes@197 | 445 | case RENDER_CLAMPLO: |
nkeynes@197 | 446 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@197 | 447 | break; |
nkeynes@261 | 448 | case RENDER_TEXSIZE: |
nkeynes@261 | 449 | MMIO_WRITE( PVR2, reg, val&0x00031F1F ); |
nkeynes@197 | 450 | break; |
nkeynes@261 | 451 | case RENDER_PALETTE: |
nkeynes@261 | 452 | MMIO_WRITE( PVR2, reg, val&0x00000003 ); |
nkeynes@261 | 453 | break; |
nkeynes@261 | 454 | |
nkeynes@261 | 455 | /********** CRTC registers *************/ |
nkeynes@197 | 456 | case DISP_HBORDER: |
nkeynes@197 | 457 | case DISP_VBORDER: |
nkeynes@197 | 458 | MMIO_WRITE( PVR2, reg, val&0x03FF03FF ); |
nkeynes@197 | 459 | break; |
nkeynes@261 | 460 | case DISP_TOTAL: |
nkeynes@261 | 461 | val = val & 0x03FF03FF; |
nkeynes@261 | 462 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@265 | 463 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@261 | 464 | pvr2_state.total_lines = (val >> 16) + 1; |
nkeynes@261 | 465 | pvr2_state.line_size = (val & 0x03FF) + 1; |
nkeynes@261 | 466 | pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock; |
nkeynes@265 | 467 | pvr2_state.retrace_end_line = 0x2A; |
nkeynes@265 | 468 | pvr2_state.retrace_start_line = pvr2_state.total_lines - 6; |
nkeynes@304 | 469 | pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 ); |
nkeynes@304 | 470 | pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 ); |
nkeynes@304 | 471 | pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, |
nkeynes@304 | 472 | pvr2_state.irq_hpos_time_ns ); |
nkeynes@261 | 473 | break; |
nkeynes@261 | 474 | case DISP_SYNCCFG: |
nkeynes@261 | 475 | MMIO_WRITE( PVR2, reg, val&0x000003FF ); |
nkeynes@261 | 476 | pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE; |
nkeynes@261 | 477 | break; |
nkeynes@261 | 478 | case DISP_SYNCTIME: |
nkeynes@261 | 479 | pvr2_state.vsync_lines = (val >> 8) & 0x0F; |
nkeynes@269 | 480 | pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock; |
nkeynes@197 | 481 | MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F ); |
nkeynes@197 | 482 | break; |
nkeynes@197 | 483 | case DISP_CFG2: |
nkeynes@197 | 484 | MMIO_WRITE( PVR2, reg, val&0x003F01FF ); |
nkeynes@197 | 485 | break; |
nkeynes@197 | 486 | case DISP_HPOS: |
nkeynes@261 | 487 | val = val & 0x03FF; |
nkeynes@261 | 488 | pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock; |
nkeynes@261 | 489 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@197 | 490 | break; |
nkeynes@197 | 491 | case DISP_VPOS: |
nkeynes@197 | 492 | MMIO_WRITE( PVR2, reg, val&0x03FF03FF ); |
nkeynes@197 | 493 | break; |
nkeynes@261 | 494 | |
nkeynes@261 | 495 | /*********** Tile accelerator registers ***********/ |
nkeynes@261 | 496 | case TA_POLYPOS: |
nkeynes@261 | 497 | case TA_LISTPOS: |
nkeynes@261 | 498 | /* Readonly registers */ |
nkeynes@197 | 499 | break; |
nkeynes@189 | 500 | case TA_TILEBASE: |
nkeynes@193 | 501 | case TA_LISTEND: |
nkeynes@189 | 502 | case TA_LISTBASE: |
nkeynes@191 | 503 | MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 ); |
nkeynes@189 | 504 | break; |
nkeynes@191 | 505 | case RENDER_TILEBASE: |
nkeynes@189 | 506 | case TA_POLYBASE: |
nkeynes@189 | 507 | case TA_POLYEND: |
nkeynes@191 | 508 | MMIO_WRITE( PVR2, reg, val&0x00FFFFFC ); |
nkeynes@189 | 509 | break; |
nkeynes@189 | 510 | case TA_TILESIZE: |
nkeynes@191 | 511 | MMIO_WRITE( PVR2, reg, val&0x000F003F ); |
nkeynes@189 | 512 | break; |
nkeynes@189 | 513 | case TA_TILECFG: |
nkeynes@191 | 514 | MMIO_WRITE( PVR2, reg, val&0x00133333 ); |
nkeynes@189 | 515 | break; |
nkeynes@261 | 516 | case TA_INIT: |
nkeynes@261 | 517 | if( val & 0x80000000 ) |
nkeynes@261 | 518 | pvr2_ta_init(); |
nkeynes@261 | 519 | break; |
nkeynes@261 | 520 | case TA_REINIT: |
nkeynes@261 | 521 | break; |
nkeynes@261 | 522 | /**************** Scaler registers? ****************/ |
nkeynes@335 | 523 | case RENDER_SCALER: |
nkeynes@261 | 524 | MMIO_WRITE( PVR2, reg, val&0x0007FFFF ); |
nkeynes@261 | 525 | break; |
nkeynes@261 | 526 | |
nkeynes@197 | 527 | case YUV_ADDR: |
nkeynes@284 | 528 | val = val & 0x00FFFFF8; |
nkeynes@284 | 529 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@284 | 530 | pvr2_yuv_init( val ); |
nkeynes@197 | 531 | break; |
nkeynes@197 | 532 | case YUV_CFG: |
nkeynes@197 | 533 | MMIO_WRITE( PVR2, reg, val&0x01013F3F ); |
nkeynes@284 | 534 | pvr2_yuv_set_config(val); |
nkeynes@197 | 535 | break; |
nkeynes@261 | 536 | |
nkeynes@261 | 537 | /**************** Unknowns ***************/ |
nkeynes@261 | 538 | case PVRUNK1: |
nkeynes@261 | 539 | MMIO_WRITE( PVR2, reg, val&0x000007FF ); |
nkeynes@261 | 540 | break; |
nkeynes@261 | 541 | case PVRUNK2: |
nkeynes@261 | 542 | MMIO_WRITE( PVR2, reg, val&0x00000007 ); |
nkeynes@100 | 543 | break; |
nkeynes@261 | 544 | case PVRUNK3: |
nkeynes@261 | 545 | MMIO_WRITE( PVR2, reg, val&0x000FFF3F ); |
nkeynes@261 | 546 | break; |
nkeynes@261 | 547 | case PVRUNK5: |
nkeynes@261 | 548 | MMIO_WRITE( PVR2, reg, val&0x0000FFFF ); |
nkeynes@261 | 549 | break; |
nkeynes@261 | 550 | case PVRUNK6: |
nkeynes@261 | 551 | MMIO_WRITE( PVR2, reg, val&0x000000FF ); |
nkeynes@197 | 552 | break; |
nkeynes@197 | 553 | case PVRUNK7: |
nkeynes@197 | 554 | MMIO_WRITE( PVR2, reg, val&0x00000001 ); |
nkeynes@197 | 555 | break; |
nkeynes@1 | 556 | } |
nkeynes@1 | 557 | } |
nkeynes@1 | 558 | |
nkeynes@261 | 559 | /** |
nkeynes@261 | 560 | * Calculate the current read value of the syncstat register, using |
nkeynes@261 | 561 | * the current SH4 clock time as an offset from the last timeslice. |
nkeynes@261 | 562 | * The register reads (LSB to MSB) as: |
nkeynes@261 | 563 | * 0..9 Current scan line |
nkeynes@261 | 564 | * 10 Odd/even field (1 = odd, 0 = even) |
nkeynes@261 | 565 | * 11 Display active (including border and overscan) |
nkeynes@261 | 566 | * 12 Horizontal sync off |
nkeynes@261 | 567 | * 13 Vertical sync off |
nkeynes@261 | 568 | * Note this method is probably incorrect for anything other than straight |
nkeynes@265 | 569 | * interlaced PAL/NTSC, and needs further testing. |
nkeynes@261 | 570 | */ |
nkeynes@261 | 571 | uint32_t pvr2_get_sync_status() |
nkeynes@261 | 572 | { |
nkeynes@265 | 573 | pvr2_update_raster_posn(sh4r.slice_cycle); |
nkeynes@265 | 574 | uint32_t result = pvr2_state.line_count; |
nkeynes@261 | 575 | |
nkeynes@265 | 576 | if( pvr2_state.odd_even_field ) { |
nkeynes@261 | 577 | result |= 0x0400; |
nkeynes@261 | 578 | } |
nkeynes@265 | 579 | if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) { |
nkeynes@265 | 580 | if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) { |
nkeynes@261 | 581 | result |= 0x1000; /* !HSYNC */ |
nkeynes@261 | 582 | } |
nkeynes@265 | 583 | if( pvr2_state.line_count >= pvr2_state.vsync_lines ) { |
nkeynes@265 | 584 | if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) { |
nkeynes@261 | 585 | result |= 0x2800; /* Display active */ |
nkeynes@261 | 586 | } else { |
nkeynes@261 | 587 | result |= 0x2000; /* Front porch */ |
nkeynes@261 | 588 | } |
nkeynes@261 | 589 | } |
nkeynes@261 | 590 | } else { |
nkeynes@269 | 591 | if( pvr2_state.line_count >= pvr2_state.vsync_lines ) { |
nkeynes@269 | 592 | if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) { |
nkeynes@269 | 593 | result |= 0x3800; /* Display active */ |
nkeynes@269 | 594 | } else { |
nkeynes@269 | 595 | result |= 0x3000; |
nkeynes@269 | 596 | } |
nkeynes@261 | 597 | } else { |
nkeynes@261 | 598 | result |= 0x1000; /* Back porch */ |
nkeynes@261 | 599 | } |
nkeynes@261 | 600 | } |
nkeynes@261 | 601 | return result; |
nkeynes@261 | 602 | } |
nkeynes@261 | 603 | |
nkeynes@265 | 604 | /** |
nkeynes@265 | 605 | * Schedule a "scanline" event. This actually goes off at |
nkeynes@265 | 606 | * 2 * line in even fields and 2 * line + 1 in odd fields. |
nkeynes@265 | 607 | * Otherwise this behaves as per pvr2_schedule_line_event(). |
nkeynes@265 | 608 | * The raster position should be updated before calling this |
nkeynes@265 | 609 | * method. |
nkeynes@304 | 610 | * @param eventid Event to fire at the specified time |
nkeynes@304 | 611 | * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced |
nkeynes@304 | 612 | * displays). |
nkeynes@304 | 613 | * @param hpos_ns Nanoseconds into the line at which to fire. |
nkeynes@265 | 614 | */ |
nkeynes@304 | 615 | static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns ) |
nkeynes@265 | 616 | { |
nkeynes@265 | 617 | uint32_t field = pvr2_state.odd_even_field; |
nkeynes@265 | 618 | if( line <= pvr2_state.line_count && pvr2_state.interlaced ) { |
nkeynes@265 | 619 | field = !field; |
nkeynes@265 | 620 | } |
nkeynes@304 | 621 | if( hpos_ns > pvr2_state.line_time_ns ) { |
nkeynes@304 | 622 | hpos_ns = pvr2_state.line_time_ns; |
nkeynes@304 | 623 | } |
nkeynes@265 | 624 | |
nkeynes@265 | 625 | line <<= 1; |
nkeynes@265 | 626 | if( field ) { |
nkeynes@265 | 627 | line += 1; |
nkeynes@265 | 628 | } |
nkeynes@274 | 629 | |
nkeynes@274 | 630 | if( line < pvr2_state.total_lines ) { |
nkeynes@274 | 631 | uint32_t lines; |
nkeynes@274 | 632 | uint32_t time; |
nkeynes@274 | 633 | if( line <= pvr2_state.line_count ) { |
nkeynes@274 | 634 | lines = (pvr2_state.total_lines - pvr2_state.line_count + line); |
nkeynes@274 | 635 | } else { |
nkeynes@274 | 636 | lines = (line - pvr2_state.line_count); |
nkeynes@274 | 637 | } |
nkeynes@274 | 638 | if( lines <= minimum_lines ) { |
nkeynes@274 | 639 | lines += pvr2_state.total_lines; |
nkeynes@274 | 640 | } |
nkeynes@304 | 641 | time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns; |
nkeynes@274 | 642 | event_schedule( eventid, time ); |
nkeynes@274 | 643 | } else { |
nkeynes@274 | 644 | event_cancel( eventid ); |
nkeynes@274 | 645 | } |
nkeynes@265 | 646 | } |
nkeynes@265 | 647 | |
nkeynes@1 | 648 | MMIO_REGION_READ_FN( PVR2, reg ) |
nkeynes@1 | 649 | { |
nkeynes@1 | 650 | switch( reg ) { |
nkeynes@261 | 651 | case DISP_SYNCSTAT: |
nkeynes@261 | 652 | return pvr2_get_sync_status(); |
nkeynes@1 | 653 | default: |
nkeynes@1 | 654 | return MMIO_READ( PVR2, reg ); |
nkeynes@1 | 655 | } |
nkeynes@1 | 656 | } |
nkeynes@19 | 657 | |
nkeynes@337 | 658 | MMIO_REGION_WRITE_FN( PVR2PAL, reg, val ) |
nkeynes@337 | 659 | { |
nkeynes@337 | 660 | MMIO_WRITE( PVR2PAL, reg, val ); |
nkeynes@337 | 661 | pvr2_state.palette_changed = TRUE; |
nkeynes@337 | 662 | } |
nkeynes@337 | 663 | |
nkeynes@337 | 664 | void pvr2_check_palette_changed() |
nkeynes@337 | 665 | { |
nkeynes@337 | 666 | if( pvr2_state.palette_changed ) { |
nkeynes@337 | 667 | texcache_invalidate_palette(); |
nkeynes@337 | 668 | pvr2_state.palette_changed = FALSE; |
nkeynes@337 | 669 | } |
nkeynes@337 | 670 | } |
nkeynes@337 | 671 | |
nkeynes@337 | 672 | MMIO_REGION_READ_DEFFN( PVR2PAL ); |
nkeynes@85 | 673 | |
nkeynes@19 | 674 | void pvr2_set_base_address( uint32_t base ) |
nkeynes@19 | 675 | { |
nkeynes@197 | 676 | mmio_region_PVR2_write( DISP_ADDR1, base ); |
nkeynes@19 | 677 | } |
nkeynes@56 | 678 | |
nkeynes@56 | 679 | |
nkeynes@65 | 680 | |
nkeynes@98 | 681 | |
nkeynes@56 | 682 | int32_t mmio_region_PVR2TA_read( uint32_t reg ) |
nkeynes@56 | 683 | { |
nkeynes@56 | 684 | return 0xFFFFFFFF; |
nkeynes@56 | 685 | } |
nkeynes@56 | 686 | |
nkeynes@56 | 687 | void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val ) |
nkeynes@56 | 688 | { |
nkeynes@189 | 689 | pvr2_ta_write( (char *)&val, sizeof(uint32_t) ); |
nkeynes@56 | 690 | } |
nkeynes@56 | 691 | |
nkeynes@352 | 692 | /** |
nkeynes@352 | 693 | * Find the render buffer corresponding to the requested output frame |
nkeynes@352 | 694 | * (does not consider texture renders). |
nkeynes@352 | 695 | * @return the render_buffer if found, or null if no such buffer. |
nkeynes@352 | 696 | * |
nkeynes@352 | 697 | * Note: Currently does not consider "partial matches", ie partial |
nkeynes@352 | 698 | * frame overlap - it probably needs to do this. |
nkeynes@352 | 699 | */ |
nkeynes@352 | 700 | render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame ) |
nkeynes@352 | 701 | { |
nkeynes@352 | 702 | int i; |
nkeynes@352 | 703 | for( i=0; i<render_buffer_count; i++ ) { |
nkeynes@352 | 704 | if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) { |
nkeynes@352 | 705 | return render_buffers[i]; |
nkeynes@352 | 706 | } |
nkeynes@352 | 707 | } |
nkeynes@352 | 708 | return NULL; |
nkeynes@352 | 709 | } |
nkeynes@352 | 710 | |
nkeynes@352 | 711 | /** |
nkeynes@352 | 712 | * Determine the next render buffer to write into. The order of preference is: |
nkeynes@352 | 713 | * 1. An existing buffer with the same address. (not flushed unless the new |
nkeynes@352 | 714 | * size is smaller than the old one). |
nkeynes@352 | 715 | * 2. An existing buffer with the same size chosen by LRU order. Old buffer |
nkeynes@352 | 716 | * is flushed to vram. |
nkeynes@352 | 717 | * 3. A new buffer if one can be created. |
nkeynes@352 | 718 | * 4. The current display buff |
nkeynes@352 | 719 | * Note: The current display field(s) will never be overwritten except as a last |
nkeynes@352 | 720 | * resort. |
nkeynes@352 | 721 | */ |
nkeynes@352 | 722 | render_buffer_t pvr2_next_render_buffer() |
nkeynes@352 | 723 | { |
nkeynes@352 | 724 | render_buffer_t result = NULL; |
nkeynes@352 | 725 | uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 ); |
nkeynes@352 | 726 | uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE ); |
nkeynes@352 | 727 | uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER ); |
nkeynes@352 | 728 | uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3; |
nkeynes@352 | 729 | gboolean render_to_tex; |
nkeynes@352 | 730 | if( render_addr & 0x01000000 ) { /* vram64 */ |
nkeynes@352 | 731 | render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT; |
nkeynes@352 | 732 | } else { /* vram32 */ |
nkeynes@352 | 733 | render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE; |
nkeynes@352 | 734 | } |
nkeynes@352 | 735 | |
nkeynes@352 | 736 | int width, height, i; |
nkeynes@352 | 737 | int colour_format = pvr2_render_colour_format[render_mode&0x07]; |
nkeynes@352 | 738 | pvr2_render_getsize( &width, &height ); |
nkeynes@352 | 739 | |
nkeynes@352 | 740 | /* Check existing buffers for an available buffer */ |
nkeynes@352 | 741 | for( i=0; i<render_buffer_count; i++ ) { |
nkeynes@352 | 742 | if( render_buffers[i]->width == width && render_buffers[i]->height == height ) { |
nkeynes@352 | 743 | /* needs to be the right dimensions */ |
nkeynes@352 | 744 | if( render_buffers[i]->address == render_addr ) { |
nkeynes@352 | 745 | /* perfect */ |
nkeynes@352 | 746 | result = render_buffers[i]; |
nkeynes@352 | 747 | break; |
nkeynes@352 | 748 | } else if( render_buffers[i]->address == -1 && result == NULL ) { |
nkeynes@352 | 749 | result = render_buffers[i]; |
nkeynes@352 | 750 | } |
nkeynes@352 | 751 | } else if( render_buffers[i]->address == render_addr ) { |
nkeynes@352 | 752 | /* right address, wrong size - if it's larger, flush it, otherwise |
nkeynes@352 | 753 | * nuke it quietly */ |
nkeynes@352 | 754 | if( render_buffers[i]->width * render_buffers[i]->height > |
nkeynes@352 | 755 | width*height ) { |
nkeynes@352 | 756 | pvr2_render_buffer_copy_to_sh4( render_buffers[i] ); |
nkeynes@352 | 757 | } |
nkeynes@352 | 758 | render_buffers[i]->address == -1; |
nkeynes@352 | 759 | } |
nkeynes@352 | 760 | } |
nkeynes@352 | 761 | |
nkeynes@352 | 762 | /* Nothing available - make one */ |
nkeynes@352 | 763 | if( result == NULL ) { |
nkeynes@352 | 764 | if( render_buffer_count == MAX_RENDER_BUFFERS ) { |
nkeynes@352 | 765 | /* maximum buffers reached - need to throw one away */ |
nkeynes@352 | 766 | uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 ); |
nkeynes@352 | 767 | uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 ); |
nkeynes@352 | 768 | for( i=0; i<render_buffer_count; i++ ) { |
nkeynes@352 | 769 | if( render_buffers[i]->address != field1_addr && |
nkeynes@352 | 770 | render_buffers[i]->address != field2_addr ) { |
nkeynes@352 | 771 | /* Never throw away the current "front buffer(s)" */ |
nkeynes@352 | 772 | result = render_buffers[i]; |
nkeynes@352 | 773 | pvr2_render_buffer_copy_to_sh4( result ); |
nkeynes@352 | 774 | if( result->width != width || result->height != height ) { |
nkeynes@352 | 775 | display_driver->destroy_render_buffer(render_buffers[i]); |
nkeynes@352 | 776 | result = display_driver->create_render_buffer(width,height); |
nkeynes@352 | 777 | render_buffers[i] = result; |
nkeynes@352 | 778 | } |
nkeynes@352 | 779 | break; |
nkeynes@352 | 780 | } |
nkeynes@352 | 781 | } |
nkeynes@352 | 782 | } else { |
nkeynes@352 | 783 | result = display_driver->create_render_buffer(width,height); |
nkeynes@352 | 784 | if( result != NULL ) { |
nkeynes@352 | 785 | render_buffers[render_buffer_count++] = result; |
nkeynes@352 | 786 | } else { |
nkeynes@352 | 787 | ERROR( "Failed to obtain a render buffer!" ); |
nkeynes@352 | 788 | return NULL; |
nkeynes@352 | 789 | } |
nkeynes@352 | 790 | } |
nkeynes@352 | 791 | } |
nkeynes@352 | 792 | |
nkeynes@352 | 793 | /* Setup the buffer */ |
nkeynes@352 | 794 | result->rowstride = render_stride; |
nkeynes@352 | 795 | result->colour_format = colour_format; |
nkeynes@352 | 796 | result->scale = render_scale; |
nkeynes@352 | 797 | result->size = width * height * colour_formats[colour_format].bpp; |
nkeynes@352 | 798 | result->address = render_addr; |
nkeynes@352 | 799 | result->flushed = FALSE; |
nkeynes@352 | 800 | return result; |
nkeynes@352 | 801 | } |
nkeynes@352 | 802 | |
nkeynes@352 | 803 | /** |
nkeynes@352 | 804 | * Invalidate any caching on the supplied address. Specifically, if it falls |
nkeynes@352 | 805 | * within any of the render buffers, flush the buffer back to PVR2 ram. |
nkeynes@352 | 806 | */ |
nkeynes@352 | 807 | gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite ) |
nkeynes@352 | 808 | { |
nkeynes@352 | 809 | int i; |
nkeynes@352 | 810 | address = address & 0x1FFFFFFF; |
nkeynes@352 | 811 | for( i=0; i<render_buffer_count; i++ ) { |
nkeynes@352 | 812 | uint32_t bufaddr = render_buffers[i]->address; |
nkeynes@352 | 813 | uint32_t size = render_buffers[i]->size; |
nkeynes@352 | 814 | if( bufaddr != -1 && bufaddr <= address && |
nkeynes@352 | 815 | (bufaddr + render_buffers[i]->size) > address ) { |
nkeynes@352 | 816 | if( !render_buffers[i]->flushed ) { |
nkeynes@352 | 817 | pvr2_render_buffer_copy_to_sh4( render_buffers[i] ); |
nkeynes@352 | 818 | render_buffers[i]->flushed = TRUE; |
nkeynes@352 | 819 | } |
nkeynes@352 | 820 | if( isWrite ) { |
nkeynes@352 | 821 | render_buffers[i]->address = -1; /* Invalid */ |
nkeynes@352 | 822 | } |
nkeynes@352 | 823 | return TRUE; /* should never have overlapping buffers */ |
nkeynes@352 | 824 | } |
nkeynes@352 | 825 | } |
nkeynes@352 | 826 | return FALSE; |
nkeynes@352 | 827 | } |
.