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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 953:f4a156508ad1
prev927:17b6b9e245d8
next956:4c1ed9e03985
author nkeynes
date Tue Jan 13 11:56:28 2009 +0000 (11 years ago)
permissions -rw-r--r--
last change Merge lxdream-mem branch back to trunk
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "sh4/mmu.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
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        if( sh4_x86.in_delay_slot ) { \
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            JMP_exc(EXC_SLOT_ILLEGAL); \
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        } else { \
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            JMP_exc(EXC_ILLEGAL ); \
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        } \
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        sh4_x86.in_delay_slot = DELAY_NONE; \
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        return 2; \
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    }
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
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 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
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 */
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#ifdef HAVE_FRAME_ADDRESS
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#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
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        call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
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        call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 
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#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
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        call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
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        call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }
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#else 
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#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg)
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#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)
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#endif
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#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)
nkeynes@953
   312
#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)
nkeynes@953
   313
#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)
nkeynes@953
   314
#define MEM_PREFETCH( addr_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, prefetch)
nkeynes@361
   315
nkeynes@953
   316
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388
   317
nkeynes@539
   318
/****** Import appropriate calling conventions ******/
nkeynes@675
   319
#if SIZEOF_VOID_P == 8
nkeynes@539
   320
#include "sh4/ia64abi.h"
nkeynes@675
   321
#else /* 32-bit system */
nkeynes@539
   322
#include "sh4/ia32abi.h"
nkeynes@539
   323
#endif
nkeynes@539
   324
nkeynes@901
   325
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   326
{
nkeynes@927
   327
    enter_block();
nkeynes@901
   328
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   329
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   330
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   331
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   332
    sh4_x86.block_start_pc = pc;
nkeynes@953
   333
    sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901
   334
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   335
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   336
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   337
}
nkeynes@901
   338
nkeynes@901
   339
nkeynes@593
   340
uint32_t sh4_translate_end_block_size()
nkeynes@593
   341
{
nkeynes@596
   342
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   343
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   344
    } else {
nkeynes@901
   345
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   346
    }
nkeynes@593
   347
}
nkeynes@593
   348
nkeynes@593
   349
nkeynes@590
   350
/**
nkeynes@590
   351
 * Embed a breakpoint into the generated code
nkeynes@590
   352
 */
nkeynes@586
   353
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   354
{
nkeynes@591
   355
    load_imm32( R_EAX, pc );
nkeynes@591
   356
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   357
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   358
}
nkeynes@590
   359
nkeynes@601
   360
nkeynes@601
   361
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   362
nkeynes@590
   363
/**
nkeynes@590
   364
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   365
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   366
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   367
 *
nkeynes@601
   368
 * Performs:
nkeynes@601
   369
 *   Set PC = endpc
nkeynes@601
   370
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   371
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   372
 *   Call sh4_execute_instruction
nkeynes@601
   373
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   374
 */
nkeynes@601
   375
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   376
{
nkeynes@590
   377
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   378
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   379
    
nkeynes@601
   380
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   381
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   382
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   383
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   384
nkeynes@590
   385
    call_func0( sh4_execute_instruction );    
nkeynes@601
   386
    load_spreg( R_EAX, R_PC );
nkeynes@590
   387
    if( sh4_x86.tlb_on ) {
nkeynes@590
   388
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   389
    } else {
nkeynes@590
   390
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   391
    }
nkeynes@926
   392
    exit_block();
nkeynes@590
   393
} 
nkeynes@539
   394
nkeynes@359
   395
/**
nkeynes@359
   396
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   397
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   398
 * 
nkeynes@586
   399
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   400
 *
nkeynes@359
   401
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   402
 * (eg a branch or 
nkeynes@359
   403
 */
nkeynes@590
   404
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   405
{
nkeynes@388
   406
    uint32_t ir;
nkeynes@586
   407
    /* Read instruction from icache */
nkeynes@586
   408
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   409
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   410
    
nkeynes@586
   411
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   412
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   413
    }
nkeynes@359
   414
%%
nkeynes@359
   415
/* ALU operations */
nkeynes@359
   416
ADD Rm, Rn {:
nkeynes@671
   417
    COUNT_INST(I_ADD);
nkeynes@359
   418
    load_reg( R_EAX, Rm );
nkeynes@359
   419
    load_reg( R_ECX, Rn );
nkeynes@359
   420
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   421
    store_reg( R_ECX, Rn );
nkeynes@417
   422
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   423
:}
nkeynes@359
   424
ADD #imm, Rn {:  
nkeynes@671
   425
    COUNT_INST(I_ADDI);
nkeynes@953
   426
    ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );
nkeynes@417
   427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   428
:}
nkeynes@359
   429
ADDC Rm, Rn {:
nkeynes@671
   430
    COUNT_INST(I_ADDC);
nkeynes@417
   431
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   432
        LDC_t();
nkeynes@417
   433
    }
nkeynes@359
   434
    load_reg( R_EAX, Rm );
nkeynes@359
   435
    load_reg( R_ECX, Rn );
nkeynes@359
   436
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   437
    store_reg( R_ECX, Rn );
nkeynes@359
   438
    SETC_t();
nkeynes@417
   439
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   440
:}
nkeynes@359
   441
ADDV Rm, Rn {:
nkeynes@671
   442
    COUNT_INST(I_ADDV);
nkeynes@359
   443
    load_reg( R_EAX, Rm );
nkeynes@359
   444
    load_reg( R_ECX, Rn );
nkeynes@359
   445
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   446
    store_reg( R_ECX, Rn );
nkeynes@359
   447
    SETO_t();
nkeynes@417
   448
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   449
:}
nkeynes@359
   450
AND Rm, Rn {:
nkeynes@671
   451
    COUNT_INST(I_AND);
nkeynes@359
   452
    load_reg( R_EAX, Rm );
nkeynes@359
   453
    load_reg( R_ECX, Rn );
nkeynes@359
   454
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   455
    store_reg( R_ECX, Rn );
nkeynes@417
   456
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   457
:}
nkeynes@359
   458
AND #imm, R0 {:  
nkeynes@671
   459
    COUNT_INST(I_ANDI);
nkeynes@359
   460
    load_reg( R_EAX, 0 );
nkeynes@359
   461
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   462
    store_reg( R_EAX, 0 );
nkeynes@417
   463
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   464
:}
nkeynes@359
   465
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   466
    COUNT_INST(I_ANDB);
nkeynes@359
   467
    load_reg( R_EAX, 0 );
nkeynes@953
   468
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@926
   469
    MOV_r32_esp8(R_EAX, 0);
nkeynes@905
   470
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926
   471
    MOV_esp8_r32(0, R_EAX);
nkeynes@905
   472
    AND_imm32_r32(imm, R_EDX );
nkeynes@905
   473
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   474
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   475
:}
nkeynes@359
   476
CMP/EQ Rm, Rn {:  
nkeynes@671
   477
    COUNT_INST(I_CMPEQ);
nkeynes@359
   478
    load_reg( R_EAX, Rm );
nkeynes@359
   479
    load_reg( R_ECX, Rn );
nkeynes@359
   480
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   481
    SETE_t();
nkeynes@417
   482
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   483
:}
nkeynes@359
   484
CMP/EQ #imm, R0 {:  
nkeynes@671
   485
    COUNT_INST(I_CMPEQI);
nkeynes@359
   486
    load_reg( R_EAX, 0 );
nkeynes@359
   487
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   488
    SETE_t();
nkeynes@417
   489
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   490
:}
nkeynes@359
   491
CMP/GE Rm, Rn {:  
nkeynes@671
   492
    COUNT_INST(I_CMPGE);
nkeynes@359
   493
    load_reg( R_EAX, Rm );
nkeynes@359
   494
    load_reg( R_ECX, Rn );
nkeynes@359
   495
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   496
    SETGE_t();
nkeynes@417
   497
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   498
:}
nkeynes@359
   499
CMP/GT Rm, Rn {: 
nkeynes@671
   500
    COUNT_INST(I_CMPGT);
nkeynes@359
   501
    load_reg( R_EAX, Rm );
nkeynes@359
   502
    load_reg( R_ECX, Rn );
nkeynes@359
   503
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   504
    SETG_t();
nkeynes@417
   505
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   506
:}
nkeynes@359
   507
CMP/HI Rm, Rn {:  
nkeynes@671
   508
    COUNT_INST(I_CMPHI);
nkeynes@359
   509
    load_reg( R_EAX, Rm );
nkeynes@359
   510
    load_reg( R_ECX, Rn );
nkeynes@359
   511
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   512
    SETA_t();
nkeynes@417
   513
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   514
:}
nkeynes@359
   515
CMP/HS Rm, Rn {: 
nkeynes@671
   516
    COUNT_INST(I_CMPHS);
nkeynes@359
   517
    load_reg( R_EAX, Rm );
nkeynes@359
   518
    load_reg( R_ECX, Rn );
nkeynes@359
   519
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   520
    SETAE_t();
nkeynes@417
   521
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   522
 :}
nkeynes@359
   523
CMP/PL Rn {: 
nkeynes@671
   524
    COUNT_INST(I_CMPPL);
nkeynes@359
   525
    load_reg( R_EAX, Rn );
nkeynes@359
   526
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   527
    SETG_t();
nkeynes@417
   528
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   529
:}
nkeynes@359
   530
CMP/PZ Rn {:  
nkeynes@671
   531
    COUNT_INST(I_CMPPZ);
nkeynes@359
   532
    load_reg( R_EAX, Rn );
nkeynes@359
   533
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   534
    SETGE_t();
nkeynes@417
   535
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   536
:}
nkeynes@361
   537
CMP/STR Rm, Rn {:  
nkeynes@671
   538
    COUNT_INST(I_CMPSTR);
nkeynes@368
   539
    load_reg( R_EAX, Rm );
nkeynes@368
   540
    load_reg( R_ECX, Rn );
nkeynes@368
   541
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   542
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   543
    JE_rel8(target1);
nkeynes@669
   544
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   545
    JE_rel8(target2);
nkeynes@669
   546
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   547
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   548
    JE_rel8(target3);
nkeynes@669
   549
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   550
    JMP_TARGET(target1);
nkeynes@380
   551
    JMP_TARGET(target2);
nkeynes@380
   552
    JMP_TARGET(target3);
nkeynes@368
   553
    SETE_t();
nkeynes@417
   554
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   555
:}
nkeynes@361
   556
DIV0S Rm, Rn {:
nkeynes@671
   557
    COUNT_INST(I_DIV0S);
nkeynes@361
   558
    load_reg( R_EAX, Rm );
nkeynes@386
   559
    load_reg( R_ECX, Rn );
nkeynes@361
   560
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   561
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   562
    store_spreg( R_EAX, R_M );
nkeynes@361
   563
    store_spreg( R_ECX, R_Q );
nkeynes@361
   564
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   565
    SETNE_t();
nkeynes@417
   566
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   567
:}
nkeynes@361
   568
DIV0U {:  
nkeynes@671
   569
    COUNT_INST(I_DIV0U);
nkeynes@361
   570
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   571
    store_spreg( R_EAX, R_Q );
nkeynes@361
   572
    store_spreg( R_EAX, R_M );
nkeynes@361
   573
    store_spreg( R_EAX, R_T );
nkeynes@417
   574
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   575
:}
nkeynes@386
   576
DIV1 Rm, Rn {:
nkeynes@671
   577
    COUNT_INST(I_DIV1);
nkeynes@386
   578
    load_spreg( R_ECX, R_M );
nkeynes@386
   579
    load_reg( R_EAX, Rn );
nkeynes@417
   580
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   581
	LDC_t();
nkeynes@417
   582
    }
nkeynes@386
   583
    RCL1_r32( R_EAX );
nkeynes@386
   584
    SETC_r8( R_DL ); // Q'
nkeynes@386
   585
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   586
    JE_rel8(mqequal);
nkeynes@386
   587
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   588
    JMP_rel8(end);
nkeynes@380
   589
    JMP_TARGET(mqequal);
nkeynes@386
   590
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   591
    JMP_TARGET(end);
nkeynes@386
   592
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   593
    SETC_r8(R_AL); // tmp1
nkeynes@386
   594
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   595
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   596
    store_spreg( R_ECX, R_Q );
nkeynes@386
   597
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   598
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   599
    store_spreg( R_EAX, R_T );
nkeynes@417
   600
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   601
:}
nkeynes@361
   602
DMULS.L Rm, Rn {:  
nkeynes@671
   603
    COUNT_INST(I_DMULS);
nkeynes@361
   604
    load_reg( R_EAX, Rm );
nkeynes@361
   605
    load_reg( R_ECX, Rn );
nkeynes@361
   606
    IMUL_r32(R_ECX);
nkeynes@361
   607
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   608
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   609
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   610
:}
nkeynes@361
   611
DMULU.L Rm, Rn {:  
nkeynes@671
   612
    COUNT_INST(I_DMULU);
nkeynes@361
   613
    load_reg( R_EAX, Rm );
nkeynes@361
   614
    load_reg( R_ECX, Rn );
nkeynes@361
   615
    MUL_r32(R_ECX);
nkeynes@361
   616
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   617
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   618
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   619
:}
nkeynes@359
   620
DT Rn {:  
nkeynes@671
   621
    COUNT_INST(I_DT);
nkeynes@359
   622
    load_reg( R_EAX, Rn );
nkeynes@382
   623
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   624
    store_reg( R_EAX, Rn );
nkeynes@359
   625
    SETE_t();
nkeynes@417
   626
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   627
:}
nkeynes@359
   628
EXTS.B Rm, Rn {:  
nkeynes@671
   629
    COUNT_INST(I_EXTSB);
nkeynes@359
   630
    load_reg( R_EAX, Rm );
nkeynes@359
   631
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   632
    store_reg( R_EAX, Rn );
nkeynes@359
   633
:}
nkeynes@361
   634
EXTS.W Rm, Rn {:  
nkeynes@671
   635
    COUNT_INST(I_EXTSW);
nkeynes@361
   636
    load_reg( R_EAX, Rm );
nkeynes@361
   637
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   638
    store_reg( R_EAX, Rn );
nkeynes@361
   639
:}
nkeynes@361
   640
EXTU.B Rm, Rn {:  
nkeynes@671
   641
    COUNT_INST(I_EXTUB);
nkeynes@361
   642
    load_reg( R_EAX, Rm );
nkeynes@361
   643
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   644
    store_reg( R_EAX, Rn );
nkeynes@361
   645
:}
nkeynes@361
   646
EXTU.W Rm, Rn {:  
nkeynes@671
   647
    COUNT_INST(I_EXTUW);
nkeynes@361
   648
    load_reg( R_EAX, Rm );
nkeynes@361
   649
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   650
    store_reg( R_EAX, Rn );
nkeynes@361
   651
:}
nkeynes@586
   652
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   653
    COUNT_INST(I_MACL);
nkeynes@586
   654
    if( Rm == Rn ) {
nkeynes@586
   655
	load_reg( R_EAX, Rm );
nkeynes@586
   656
	check_ralign32( R_EAX );
nkeynes@953
   657
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   658
	MOV_r32_esp8(R_EAX, 0);
nkeynes@953
   659
	load_reg( R_EAX, Rm );
nkeynes@953
   660
	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953
   661
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
   662
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   663
    } else {
nkeynes@586
   664
	load_reg( R_EAX, Rm );
nkeynes@586
   665
	check_ralign32( R_EAX );
nkeynes@953
   666
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   667
	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   668
	load_reg( R_EAX, Rn );
nkeynes@926
   669
	check_ralign32( R_EAX );
nkeynes@953
   670
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
   671
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   672
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   673
    }
nkeynes@953
   674
    
nkeynes@953
   675
    IMUL_esp8( 0 );
nkeynes@386
   676
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   677
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   678
nkeynes@386
   679
    load_spreg( R_ECX, R_S );
nkeynes@386
   680
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   681
    JE_rel8( nosat );
nkeynes@386
   682
    call_func0( signsat48 );
nkeynes@386
   683
    JMP_TARGET( nosat );
nkeynes@417
   684
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   685
:}
nkeynes@386
   686
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   687
    COUNT_INST(I_MACW);
nkeynes@586
   688
    if( Rm == Rn ) {
nkeynes@586
   689
	load_reg( R_EAX, Rm );
nkeynes@586
   690
	check_ralign16( R_EAX );
nkeynes@953
   691
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   692
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@953
   693
	load_reg( R_EAX, Rm );
nkeynes@953
   694
	LEA_r32disp8_r32( R_EAX, 2, R_EAX );
nkeynes@953
   695
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   696
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   697
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   698
	// adding a page-boundary check to skip the second translation
nkeynes@586
   699
    } else {
nkeynes@586
   700
	load_reg( R_EAX, Rm );
nkeynes@586
   701
	check_ralign16( R_EAX );
nkeynes@953
   702
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   703
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   704
	load_reg( R_EAX, Rn );
nkeynes@926
   705
	check_ralign16( R_EAX );
nkeynes@953
   706
	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
   707
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   708
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   709
    }
nkeynes@953
   710
    IMUL_esp8( 0 );
nkeynes@386
   711
    load_spreg( R_ECX, R_S );
nkeynes@386
   712
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   713
    JE_rel8( nosat );
nkeynes@386
   714
nkeynes@386
   715
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   716
    JNO_rel8( end );            // 2
nkeynes@386
   717
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   718
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   719
    JS_rel8( positive );        // 2
nkeynes@386
   720
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   721
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   722
    JMP_rel8(end2);           // 2
nkeynes@386
   723
nkeynes@386
   724
    JMP_TARGET(positive);
nkeynes@386
   725
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   726
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   727
    JMP_rel8(end3);            // 2
nkeynes@386
   728
nkeynes@386
   729
    JMP_TARGET(nosat);
nkeynes@386
   730
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   731
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   732
    JMP_TARGET(end);
nkeynes@386
   733
    JMP_TARGET(end2);
nkeynes@386
   734
    JMP_TARGET(end3);
nkeynes@417
   735
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   736
:}
nkeynes@359
   737
MOVT Rn {:  
nkeynes@671
   738
    COUNT_INST(I_MOVT);
nkeynes@359
   739
    load_spreg( R_EAX, R_T );
nkeynes@359
   740
    store_reg( R_EAX, Rn );
nkeynes@359
   741
:}
nkeynes@361
   742
MUL.L Rm, Rn {:  
nkeynes@671
   743
    COUNT_INST(I_MULL);
nkeynes@361
   744
    load_reg( R_EAX, Rm );
nkeynes@361
   745
    load_reg( R_ECX, Rn );
nkeynes@361
   746
    MUL_r32( R_ECX );
nkeynes@361
   747
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   748
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   749
:}
nkeynes@374
   750
MULS.W Rm, Rn {:
nkeynes@671
   751
    COUNT_INST(I_MULSW);
nkeynes@374
   752
    load_reg16s( R_EAX, Rm );
nkeynes@374
   753
    load_reg16s( R_ECX, Rn );
nkeynes@374
   754
    MUL_r32( R_ECX );
nkeynes@374
   755
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   756
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   757
:}
nkeynes@374
   758
MULU.W Rm, Rn {:  
nkeynes@671
   759
    COUNT_INST(I_MULUW);
nkeynes@374
   760
    load_reg16u( R_EAX, Rm );
nkeynes@374
   761
    load_reg16u( R_ECX, Rn );
nkeynes@374
   762
    MUL_r32( R_ECX );
nkeynes@374
   763
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   764
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   765
:}
nkeynes@359
   766
NEG Rm, Rn {:
nkeynes@671
   767
    COUNT_INST(I_NEG);
nkeynes@359
   768
    load_reg( R_EAX, Rm );
nkeynes@359
   769
    NEG_r32( R_EAX );
nkeynes@359
   770
    store_reg( R_EAX, Rn );
nkeynes@417
   771
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   772
:}
nkeynes@359
   773
NEGC Rm, Rn {:  
nkeynes@671
   774
    COUNT_INST(I_NEGC);
nkeynes@359
   775
    load_reg( R_EAX, Rm );
nkeynes@359
   776
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   777
    LDC_t();
nkeynes@359
   778
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   779
    store_reg( R_ECX, Rn );
nkeynes@359
   780
    SETC_t();
nkeynes@417
   781
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   782
:}
nkeynes@359
   783
NOT Rm, Rn {:  
nkeynes@671
   784
    COUNT_INST(I_NOT);
nkeynes@359
   785
    load_reg( R_EAX, Rm );
nkeynes@359
   786
    NOT_r32( R_EAX );
nkeynes@359
   787
    store_reg( R_EAX, Rn );
nkeynes@417
   788
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   789
:}
nkeynes@359
   790
OR Rm, Rn {:  
nkeynes@671
   791
    COUNT_INST(I_OR);
nkeynes@359
   792
    load_reg( R_EAX, Rm );
nkeynes@359
   793
    load_reg( R_ECX, Rn );
nkeynes@359
   794
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   795
    store_reg( R_ECX, Rn );
nkeynes@417
   796
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   797
:}
nkeynes@359
   798
OR #imm, R0 {:
nkeynes@671
   799
    COUNT_INST(I_ORI);
nkeynes@359
   800
    load_reg( R_EAX, 0 );
nkeynes@359
   801
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   802
    store_reg( R_EAX, 0 );
nkeynes@417
   803
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   804
:}
nkeynes@374
   805
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   806
    COUNT_INST(I_ORB);
nkeynes@374
   807
    load_reg( R_EAX, 0 );
nkeynes@953
   808
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@926
   809
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
   810
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926
   811
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
   812
    OR_imm32_r32(imm, R_EDX );
nkeynes@905
   813
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   814
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   815
:}
nkeynes@359
   816
ROTCL Rn {:
nkeynes@671
   817
    COUNT_INST(I_ROTCL);
nkeynes@359
   818
    load_reg( R_EAX, Rn );
nkeynes@417
   819
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   820
	LDC_t();
nkeynes@417
   821
    }
nkeynes@359
   822
    RCL1_r32( R_EAX );
nkeynes@359
   823
    store_reg( R_EAX, Rn );
nkeynes@359
   824
    SETC_t();
nkeynes@417
   825
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   826
:}
nkeynes@359
   827
ROTCR Rn {:  
nkeynes@671
   828
    COUNT_INST(I_ROTCR);
nkeynes@359
   829
    load_reg( R_EAX, Rn );
nkeynes@417
   830
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   831
	LDC_t();
nkeynes@417
   832
    }
nkeynes@359
   833
    RCR1_r32( R_EAX );
nkeynes@359
   834
    store_reg( R_EAX, Rn );
nkeynes@359
   835
    SETC_t();
nkeynes@417
   836
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   837
:}
nkeynes@359
   838
ROTL Rn {:  
nkeynes@671
   839
    COUNT_INST(I_ROTL);
nkeynes@359
   840
    load_reg( R_EAX, Rn );
nkeynes@359
   841
    ROL1_r32( R_EAX );
nkeynes@359
   842
    store_reg( R_EAX, Rn );
nkeynes@359
   843
    SETC_t();
nkeynes@417
   844
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   845
:}
nkeynes@359
   846
ROTR Rn {:  
nkeynes@671
   847
    COUNT_INST(I_ROTR);
nkeynes@359
   848
    load_reg( R_EAX, Rn );
nkeynes@359
   849
    ROR1_r32( R_EAX );
nkeynes@359
   850
    store_reg( R_EAX, Rn );
nkeynes@359
   851
    SETC_t();
nkeynes@417
   852
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   853
:}
nkeynes@359
   854
SHAD Rm, Rn {:
nkeynes@671
   855
    COUNT_INST(I_SHAD);
nkeynes@359
   856
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   857
    load_reg( R_EAX, Rn );
nkeynes@361
   858
    load_reg( R_ECX, Rm );
nkeynes@361
   859
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   860
    JGE_rel8(doshl);
nkeynes@361
   861
                    
nkeynes@361
   862
    NEG_r32( R_ECX );      // 2
nkeynes@361
   863
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   864
    JE_rel8(emptysar);     // 2
nkeynes@361
   865
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   866
    JMP_rel8(end);          // 2
nkeynes@386
   867
nkeynes@386
   868
    JMP_TARGET(emptysar);
nkeynes@386
   869
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   870
    JMP_rel8(end2);
nkeynes@382
   871
nkeynes@380
   872
    JMP_TARGET(doshl);
nkeynes@361
   873
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   874
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   875
    JMP_TARGET(end);
nkeynes@386
   876
    JMP_TARGET(end2);
nkeynes@361
   877
    store_reg( R_EAX, Rn );
nkeynes@417
   878
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   879
:}
nkeynes@359
   880
SHLD Rm, Rn {:  
nkeynes@671
   881
    COUNT_INST(I_SHLD);
nkeynes@368
   882
    load_reg( R_EAX, Rn );
nkeynes@368
   883
    load_reg( R_ECX, Rm );
nkeynes@382
   884
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   885
    JGE_rel8(doshl);
nkeynes@368
   886
nkeynes@382
   887
    NEG_r32( R_ECX );      // 2
nkeynes@382
   888
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   889
    JE_rel8(emptyshr );
nkeynes@382
   890
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   891
    JMP_rel8(end);          // 2
nkeynes@386
   892
nkeynes@386
   893
    JMP_TARGET(emptyshr);
nkeynes@386
   894
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   895
    JMP_rel8(end2);
nkeynes@382
   896
nkeynes@382
   897
    JMP_TARGET(doshl);
nkeynes@382
   898
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   899
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   900
    JMP_TARGET(end);
nkeynes@386
   901
    JMP_TARGET(end2);
nkeynes@368
   902
    store_reg( R_EAX, Rn );
nkeynes@417
   903
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   904
:}
nkeynes@359
   905
SHAL Rn {: 
nkeynes@671
   906
    COUNT_INST(I_SHAL);
nkeynes@359
   907
    load_reg( R_EAX, Rn );
nkeynes@359
   908
    SHL1_r32( R_EAX );
nkeynes@397
   909
    SETC_t();
nkeynes@359
   910
    store_reg( R_EAX, Rn );
nkeynes@417
   911
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   912
:}
nkeynes@359
   913
SHAR Rn {:  
nkeynes@671
   914
    COUNT_INST(I_SHAR);
nkeynes@359
   915
    load_reg( R_EAX, Rn );
nkeynes@359
   916
    SAR1_r32( R_EAX );
nkeynes@397
   917
    SETC_t();
nkeynes@359
   918
    store_reg( R_EAX, Rn );
nkeynes@417
   919
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   920
:}
nkeynes@359
   921
SHLL Rn {:  
nkeynes@671
   922
    COUNT_INST(I_SHLL);
nkeynes@359
   923
    load_reg( R_EAX, Rn );
nkeynes@359
   924
    SHL1_r32( R_EAX );
nkeynes@397
   925
    SETC_t();
nkeynes@359
   926
    store_reg( R_EAX, Rn );
nkeynes@417
   927
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   928
:}
nkeynes@359
   929
SHLL2 Rn {:
nkeynes@671
   930
    COUNT_INST(I_SHLL);
nkeynes@359
   931
    load_reg( R_EAX, Rn );
nkeynes@359
   932
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   933
    store_reg( R_EAX, Rn );
nkeynes@417
   934
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   935
:}
nkeynes@359
   936
SHLL8 Rn {:  
nkeynes@671
   937
    COUNT_INST(I_SHLL);
nkeynes@359
   938
    load_reg( R_EAX, Rn );
nkeynes@359
   939
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   940
    store_reg( R_EAX, Rn );
nkeynes@417
   941
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   942
:}
nkeynes@359
   943
SHLL16 Rn {:  
nkeynes@671
   944
    COUNT_INST(I_SHLL);
nkeynes@359
   945
    load_reg( R_EAX, Rn );
nkeynes@359
   946
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   947
    store_reg( R_EAX, Rn );
nkeynes@417
   948
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   949
:}
nkeynes@359
   950
SHLR Rn {:  
nkeynes@671
   951
    COUNT_INST(I_SHLR);
nkeynes@359
   952
    load_reg( R_EAX, Rn );
nkeynes@359
   953
    SHR1_r32( R_EAX );
nkeynes@397
   954
    SETC_t();
nkeynes@359
   955
    store_reg( R_EAX, Rn );
nkeynes@417
   956
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   957
:}
nkeynes@359
   958
SHLR2 Rn {:  
nkeynes@671
   959
    COUNT_INST(I_SHLR);
nkeynes@359
   960
    load_reg( R_EAX, Rn );
nkeynes@359
   961
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   962
    store_reg( R_EAX, Rn );
nkeynes@417
   963
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   964
:}
nkeynes@359
   965
SHLR8 Rn {:  
nkeynes@671
   966
    COUNT_INST(I_SHLR);
nkeynes@359
   967
    load_reg( R_EAX, Rn );
nkeynes@359
   968
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   969
    store_reg( R_EAX, Rn );
nkeynes@417
   970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   971
:}
nkeynes@359
   972
SHLR16 Rn {:  
nkeynes@671
   973
    COUNT_INST(I_SHLR);
nkeynes@359
   974
    load_reg( R_EAX, Rn );
nkeynes@359
   975
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   976
    store_reg( R_EAX, Rn );
nkeynes@417
   977
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   978
:}
nkeynes@359
   979
SUB Rm, Rn {:  
nkeynes@671
   980
    COUNT_INST(I_SUB);
nkeynes@359
   981
    load_reg( R_EAX, Rm );
nkeynes@359
   982
    load_reg( R_ECX, Rn );
nkeynes@359
   983
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   984
    store_reg( R_ECX, Rn );
nkeynes@417
   985
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   986
:}
nkeynes@359
   987
SUBC Rm, Rn {:  
nkeynes@671
   988
    COUNT_INST(I_SUBC);
nkeynes@359
   989
    load_reg( R_EAX, Rm );
nkeynes@359
   990
    load_reg( R_ECX, Rn );
nkeynes@417
   991
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   992
	LDC_t();
nkeynes@417
   993
    }
nkeynes@359
   994
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   995
    store_reg( R_ECX, Rn );
nkeynes@394
   996
    SETC_t();
nkeynes@417
   997
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   998
:}
nkeynes@359
   999
SUBV Rm, Rn {:  
nkeynes@671
  1000
    COUNT_INST(I_SUBV);
nkeynes@359
  1001
    load_reg( R_EAX, Rm );
nkeynes@359
  1002
    load_reg( R_ECX, Rn );
nkeynes@359
  1003
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1004
    store_reg( R_ECX, Rn );
nkeynes@359
  1005
    SETO_t();
nkeynes@417
  1006
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1007
:}
nkeynes@359
  1008
SWAP.B Rm, Rn {:  
nkeynes@671
  1009
    COUNT_INST(I_SWAPB);
nkeynes@359
  1010
    load_reg( R_EAX, Rm );
nkeynes@601
  1011
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1012
    store_reg( R_EAX, Rn );
nkeynes@359
  1013
:}
nkeynes@359
  1014
SWAP.W Rm, Rn {:  
nkeynes@671
  1015
    COUNT_INST(I_SWAPB);
nkeynes@359
  1016
    load_reg( R_EAX, Rm );
nkeynes@359
  1017
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1018
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1019
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1020
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1021
    store_reg( R_ECX, Rn );
nkeynes@417
  1022
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1023
:}
nkeynes@361
  1024
TAS.B @Rn {:  
nkeynes@671
  1025
    COUNT_INST(I_TASB);
nkeynes@586
  1026
    load_reg( R_EAX, Rn );
nkeynes@926
  1027
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
  1028
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1029
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1030
    SETE_t();
nkeynes@905
  1031
    OR_imm8_r8( 0x80, R_DL );
nkeynes@926
  1032
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1033
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1034
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1035
:}
nkeynes@361
  1036
TST Rm, Rn {:  
nkeynes@671
  1037
    COUNT_INST(I_TST);
nkeynes@361
  1038
    load_reg( R_EAX, Rm );
nkeynes@361
  1039
    load_reg( R_ECX, Rn );
nkeynes@361
  1040
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1041
    SETE_t();
nkeynes@417
  1042
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1043
:}
nkeynes@368
  1044
TST #imm, R0 {:  
nkeynes@671
  1045
    COUNT_INST(I_TSTI);
nkeynes@368
  1046
    load_reg( R_EAX, 0 );
nkeynes@368
  1047
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1048
    SETE_t();
nkeynes@417
  1049
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1050
:}
nkeynes@368
  1051
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1052
    COUNT_INST(I_TSTB);
nkeynes@368
  1053
    load_reg( R_EAX, 0);
nkeynes@953
  1054
    ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@586
  1055
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1056
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1057
    SETE_t();
nkeynes@417
  1058
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1059
:}
nkeynes@359
  1060
XOR Rm, Rn {:  
nkeynes@671
  1061
    COUNT_INST(I_XOR);
nkeynes@359
  1062
    load_reg( R_EAX, Rm );
nkeynes@359
  1063
    load_reg( R_ECX, Rn );
nkeynes@359
  1064
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1065
    store_reg( R_ECX, Rn );
nkeynes@417
  1066
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1067
:}
nkeynes@359
  1068
XOR #imm, R0 {:  
nkeynes@671
  1069
    COUNT_INST(I_XORI);
nkeynes@359
  1070
    load_reg( R_EAX, 0 );
nkeynes@359
  1071
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1072
    store_reg( R_EAX, 0 );
nkeynes@417
  1073
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1074
:}
nkeynes@359
  1075
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1076
    COUNT_INST(I_XORB);
nkeynes@359
  1077
    load_reg( R_EAX, 0 );
nkeynes@953
  1078
    ADD_sh4r_r32( R_GBR, R_EAX ); 
nkeynes@926
  1079
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
  1080
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@926
  1081
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1082
    XOR_imm32_r32( imm, R_EDX );
nkeynes@905
  1083
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1084
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1085
:}
nkeynes@361
  1086
XTRCT Rm, Rn {:
nkeynes@671
  1087
    COUNT_INST(I_XTRCT);
nkeynes@361
  1088
    load_reg( R_EAX, Rm );
nkeynes@394
  1089
    load_reg( R_ECX, Rn );
nkeynes@394
  1090
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1091
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1092
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1093
    store_reg( R_ECX, Rn );
nkeynes@417
  1094
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1095
:}
nkeynes@359
  1096
nkeynes@359
  1097
/* Data move instructions */
nkeynes@359
  1098
MOV Rm, Rn {:  
nkeynes@671
  1099
    COUNT_INST(I_MOV);
nkeynes@359
  1100
    load_reg( R_EAX, Rm );
nkeynes@359
  1101
    store_reg( R_EAX, Rn );
nkeynes@359
  1102
:}
nkeynes@359
  1103
MOV #imm, Rn {:  
nkeynes@671
  1104
    COUNT_INST(I_MOVI);
nkeynes@359
  1105
    load_imm32( R_EAX, imm );
nkeynes@359
  1106
    store_reg( R_EAX, Rn );
nkeynes@359
  1107
:}
nkeynes@359
  1108
MOV.B Rm, @Rn {:  
nkeynes@671
  1109
    COUNT_INST(I_MOVB);
nkeynes@586
  1110
    load_reg( R_EAX, Rn );
nkeynes@586
  1111
    load_reg( R_EDX, Rm );
nkeynes@586
  1112
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1113
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1114
:}
nkeynes@359
  1115
MOV.B Rm, @-Rn {:  
nkeynes@671
  1116
    COUNT_INST(I_MOVB);
nkeynes@586
  1117
    load_reg( R_EAX, Rn );
nkeynes@953
  1118
    LEA_r32disp8_r32( R_EAX, -1, R_EAX );
nkeynes@586
  1119
    load_reg( R_EDX, Rm );
nkeynes@953
  1120
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@586
  1121
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@417
  1122
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1123
:}
nkeynes@359
  1124
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1125
    COUNT_INST(I_MOVB);
nkeynes@359
  1126
    load_reg( R_EAX, 0 );
nkeynes@953
  1127
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1128
    load_reg( R_EDX, Rm );
nkeynes@586
  1129
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1130
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1131
:}
nkeynes@359
  1132
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1133
    COUNT_INST(I_MOVB);
nkeynes@586
  1134
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1135
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1136
    load_reg( R_EDX, 0 );
nkeynes@586
  1137
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1138
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1139
:}
nkeynes@359
  1140
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1141
    COUNT_INST(I_MOVB);
nkeynes@586
  1142
    load_reg( R_EAX, Rn );
nkeynes@586
  1143
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1144
    load_reg( R_EDX, 0 );
nkeynes@586
  1145
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1146
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1147
:}
nkeynes@359
  1148
MOV.B @Rm, Rn {:  
nkeynes@671
  1149
    COUNT_INST(I_MOVB);
nkeynes@586
  1150
    load_reg( R_EAX, Rm );
nkeynes@586
  1151
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1152
    store_reg( R_EAX, Rn );
nkeynes@417
  1153
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1154
:}
nkeynes@359
  1155
MOV.B @Rm+, Rn {:  
nkeynes@671
  1156
    COUNT_INST(I_MOVB);
nkeynes@586
  1157
    load_reg( R_EAX, Rm );
nkeynes@586
  1158
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@953
  1159
    if( Rm != Rn ) {
nkeynes@953
  1160
    	ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@953
  1161
    }
nkeynes@359
  1162
    store_reg( R_EAX, Rn );
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1164
:}
nkeynes@359
  1165
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1166
    COUNT_INST(I_MOVB);
nkeynes@359
  1167
    load_reg( R_EAX, 0 );
nkeynes@953
  1168
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1169
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1170
    store_reg( R_EAX, Rn );
nkeynes@417
  1171
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1172
:}
nkeynes@359
  1173
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1174
    COUNT_INST(I_MOVB);
nkeynes@586
  1175
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1176
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1177
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1178
    store_reg( R_EAX, 0 );
nkeynes@417
  1179
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1180
:}
nkeynes@359
  1181
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1182
    COUNT_INST(I_MOVB);
nkeynes@586
  1183
    load_reg( R_EAX, Rm );
nkeynes@586
  1184
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1185
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1186
    store_reg( R_EAX, 0 );
nkeynes@417
  1187
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1188
:}
nkeynes@374
  1189
MOV.L Rm, @Rn {:
nkeynes@671
  1190
    COUNT_INST(I_MOVL);
nkeynes@586
  1191
    load_reg( R_EAX, Rn );
nkeynes@586
  1192
    check_walign32(R_EAX);
nkeynes@953
  1193
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@953
  1194
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@953
  1195
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@953
  1196
    JNE_rel8( notsq );
nkeynes@953
  1197
    AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@953
  1198
    load_reg( R_EDX, Rm );
nkeynes@953
  1199
    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@953
  1200
    JMP_rel8(end);
nkeynes@953
  1201
    JMP_TARGET(notsq);
nkeynes@586
  1202
    load_reg( R_EDX, Rm );
nkeynes@586
  1203
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953
  1204
    JMP_TARGET(end);
nkeynes@417
  1205
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1206
:}
nkeynes@361
  1207
MOV.L Rm, @-Rn {:  
nkeynes@671
  1208
    COUNT_INST(I_MOVL);
nkeynes@586
  1209
    load_reg( R_EAX, Rn );
nkeynes@586
  1210
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1211
    check_walign32( R_EAX );
nkeynes@586
  1212
    load_reg( R_EDX, Rm );
nkeynes@953
  1213
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  1214
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  1215
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1216
:}
nkeynes@361
  1217
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1218
    COUNT_INST(I_MOVL);
nkeynes@361
  1219
    load_reg( R_EAX, 0 );
nkeynes@953
  1220
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1221
    check_walign32( R_EAX );
nkeynes@586
  1222
    load_reg( R_EDX, Rm );
nkeynes@586
  1223
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1224
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1225
:}
nkeynes@361
  1226
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1227
    COUNT_INST(I_MOVL);
nkeynes@586
  1228
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1229
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1230
    check_walign32( R_EAX );
nkeynes@586
  1231
    load_reg( R_EDX, 0 );
nkeynes@586
  1232
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1233
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1234
:}
nkeynes@361
  1235
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1236
    COUNT_INST(I_MOVL);
nkeynes@586
  1237
    load_reg( R_EAX, Rn );
nkeynes@586
  1238
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1239
    check_walign32( R_EAX );
nkeynes@953
  1240
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@953
  1241
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@953
  1242
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@953
  1243
    JNE_rel8( notsq );
nkeynes@953
  1244
    AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@953
  1245
    load_reg( R_EDX, Rm );
nkeynes@953
  1246
    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@953
  1247
    JMP_rel8(end);
nkeynes@953
  1248
    JMP_TARGET(notsq);
nkeynes@586
  1249
    load_reg( R_EDX, Rm );
nkeynes@586
  1250
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953
  1251
    JMP_TARGET(end);
nkeynes@417
  1252
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1253
:}
nkeynes@361
  1254
MOV.L @Rm, Rn {:  
nkeynes@671
  1255
    COUNT_INST(I_MOVL);
nkeynes@586
  1256
    load_reg( R_EAX, Rm );
nkeynes@586
  1257
    check_ralign32( R_EAX );
nkeynes@586
  1258
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1259
    store_reg( R_EAX, Rn );
nkeynes@417
  1260
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1261
:}
nkeynes@361
  1262
MOV.L @Rm+, Rn {:  
nkeynes@671
  1263
    COUNT_INST(I_MOVL);
nkeynes@361
  1264
    load_reg( R_EAX, Rm );
nkeynes@382
  1265
    check_ralign32( R_EAX );
nkeynes@586
  1266
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
  1267
    if( Rm != Rn ) {
nkeynes@953
  1268
    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@953
  1269
    }
nkeynes@361
  1270
    store_reg( R_EAX, Rn );
nkeynes@417
  1271
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1272
:}
nkeynes@361
  1273
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1274
    COUNT_INST(I_MOVL);
nkeynes@361
  1275
    load_reg( R_EAX, 0 );
nkeynes@953
  1276
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1277
    check_ralign32( R_EAX );
nkeynes@586
  1278
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1279
    store_reg( R_EAX, Rn );
nkeynes@417
  1280
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1281
:}
nkeynes@361
  1282
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1283
    COUNT_INST(I_MOVL);
nkeynes@586
  1284
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1285
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1286
    check_ralign32( R_EAX );
nkeynes@586
  1287
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1288
    store_reg( R_EAX, 0 );
nkeynes@417
  1289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1290
:}
nkeynes@361
  1291
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1292
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1293
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1294
	SLOTILLEGAL();
nkeynes@374
  1295
    } else {
nkeynes@388
  1296
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1297
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1298
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1299
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1300
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1301
nkeynes@586
  1302
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1303
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1304
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1305
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1306
	    // behaviour though.
nkeynes@586
  1307
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1308
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1309
	} else {
nkeynes@586
  1310
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1311
	    // different virtual address than the translation was done with,
nkeynes@586
  1312
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1313
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1314
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1315
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1316
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1317
	}
nkeynes@382
  1318
	store_reg( R_EAX, Rn );
nkeynes@374
  1319
    }
nkeynes@361
  1320
:}
nkeynes@361
  1321
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1322
    COUNT_INST(I_MOVL);
nkeynes@586
  1323
    load_reg( R_EAX, Rm );
nkeynes@586
  1324
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1325
    check_ralign32( R_EAX );
nkeynes@586
  1326
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1327
    store_reg( R_EAX, Rn );
nkeynes@417
  1328
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1329
:}
nkeynes@361
  1330
MOV.W Rm, @Rn {:  
nkeynes@671
  1331
    COUNT_INST(I_MOVW);
nkeynes@586
  1332
    load_reg( R_EAX, Rn );
nkeynes@586
  1333
    check_walign16( R_EAX );
nkeynes@586
  1334
    load_reg( R_EDX, Rm );
nkeynes@586
  1335
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1336
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1337
:}
nkeynes@361
  1338
MOV.W Rm, @-Rn {:  
nkeynes@671
  1339
    COUNT_INST(I_MOVW);
nkeynes@586
  1340
    load_reg( R_EAX, Rn );
nkeynes@586
  1341
    check_walign16( R_EAX );
nkeynes@953
  1342
    LEA_r32disp8_r32( R_EAX, -2, R_EAX );
nkeynes@586
  1343
    load_reg( R_EDX, Rm );
nkeynes@953
  1344
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@586
  1345
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@417
  1346
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1347
:}
nkeynes@361
  1348
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1349
    COUNT_INST(I_MOVW);
nkeynes@361
  1350
    load_reg( R_EAX, 0 );
nkeynes@953
  1351
    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586
  1352
    check_walign16( R_EAX );
nkeynes@586
  1353
    load_reg( R_EDX, Rm );
nkeynes@586
  1354
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1355
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1356
:}
nkeynes@361
  1357
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1358
    COUNT_INST(I_MOVW);
nkeynes@586
  1359
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1360
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1361
    check_walign16( R_EAX );
nkeynes@586
  1362
    load_reg( R_EDX, 0 );
nkeynes@586
  1363
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1364
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1365
:}
nkeynes@361
  1366
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1367
    COUNT_INST(I_MOVW);
nkeynes@586
  1368
    load_reg( R_EAX, Rn );
nkeynes@586
  1369
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1370
    check_walign16( R_EAX );
nkeynes@586
  1371
    load_reg( R_EDX, 0 );
nkeynes@586
  1372
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1373
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1374
:}
nkeynes@361
  1375
MOV.W @Rm, Rn {:  
nkeynes@671
  1376
    COUNT_INST(I_MOVW);
nkeynes@586
  1377
    load_reg( R_EAX, Rm );
nkeynes@586
  1378
    check_ralign16( R_EAX );
nkeynes@586
  1379
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1380
    store_reg( R_EAX, Rn );
nkeynes@417
  1381
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1382
:}
nkeynes@361
  1383
MOV.W @Rm+, Rn {:  
nkeynes@671
  1384
    COUNT_INST(I_MOVW);
nkeynes@361
  1385
    load_reg( R_EAX, Rm );
nkeynes@374
  1386
    check_ralign16( R_EAX );
nkeynes@586
  1387
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@953
  1388
    if( Rm != Rn ) {
nkeynes@953
  1389
        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@953
  1390
    }
nkeynes@361
  1391
    store_reg( R_EAX, Rn );
nkeynes@417
  1392
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1393
:}
nkeynes@361
  1394
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1395
    COUNT_INST(I_MOVW);
nkeynes@361
  1396
    load_reg( R_EAX, 0 );
nkeynes@953
  1397
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586
  1398
    check_ralign16( R_EAX );
nkeynes@586
  1399
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1400
    store_reg( R_EAX, Rn );
nkeynes@417
  1401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1402
:}
nkeynes@361
  1403
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1404
    COUNT_INST(I_MOVW);
nkeynes@586
  1405
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1406
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1407
    check_ralign16( R_EAX );
nkeynes@586
  1408
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1409
    store_reg( R_EAX, 0 );
nkeynes@417
  1410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1411
:}
nkeynes@361
  1412
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1413
    COUNT_INST(I_MOVW);
nkeynes@374
  1414
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1415
	SLOTILLEGAL();
nkeynes@374
  1416
    } else {
nkeynes@586
  1417
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1418
	uint32_t target = pc + disp + 4;
nkeynes@586
  1419
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1420
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1421
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1422
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1423
	} else {
nkeynes@586
  1424
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1425
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1426
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1427
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1428
	}
nkeynes@374
  1429
	store_reg( R_EAX, Rn );
nkeynes@374
  1430
    }
nkeynes@361
  1431
:}
nkeynes@361
  1432
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1433
    COUNT_INST(I_MOVW);
nkeynes@586
  1434
    load_reg( R_EAX, Rm );
nkeynes@586
  1435
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1436
    check_ralign16( R_EAX );
nkeynes@586
  1437
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1438
    store_reg( R_EAX, 0 );
nkeynes@417
  1439
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1440
:}
nkeynes@361
  1441
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1442
    COUNT_INST(I_MOVA);
nkeynes@374
  1443
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1444
	SLOTILLEGAL();
nkeynes@374
  1445
    } else {
nkeynes@586
  1446
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1447
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1448
	store_reg( R_ECX, 0 );
nkeynes@586
  1449
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1450
    }
nkeynes@361
  1451
:}
nkeynes@361
  1452
MOVCA.L R0, @Rn {:  
nkeynes@671
  1453
    COUNT_INST(I_MOVCA);
nkeynes@586
  1454
    load_reg( R_EAX, Rn );
nkeynes@586
  1455
    check_walign32( R_EAX );
nkeynes@586
  1456
    load_reg( R_EDX, 0 );
nkeynes@586
  1457
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1458
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1459
:}
nkeynes@359
  1460
nkeynes@359
  1461
/* Control transfer instructions */
nkeynes@374
  1462
BF disp {:
nkeynes@671
  1463
    COUNT_INST(I_BF);
nkeynes@374
  1464
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1465
	SLOTILLEGAL();
nkeynes@374
  1466
    } else {
nkeynes@586
  1467
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1468
	JT_rel8( nottaken );
nkeynes@586
  1469
	exit_block_rel(target, pc+2 );
nkeynes@380
  1470
	JMP_TARGET(nottaken);
nkeynes@408
  1471
	return 2;
nkeynes@374
  1472
    }
nkeynes@374
  1473
:}
nkeynes@374
  1474
BF/S disp {:
nkeynes@671
  1475
    COUNT_INST(I_BFS);
nkeynes@374
  1476
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1477
	SLOTILLEGAL();
nkeynes@374
  1478
    } else {
nkeynes@590
  1479
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1480
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1481
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1482
	    JT_rel8(nottaken);
nkeynes@601
  1483
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1484
	    JMP_TARGET(nottaken);
nkeynes@601
  1485
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1486
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1487
	    exit_block_emu(pc+2);
nkeynes@601
  1488
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1489
	    return 2;
nkeynes@601
  1490
	} else {
nkeynes@601
  1491
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1492
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1493
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1494
	    }
nkeynes@601
  1495
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1496
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1497
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1498
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1499
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1500
	    
nkeynes@601
  1501
	    // not taken
nkeynes@601
  1502
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1503
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1504
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1505
	    return 4;
nkeynes@417
  1506
	}
nkeynes@374
  1507
    }
nkeynes@374
  1508
:}
nkeynes@374
  1509
BRA disp {:  
nkeynes@671
  1510
    COUNT_INST(I_BRA);
nkeynes@374
  1511
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1512
	SLOTILLEGAL();
nkeynes@374
  1513
    } else {
nkeynes@590
  1514
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1515
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1516
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1517
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1518
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1519
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1520
	    exit_block_emu(pc+2);
nkeynes@601
  1521
	    return 2;
nkeynes@601
  1522
	} else {
nkeynes@601
  1523
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1524
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1525
	    return 4;
nkeynes@601
  1526
	}
nkeynes@374
  1527
    }
nkeynes@374
  1528
:}
nkeynes@374
  1529
BRAF Rn {:  
nkeynes@671
  1530
    COUNT_INST(I_BRAF);
nkeynes@374
  1531
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1532
	SLOTILLEGAL();
nkeynes@374
  1533
    } else {
nkeynes@590
  1534
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1535
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1536
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1537
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1538
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1539
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1540
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1541
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1542
	    exit_block_emu(pc+2);
nkeynes@601
  1543
	    return 2;
nkeynes@601
  1544
	} else {
nkeynes@601
  1545
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1546
	    exit_block_newpcset(pc+2);
nkeynes@601
  1547
	    return 4;
nkeynes@601
  1548
	}
nkeynes@374
  1549
    }
nkeynes@374
  1550
:}
nkeynes@374
  1551
BSR disp {:  
nkeynes@671
  1552
    COUNT_INST(I_BSR);
nkeynes@374
  1553
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1554
	SLOTILLEGAL();
nkeynes@374
  1555
    } else {
nkeynes@590
  1556
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1557
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1558
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1559
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1560
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1561
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1562
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1563
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1564
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1565
	    exit_block_emu(pc+2);
nkeynes@601
  1566
	    return 2;
nkeynes@601
  1567
	} else {
nkeynes@601
  1568
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1569
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1570
	    return 4;
nkeynes@601
  1571
	}
nkeynes@374
  1572
    }
nkeynes@374
  1573
:}
nkeynes@374
  1574
BSRF Rn {:  
nkeynes@671
  1575
    COUNT_INST(I_BSRF);
nkeynes@374
  1576
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1577
	SLOTILLEGAL();
nkeynes@374
  1578
    } else {
nkeynes@590
  1579
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1580
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1581
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1582
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1583
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1584
nkeynes@601
  1585
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1586
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1587
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1588
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1589
	    exit_block_emu(pc+2);
nkeynes@601
  1590
	    return 2;
nkeynes@601
  1591
	} else {
nkeynes@601
  1592
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1593
	    exit_block_newpcset(pc+2);
nkeynes@601
  1594
	    return 4;
nkeynes@601
  1595
	}
nkeynes@374
  1596
    }
nkeynes@374
  1597
:}
nkeynes@374
  1598
BT disp {:
nkeynes@671
  1599
    COUNT_INST(I_BT);
nkeynes@374
  1600
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1601
	SLOTILLEGAL();
nkeynes@374
  1602
    } else {
nkeynes@586
  1603
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1604
	JF_rel8( nottaken );
nkeynes@586
  1605
	exit_block_rel(target, pc+2 );
nkeynes@380
  1606
	JMP_TARGET(nottaken);
nkeynes@408
  1607
	return 2;
nkeynes@374
  1608
    }
nkeynes@374
  1609
:}
nkeynes@374
  1610
BT/S disp {:
nkeynes@671
  1611
    COUNT_INST(I_BTS);
nkeynes@374
  1612
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1613
	SLOTILLEGAL();
nkeynes@374
  1614
    } else {
nkeynes@590
  1615
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1616
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1617
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1618
	    JF_rel8(nottaken);
nkeynes@601
  1619
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1620
	    JMP_TARGET(nottaken);
nkeynes@601
  1621
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1622
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1623
	    exit_block_emu(pc+2);
nkeynes@601
  1624
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1625
	    return 2;
nkeynes@601
  1626
	} else {
nkeynes@601
  1627
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1628
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1629
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1630
	    }
nkeynes@601
  1631
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1632
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1633
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1634
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1635
	    // not taken
nkeynes@601
  1636
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1637
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1638
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1639
	    return 4;
nkeynes@417
  1640
	}
nkeynes@374
  1641
    }
nkeynes@374
  1642
:}
nkeynes@374
  1643
JMP @Rn {:  
nkeynes@671
  1644
    COUNT_INST(I_JMP);
nkeynes@374
  1645
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1646
	SLOTILLEGAL();
nkeynes@374
  1647
    } else {
nkeynes@408
  1648
	load_reg( R_ECX, Rn );
nkeynes@590
  1649
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1650
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1651
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1652
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1653
	    exit_block_emu(pc+2);
nkeynes@601
  1654
	    return 2;
nkeynes@601
  1655
	} else {
nkeynes@601
  1656
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1657
	    exit_block_newpcset(pc+2);
nkeynes@601
  1658
	    return 4;
nkeynes@601
  1659
	}
nkeynes@374
  1660
    }
nkeynes@374
  1661
:}
nkeynes@374
  1662
JSR @Rn {:  
nkeynes@671
  1663
    COUNT_INST(I_JSR);
nkeynes@374
  1664
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1665
	SLOTILLEGAL();
nkeynes@374
  1666
    } else {
nkeynes@590
  1667
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1668
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1669
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1670
	load_reg( R_ECX, Rn );
nkeynes@590
  1671
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1672
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1673
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1674
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1675
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1676
	    exit_block_emu(pc+2);
nkeynes@601
  1677
	    return 2;
nkeynes@601
  1678
	} else {
nkeynes@601
  1679
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1680
	    exit_block_newpcset(pc+2);
nkeynes@601
  1681
	    return 4;
nkeynes@601
  1682
	}
nkeynes@374
  1683
    }
nkeynes@374
  1684
:}
nkeynes@374
  1685
RTE {:  
nkeynes@671
  1686
    COUNT_INST(I_RTE);
nkeynes@374
  1687
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1688
	SLOTILLEGAL();
nkeynes@374
  1689
    } else {
nkeynes@408
  1690
	check_priv();
nkeynes@408
  1691
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1692
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1693
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1694
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1695
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1696
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1697
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1698
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1699
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1700
	    exit_block_emu(pc+2);
nkeynes@601
  1701
	    return 2;
nkeynes@601
  1702
	} else {
nkeynes@601
  1703
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1704
	    exit_block_newpcset(pc+2);
nkeynes@601
  1705
	    return 4;
nkeynes@601
  1706
	}
nkeynes@374
  1707
    }
nkeynes@374
  1708
:}
nkeynes@374
  1709
RTS {:  
nkeynes@671
  1710
    COUNT_INST(I_RTS);
nkeynes@374
  1711
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1712
	SLOTILLEGAL();
nkeynes@374
  1713
    } else {
nkeynes@408
  1714
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1715
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1716
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1717
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1718
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1719
	    exit_block_emu(pc+2);
nkeynes@601
  1720
	    return 2;
nkeynes@601
  1721
	} else {
nkeynes@601
  1722
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1723
	    exit_block_newpcset(pc+2);
nkeynes@601
  1724
	    return 4;
nkeynes@601
  1725
	}
nkeynes@374
  1726
    }
nkeynes@374
  1727
:}
nkeynes@374
  1728
TRAPA #imm {:  
nkeynes@671
  1729
    COUNT_INST(I_TRAPA);
nkeynes@374
  1730
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1731
	SLOTILLEGAL();
nkeynes@374
  1732
    } else {
nkeynes@590
  1733
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1734
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1735
	load_imm32( R_EAX, imm );
nkeynes@527
  1736
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1737
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1738
	exit_block_pcset(pc);
nkeynes@409
  1739
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1740
	return 2;
nkeynes@374
  1741
    }
nkeynes@374
  1742
:}
nkeynes@374
  1743
UNDEF {:  
nkeynes@671
  1744
    COUNT_INST(I_UNDEF);
nkeynes@374
  1745
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1746
	SLOTILLEGAL();
nkeynes@374
  1747
    } else {
nkeynes@586
  1748
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1749
	return 2;
nkeynes@374
  1750
    }
nkeynes@368
  1751
:}
nkeynes@374
  1752
nkeynes@374
  1753
CLRMAC {:  
nkeynes@671
  1754
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1755
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1756
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1757
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1758
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1759
:}
nkeynes@374
  1760
CLRS {:
nkeynes@671
  1761
    COUNT_INST(I_CLRS);
nkeynes@374
  1762
    CLC();
nkeynes@374
  1763
    SETC_sh4r(R_S);
nkeynes@872
  1764
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1765
:}
nkeynes@374
  1766
CLRT {:  
nkeynes@671
  1767
    COUNT_INST(I_CLRT);
nkeynes@374
  1768
    CLC();
nkeynes@374
  1769
    SETC_t();
nkeynes@417
  1770
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1771
:}
nkeynes@374
  1772
SETS {:  
nkeynes@671
  1773
    COUNT_INST(I_SETS);
nkeynes@374
  1774
    STC();
nkeynes@374
  1775
    SETC_sh4r(R_S);
nkeynes@872
  1776
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1777
:}
nkeynes@374
  1778
SETT {:  
nkeynes@671
  1779
    COUNT_INST(I_SETT);
nkeynes@374
  1780
    STC();
nkeynes@374
  1781
    SETC_t();
nkeynes@417
  1782
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1783
:}
nkeynes@359
  1784
nkeynes@375
  1785
/* Floating point moves */
nkeynes@375
  1786
FMOV FRm, FRn {:  
nkeynes@671
  1787
    COUNT_INST(I_FMOV1);
nkeynes@377
  1788
    check_fpuen();
nkeynes@901
  1789
    if( sh4_x86.double_size ) {
nkeynes@901
  1790
        load_dr0( R_EAX, FRm );
nkeynes@901
  1791
        load_dr1( R_ECX, FRm );
nkeynes@901
  1792
        store_dr0( R_EAX, FRn );
nkeynes@901
  1793
        store_dr1( R_ECX, FRn );
nkeynes@901
  1794
    } else {
nkeynes@901
  1795
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1796
        store_fr( R_EAX, FRn );
nkeynes@901
  1797
    }
nkeynes@375
  1798
:}
nkeynes@416
  1799
FMOV FRm, @Rn {: 
nkeynes@671
  1800
    COUNT_INST(I_FMOV2);
nkeynes@586
  1801
    check_fpuen();
nkeynes@586
  1802
    load_reg( R_EAX, Rn );
nkeynes@901
  1803
    if( sh4_x86.double_size ) {
nkeynes@901
  1804
        check_walign64( R_EAX );
nkeynes@905
  1805
        load_dr0( R_EDX, FRm );
nkeynes@953
  1806
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953
  1807
        load_reg( R_EAX, Rn );
nkeynes@953
  1808
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953
  1809
        load_dr1( R_EDX, FRm );
nkeynes@953
  1810
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1811
    } else {
nkeynes@901
  1812
        check_walign32( R_EAX );
nkeynes@905
  1813
        load_fr( R_EDX, FRm );
nkeynes@905
  1814
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1815
    }
nkeynes@417
  1816
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1817
:}
nkeynes@375
  1818
FMOV @Rm, FRn {:  
nkeynes@671
  1819
    COUNT_INST(I_FMOV5);
nkeynes@586
  1820
    check_fpuen();
nkeynes@586
  1821
    load_reg( R_EAX, Rm );
nkeynes@901
  1822
    if( sh4_x86.double_size ) {
nkeynes@901
  1823
        check_ralign64( R_EAX );
nkeynes@953
  1824
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
  1825
        store_dr0( R_EAX, FRn );
nkeynes@953
  1826
        load_reg( R_EAX, Rm );
nkeynes@953
  1827
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953
  1828
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
  1829
        store_dr1( R_EAX, FRn );
nkeynes@901
  1830
    } else {
nkeynes@901
  1831
        check_ralign32( R_EAX );
nkeynes@901
  1832
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1833
        store_fr( R_EAX, FRn );
nkeynes@901
  1834
    }
nkeynes@417
  1835
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1836
:}
nkeynes@377
  1837
FMOV FRm, @-Rn {:  
nkeynes@671
  1838
    COUNT_INST(I_FMOV3);
nkeynes@586
  1839
    check_fpuen();
nkeynes@586
  1840
    load_reg( R_EAX, Rn );
nkeynes@901
  1841
    if( sh4_x86.double_size ) {
nkeynes@901
  1842
        check_walign64( R_EAX );
nkeynes@953
  1843
        LEA_r32disp8_r32( R_EAX, -8, R_EAX );
nkeynes@905
  1844
        load_dr0( R_EDX, FRm );
nkeynes@953
  1845
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953
  1846
        load_reg( R_EAX, Rn );
nkeynes@953
  1847
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@953
  1848
        load_dr1( R_EDX, FRm );
nkeynes@953
  1849
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1850
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@901
  1851
    } else {
nkeynes@901
  1852
        check_walign32( R_EAX );
nkeynes@953
  1853
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@905
  1854
        load_fr( R_EDX, FRm );
nkeynes@953
  1855
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1856
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@901
  1857
    }
nkeynes@417
  1858
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1859
:}
nkeynes@416
  1860
FMOV @Rm+, FRn {:
nkeynes@671
  1861
    COUNT_INST(I_FMOV6);
nkeynes@586
  1862
    check_fpuen();
nkeynes@586
  1863
    load_reg( R_EAX, Rm );
nkeynes@901
  1864
    if( sh4_x86.double_size ) {
nkeynes@901
  1865
        check_ralign64( R_EAX );
nkeynes@953
  1866
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
  1867
        store_dr0( R_EAX, FRn );
nkeynes@953
  1868
        load_reg( R_EAX, Rm );
nkeynes@953
  1869
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953
  1870
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
  1871
        store_dr1( R_EAX, FRn );
nkeynes@901
  1872
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@901
  1873
    } else {
nkeynes@901
  1874
        check_ralign32( R_EAX );
nkeynes@901
  1875
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1876
        store_fr( R_EAX, FRn );
nkeynes@953
  1877
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1878
    }
nkeynes@417
  1879
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1880
:}
nkeynes@377
  1881
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1882
    COUNT_INST(I_FMOV4);
nkeynes@586
  1883
    check_fpuen();
nkeynes@586
  1884
    load_reg( R_EAX, Rn );
nkeynes@586
  1885
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1886
    if( sh4_x86.double_size ) {
nkeynes@901
  1887
        check_walign64( R_EAX );
nkeynes@905
  1888
        load_dr0( R_EDX, FRm );
nkeynes@953
  1889
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953
  1890
        load_reg( R_EAX, Rn );
nkeynes@953
  1891
        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@953
  1892
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953
  1893
        load_dr1( R_EDX, FRm );
nkeynes@953
  1894
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1895
    } else {
nkeynes@901
  1896
        check_walign32( R_EAX );
nkeynes@905
  1897
        load_fr( R_EDX, FRm );
nkeynes@905
  1898
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1899
    }
nkeynes@417
  1900
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1901
:}
nkeynes@377
  1902
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1903
    COUNT_INST(I_FMOV7);
nkeynes@586
  1904
    check_fpuen();
nkeynes@586
  1905
    load_reg( R_EAX, Rm );
nkeynes@586
  1906
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1907
    if( sh4_x86.double_size ) {
nkeynes@901
  1908
        check_ralign64( R_EAX );
nkeynes@953
  1909
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953
  1910
        store_dr0( R_EAX, FRn );
nkeynes@953
  1911
        load_reg( R_EAX, Rm );
nkeynes@953
  1912
        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@953
  1913
        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953
  1914
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1915
        store_dr1( R_EAX, FRn );
nkeynes@901
  1916
    } else {
nkeynes@901
  1917
        check_ralign32( R_EAX );
nkeynes@901
  1918
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1919
        store_fr( R_EAX, FRn );
nkeynes@901
  1920
    }
nkeynes@417
  1921
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1922
:}
nkeynes@377
  1923
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1924
    COUNT_INST(I_FLDI0);
nkeynes@377
  1925
    check_fpuen();
nkeynes@901
  1926
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1927
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1928
        store_fr( R_EAX, FRn );
nkeynes@901
  1929
    }
nkeynes@417
  1930
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1931
:}
nkeynes@377
  1932
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1933
    COUNT_INST(I_FLDI1);
nkeynes@377
  1934
    check_fpuen();
nkeynes@901
  1935
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1936
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1937
        store_fr( R_EAX, FRn );
nkeynes@901
  1938
    }
nkeynes@377
  1939
:}
nkeynes@377
  1940
nkeynes@377
  1941
FLOAT FPUL, FRn {:  
nkeynes@671
  1942
    COUNT_INST(I_FLOAT);
nkeynes@377
  1943
    check_fpuen();
nkeynes@377
  1944
    FILD_sh4r(R_FPUL);
nkeynes@901
  1945
    if( sh4_x86.double_prec ) {
nkeynes@901
  1946
        pop_dr( FRn );
nkeynes@901
  1947
    } else {
nkeynes@901
  1948
        pop_fr( FRn );
nkeynes@901
  1949
    }
nkeynes@377
  1950
:}
nkeynes@377
  1951
FTRC FRm, FPUL {:  
nkeynes@671
  1952
    COUNT_INST(I_FTRC);
nkeynes@377
  1953
    check_fpuen();
nkeynes@901
  1954
    if( sh4_x86.double_prec ) {
nkeynes@901
  1955
        push_dr( FRm );
nkeynes@901
  1956
    } else {
nkeynes@901
  1957
        push_fr( FRm );
nkeynes@901
  1958
    }
nkeynes@789
  1959
    load_ptr( R_ECX, &max_int );
nkeynes@388
  1960
    FILD_r32ind( R_ECX );
nkeynes@388
  1961
    FCOMIP_st(1);
nkeynes@669
  1962
    JNA_rel8( sat );
nkeynes@789
  1963
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  1964
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1965
    FCOMIP_st(1);                   // 2
nkeynes@669
  1966
    JAE_rel8( sat2 );            // 2
nkeynes@789
  1967
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  1968
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  1969
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  1970
    FLDCW_r32ind( R_EDX );
nkeynes@388
  1971
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  1972
    FLDCW_r32ind( R_EAX );
nkeynes@669
  1973
    JMP_rel8(end);             // 2
nkeynes@388
  1974
nkeynes@388
  1975
    JMP_TARGET(sat);
nkeynes@388
  1976
    JMP_TARGET(sat2);
nkeynes@388
  1977
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  1978
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  1979
    FPOP_st();
nkeynes@388
  1980
    JMP_TARGET(end);
nkeynes@417
  1981
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1982
:}
nkeynes@377
  1983
FLDS FRm, FPUL {:  
nkeynes@671
  1984
    COUNT_INST(I_FLDS);
nkeynes@377
  1985
    check_fpuen();
nkeynes@669
  1986
    load_fr( R_EAX, FRm );
nkeynes@377
  1987
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1988
:}
nkeynes@377
  1989
FSTS FPUL, FRn {:  
nkeynes@671
  1990
    COUNT_INST(I_FSTS);
nkeynes@377
  1991
    check_fpuen();
nkeynes@377
  1992
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  1993
    store_fr( R_EAX, FRn );
nkeynes@377
  1994
:}
nkeynes@377
  1995
FCNVDS FRm, FPUL {:  
nkeynes@671
  1996
    COUNT_INST(I_FCNVDS);
nkeynes@377
  1997
    check_fpuen();
nkeynes@901
  1998
    if( sh4_x86.double_prec ) {
nkeynes@901
  1999
        push_dr( FRm );
nkeynes@901
  2000
        pop_fpul();
nkeynes@901
  2001
    }
nkeynes@377
  2002
:}
nkeynes@377
  2003
FCNVSD FPUL, FRn {:  
nkeynes@671
  2004
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2005
    check_fpuen();
nkeynes@901
  2006
    if( sh4_x86.double_prec ) {
nkeynes@901
  2007
        push_fpul();
nkeynes@901
  2008
        pop_dr( FRn );
nkeynes@901
  2009
    }
nkeynes@377
  2010
:}
nkeynes@375
  2011
nkeynes@359
  2012
/* Floating point instructions */
nkeynes@374
  2013
FABS FRn {:  
nkeynes@671
  2014
    COUNT_INST(I_FABS);
nkeynes@377
  2015
    check_fpuen();
nkeynes@901
  2016
    if( sh4_x86.double_prec ) {
nkeynes@901
  2017
        push_dr(FRn);
nkeynes@901
  2018
        FABS_st0();
nkeynes@901
  2019
        pop_dr(FRn);
nkeynes@901
  2020
    } else {
nkeynes@901
  2021
        push_fr(FRn);
nkeynes@901
  2022
        FABS_st0();
nkeynes@901
  2023
        pop_fr(FRn);
nkeynes@901
  2024
    }
nkeynes@374
  2025
:}
nkeynes@377
  2026
FADD FRm, FRn {:  
nkeynes@671
  2027
    COUNT_INST(I_FADD);
nkeynes@377
  2028
    check_fpuen();
nkeynes@901
  2029
    if( sh4_x86.double_prec ) {
nkeynes@901
  2030
        push_dr(FRm);
nkeynes@901
  2031
        push_dr(FRn);
nkeynes@901
  2032
        FADDP_st(1);
nkeynes@901
  2033
        pop_dr(FRn);
nkeynes@901
  2034
    } else {
nkeynes@901
  2035
        push_fr(FRm);
nkeynes@901
  2036
        push_fr(FRn);
nkeynes@901
  2037
        FADDP_st(1);
nkeynes@901
  2038
        pop_fr(FRn);
nkeynes@901
  2039
    }
nkeynes@375
  2040
:}
nkeynes@377
  2041
FDIV FRm, FRn {:  
nkeynes@671
  2042
    COUNT_INST(I_FDIV);
nkeynes@377
  2043
    check_fpuen();
nkeynes@901
  2044
    if( sh4_x86.double_prec ) {
nkeynes@901
  2045
        push_dr(FRn);
nkeynes@901
  2046
        push_dr(FRm);
nkeynes@901
  2047
        FDIVP_st(1);
nkeynes@901
  2048
        pop_dr(FRn);
nkeynes@901
  2049
    } else {
nkeynes@901
  2050
        push_fr(FRn);
nkeynes@901
  2051
        push_fr(FRm);
nkeynes@901
  2052
        FDIVP_st(1);
nkeynes@901
  2053
        pop_fr(FRn);
nkeynes@901
  2054
    }
nkeynes@375
  2055
:}
nkeynes@375
  2056
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2057
    COUNT_INST(I_FMAC);
nkeynes@377
  2058
    check_fpuen();
nkeynes@901
  2059
    if( sh4_x86.double_prec ) {
nkeynes@901
  2060
        push_dr( 0 );
nkeynes@901
  2061
        push_dr( FRm );
nkeynes@901
  2062
        FMULP_st(1);
nkeynes@901
  2063
        push_dr( FRn );
nkeynes@901
  2064
        FADDP_st(1);
nkeynes@901
  2065
        pop_dr( FRn );
nkeynes@901
  2066
    } else {
nkeynes@901
  2067
        push_fr( 0 );
nkeynes@901
  2068
        push_fr( FRm );
nkeynes@901
  2069
        FMULP_st(1);
nkeynes@901
  2070
        push_fr( FRn );
nkeynes@901
  2071
        FADDP_st(1);
nkeynes@901
  2072
        pop_fr( FRn );
nkeynes@901
  2073
    }
nkeynes@375
  2074
:}
nkeynes@375
  2075
nkeynes@377
  2076
FMUL FRm, FRn {:  
nkeynes@671
  2077
    COUNT_INST(I_FMUL);
nkeynes@377
  2078
    check_fpuen();
nkeynes@901
  2079
    if( sh4_x86.double_prec ) {
nkeynes@901
  2080
        push_dr(FRm);
nkeynes@901
  2081
        push_dr(FRn);
nkeynes@901
  2082
        FMULP_st(1);
nkeynes@901
  2083
        pop_dr(FRn);
nkeynes@901
  2084
    } else {
nkeynes@901
  2085
        push_fr(FRm);
nkeynes@901
  2086
        push_fr(FRn);
nkeynes@901
  2087
        FMULP_st(1);
nkeynes@901
  2088
        pop_fr(FRn);
nkeynes@901
  2089
    }
nkeynes@377
  2090
:}
nkeynes@377
  2091
FNEG FRn {:  
nkeynes@671
  2092
    COUNT_INST(I_FNEG);
nkeynes@377
  2093
    check_fpuen();
nkeynes@901
  2094
    if( sh4_x86.double_prec ) {
nkeynes@901
  2095
        push_dr(FRn);
nkeynes@901
  2096
        FCHS_st0();
nkeynes@901
  2097
        pop_dr(FRn);
nkeynes@901
  2098
    } else {
nkeynes@901
  2099
        push_fr(FRn);
nkeynes@901
  2100
        FCHS_st0();
nkeynes@901
  2101
        pop_fr(FRn);
nkeynes@901
  2102
    }
nkeynes@377
  2103
:}
nkeynes@377
  2104
FSRRA FRn {:  
nkeynes@671
  2105
    COUNT_INST(I_FSRRA);
nkeynes@377
  2106
    check_fpuen();
nkeynes@901
  2107
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2108
        FLD1_st0();
nkeynes@901
  2109
        push_fr(FRn);
nkeynes@901
  2110
        FSQRT_st0();
nkeynes@901
  2111
        FDIVP_st(1);
nkeynes@901
  2112
        pop_fr(FRn);
nkeynes@901
  2113
    }
nkeynes@377
  2114
:}
nkeynes@377
  2115
FSQRT FRn {:  
nkeynes@671
  2116
    COUNT_INST(I_FSQRT);
nkeynes@377
  2117
    check_fpuen();
nkeynes@901
  2118
    if( sh4_x86.double_prec ) {
nkeynes@901
  2119
        push_dr(FRn);
nkeynes@901
  2120
        FSQRT_st0();
nkeynes@901
  2121
        pop_dr(FRn);
nkeynes@901
  2122
    } else {
nkeynes@901
  2123
        push_fr(FRn);
nkeynes@901
  2124
        FSQRT_st0();
nkeynes@901
  2125
        pop_fr(FRn);
nkeynes@901
  2126
    }
nkeynes@377
  2127
:}
nkeynes@377
  2128
FSUB FRm, FRn {:  
nkeynes@671
  2129
    COUNT_INST(I_FSUB);
nkeynes@377
  2130
    check_fpuen();
nkeynes@901
  2131
    if( sh4_x86.double_prec ) {
nkeynes@901
  2132
        push_dr(FRn);
nkeynes@901
  2133
        push_dr(FRm);
nkeynes@901
  2134
        FSUBP_st(1);
nkeynes@901
  2135
        pop_dr(FRn);
nkeynes@901
  2136
    } else {
nkeynes@901
  2137
        push_fr(FRn);
nkeynes@901
  2138
        push_fr(FRm);
nkeynes@901
  2139
        FSUBP_st(1);
nkeynes@901
  2140
        pop_fr(FRn);
nkeynes@901
  2141
    }
nkeynes@377
  2142
:}
nkeynes@377
  2143
nkeynes@377
  2144
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2145
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2146
    check_fpuen();
nkeynes@901
  2147
    if( sh4_x86.double_prec ) {
nkeynes@901
  2148
        push_dr(FRm);
nkeynes@901
  2149
        push_dr(FRn);
nkeynes@901
  2150
    } else {
nkeynes@901
  2151
        push_fr(FRm);
nkeynes@901
  2152
        push_fr(FRn);
nkeynes@901
  2153
    }
nkeynes@377
  2154
    FCOMIP_st(1);
nkeynes@377
  2155
    SETE_t();
nkeynes@377
  2156
    FPOP_st();
nkeynes@901
  2157
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2158
:}
nkeynes@377
  2159
FCMP/GT FRm, FRn {:  
nkeynes@671
  2160
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2161
    check_fpuen();
nkeynes@901
  2162
    if( sh4_x86.double_prec ) {
nkeynes@901
  2163
        push_dr(FRm);
nkeynes@901
  2164
        push_dr(FRn);
nkeynes@901
  2165
    } else {
nkeynes@901
  2166
        push_fr(FRm);
nkeynes@901
  2167
        push_fr(FRn);
nkeynes@901
  2168
    }
nkeynes@377
  2169
    FCOMIP_st(1);
nkeynes@377
  2170
    SETA_t();
nkeynes@377
  2171
    FPOP_st();
nkeynes@901
  2172
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2173
:}
nkeynes@377
  2174
nkeynes@377
  2175
FSCA FPUL, FRn {:  
nkeynes@671
  2176
    COUNT_INST(I_FSCA);
nkeynes@377
  2177
    check_fpuen();
nkeynes@901
  2178
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2179
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2180
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2181
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2182
    }
nkeynes@417
  2183
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2184
:}
nkeynes@377
  2185
FIPR FVm, FVn {:  
nkeynes@671
  2186
    COUNT_INST(I_FIPR);
nkeynes@377
  2187
    check_fpuen();
nkeynes@901
  2188
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2189
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2190
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2191
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2192
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2193
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2194
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2195
        } else {
nkeynes@904
  2196
            push_fr( FVm<<2 );
nkeynes@903
  2197
            push_fr( FVn<<2 );
nkeynes@903
  2198
            FMULP_st(1);
nkeynes@903
  2199
            push_fr( (FVm<<2)+1);
nkeynes@903
  2200
            push_fr( (FVn<<2)+1);
nkeynes@903
  2201
            FMULP_st(1);
nkeynes@903
  2202
            FADDP_st(1);
nkeynes@903
  2203
            push_fr( (FVm<<2)+2);
nkeynes@903
  2204
            push_fr( (FVn<<2)+2);
nkeynes@903
  2205
            FMULP_st(1);
nkeynes@903
  2206
            FADDP_st(1);
nkeynes@903
  2207
            push_fr( (FVm<<2)+3);
nkeynes@903
  2208
            push_fr( (FVn<<2)+3);
nkeynes@903
  2209
            FMULP_st(1);
nkeynes@903
  2210
            FADDP_st(1);
nkeynes@903
  2211
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2212
        }
nkeynes@901
  2213
    }
nkeynes@377
  2214
:}
nkeynes@377
  2215
FTRV XMTRX, FVn {:  
nkeynes@671
  2216
    COUNT_INST(I_FTRV);
nkeynes@377
  2217
    check_fpuen();
nkeynes@901
  2218
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2219
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2220
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2221
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2222
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2223
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2224
nkeynes@903
  2225
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2226
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2227
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2228
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2229
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2230
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2231
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2232
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2233
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2234
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2235
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2236
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2237
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2238
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2239
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2240
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2241
        } else {
nkeynes@903
  2242
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2243
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2244
        }
nkeynes@901
  2245
    }
nkeynes@417
  2246
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2247
:}
nkeynes@377
  2248
nkeynes@377
  2249
FRCHG {:  
nkeynes@671
  2250
    COUNT_INST(I_FRCHG);
nkeynes@377
  2251
    check_fpuen();
nkeynes@953
  2252
    XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );
nkeynes@669
  2253
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2254
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2255
:}
nkeynes@377
  2256
FSCHG {:  
nkeynes@671
  2257
    COUNT_INST(I_FSCHG);
nkeynes@377
  2258
    check_fpuen();
nkeynes@953
  2259
    XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);
nkeynes@953
  2260
    XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417
  2261
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2262
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2263
:}
nkeynes@359
  2264
nkeynes@359
  2265
/* Processor control instructions */
nkeynes@368
  2266
LDC Rm, SR {:
nkeynes@671
  2267
    COUNT_INST(I_LDCSR);
nkeynes@386
  2268
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2269
	SLOTILLEGAL();
nkeynes@386
  2270
    } else {
nkeynes@386
  2271
	check_priv();
nkeynes@386
  2272
	load_reg( R_EAX, Rm );
nkeynes@386
  2273
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2274
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2275
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2276
	return 2;
nkeynes@386
  2277
    }
nkeynes@368
  2278
:}
nkeynes@359
  2279
LDC Rm, GBR {: 
nkeynes@671
  2280
    COUNT_INST(I_LDC);
nkeynes@359
  2281
    load_reg( R_EAX, Rm );
nkeynes@359
  2282
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2283
:}
nkeynes@359
  2284
LDC Rm, VBR {:  
nkeynes@671
  2285
    COUNT_INST(I_LDC);
nkeynes@386
  2286
    check_priv();
nkeynes@359
  2287
    load_reg( R_EAX, Rm );
nkeynes@359
  2288
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2289
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2290
:}
nkeynes@359
  2291
LDC Rm, SSR {:  
nkeynes@671
  2292
    COUNT_INST(I_LDC);
nkeynes@386
  2293
    check_priv();
nkeynes@359
  2294
    load_reg( R_EAX, Rm );
nkeynes@359
  2295
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2296
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2297
:}
nkeynes@359
  2298
LDC Rm, SGR {:  
nkeynes@671
  2299
    COUNT_INST(I_LDC);
nkeynes@386
  2300
    check_priv();
nkeynes@359
  2301
    load_reg( R_EAX, Rm );
nkeynes@359
  2302
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2303
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2304
:}
nkeynes@359
  2305
LDC Rm, SPC {:  
nkeynes@671
  2306
    COUNT_INST(I_LDC);
nkeynes@386
  2307
    check_priv();
nkeynes@359
  2308
    load_reg( R_EAX, Rm );
nkeynes@359
  2309
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2310
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2311
:}
nkeynes@359
  2312
LDC Rm, DBR {:  
nkeynes@671
  2313
    COUNT_INST(I_LDC);
nkeynes@386
  2314
    check_priv();
nkeynes@359
  2315
    load_reg( R_EAX, Rm );
nkeynes@359
  2316
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2317
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2318
:}
nkeynes@374
  2319
LDC Rm, Rn_BANK {:  
nkeynes@671
  2320
    COUNT_INST(I_LDC);
nkeynes@386
  2321
    check_priv();
nkeynes@374
  2322
    load_reg( R_EAX, Rm );
nkeynes@374
  2323
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2324
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2325
:}
nkeynes@359
  2326
LDC.L @Rm+, GBR {:  
nkeynes@671
  2327
    COUNT_INST(I_LDCM);
nkeynes@359
  2328
    load_reg( R_EAX, Rm );
nkeynes@395
  2329
    check_ralign32( R_EAX );
nkeynes@953
  2330
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2331
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2332
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2334
:}
nkeynes@368
  2335
LDC.L @Rm+, SR {:
nkeynes@671
  2336
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2337
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2338
	SLOTILLEGAL();
nkeynes@386
  2339
    } else {
nkeynes@586
  2340
	check_priv();
nkeynes@386
  2341
	load_reg( R_EAX, Rm );
nkeynes@395
  2342
	check_ralign32( R_EAX );
nkeynes@953
  2343
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2344
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
  2345
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2346
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2347
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953
  2348
	return 2;
nkeynes@386
  2349
    }
nkeynes@359
  2350
:}
nkeynes@359
  2351
LDC.L @Rm+, VBR {:  
nkeynes@671
  2352
    COUNT_INST(I_LDCM);
nkeynes@586
  2353
    check_priv();
nkeynes@359
  2354
    load_reg( R_EAX, Rm );
nkeynes@395
  2355
    check_ralign32( R_EAX );
nkeynes@953
  2356
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2357
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2358
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2359
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2360
:}
nkeynes@359
  2361
LDC.L @Rm+, SSR {:
nkeynes@671
  2362
    COUNT_INST(I_LDCM);
nkeynes@586
  2363
    check_priv();
nkeynes@359
  2364
    load_reg( R_EAX, Rm );
nkeynes@416
  2365
    check_ralign32( R_EAX );
nkeynes@953
  2366
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2367
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2368
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2369
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2370
:}
nkeynes@359
  2371
LDC.L @Rm+, SGR {:  
nkeynes@671
  2372
    COUNT_INST(I_LDCM);
nkeynes@586
  2373
    check_priv();
nkeynes@359
  2374
    load_reg( R_EAX, Rm );
nkeynes@395
  2375
    check_ralign32( R_EAX );
nkeynes@953
  2376
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2377
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2378
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2379
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2380
:}
nkeynes@359
  2381
LDC.L @Rm+, SPC {:  
nkeynes@671
  2382
    COUNT_INST(I_LDCM);
nkeynes@586
  2383
    check_priv();
nkeynes@359
  2384
    load_reg( R_EAX, Rm );
nkeynes@395
  2385
    check_ralign32( R_EAX );
nkeynes@953
  2386
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2387
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2388
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2389
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2390
:}
nkeynes@359
  2391
LDC.L @Rm+, DBR {:  
nkeynes@671
  2392
    COUNT_INST(I_LDCM);
nkeynes@586
  2393
    check_priv();
nkeynes@359
  2394
    load_reg( R_EAX, Rm );
nkeynes@395
  2395
    check_ralign32( R_EAX );
nkeynes@953
  2396
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2397
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2398
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2399
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2400
:}
nkeynes@359
  2401
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2402
    COUNT_INST(I_LDCM);
nkeynes@586
  2403
    check_priv();
nkeynes@374
  2404
    load_reg( R_EAX, Rm );
nkeynes@395
  2405
    check_ralign32( R_EAX );
nkeynes@953
  2406
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2407
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@374
  2408
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2409
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2410
:}
nkeynes@626
  2411
LDS Rm, FPSCR {:
nkeynes@673
  2412
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2413
    check_fpuen();
nkeynes@359
  2414
    load_reg( R_EAX, Rm );
nkeynes@669
  2415
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2416
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2417
    return 2;
nkeynes@359
  2418
:}
nkeynes@359
  2419
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2420
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2421
    check_fpuen();
nkeynes@359
  2422
    load_reg( R_EAX, Rm );
nkeynes@395
  2423
    check_ralign32( R_EAX );
nkeynes@953
  2424
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2425
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@669
  2426
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2427
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2428
    return 2;
nkeynes@359
  2429
:}
nkeynes@359
  2430
LDS Rm, FPUL {:  
nkeynes@671
  2431
    COUNT_INST(I_LDS);
nkeynes@626
  2432
    check_fpuen();
nkeynes@359
  2433
    load_reg( R_EAX, Rm );
nkeynes@359
  2434
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2435
:}
nkeynes@359
  2436
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2437
    COUNT_INST(I_LDSM);
nkeynes@626
  2438
    check_fpuen();
nkeynes@359
  2439
    load_reg( R_EAX, Rm );
nkeynes@395
  2440
    check_ralign32( R_EAX );
nkeynes@953
  2441
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2442
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2443
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2444
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2445
:}
nkeynes@359
  2446
LDS Rm, MACH {: 
nkeynes@671
  2447
    COUNT_INST(I_LDS);
nkeynes@359
  2448
    load_reg( R_EAX, Rm );
nkeynes@359
  2449
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2450
:}
nkeynes@359
  2451
LDS.L @Rm+, MACH {:  
nkeynes@671
  2452
    COUNT_INST(I_LDSM);
nkeynes@359
  2453
    load_reg( R_EAX, Rm );
nkeynes@395
  2454
    check_ralign32( R_EAX );
nkeynes@953
  2455
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2456
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2457
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2458
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2459
:}
nkeynes@359
  2460
LDS Rm, MACL {:  
nkeynes@671
  2461
    COUNT_INST(I_LDS);
nkeynes@359
  2462
    load_reg( R_EAX, Rm );
nkeynes@359
  2463
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2464
:}
nkeynes@359
  2465
LDS.L @Rm+, MACL {:  
nkeynes@671
  2466
    COUNT_INST(I_LDSM);
nkeynes@359
  2467
    load_reg( R_EAX, Rm );
nkeynes@395
  2468
    check_ralign32( R_EAX );
nkeynes@953
  2469
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2470
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2471
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2472
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2473
:}
nkeynes@359
  2474
LDS Rm, PR {:  
nkeynes@671
  2475
    COUNT_INST(I_LDS);
nkeynes@359
  2476
    load_reg( R_EAX, Rm );
nkeynes@359
  2477
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2478
:}
nkeynes@359
  2479
LDS.L @Rm+, PR {:  
nkeynes@671
  2480
    COUNT_INST(I_LDSM);
nkeynes@359
  2481
    load_reg( R_EAX, Rm );
nkeynes@395
  2482
    check_ralign32( R_EAX );
nkeynes@953
  2483
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  2484
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359
  2485
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2486
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2487
:}
nkeynes@550
  2488
LDTLB {:  
nkeynes@671
  2489
    COUNT_INST(I_LDTLB);
nkeynes@553
  2490
    call_func0( MMU_ldtlb );
nkeynes@875
  2491
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2492
:}
nkeynes@671
  2493
OCBI @Rn {:
nkeynes@671
  2494
    COUNT_INST(I_OCBI);
nkeynes@671
  2495
:}
nkeynes@671
  2496
OCBP @Rn {:
nkeynes@671
  2497
    COUNT_INST(I_OCBP);
nkeynes@671
  2498
:}
nkeynes@671
  2499
OCBWB @Rn {:
nkeynes@671
  2500
    COUNT_INST(I_OCBWB);
nkeynes@671
  2501
:}
nkeynes@374
  2502
PREF @Rn {:
nkeynes@671
  2503
    COUNT_INST(I_PREF);
nkeynes@374
  2504
    load_reg( R_EAX, Rn );
nkeynes@953
  2505
    MEM_PREFETCH( R_EAX );
nkeynes@417
  2506
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2507
:}
nkeynes@388
  2508
SLEEP {: 
nkeynes@671
  2509
    COUNT_INST(I_SLEEP);
nkeynes@388
  2510
    check_priv();
nkeynes@388
  2511
    call_func0( sh4_sleep );
nkeynes@417
  2512
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2513
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2514
    return 2;
nkeynes@388
  2515
:}
nkeynes@386
  2516
STC SR, Rn {:
nkeynes@671
  2517
    COUNT_INST(I_STCSR);
nkeynes@386
  2518
    check_priv();
nkeynes@386
  2519
    call_func0(sh4_read_sr);
nkeynes@386
  2520
    store_reg( R_EAX, Rn );
nkeynes@417
  2521
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2522
:}
nkeynes@359
  2523
STC GBR, Rn {:  
nkeynes@671
  2524
    COUNT_INST(I_STC);
nkeynes@359
  2525
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2526
    store_reg( R_EAX, Rn );
nkeynes@359
  2527
:}
nkeynes@359
  2528
STC VBR, Rn {:  
nkeynes@671
  2529
    COUNT_INST(I_STC);
nkeynes@386
  2530
    check_priv();
nkeynes@359
  2531
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2532
    store_reg( R_EAX, Rn );
nkeynes@417
  2533
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2534
:}
nkeynes@359
  2535
STC SSR, Rn {:  
nkeynes@671
  2536
    COUNT_INST(I_STC);
nkeynes@386
  2537
    check_priv();
nkeynes@359
  2538
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2539
    store_reg( R_EAX, Rn );
nkeynes@417
  2540
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2541
:}
nkeynes@359
  2542
STC SPC, Rn {:  
nkeynes@671
  2543
    COUNT_INST(I_STC);
nkeynes@386
  2544
    check_priv();
nkeynes@359
  2545
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2546
    store_reg( R_EAX, Rn );
nkeynes@417
  2547
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2548
:}
nkeynes@359
  2549
STC SGR, Rn {:  
nkeynes@671
  2550
    COUNT_INST(I_STC);
nkeynes@386
  2551
    check_priv();
nkeynes@359
  2552
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2553
    store_reg( R_EAX, Rn );
nkeynes@417
  2554
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2555
:}
nkeynes@359
  2556
STC DBR, Rn {:  
nkeynes@671
  2557
    COUNT_INST(I_STC);
nkeynes@386
  2558
    check_priv();
nkeynes@359
  2559
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2560
    store_reg( R_EAX, Rn );
nkeynes@417
  2561
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2562
:}
nkeynes@374
  2563
STC Rm_BANK, Rn {:
nkeynes@671
  2564
    COUNT_INST(I_STC);
nkeynes@386
  2565
    check_priv();
nkeynes@374
  2566
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2567
    store_reg( R_EAX, Rn );
nkeynes@417
  2568
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2569
:}
nkeynes@374
  2570
STC.L SR, @-Rn {:
nkeynes@671
  2571
    COUNT_INST(I_STCSRM);
nkeynes@586
  2572
    check_priv();
nkeynes@953
  2573
    call_func0( sh4_read_sr );
nkeynes@953
  2574
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@586
  2575
    load_reg( R_EAX, Rn );
nkeynes@586
  2576
    check_walign32( R_EAX );
nkeynes@953
  2577
    LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@953
  2578
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2579
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2580
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2581
:}
nkeynes@359
  2582
STC.L VBR, @-Rn {:  
nkeynes@671
  2583
    COUNT_INST(I_STCM);
nkeynes@586
  2584
    check_priv();
nkeynes@586
  2585
    load_reg( R_EAX, Rn );
nkeynes@586
  2586
    check_walign32( R_EAX );
nkeynes@586
  2587
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2588
    load_spreg( R_EDX, R_VBR );
nkeynes@953
  2589
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2590
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2592
:}
nkeynes@359
  2593
STC.L SSR, @-Rn {:  
nkeynes@671
  2594
    COUNT_INST(I_STCM);
nkeynes@586
  2595
    check_priv();
nkeynes@586
  2596
    load_reg( R_EAX, Rn );
nkeynes@586
  2597
    check_walign32( R_EAX );
nkeynes@586
  2598
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2599
    load_spreg( R_EDX, R_SSR );
nkeynes@953
  2600
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2601
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2602
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2603
:}
nkeynes@416
  2604
STC.L SPC, @-Rn {:
nkeynes@671
  2605
    COUNT_INST(I_STCM);
nkeynes@586
  2606
    check_priv();
nkeynes@586
  2607
    load_reg( R_EAX, Rn );
nkeynes@586
  2608
    check_walign32( R_EAX );
nkeynes@586
  2609
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2610
    load_spreg( R_EDX, R_SPC );
nkeynes@953
  2611
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2612
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2613
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2614
:}
nkeynes@359
  2615
STC.L SGR, @-Rn {:  
nkeynes@671
  2616
    COUNT_INST(I_STCM);
nkeynes@586
  2617
    check_priv();
nkeynes@586
  2618
    load_reg( R_EAX, Rn );
nkeynes@586
  2619
    check_walign32( R_EAX );
nkeynes@586
  2620
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2621
    load_spreg( R_EDX, R_SGR );
nkeynes@953
  2622
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2623
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2624
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2625
:}
nkeynes@359
  2626
STC.L DBR, @-Rn {:  
nkeynes@671
  2627
    COUNT_INST(I_STCM);
nkeynes@586
  2628
    check_priv();
nkeynes@586
  2629
    load_reg( R_EAX, Rn );
nkeynes@586
  2630
    check_walign32( R_EAX );
nkeynes@586
  2631
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2632
    load_spreg( R_EDX, R_DBR );
nkeynes@953
  2633
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2634
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2635
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2636
:}
nkeynes@374
  2637
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2638
    COUNT_INST(I_STCM);
nkeynes@586
  2639
    check_priv();
nkeynes@586
  2640
    load_reg( R_EAX, Rn );
nkeynes@586
  2641
    check_walign32( R_EAX );
nkeynes@586
  2642
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2643
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@953
  2644
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2645
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2646
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2647
:}
nkeynes@359
  2648
STC.L GBR, @-Rn {:  
nkeynes@671
  2649
    COUNT_INST(I_STCM);
nkeynes@586
  2650
    load_reg( R_EAX, Rn );
nkeynes@586
  2651
    check_walign32( R_EAX );
nkeynes@586
  2652
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2653
    load_spreg( R_EDX, R_GBR );
nkeynes@953
  2654
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2655
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2656
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2657
:}
nkeynes@359
  2658
STS FPSCR, Rn {:  
nkeynes@673
  2659
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2660
    check_fpuen();
nkeynes@359
  2661
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2662
    store_reg( R_EAX, Rn );
nkeynes@359
  2663
:}
nkeynes@359
  2664
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2665
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2666
    check_fpuen();
nkeynes@586
  2667
    load_reg( R_EAX, Rn );
nkeynes@586
  2668
    check_walign32( R_EAX );
nkeynes@586
  2669
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2670
    load_spreg( R_EDX, R_FPSCR );
nkeynes@953
  2671
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2672
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2673
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2674
:}
nkeynes@359
  2675
STS FPUL, Rn {:  
nkeynes@671
  2676
    COUNT_INST(I_STS);
nkeynes@626
  2677
    check_fpuen();
nkeynes@359
  2678
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2679
    store_reg( R_EAX, Rn );
nkeynes@359
  2680
:}
nkeynes@359
  2681
STS.L FPUL, @-Rn {:  
nkeynes@671
  2682
    COUNT_INST(I_STSM);
nkeynes@626
  2683
    check_fpuen();
nkeynes@586
  2684
    load_reg( R_EAX, Rn );
nkeynes@586
  2685
    check_walign32( R_EAX );
nkeynes@586
  2686
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2687
    load_spreg( R_EDX, R_FPUL );
nkeynes@953
  2688
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2689
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2690
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2691
:}
nkeynes@359
  2692
STS MACH, Rn {:  
nkeynes@671
  2693
    COUNT_INST(I_STS);
nkeynes@359
  2694
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2695
    store_reg( R_EAX, Rn );
nkeynes@359
  2696
:}
nkeynes@359
  2697
STS.L MACH, @-Rn {:  
nkeynes@671
  2698
    COUNT_INST(I_STSM);
nkeynes@586
  2699
    load_reg( R_EAX, Rn );
nkeynes@586
  2700
    check_walign32( R_EAX );
nkeynes@586
  2701
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2702
    load_spreg( R_EDX, R_MACH );
nkeynes@953
  2703
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2704
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2705
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2706
:}
nkeynes@359
  2707
STS MACL, Rn {:  
nkeynes@671
  2708
    COUNT_INST(I_STS);
nkeynes@359
  2709
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2710
    store_reg( R_EAX, Rn );
nkeynes@359
  2711
:}
nkeynes@359
  2712
STS.L MACL, @-Rn {:  
nkeynes@671
  2713
    COUNT_INST(I_STSM);
nkeynes@586
  2714
    load_reg( R_EAX, Rn );
nkeynes@586
  2715
    check_walign32( R_EAX );
nkeynes@586
  2716
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2717
    load_spreg( R_EDX, R_MACL );
nkeynes@953
  2718
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2719
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2720
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2721
:}
nkeynes@359
  2722
STS PR, Rn {:  
nkeynes@671
  2723
    COUNT_INST(I_STS);
nkeynes@359
  2724
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2725
    store_reg( R_EAX, Rn );
nkeynes@359
  2726
:}
nkeynes@359
  2727
STS.L PR, @-Rn {:  
nkeynes@671
  2728
    COUNT_INST(I_STSM);
nkeynes@586
  2729
    load_reg( R_EAX, Rn );
nkeynes@586
  2730
    check_walign32( R_EAX );
nkeynes@586
  2731
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2732
    load_spreg( R_EDX, R_PR );
nkeynes@953
  2733
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586
  2734
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417
  2735
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2736
:}
nkeynes@359
  2737
nkeynes@671
  2738
NOP {: 
nkeynes@671
  2739
    COUNT_INST(I_NOP);
nkeynes@671
  2740
    /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ 
nkeynes@671
  2741
:}
nkeynes@359
  2742
%%
nkeynes@590
  2743
    sh4_x86.in_delay_slot = DELAY_NONE;