nkeynes@23 | 1 | /**
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nkeynes@36 | 2 | * $Id: sh4core.c,v 1.14 2005-12-26 06:38:13 nkeynes Exp $
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nkeynes@23 | 3 | *
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nkeynes@23 | 4 | * SH4 emulation core, and parent module for all the SH4 peripheral
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nkeynes@23 | 5 | * modules.
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nkeynes@23 | 6 | *
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nkeynes@23 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@23 | 8 | *
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nkeynes@23 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@23 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@23 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@23 | 12 | * (at your option) any later version.
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nkeynes@23 | 13 | *
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nkeynes@23 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@23 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@23 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@23 | 17 | * GNU General Public License for more details.
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nkeynes@23 | 18 | */
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nkeynes@23 | 19 |
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nkeynes@35 | 20 | #define MODULE sh4_module
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nkeynes@1 | 21 | #include <math.h>
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nkeynes@1 | 22 | #include "dream.h"
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nkeynes@1 | 23 | #include "sh4core.h"
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nkeynes@1 | 24 | #include "sh4mmio.h"
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nkeynes@1 | 25 | #include "mem.h"
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nkeynes@23 | 26 | #include "clock.h"
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nkeynes@1 | 27 | #include "intc.h"
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nkeynes@1 | 28 |
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nkeynes@27 | 29 | /* CPU-generated exception code/vector pairs */
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nkeynes@27 | 30 | #define EXC_POWER_RESET 0x000 /* vector special */
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nkeynes@27 | 31 | #define EXC_MANUAL_RESET 0x020
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nkeynes@27 | 32 | #define EXC_SLOT_ILLEGAL 0x1A0
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nkeynes@27 | 33 | #define EXC_ILLEGAL 0x180
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nkeynes@27 | 34 | #define EXV_ILLEGAL 0x100
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nkeynes@27 | 35 | #define EXC_TRAP 0x160
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nkeynes@27 | 36 | #define EXV_TRAP 0x100
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nkeynes@27 | 37 | #define EXC_FPDISABLE 0x800
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nkeynes@27 | 38 | #define EXV_FPDISABLE 0x100
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nkeynes@27 | 39 |
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nkeynes@23 | 40 | uint32_t sh4_freq = SH4_BASE_RATE;
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nkeynes@23 | 41 | uint32_t sh4_bus_freq = SH4_BASE_RATE;
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nkeynes@23 | 42 | uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
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nkeynes@23 | 43 |
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nkeynes@30 | 44 | uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
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nkeynes@30 | 45 | uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE;
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nkeynes@30 | 46 | uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE;
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nkeynes@30 | 47 |
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nkeynes@23 | 48 | /********************** SH4 Module Definition ****************************/
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nkeynes@23 | 49 |
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nkeynes@23 | 50 | void sh4_init( void );
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nkeynes@23 | 51 | void sh4_reset( void );
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nkeynes@30 | 52 | uint32_t sh4_run_slice( uint32_t );
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nkeynes@23 | 53 | void sh4_start( void );
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nkeynes@23 | 54 | void sh4_stop( void );
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nkeynes@23 | 55 | void sh4_save_state( FILE *f );
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nkeynes@23 | 56 | int sh4_load_state( FILE *f );
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nkeynes@16 | 57 |
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nkeynes@15 | 58 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
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nkeynes@23 | 59 | NULL, sh4_run_slice, sh4_stop,
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nkeynes@23 | 60 | sh4_save_state, sh4_load_state };
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nkeynes@15 | 61 |
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nkeynes@1 | 62 | struct sh4_registers sh4r;
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nkeynes@1 | 63 |
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nkeynes@1 | 64 | void sh4_init(void)
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nkeynes@1 | 65 | {
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nkeynes@1 | 66 | register_io_regions( mmio_list_sh4mmio );
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nkeynes@10 | 67 | mmu_init();
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nkeynes@27 | 68 | sh4_reset();
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nkeynes@1 | 69 | }
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nkeynes@1 | 70 |
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nkeynes@1 | 71 | void sh4_reset(void)
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nkeynes@1 | 72 | {
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nkeynes@19 | 73 | /* zero everything out, for the sake of having a consistent state. */
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nkeynes@19 | 74 | memset( &sh4r, 0, sizeof(sh4r) );
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nkeynes@27 | 75 |
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nkeynes@27 | 76 | /* Resume running if we were halted */
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nkeynes@27 | 77 | sh4r.sh4_state = SH4_STATE_RUNNING;
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nkeynes@27 | 78 |
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nkeynes@1 | 79 | sh4r.pc = 0xA0000000;
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nkeynes@1 | 80 | sh4r.new_pc= 0xA0000002;
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nkeynes@1 | 81 | sh4r.vbr = 0x00000000;
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nkeynes@1 | 82 | sh4r.fpscr = 0x00040001;
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nkeynes@1 | 83 | sh4r.sr = 0x700000F0;
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nkeynes@27 | 84 |
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nkeynes@27 | 85 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */
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nkeynes@27 | 86 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
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nkeynes@27 | 87 |
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nkeynes@27 | 88 | /* Peripheral modules */
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nkeynes@1 | 89 | intc_reset();
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nkeynes@32 | 90 | SCIF_reset();
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nkeynes@1 | 91 | }
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nkeynes@1 | 92 |
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nkeynes@30 | 93 | uint32_t sh4_run_slice( uint32_t nanosecs )
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nkeynes@1 | 94 | {
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nkeynes@30 | 95 | int target = sh4r.icount + nanosecs / sh4_cpu_period;
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nkeynes@27 | 96 | int start = sh4r.icount;
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nkeynes@23 | 97 | int i;
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nkeynes@23 | 98 |
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nkeynes@27 | 99 | if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
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nkeynes@27 | 100 | if( sh4r.int_pending != 0 )
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nkeynes@27 | 101 | sh4r.sh4_state = SH4_STATE_RUNNING;;
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nkeynes@23 | 102 | }
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nkeynes@27 | 103 |
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nkeynes@27 | 104 | while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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nkeynes@27 | 105 | sh4r.icount++;
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nkeynes@27 | 106 | if( !sh4_execute_instruction() )
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nkeynes@27 | 107 | break;
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nkeynes@27 | 108 | }
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nkeynes@30 | 109 |
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nkeynes@30 | 110 | /* If we aborted early, but the cpu is still technically running,
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nkeynes@30 | 111 | * we're doing a hard abort - cut the timeslice back to what we
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nkeynes@30 | 112 | * actually executed
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nkeynes@30 | 113 | */
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nkeynes@30 | 114 | if( target != sh4r.icount && sh4r.sh4_state == SH4_STATE_RUNNING ) {
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nkeynes@27 | 115 | /* Halted - compute time actually executed */
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nkeynes@30 | 116 | nanosecs = (sh4r.icount - start) * sh4_cpu_period;
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nkeynes@27 | 117 | }
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nkeynes@27 | 118 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
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nkeynes@30 | 119 | TMU_run_slice( nanosecs );
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nkeynes@30 | 120 | SCIF_run_slice( nanosecs );
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nkeynes@27 | 121 | }
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nkeynes@30 | 122 | return nanosecs;
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nkeynes@1 | 123 | }
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nkeynes@1 | 124 |
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nkeynes@1 | 125 | void sh4_stop(void)
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nkeynes@1 | 126 | {
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nkeynes@27 | 127 |
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nkeynes@1 | 128 | }
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nkeynes@1 | 129 |
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nkeynes@23 | 130 | void sh4_save_state( FILE *f )
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nkeynes@16 | 131 | {
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nkeynes@16 | 132 | fwrite( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@23 | 133 | SCIF_save_state( f );
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nkeynes@16 | 134 | }
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nkeynes@16 | 135 |
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nkeynes@23 | 136 | int sh4_load_state( FILE * f )
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nkeynes@16 | 137 | {
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nkeynes@18 | 138 | fread( &sh4r, sizeof(sh4r), 1, f );
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nkeynes@23 | 139 | return SCIF_load_state( f );
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nkeynes@16 | 140 | }
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nkeynes@16 | 141 |
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nkeynes@23 | 142 | /********************** SH4 emulation core ****************************/
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nkeynes@23 | 143 |
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nkeynes@23 | 144 | void sh4_set_pc( int pc )
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nkeynes@23 | 145 | {
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nkeynes@23 | 146 | sh4r.pc = pc;
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nkeynes@23 | 147 | sh4r.new_pc = pc+2;
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nkeynes@23 | 148 | }
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nkeynes@23 | 149 |
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nkeynes@23 | 150 | void sh4_set_breakpoint( uint32_t pc, int type )
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nkeynes@23 | 151 | {
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nkeynes@23 | 152 |
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nkeynes@23 | 153 | }
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nkeynes@23 | 154 |
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nkeynes@27 | 155 | #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
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nkeynes@27 | 156 | #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
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nkeynes@1 | 157 |
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nkeynes@1 | 158 | #define RAISE( x, v ) do{ \
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nkeynes@1 | 159 | if( sh4r.vbr == 0 ) { \
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nkeynes@1 | 160 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
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nkeynes@1 | 161 | sh4_stop(); \
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nkeynes@1 | 162 | } else { \
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nkeynes@1 | 163 | sh4r.spc = sh4r.pc + 2; \
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nkeynes@1 | 164 | sh4r.ssr = sh4_read_sr(); \
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nkeynes@1 | 165 | sh4r.sgr = sh4r.r[15]; \
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nkeynes@1 | 166 | MMIO_WRITE(MMU,EXPEVT,x); \
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nkeynes@1 | 167 | sh4r.pc = sh4r.vbr + v; \
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nkeynes@1 | 168 | sh4r.new_pc = sh4r.pc + 2; \
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nkeynes@1 | 169 | sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
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nkeynes@1 | 170 | } \
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nkeynes@27 | 171 | return TRUE; } while(0)
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nkeynes@1 | 172 |
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nkeynes@10 | 173 | #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
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nkeynes@10 | 174 | #define MEM_READ_WORD( addr ) sh4_read_word(addr)
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nkeynes@10 | 175 | #define MEM_READ_LONG( addr ) sh4_read_long(addr)
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nkeynes@10 | 176 | #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
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nkeynes@10 | 177 | #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
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nkeynes@10 | 178 | #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
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nkeynes@1 | 179 |
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nkeynes@1 | 180 | #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
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nkeynes@10 | 181 | ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
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nkeynes@10 | 182 | ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
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nkeynes@10 | 183 | } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
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nkeynes@1 | 184 |
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nkeynes@1 | 185 | #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
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nkeynes@10 | 186 | sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
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nkeynes@10 | 187 | sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
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nkeynes@10 | 188 | } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
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nkeynes@1 | 189 |
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nkeynes@1 | 190 | #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
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nkeynes@1 | 191 |
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nkeynes@1 | 192 | #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
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nkeynes@1 | 193 | #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
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nkeynes@1 | 194 | #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
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nkeynes@1 | 195 | #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
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nkeynes@2 | 196 | #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
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nkeynes@1 | 197 |
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nkeynes@1 | 198 | static void sh4_switch_banks( )
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nkeynes@1 | 199 | {
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nkeynes@1 | 200 | uint32_t tmp[8];
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nkeynes@1 | 201 |
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nkeynes@1 | 202 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
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nkeynes@1 | 203 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
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nkeynes@1 | 204 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
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nkeynes@1 | 205 | }
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nkeynes@1 | 206 |
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nkeynes@1 | 207 | static void sh4_load_sr( uint32_t newval )
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nkeynes@1 | 208 | {
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nkeynes@1 | 209 | if( (newval ^ sh4r.sr) & SR_RB )
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nkeynes@1 | 210 | sh4_switch_banks();
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nkeynes@1 | 211 | sh4r.sr = newval;
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nkeynes@1 | 212 | sh4r.t = (newval&SR_T) ? 1 : 0;
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nkeynes@1 | 213 | sh4r.s = (newval&SR_S) ? 1 : 0;
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nkeynes@1 | 214 | sh4r.m = (newval&SR_M) ? 1 : 0;
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nkeynes@1 | 215 | sh4r.q = (newval&SR_Q) ? 1 : 0;
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nkeynes@1 | 216 | intc_mask_changed();
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nkeynes@1 | 217 | }
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nkeynes@1 | 218 |
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nkeynes@1 | 219 | static uint32_t sh4_read_sr( void )
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nkeynes@1 | 220 | {
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nkeynes@1 | 221 | /* synchronize sh4r.sr with the various bitflags */
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nkeynes@1 | 222 | sh4r.sr &= SR_MQSTMASK;
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nkeynes@1 | 223 | if( sh4r.t ) sh4r.sr |= SR_T;
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nkeynes@1 | 224 | if( sh4r.s ) sh4r.sr |= SR_S;
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nkeynes@1 | 225 | if( sh4r.m ) sh4r.sr |= SR_M;
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nkeynes@1 | 226 | if( sh4r.q ) sh4r.sr |= SR_Q;
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nkeynes@1 | 227 | return sh4r.sr;
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nkeynes@1 | 228 | }
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nkeynes@1 | 229 | /* function for external use */
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nkeynes@1 | 230 | void sh4_raise_exception( int code, int vector )
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nkeynes@1 | 231 | {
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nkeynes@1 | 232 | RAISE(code, vector);
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nkeynes@1 | 233 | }
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nkeynes@1 | 234 |
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nkeynes@1 | 235 | static void sh4_accept_interrupt( void )
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nkeynes@1 | 236 | {
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nkeynes@1 | 237 | uint32_t code = intc_accept_interrupt();
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nkeynes@1 | 238 | sh4r.ssr = sh4_read_sr();
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nkeynes@1 | 239 | sh4r.spc = sh4r.pc;
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nkeynes@1 | 240 | sh4r.sgr = sh4r.r[15];
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nkeynes@1 | 241 | sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
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nkeynes@1 | 242 | MMIO_WRITE( MMU, INTEVT, code );
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nkeynes@1 | 243 | sh4r.pc = sh4r.vbr + 0x600;
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nkeynes@1 | 244 | sh4r.new_pc = sh4r.pc + 2;
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nkeynes@2 | 245 | WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
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nkeynes@1 | 246 | }
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nkeynes@1 | 247 |
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nkeynes@27 | 248 | gboolean sh4_execute_instruction( void )
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nkeynes@1 | 249 | {
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nkeynes@2 | 250 | int pc;
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nkeynes@2 | 251 | unsigned short ir;
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nkeynes@1 | 252 | uint32_t tmp;
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nkeynes@1 | 253 | uint64_t tmpl;
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nkeynes@1 | 254 |
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nkeynes@1 | 255 | #define R0 sh4r.r[0]
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nkeynes@1 | 256 | #define FR0 (FR[0])
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nkeynes@1 | 257 | #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
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nkeynes@1 | 258 | #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
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nkeynes@1 | 259 | #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
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nkeynes@1 | 260 | #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
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nkeynes@1 | 261 | #define DISP8(ir) (ir&0x00FF)
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nkeynes@1 | 262 | #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
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nkeynes@1 | 263 | #define IMM8(ir) SIGNEXT8(ir&0x00FF)
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nkeynes@1 | 264 | #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
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nkeynes@1 | 265 | #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
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nkeynes@2 | 266 | #define FVN(ir) ((ir&0x0C00)>>8)
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nkeynes@2 | 267 | #define FVM(ir) ((ir&0x0300)>>6)
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nkeynes@1 | 268 | #define FRN(ir) (FR[(ir&0x0F00)>>8])
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nkeynes@1 | 269 | #define FRM(ir) (FR[(ir&0x00F0)>>4])
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nkeynes@1 | 270 | #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
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nkeynes@1 | 271 | #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
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nkeynes@1 | 272 | #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
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nkeynes@1 | 273 | #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
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nkeynes@1 | 274 | #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
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nkeynes@1 | 275 | #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
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nkeynes@1 | 276 | #define FRNn(ir) ((ir&0x0F00)>>8)
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nkeynes@1 | 277 | #define FRMn(ir) ((ir&0x00F0)>>4)
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nkeynes@1 | 278 | #define FPULf *((float *)&sh4r.fpul)
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nkeynes@1 | 279 | #define FPULi (sh4r.fpul)
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nkeynes@1 | 280 |
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nkeynes@2 | 281 | if( SH4_INT_PENDING() )
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nkeynes@2 | 282 | sh4_accept_interrupt();
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nkeynes@1 | 283 |
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nkeynes@2 | 284 | pc = sh4r.pc;
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nkeynes@2 | 285 | ir = MEM_READ_WORD(pc);
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nkeynes@1 | 286 | sh4r.icount++;
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nkeynes@1 | 287 |
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nkeynes@1 | 288 | switch( (ir&0xF000)>>12 ) {
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nkeynes@1 | 289 | case 0: /* 0000nnnnmmmmxxxx */
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nkeynes@1 | 290 | switch( ir&0x000F ) {
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nkeynes@1 | 291 | case 2:
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nkeynes@1 | 292 | switch( (ir&0x00F0)>>4 ) {
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nkeynes@1 | 293 | case 0: /* STC SR, Rn */
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nkeynes@1 | 294 | CHECKPRIV();
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nkeynes@1 | 295 | RN(ir) = sh4_read_sr();
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nkeynes@1 | 296 | break;
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nkeynes@1 | 297 | case 1: /* STC GBR, Rn */
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nkeynes@1 | 298 | RN(ir) = sh4r.gbr;
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nkeynes@1 | 299 | break;
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nkeynes@1 | 300 | case 2: /* STC VBR, Rn */
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nkeynes@1 | 301 | CHECKPRIV();
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nkeynes@1 | 302 | RN(ir) = sh4r.vbr;
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nkeynes@1 | 303 | break;
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nkeynes@1 | 304 | case 3: /* STC SSR, Rn */
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nkeynes@1 | 305 | CHECKPRIV();
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nkeynes@1 | 306 | RN(ir) = sh4r.ssr;
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nkeynes@1 | 307 | break;
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nkeynes@1 | 308 | case 4: /* STC SPC, Rn */
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nkeynes@1 | 309 | CHECKPRIV();
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nkeynes@1 | 310 | RN(ir) = sh4r.spc;
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nkeynes@1 | 311 | break;
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nkeynes@1 | 312 | case 8: case 9: case 10: case 11: case 12: case 13:
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nkeynes@1 | 313 | case 14: case 15:/* STC Rm_bank, Rn */
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nkeynes@1 | 314 | CHECKPRIV();
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nkeynes@1 | 315 | RN(ir) = RN_BANK(ir);
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nkeynes@1 | 316 | break;
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nkeynes@1 | 317 | default: UNDEF(ir);
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nkeynes@1 | 318 | }
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nkeynes@1 | 319 | break;
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nkeynes@1 | 320 | case 3:
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nkeynes@1 | 321 | switch( (ir&0x00F0)>>4 ) {
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nkeynes@1 | 322 | case 0: /* BSRF Rn */
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nkeynes@1 | 323 | CHECKDEST( pc + 4 + RN(ir) );
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nkeynes@2 | 324 | CHECKSLOTILLEGAL();
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nkeynes@2 | 325 | sh4r.in_delay_slot = 1;
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nkeynes@1 | 326 | sh4r.pr = sh4r.pc + 4;
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nkeynes@1 | 327 | sh4r.pc = sh4r.new_pc;
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nkeynes@1 | 328 | sh4r.new_pc = pc + 4 + RN(ir);
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nkeynes@27 | 329 | return TRUE;
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nkeynes@1 | 330 | case 2: /* BRAF Rn */
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nkeynes@1 | 331 | CHECKDEST( pc + 4 + RN(ir) );
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nkeynes@2 | 332 | CHECKSLOTILLEGAL();
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nkeynes@2 | 333 | sh4r.in_delay_slot = 1;
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nkeynes@1 | 334 | sh4r.pc = sh4r.new_pc;
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nkeynes@1 | 335 | sh4r.new_pc = pc + 4 + RN(ir);
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nkeynes@27 | 336 | return TRUE;
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nkeynes@1 | 337 | case 8: /* PREF [Rn] */
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nkeynes@2 | 338 | tmp = RN(ir);
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nkeynes@2 | 339 | if( (tmp & 0xFC000000) == 0xE0000000 ) {
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nkeynes@2 | 340 | /* Store queue operation */
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nkeynes@2 | 341 | int queue = (tmp&0x20)>>2;
|
nkeynes@2 | 342 | int32_t *src = &sh4r.store_queue[queue];
|
nkeynes@2 | 343 | uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
|
nkeynes@2 | 344 | uint32_t target = tmp&0x03FFFFE0 | hi;
|
nkeynes@2 | 345 | mem_copy_to_sh4( target, src, 32 );
|
nkeynes@2 | 346 | WARN( "Executed SQ%c => %08X",
|
nkeynes@2 | 347 | (queue == 0 ? '0' : '1'), target );
|
nkeynes@2 | 348 | }
|
nkeynes@2 | 349 | break;
|
nkeynes@1 | 350 | case 9: /* OCBI [Rn] */
|
nkeynes@1 | 351 | case 10:/* OCBP [Rn] */
|
nkeynes@1 | 352 | case 11:/* OCBWB [Rn] */
|
nkeynes@1 | 353 | /* anything? */
|
nkeynes@1 | 354 | break;
|
nkeynes@1 | 355 | case 12:/* MOVCA.L R0, [Rn] */
|
nkeynes@1 | 356 | UNIMP(ir);
|
nkeynes@1 | 357 | default: UNDEF(ir);
|
nkeynes@1 | 358 | }
|
nkeynes@1 | 359 | break;
|
nkeynes@1 | 360 | case 4: /* MOV.B Rm, [R0 + Rn] */
|
nkeynes@1 | 361 | MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 362 | break;
|
nkeynes@1 | 363 | case 5: /* MOV.W Rm, [R0 + Rn] */
|
nkeynes@1 | 364 | MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 365 | break;
|
nkeynes@1 | 366 | case 6: /* MOV.L Rm, [R0 + Rn] */
|
nkeynes@1 | 367 | MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
|
nkeynes@1 | 368 | break;
|
nkeynes@1 | 369 | case 7: /* MUL.L Rm, Rn */
|
nkeynes@2 | 370 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 371 | (RM(ir) * RN(ir));
|
nkeynes@1 | 372 | break;
|
nkeynes@1 | 373 | case 8:
|
nkeynes@1 | 374 | switch( (ir&0x0FF0)>>4 ) {
|
nkeynes@1 | 375 | case 0: /* CLRT */
|
nkeynes@1 | 376 | sh4r.t = 0;
|
nkeynes@1 | 377 | break;
|
nkeynes@1 | 378 | case 1: /* SETT */
|
nkeynes@1 | 379 | sh4r.t = 1;
|
nkeynes@1 | 380 | break;
|
nkeynes@1 | 381 | case 2: /* CLRMAC */
|
nkeynes@1 | 382 | sh4r.mac = 0;
|
nkeynes@1 | 383 | break;
|
nkeynes@1 | 384 | case 3: /* LDTLB */
|
nkeynes@1 | 385 | break;
|
nkeynes@1 | 386 | case 4: /* CLRS */
|
nkeynes@1 | 387 | sh4r.s = 0;
|
nkeynes@1 | 388 | break;
|
nkeynes@1 | 389 | case 5: /* SETS */
|
nkeynes@1 | 390 | sh4r.s = 1;
|
nkeynes@1 | 391 | break;
|
nkeynes@1 | 392 | default: UNDEF(ir);
|
nkeynes@1 | 393 | }
|
nkeynes@1 | 394 | break;
|
nkeynes@1 | 395 | case 9:
|
nkeynes@1 | 396 | if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
|
nkeynes@1 | 397 | RN(ir) = sh4r.t;
|
nkeynes@1 | 398 | else if( ir == 0x0019 ) /* DIV0U */
|
nkeynes@1 | 399 | sh4r.m = sh4r.q = sh4r.t = 0;
|
nkeynes@1 | 400 | else if( ir == 0x0009 )
|
nkeynes@1 | 401 | /* NOP */;
|
nkeynes@1 | 402 | else UNDEF(ir);
|
nkeynes@1 | 403 | break;
|
nkeynes@1 | 404 | case 10:
|
nkeynes@1 | 405 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@1 | 406 | case 0: /* STS MACH, Rn */
|
nkeynes@1 | 407 | RN(ir) = sh4r.mac >> 32;
|
nkeynes@1 | 408 | break;
|
nkeynes@1 | 409 | case 1: /* STS MACL, Rn */
|
nkeynes@1 | 410 | RN(ir) = (uint32_t)sh4r.mac;
|
nkeynes@1 | 411 | break;
|
nkeynes@1 | 412 | case 2: /* STS PR, Rn */
|
nkeynes@1 | 413 | RN(ir) = sh4r.pr;
|
nkeynes@1 | 414 | break;
|
nkeynes@1 | 415 | case 3: /* STC SGR, Rn */
|
nkeynes@1 | 416 | CHECKPRIV();
|
nkeynes@1 | 417 | RN(ir) = sh4r.sgr;
|
nkeynes@1 | 418 | break;
|
nkeynes@1 | 419 | case 5:/* STS FPUL, Rn */
|
nkeynes@1 | 420 | RN(ir) = sh4r.fpul;
|
nkeynes@1 | 421 | break;
|
nkeynes@1 | 422 | case 6: /* STS FPSCR, Rn */
|
nkeynes@1 | 423 | RN(ir) = sh4r.fpscr;
|
nkeynes@1 | 424 | break;
|
nkeynes@1 | 425 | case 15:/* STC DBR, Rn */
|
nkeynes@1 | 426 | CHECKPRIV();
|
nkeynes@1 | 427 | RN(ir) = sh4r.dbr;
|
nkeynes@1 | 428 | break;
|
nkeynes@1 | 429 | default: UNDEF(ir);
|
nkeynes@1 | 430 | }
|
nkeynes@1 | 431 | break;
|
nkeynes@1 | 432 | case 11:
|
nkeynes@1 | 433 | switch( (ir&0x0FF0)>>4 ) {
|
nkeynes@1 | 434 | case 0: /* RTS */
|
nkeynes@1 | 435 | CHECKDEST( sh4r.pr );
|
nkeynes@2 | 436 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 437 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 438 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 439 | sh4r.new_pc = sh4r.pr;
|
nkeynes@27 | 440 | return TRUE;
|
nkeynes@1 | 441 | case 1: /* SLEEP */
|
nkeynes@27 | 442 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
|
nkeynes@27 | 443 | sh4r.sh4_state = SH4_STATE_STANDBY;
|
nkeynes@27 | 444 | } else {
|
nkeynes@27 | 445 | sh4r.sh4_state = SH4_STATE_SLEEP;
|
nkeynes@27 | 446 | }
|
nkeynes@27 | 447 | return FALSE; /* Halt CPU */
|
nkeynes@1 | 448 | case 2: /* RTE */
|
nkeynes@1 | 449 | CHECKPRIV();
|
nkeynes@1 | 450 | CHECKDEST( sh4r.spc );
|
nkeynes@2 | 451 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 452 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 453 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 454 | sh4r.new_pc = sh4r.spc;
|
nkeynes@1 | 455 | sh4_load_sr( sh4r.ssr );
|
nkeynes@27 | 456 | return TRUE;
|
nkeynes@1 | 457 | default:UNDEF(ir);
|
nkeynes@1 | 458 | }
|
nkeynes@1 | 459 | break;
|
nkeynes@1 | 460 | case 12:/* MOV.B [R0+R%d], R%d */
|
nkeynes@1 | 461 | RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
|
nkeynes@1 | 462 | break;
|
nkeynes@1 | 463 | case 13:/* MOV.W [R0+R%d], R%d */
|
nkeynes@1 | 464 | RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
|
nkeynes@1 | 465 | break;
|
nkeynes@1 | 466 | case 14:/* MOV.L [R0+R%d], R%d */
|
nkeynes@1 | 467 | RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
|
nkeynes@1 | 468 | break;
|
nkeynes@1 | 469 | case 15:/* MAC.L [Rm++], [Rn++] */
|
nkeynes@1 | 470 | tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
|
nkeynes@1 | 471 | SIGNEXT32(MEM_READ_LONG(RN(ir))) );
|
nkeynes@1 | 472 | if( sh4r.s ) {
|
nkeynes@1 | 473 | /* 48-bit Saturation. Yuch */
|
nkeynes@1 | 474 | tmpl += SIGNEXT48(sh4r.mac);
|
nkeynes@2 | 475 | if( tmpl < 0xFFFF800000000000LL )
|
nkeynes@2 | 476 | tmpl = 0xFFFF800000000000LL;
|
nkeynes@2 | 477 | else if( tmpl > 0x00007FFFFFFFFFFFLL )
|
nkeynes@2 | 478 | tmpl = 0x00007FFFFFFFFFFFLL;
|
nkeynes@2 | 479 | sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
|
nkeynes@2 | 480 | (tmpl&0x0000FFFFFFFFFFFFLL);
|
nkeynes@1 | 481 | } else sh4r.mac = tmpl;
|
nkeynes@1 | 482 |
|
nkeynes@1 | 483 | RM(ir) += 4;
|
nkeynes@1 | 484 | RN(ir) += 4;
|
nkeynes@1 | 485 |
|
nkeynes@1 | 486 | break;
|
nkeynes@1 | 487 | default: UNDEF(ir);
|
nkeynes@1 | 488 | }
|
nkeynes@1 | 489 | break;
|
nkeynes@1 | 490 | case 1: /* 0001nnnnmmmmdddd */
|
nkeynes@1 | 491 | /* MOV.L Rm, [Rn + disp4*4] */
|
nkeynes@1 | 492 | MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
|
nkeynes@1 | 493 | break;
|
nkeynes@1 | 494 | case 2: /* 0010nnnnmmmmxxxx */
|
nkeynes@1 | 495 | switch( ir&0x000F ) {
|
nkeynes@1 | 496 | case 0: /* MOV.B Rm, [Rn] */
|
nkeynes@1 | 497 | MEM_WRITE_BYTE( RN(ir), RM(ir) );
|
nkeynes@1 | 498 | break;
|
nkeynes@1 | 499 | case 1: /* MOV.W Rm, [Rn] */
|
nkeynes@1 | 500 | MEM_WRITE_WORD( RN(ir), RM(ir) );
|
nkeynes@1 | 501 | break;
|
nkeynes@1 | 502 | case 2: /* MOV.L Rm, [Rn] */
|
nkeynes@1 | 503 | MEM_WRITE_LONG( RN(ir), RM(ir) );
|
nkeynes@1 | 504 | break;
|
nkeynes@1 | 505 | case 3: UNDEF(ir);
|
nkeynes@1 | 506 | break;
|
nkeynes@1 | 507 | case 4: /* MOV.B Rm, [--Rn] */
|
nkeynes@1 | 508 | RN(ir) --;
|
nkeynes@1 | 509 | MEM_WRITE_BYTE( RN(ir), RM(ir) );
|
nkeynes@1 | 510 | break;
|
nkeynes@1 | 511 | case 5: /* MOV.W Rm, [--Rn] */
|
nkeynes@1 | 512 | RN(ir) -= 2;
|
nkeynes@1 | 513 | MEM_WRITE_WORD( RN(ir), RM(ir) );
|
nkeynes@1 | 514 | break;
|
nkeynes@1 | 515 | case 6: /* MOV.L Rm, [--Rn] */
|
nkeynes@1 | 516 | RN(ir) -= 4;
|
nkeynes@1 | 517 | MEM_WRITE_LONG( RN(ir), RM(ir) );
|
nkeynes@1 | 518 | break;
|
nkeynes@1 | 519 | case 7: /* DIV0S Rm, Rn */
|
nkeynes@1 | 520 | sh4r.q = RN(ir)>>31;
|
nkeynes@1 | 521 | sh4r.m = RM(ir)>>31;
|
nkeynes@1 | 522 | sh4r.t = sh4r.q ^ sh4r.m;
|
nkeynes@1 | 523 | break;
|
nkeynes@1 | 524 | case 8: /* TST Rm, Rn */
|
nkeynes@1 | 525 | sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
|
nkeynes@1 | 526 | break;
|
nkeynes@1 | 527 | case 9: /* AND Rm, Rn */
|
nkeynes@1 | 528 | RN(ir) &= RM(ir);
|
nkeynes@1 | 529 | break;
|
nkeynes@1 | 530 | case 10:/* XOR Rm, Rn */
|
nkeynes@1 | 531 | RN(ir) ^= RM(ir);
|
nkeynes@1 | 532 | break;
|
nkeynes@1 | 533 | case 11:/* OR Rm, Rn */
|
nkeynes@1 | 534 | RN(ir) |= RM(ir);
|
nkeynes@1 | 535 | break;
|
nkeynes@1 | 536 | case 12:/* CMP/STR Rm, Rn */
|
nkeynes@1 | 537 | /* set T = 1 if any byte in RM & RN is the same */
|
nkeynes@1 | 538 | tmp = RM(ir) ^ RN(ir);
|
nkeynes@1 | 539 | sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
|
nkeynes@1 | 540 | (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
|
nkeynes@1 | 541 | break;
|
nkeynes@1 | 542 | case 13:/* XTRCT Rm, Rn */
|
nkeynes@1 | 543 | RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
|
nkeynes@1 | 544 | break;
|
nkeynes@1 | 545 | case 14:/* MULU.W Rm, Rn */
|
nkeynes@2 | 546 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 547 | (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
|
nkeynes@1 | 548 | break;
|
nkeynes@1 | 549 | case 15:/* MULS.W Rm, Rn */
|
nkeynes@2 | 550 | sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 551 | (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
|
nkeynes@1 | 552 | break;
|
nkeynes@1 | 553 | }
|
nkeynes@1 | 554 | break;
|
nkeynes@1 | 555 | case 3: /* 0011nnnnmmmmxxxx */
|
nkeynes@1 | 556 | switch( ir&0x000F ) {
|
nkeynes@1 | 557 | case 0: /* CMP/EQ Rm, Rn */
|
nkeynes@1 | 558 | sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
|
nkeynes@1 | 559 | break;
|
nkeynes@1 | 560 | case 2: /* CMP/HS Rm, Rn */
|
nkeynes@1 | 561 | sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
|
nkeynes@1 | 562 | break;
|
nkeynes@1 | 563 | case 3: /* CMP/GE Rm, Rn */
|
nkeynes@1 | 564 | sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
|
nkeynes@1 | 565 | break;
|
nkeynes@1 | 566 | case 4: { /* DIV1 Rm, Rn */
|
nkeynes@1 | 567 | /* This is just from the sh4p manual with some
|
nkeynes@1 | 568 | * simplifications (someone want to check it's correct? :)
|
nkeynes@1 | 569 | * Why they couldn't just provide a real DIV instruction...
|
nkeynes@1 | 570 | * Please oh please let the translator batch these things
|
nkeynes@1 | 571 | * up into a single DIV... */
|
nkeynes@1 | 572 | uint32_t tmp0, tmp1, tmp2, dir;
|
nkeynes@1 | 573 |
|
nkeynes@1 | 574 | dir = sh4r.q ^ sh4r.m;
|
nkeynes@1 | 575 | sh4r.q = (RN(ir) >> 31);
|
nkeynes@1 | 576 | tmp2 = RM(ir);
|
nkeynes@1 | 577 | RN(ir) = (RN(ir) << 1) | sh4r.t;
|
nkeynes@1 | 578 | tmp0 = RN(ir);
|
nkeynes@1 | 579 | if( dir ) {
|
nkeynes@1 | 580 | RN(ir) += tmp2;
|
nkeynes@1 | 581 | tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
|
nkeynes@1 | 582 | } else {
|
nkeynes@1 | 583 | RN(ir) -= tmp2;
|
nkeynes@1 | 584 | tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
|
nkeynes@1 | 585 | }
|
nkeynes@1 | 586 | sh4r.q ^= sh4r.m ^ tmp1;
|
nkeynes@1 | 587 | sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
|
nkeynes@1 | 588 | break; }
|
nkeynes@1 | 589 | case 5: /* DMULU.L Rm, Rn */
|
nkeynes@1 | 590 | sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
|
nkeynes@1 | 591 | break;
|
nkeynes@1 | 592 | case 6: /* CMP/HI Rm, Rn */
|
nkeynes@1 | 593 | sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
|
nkeynes@1 | 594 | break;
|
nkeynes@1 | 595 | case 7: /* CMP/GT Rm, Rn */
|
nkeynes@1 | 596 | sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
|
nkeynes@1 | 597 | break;
|
nkeynes@1 | 598 | case 8: /* SUB Rm, Rn */
|
nkeynes@1 | 599 | RN(ir) -= RM(ir);
|
nkeynes@1 | 600 | break;
|
nkeynes@1 | 601 | case 10:/* SUBC Rm, Rn */
|
nkeynes@1 | 602 | tmp = RN(ir);
|
nkeynes@1 | 603 | RN(ir) = RN(ir) - RM(ir) - sh4r.t;
|
nkeynes@1 | 604 | sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
|
nkeynes@1 | 605 | break;
|
nkeynes@1 | 606 | case 11:/* SUBV Rm, Rn */
|
nkeynes@1 | 607 | UNIMP(ir);
|
nkeynes@1 | 608 | break;
|
nkeynes@1 | 609 | case 12:/* ADD Rm, Rn */
|
nkeynes@1 | 610 | RN(ir) += RM(ir);
|
nkeynes@1 | 611 | break;
|
nkeynes@1 | 612 | case 13:/* DMULS.L Rm, Rn */
|
nkeynes@1 | 613 | sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
|
nkeynes@1 | 614 | break;
|
nkeynes@1 | 615 | case 14:/* ADDC Rm, Rn */
|
nkeynes@1 | 616 | tmp = RN(ir);
|
nkeynes@1 | 617 | RN(ir) += RM(ir) + sh4r.t;
|
nkeynes@1 | 618 | sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
|
nkeynes@1 | 619 | break;
|
nkeynes@1 | 620 | case 15:/* ADDV Rm, Rn */
|
nkeynes@1 | 621 | UNIMP(ir);
|
nkeynes@1 | 622 | break;
|
nkeynes@1 | 623 | default: UNDEF(ir);
|
nkeynes@1 | 624 | }
|
nkeynes@1 | 625 | break;
|
nkeynes@1 | 626 | case 4: /* 0100nnnnxxxxxxxx */
|
nkeynes@1 | 627 | switch( ir&0x00FF ) {
|
nkeynes@1 | 628 | case 0x00: /* SHLL Rn */
|
nkeynes@1 | 629 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 630 | RN(ir) <<= 1;
|
nkeynes@1 | 631 | break;
|
nkeynes@1 | 632 | case 0x01: /* SHLR Rn */
|
nkeynes@1 | 633 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 634 | RN(ir) >>= 1;
|
nkeynes@1 | 635 | break;
|
nkeynes@1 | 636 | case 0x02: /* STS.L MACH, [--Rn] */
|
nkeynes@1 | 637 | RN(ir) -= 4;
|
nkeynes@1 | 638 | MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
|
nkeynes@1 | 639 | break;
|
nkeynes@1 | 640 | case 0x03: /* STC.L SR, [--Rn] */
|
nkeynes@1 | 641 | CHECKPRIV();
|
nkeynes@1 | 642 | RN(ir) -= 4;
|
nkeynes@1 | 643 | MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
|
nkeynes@1 | 644 | break;
|
nkeynes@1 | 645 | case 0x04: /* ROTL Rn */
|
nkeynes@1 | 646 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 647 | RN(ir) <<= 1;
|
nkeynes@1 | 648 | RN(ir) |= sh4r.t;
|
nkeynes@1 | 649 | break;
|
nkeynes@1 | 650 | case 0x05: /* ROTR Rn */
|
nkeynes@1 | 651 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 652 | RN(ir) >>= 1;
|
nkeynes@1 | 653 | RN(ir) |= (sh4r.t << 31);
|
nkeynes@1 | 654 | break;
|
nkeynes@1 | 655 | case 0x06: /* LDS.L [Rn++], MACH */
|
nkeynes@1 | 656 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
|
nkeynes@1 | 657 | (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
|
nkeynes@1 | 658 | RN(ir) += 4;
|
nkeynes@1 | 659 | break;
|
nkeynes@1 | 660 | case 0x07: /* LDC.L [Rn++], SR */
|
nkeynes@1 | 661 | CHECKPRIV();
|
nkeynes@1 | 662 | sh4_load_sr( MEM_READ_LONG(RN(ir)) );
|
nkeynes@1 | 663 | RN(ir) +=4;
|
nkeynes@1 | 664 | break;
|
nkeynes@1 | 665 | case 0x08: /* SHLL2 Rn */
|
nkeynes@1 | 666 | RN(ir) <<= 2;
|
nkeynes@1 | 667 | break;
|
nkeynes@1 | 668 | case 0x09: /* SHLR2 Rn */
|
nkeynes@1 | 669 | RN(ir) >>= 2;
|
nkeynes@1 | 670 | break;
|
nkeynes@1 | 671 | case 0x0A: /* LDS Rn, MACH */
|
nkeynes@1 | 672 | sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
|
nkeynes@1 | 673 | (((uint64_t)RN(ir))<<32);
|
nkeynes@1 | 674 | break;
|
nkeynes@1 | 675 | case 0x0B: /* JSR [Rn] */
|
nkeynes@1 | 676 | CHECKDEST( RN(ir) );
|
nkeynes@2 | 677 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 678 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 679 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 680 | sh4r.new_pc = RN(ir);
|
nkeynes@1 | 681 | sh4r.pr = pc + 4;
|
nkeynes@27 | 682 | return TRUE;
|
nkeynes@1 | 683 | case 0x0E: /* LDC Rn, SR */
|
nkeynes@1 | 684 | CHECKPRIV();
|
nkeynes@1 | 685 | sh4_load_sr( RN(ir) );
|
nkeynes@1 | 686 | break;
|
nkeynes@1 | 687 | case 0x10: /* DT Rn */
|
nkeynes@1 | 688 | RN(ir) --;
|
nkeynes@1 | 689 | sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
|
nkeynes@1 | 690 | break;
|
nkeynes@1 | 691 | case 0x11: /* CMP/PZ Rn */
|
nkeynes@1 | 692 | sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
|
nkeynes@1 | 693 | break;
|
nkeynes@1 | 694 | case 0x12: /* STS.L MACL, [--Rn] */
|
nkeynes@1 | 695 | RN(ir) -= 4;
|
nkeynes@1 | 696 | MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
|
nkeynes@1 | 697 | break;
|
nkeynes@1 | 698 | case 0x13: /* STC.L GBR, [--Rn] */
|
nkeynes@1 | 699 | RN(ir) -= 4;
|
nkeynes@1 | 700 | MEM_WRITE_LONG( RN(ir), sh4r.gbr );
|
nkeynes@1 | 701 | break;
|
nkeynes@1 | 702 | case 0x15: /* CMP/PL Rn */
|
nkeynes@1 | 703 | sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
|
nkeynes@1 | 704 | break;
|
nkeynes@1 | 705 | case 0x16: /* LDS.L [Rn++], MACL */
|
nkeynes@2 | 706 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 707 | (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
|
nkeynes@1 | 708 | RN(ir) += 4;
|
nkeynes@1 | 709 | break;
|
nkeynes@1 | 710 | case 0x17: /* LDC.L [Rn++], GBR */
|
nkeynes@1 | 711 | sh4r.gbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 712 | RN(ir) +=4;
|
nkeynes@1 | 713 | break;
|
nkeynes@1 | 714 | case 0x18: /* SHLL8 Rn */
|
nkeynes@1 | 715 | RN(ir) <<= 8;
|
nkeynes@1 | 716 | break;
|
nkeynes@1 | 717 | case 0x19: /* SHLR8 Rn */
|
nkeynes@1 | 718 | RN(ir) >>= 8;
|
nkeynes@1 | 719 | break;
|
nkeynes@1 | 720 | case 0x1A: /* LDS Rn, MACL */
|
nkeynes@2 | 721 | sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
|
nkeynes@1 | 722 | (uint64_t)((uint32_t)(RN(ir)));
|
nkeynes@1 | 723 | break;
|
nkeynes@1 | 724 | case 0x1B: /* TAS.B [Rn] */
|
nkeynes@1 | 725 | tmp = MEM_READ_BYTE( RN(ir) );
|
nkeynes@1 | 726 | sh4r.t = ( tmp == 0 ? 1 : 0 );
|
nkeynes@1 | 727 | MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
|
nkeynes@1 | 728 | break;
|
nkeynes@1 | 729 | case 0x1E: /* LDC Rn, GBR */
|
nkeynes@1 | 730 | sh4r.gbr = RN(ir);
|
nkeynes@1 | 731 | break;
|
nkeynes@1 | 732 | case 0x20: /* SHAL Rn */
|
nkeynes@1 | 733 | sh4r.t = RN(ir) >> 31;
|
nkeynes@1 | 734 | RN(ir) <<= 1;
|
nkeynes@1 | 735 | break;
|
nkeynes@1 | 736 | case 0x21: /* SHAR Rn */
|
nkeynes@1 | 737 | sh4r.t = RN(ir) & 0x00000001;
|
nkeynes@1 | 738 | RN(ir) = ((int32_t)RN(ir)) >> 1;
|
nkeynes@1 | 739 | break;
|
nkeynes@1 | 740 | case 0x22: /* STS.L PR, [--Rn] */
|
nkeynes@1 | 741 | RN(ir) -= 4;
|
nkeynes@1 | 742 | MEM_WRITE_LONG( RN(ir), sh4r.pr );
|
nkeynes@1 | 743 | break;
|
nkeynes@1 | 744 | case 0x23: /* STC.L VBR, [--Rn] */
|
nkeynes@1 | 745 | CHECKPRIV();
|
nkeynes@1 | 746 | RN(ir) -= 4;
|
nkeynes@2 | 747 | MEM_WRITE_LONG( RN(ir), sh4r.vbr );
|
nkeynes@1 | 748 | break;
|
nkeynes@1 | 749 | case 0x24: /* ROTCL Rn */
|
nkeynes@1 | 750 | tmp = RN(ir) >> 31;
|
nkeynes@1 | 751 | RN(ir) <<= 1;
|
nkeynes@1 | 752 | RN(ir) |= sh4r.t;
|
nkeynes@1 | 753 | sh4r.t = tmp;
|
nkeynes@1 | 754 | break;
|
nkeynes@1 | 755 | case 0x25: /* ROTCR Rn */
|
nkeynes@1 | 756 | tmp = RN(ir) & 0x00000001;
|
nkeynes@1 | 757 | RN(ir) >>= 1;
|
nkeynes@1 | 758 | RN(ir) |= (sh4r.t << 31 );
|
nkeynes@1 | 759 | sh4r.t = tmp;
|
nkeynes@1 | 760 | break;
|
nkeynes@1 | 761 | case 0x26: /* LDS.L [Rn++], PR */
|
nkeynes@1 | 762 | sh4r.pr = MEM_READ_LONG( RN(ir) );
|
nkeynes@1 | 763 | RN(ir) += 4;
|
nkeynes@1 | 764 | break;
|
nkeynes@1 | 765 | case 0x27: /* LDC.L [Rn++], VBR */
|
nkeynes@1 | 766 | CHECKPRIV();
|
nkeynes@1 | 767 | sh4r.vbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 768 | RN(ir) +=4;
|
nkeynes@1 | 769 | break;
|
nkeynes@1 | 770 | case 0x28: /* SHLL16 Rn */
|
nkeynes@1 | 771 | RN(ir) <<= 16;
|
nkeynes@1 | 772 | break;
|
nkeynes@1 | 773 | case 0x29: /* SHLR16 Rn */
|
nkeynes@1 | 774 | RN(ir) >>= 16;
|
nkeynes@1 | 775 | break;
|
nkeynes@1 | 776 | case 0x2A: /* LDS Rn, PR */
|
nkeynes@1 | 777 | sh4r.pr = RN(ir);
|
nkeynes@1 | 778 | break;
|
nkeynes@1 | 779 | case 0x2B: /* JMP [Rn] */
|
nkeynes@1 | 780 | CHECKDEST( RN(ir) );
|
nkeynes@2 | 781 | CHECKSLOTILLEGAL();
|
nkeynes@2 | 782 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 783 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 784 | sh4r.new_pc = RN(ir);
|
nkeynes@27 | 785 | return TRUE;
|
nkeynes@1 | 786 | case 0x2E: /* LDC Rn, VBR */
|
nkeynes@1 | 787 | CHECKPRIV();
|
nkeynes@1 | 788 | sh4r.vbr = RN(ir);
|
nkeynes@1 | 789 | break;
|
nkeynes@1 | 790 | case 0x32: /* STC.L SGR, [--Rn] */
|
nkeynes@1 | 791 | CHECKPRIV();
|
nkeynes@1 | 792 | RN(ir) -= 4;
|
nkeynes@1 | 793 | MEM_WRITE_LONG( RN(ir), sh4r.sgr );
|
nkeynes@1 | 794 | break;
|
nkeynes@1 | 795 | case 0x33: /* STC.L SSR, [--Rn] */
|
nkeynes@1 | 796 | CHECKPRIV();
|
nkeynes@1 | 797 | RN(ir) -= 4;
|
nkeynes@1 | 798 | MEM_WRITE_LONG( RN(ir), sh4r.ssr );
|
nkeynes@1 | 799 | break;
|
nkeynes@1 | 800 | case 0x37: /* LDC.L [Rn++], SSR */
|
nkeynes@1 | 801 | CHECKPRIV();
|
nkeynes@1 | 802 | sh4r.ssr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 803 | RN(ir) +=4;
|
nkeynes@1 | 804 | break;
|
nkeynes@1 | 805 | case 0x3E: /* LDC Rn, SSR */
|
nkeynes@1 | 806 | CHECKPRIV();
|
nkeynes@1 | 807 | sh4r.ssr = RN(ir);
|
nkeynes@1 | 808 | break;
|
nkeynes@1 | 809 | case 0x43: /* STC.L SPC, [--Rn] */
|
nkeynes@1 | 810 | CHECKPRIV();
|
nkeynes@1 | 811 | RN(ir) -= 4;
|
nkeynes@1 | 812 | MEM_WRITE_LONG( RN(ir), sh4r.spc );
|
nkeynes@1 | 813 | break;
|
nkeynes@1 | 814 | case 0x47: /* LDC.L [Rn++], SPC */
|
nkeynes@1 | 815 | CHECKPRIV();
|
nkeynes@1 | 816 | sh4r.spc = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 817 | RN(ir) +=4;
|
nkeynes@1 | 818 | break;
|
nkeynes@1 | 819 | case 0x4E: /* LDC Rn, SPC */
|
nkeynes@1 | 820 | CHECKPRIV();
|
nkeynes@1 | 821 | sh4r.spc = RN(ir);
|
nkeynes@1 | 822 | break;
|
nkeynes@1 | 823 | case 0x52: /* STS.L FPUL, [--Rn] */
|
nkeynes@1 | 824 | RN(ir) -= 4;
|
nkeynes@1 | 825 | MEM_WRITE_LONG( RN(ir), sh4r.fpul );
|
nkeynes@1 | 826 | break;
|
nkeynes@1 | 827 | case 0x56: /* LDS.L [Rn++], FPUL */
|
nkeynes@1 | 828 | sh4r.fpul = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 829 | RN(ir) +=4;
|
nkeynes@1 | 830 | break;
|
nkeynes@1 | 831 | case 0x5A: /* LDS Rn, FPUL */
|
nkeynes@1 | 832 | sh4r.fpul = RN(ir);
|
nkeynes@1 | 833 | break;
|
nkeynes@1 | 834 | case 0x62: /* STS.L FPSCR, [--Rn] */
|
nkeynes@1 | 835 | RN(ir) -= 4;
|
nkeynes@1 | 836 | MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
|
nkeynes@1 | 837 | break;
|
nkeynes@1 | 838 | case 0x66: /* LDS.L [Rn++], FPSCR */
|
nkeynes@1 | 839 | sh4r.fpscr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 840 | RN(ir) +=4;
|
nkeynes@1 | 841 | break;
|
nkeynes@1 | 842 | case 0x6A: /* LDS Rn, FPSCR */
|
nkeynes@1 | 843 | sh4r.fpscr = RN(ir);
|
nkeynes@1 | 844 | break;
|
nkeynes@1 | 845 | case 0xF2: /* STC.L DBR, [--Rn] */
|
nkeynes@1 | 846 | CHECKPRIV();
|
nkeynes@1 | 847 | RN(ir) -= 4;
|
nkeynes@1 | 848 | MEM_WRITE_LONG( RN(ir), sh4r.dbr );
|
nkeynes@1 | 849 | break;
|
nkeynes@1 | 850 | case 0xF6: /* LDC.L [Rn++], DBR */
|
nkeynes@1 | 851 | CHECKPRIV();
|
nkeynes@1 | 852 | sh4r.dbr = MEM_READ_LONG(RN(ir));
|
nkeynes@1 | 853 | RN(ir) +=4;
|
nkeynes@1 | 854 | break;
|
nkeynes@1 | 855 | case 0xFA: /* LDC Rn, DBR */
|
nkeynes@1 | 856 | CHECKPRIV();
|
nkeynes@1 | 857 | sh4r.dbr = RN(ir);
|
nkeynes@1 | 858 | break;
|
nkeynes@1 | 859 | case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
|
nkeynes@1 | 860 | case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
|
nkeynes@1 | 861 | CHECKPRIV();
|
nkeynes@1 | 862 | RN(ir) -= 4;
|
nkeynes@1 | 863 | MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
|
nkeynes@1 | 864 | break;
|
nkeynes@1 | 865 | case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
|
nkeynes@1 | 866 | case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
|
nkeynes@1 | 867 | CHECKPRIV();
|
nkeynes@1 | 868 | RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
|
nkeynes@1 | 869 | RN(ir) += 4;
|
nkeynes@1 | 870 | break;
|
nkeynes@1 | 871 | case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
|
nkeynes@1 | 872 | case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
|
nkeynes@1 | 873 | CHECKPRIV();
|
nkeynes@1 | 874 | RN_BANK(ir) = RM(ir);
|
nkeynes@1 | 875 | break;
|
nkeynes@1 | 876 | default:
|
nkeynes@1 | 877 | if( (ir&0x000F) == 0x0F ) {
|
nkeynes@1 | 878 | /* MAC.W [Rm++], [Rn++] */
|
nkeynes@1 | 879 | tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
|
nkeynes@1 | 880 | SIGNEXT16(MEM_READ_WORD(RN(ir)));
|
nkeynes@1 | 881 | if( sh4r.s ) {
|
nkeynes@1 | 882 | /* FIXME */
|
nkeynes@1 | 883 | UNIMP(ir);
|
nkeynes@1 | 884 | } else sh4r.mac += SIGNEXT32(tmp);
|
nkeynes@1 | 885 | RM(ir) += 2;
|
nkeynes@1 | 886 | RN(ir) += 2;
|
nkeynes@1 | 887 | } else if( (ir&0x000F) == 0x0C ) {
|
nkeynes@1 | 888 | /* SHAD Rm, Rn */
|
nkeynes@1 | 889 | tmp = RM(ir);
|
nkeynes@1 | 890 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
|
nkeynes@9 | 891 | else if( (tmp & 0x1F) == 0 )
|
nkeynes@9 | 892 | RN(ir) = ((int32_t)RN(ir)) >> 31;
|
nkeynes@9 | 893 | else
|
nkeynes@9 | 894 | RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
|
nkeynes@1 | 895 | } else if( (ir&0x000F) == 0x0D ) {
|
nkeynes@1 | 896 | /* SHLD Rm, Rn */
|
nkeynes@1 | 897 | tmp = RM(ir);
|
nkeynes@1 | 898 | if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
|
nkeynes@1 | 899 | else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
|
nkeynes@1 | 900 | else RN(ir) >>= (((~tmp) & 0x1F)+1);
|
nkeynes@1 | 901 | } else UNDEF(ir);
|
nkeynes@1 | 902 | }
|
nkeynes@1 | 903 | break;
|
nkeynes@1 | 904 | case 5: /* 0101nnnnmmmmdddd */
|
nkeynes@1 | 905 | /* MOV.L [Rm + disp4*4], Rn */
|
nkeynes@1 | 906 | RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
|
nkeynes@1 | 907 | break;
|
nkeynes@1 | 908 | case 6: /* 0110xxxxxxxxxxxx */
|
nkeynes@1 | 909 | switch( ir&0x000f ) {
|
nkeynes@1 | 910 | case 0: /* MOV.B [Rm], Rn */
|
nkeynes@1 | 911 | RN(ir) = MEM_READ_BYTE( RM(ir) );
|
nkeynes@1 | 912 | break;
|
nkeynes@1 | 913 | case 1: /* MOV.W [Rm], Rn */
|
nkeynes@1 | 914 | RN(ir) = MEM_READ_WORD( RM(ir) );
|
nkeynes@1 | 915 | break;
|
nkeynes@1 | 916 | case 2: /* MOV.L [Rm], Rn */
|
nkeynes@1 | 917 | RN(ir) = MEM_READ_LONG( RM(ir) );
|
nkeynes@1 | 918 | break;
|
nkeynes@1 | 919 | case 3: /* MOV Rm, Rn */
|
nkeynes@1 | 920 | RN(ir) = RM(ir);
|
nkeynes@1 | 921 | break;
|
nkeynes@1 | 922 | case 4: /* MOV.B [Rm++], Rn */
|
nkeynes@1 | 923 | RN(ir) = MEM_READ_BYTE( RM(ir) );
|
nkeynes@1 | 924 | RM(ir) ++;
|
nkeynes@1 | 925 | break;
|
nkeynes@1 | 926 | case 5: /* MOV.W [Rm++], Rn */
|
nkeynes@1 | 927 | RN(ir) = MEM_READ_WORD( RM(ir) );
|
nkeynes@1 | 928 | RM(ir) += 2;
|
nkeynes@1 | 929 | break;
|
nkeynes@1 | 930 | case 6: /* MOV.L [Rm++], Rn */
|
nkeynes@1 | 931 | RN(ir) = MEM_READ_LONG( RM(ir) );
|
nkeynes@1 | 932 | RM(ir) += 4;
|
nkeynes@1 | 933 | break;
|
nkeynes@1 | 934 | case 7: /* NOT Rm, Rn */
|
nkeynes@1 | 935 | RN(ir) = ~RM(ir);
|
nkeynes@1 | 936 | break;
|
nkeynes@1 | 937 | case 8: /* SWAP.B Rm, Rn */
|
nkeynes@1 | 938 | RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
|
nkeynes@1 | 939 | ((RM(ir)&0x000000FF)<<8);
|
nkeynes@1 | 940 | break;
|
nkeynes@1 | 941 | case 9: /* SWAP.W Rm, Rn */
|
nkeynes@1 | 942 | RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
|
nkeynes@1 | 943 | break;
|
nkeynes@1 | 944 | case 10:/* NEGC Rm, Rn */
|
nkeynes@1 | 945 | tmp = 0 - RM(ir);
|
nkeynes@1 | 946 | RN(ir) = tmp - sh4r.t;
|
nkeynes@1 | 947 | sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
|
nkeynes@1 | 948 | break;
|
nkeynes@1 | 949 | case 11:/* NEG Rm, Rn */
|
nkeynes@1 | 950 | RN(ir) = 0 - RM(ir);
|
nkeynes@1 | 951 | break;
|
nkeynes@1 | 952 | case 12:/* EXTU.B Rm, Rn */
|
nkeynes@1 | 953 | RN(ir) = RM(ir)&0x000000FF;
|
nkeynes@1 | 954 | break;
|
nkeynes@1 | 955 | case 13:/* EXTU.W Rm, Rn */
|
nkeynes@1 | 956 | RN(ir) = RM(ir)&0x0000FFFF;
|
nkeynes@1 | 957 | break;
|
nkeynes@1 | 958 | case 14:/* EXTS.B Rm, Rn */
|
nkeynes@1 | 959 | RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
|
nkeynes@1 | 960 | break;
|
nkeynes@1 | 961 | case 15:/* EXTS.W Rm, Rn */
|
nkeynes@1 | 962 | RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
|
nkeynes@1 | 963 | break;
|
nkeynes@1 | 964 | }
|
nkeynes@1 | 965 | break;
|
nkeynes@1 | 966 | case 7: /* 0111nnnniiiiiiii */
|
nkeynes@1 | 967 | /* ADD imm8, Rn */
|
nkeynes@1 | 968 | RN(ir) += IMM8(ir);
|
nkeynes@1 | 969 | break;
|
nkeynes@1 | 970 | case 8: /* 1000xxxxxxxxxxxx */
|
nkeynes@1 | 971 | switch( (ir&0x0F00) >> 8 ) {
|
nkeynes@1 | 972 | case 0: /* MOV.B R0, [Rm + disp4] */
|
nkeynes@1 | 973 | MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
|
nkeynes@1 | 974 | break;
|
nkeynes@1 | 975 | case 1: /* MOV.W R0, [Rm + disp4*2] */
|
nkeynes@1 | 976 | MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
|
nkeynes@1 | 977 | break;
|
nkeynes@1 | 978 | case 4: /* MOV.B [Rm + disp4], R0 */
|
nkeynes@1 | 979 | R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
|
nkeynes@1 | 980 | break;
|
nkeynes@1 | 981 | case 5: /* MOV.W [Rm + disp4*2], R0 */
|
nkeynes@1 | 982 | R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
|
nkeynes@1 | 983 | break;
|
nkeynes@1 | 984 | case 8: /* CMP/EQ imm, R0 */
|
nkeynes@1 | 985 | sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
|
nkeynes@1 | 986 | break;
|
nkeynes@1 | 987 | case 9: /* BT disp8 */
|
nkeynes@2 | 988 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 989 | if( sh4r.t ) {
|
nkeynes@1 | 990 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@1 | 991 | sh4r.pc += (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 992 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@27 | 993 | return TRUE;
|
nkeynes@1 | 994 | }
|
nkeynes@1 | 995 | break;
|
nkeynes@1 | 996 | case 11:/* BF disp8 */
|
nkeynes@2 | 997 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 998 | if( !sh4r.t ) {
|
nkeynes@1 | 999 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@1 | 1000 | sh4r.pc += (PCDISP8(ir)<<1) + 4;
|
nkeynes@1 | 1001 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@27 | 1002 | return TRUE;
|
nkeynes@1 | 1003 | }
|
nkeynes@1 | 1004 | break;
|
nkeynes@1 | 1005 | case 13:/* BT/S disp8 */
|
nkeynes@2 | 1006 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1007 | if( sh4r.t ) {
|
nkeynes@1 | 1008 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@2 | 1009 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1010 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1011 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
|
nkeynes@2 | 1012 | sh4r.in_delay_slot = 1;
|
nkeynes@27 | 1013 | return TRUE;
|
nkeynes@1 | 1014 | }
|
nkeynes@1 | 1015 | break;
|
nkeynes@1 | 1016 | case 15:/* BF/S disp8 */
|
nkeynes@2 | 1017 | CHECKSLOTILLEGAL()
|
nkeynes@1 | 1018 | if( !sh4r.t ) {
|
nkeynes@1 | 1019 | CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
|
nkeynes@2 | 1020 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1021 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1022 | sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
|
nkeynes@27 | 1023 | return TRUE;
|
nkeynes@1 | 1024 | }
|
nkeynes@1 | 1025 | break;
|
nkeynes@1 | 1026 | default: UNDEF(ir);
|
nkeynes@1 | 1027 | }
|
nkeynes@1 | 1028 | break;
|
nkeynes@1 | 1029 | case 9: /* 1001xxxxxxxxxxxx */
|
nkeynes@1 | 1030 | /* MOV.W [disp8*2 + pc + 4], Rn */
|
nkeynes@1 | 1031 | RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
|
nkeynes@1 | 1032 | break;
|
nkeynes@1 | 1033 | case 10:/* 1010dddddddddddd */
|
nkeynes@1 | 1034 | /* BRA disp12 */
|
nkeynes@2 | 1035 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
|
nkeynes@2 | 1036 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1037 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1038 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1039 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
|
nkeynes@27 | 1040 | return TRUE;
|
nkeynes@1 | 1041 | case 11:/* 1011dddddddddddd */
|
nkeynes@1 | 1042 | /* BSR disp12 */
|
nkeynes@1 | 1043 | CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
|
nkeynes@2 | 1044 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1045 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1046 | sh4r.pr = pc + 4;
|
nkeynes@1 | 1047 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1048 | sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
|
nkeynes@27 | 1049 | return TRUE;
|
nkeynes@1 | 1050 | case 12:/* 1100xxxxdddddddd */
|
nkeynes@1 | 1051 | switch( (ir&0x0F00)>>8 ) {
|
nkeynes@1 | 1052 | case 0: /* MOV.B R0, [GBR + disp8] */
|
nkeynes@1 | 1053 | MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
|
nkeynes@1 | 1054 | break;
|
nkeynes@1 | 1055 | case 1: /* MOV.W R0, [GBR + disp8*2] */
|
nkeynes@1 | 1056 | MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
|
nkeynes@1 | 1057 | break;
|
nkeynes@1 | 1058 | case 2: /*MOV.L R0, [GBR + disp8*4] */
|
nkeynes@1 | 1059 | MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
|
nkeynes@1 | 1060 | break;
|
nkeynes@1 | 1061 | case 3: /* TRAPA imm8 */
|
nkeynes@2 | 1062 | CHECKSLOTILLEGAL()
|
nkeynes@2 | 1063 | sh4r.in_delay_slot = 1;
|
nkeynes@1 | 1064 | MMIO_WRITE( MMU, TRA, UIMM8(ir) );
|
nkeynes@1 | 1065 | sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
|
nkeynes@1 | 1066 | sh4r.new_pc += 2;
|
nkeynes@1 | 1067 | RAISE( EXC_TRAP, EXV_TRAP );
|
nkeynes@1 | 1068 | break;
|
nkeynes@1 | 1069 | case 4: /* MOV.B [GBR + disp8], R0 */
|
nkeynes@1 | 1070 | R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
|
nkeynes@1 | 1071 | break;
|
nkeynes@1 | 1072 | case 5: /* MOV.W [GBR + disp8*2], R0 */
|
nkeynes@1 | 1073 | R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
|
nkeynes@1 | 1074 | break;
|
nkeynes@1 | 1075 | case 6: /* MOV.L [GBR + disp8*4], R0 */
|
nkeynes@1 | 1076 | R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
|
nkeynes@1 | 1077 | break;
|
nkeynes@1 | 1078 | case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
|
nkeynes@1 | 1079 | R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
|
nkeynes@1 | 1080 | break;
|
nkeynes@1 | 1081 | case 8: /* TST imm8, R0 */
|
nkeynes@1 | 1082 | sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
|
nkeynes@1 | 1083 | break;
|
nkeynes@1 | 1084 | case 9: /* AND imm8, R0 */
|
nkeynes@1 | 1085 | R0 &= UIMM8(ir);
|
nkeynes@1 | 1086 | break;
|
nkeynes@1 | 1087 | case 10:/* XOR imm8, R0 */
|
nkeynes@1 | 1088 | R0 ^= UIMM8(ir);
|
nkeynes@1 | 1089 | break;
|
nkeynes@1 | 1090 | case 11:/* OR imm8, R0 */
|
nkeynes@1 | 1091 | R0 |= UIMM8(ir);
|
nkeynes@1 | 1092 | break;
|
nkeynes@1 | 1093 | case 12:/* TST.B imm8, [R0+GBR] */
|
nkeynes@1 | 1094 | sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
|
nkeynes@1 | 1095 | break;
|
nkeynes@1 | 1096 | case 13:/* AND.B imm8, [R0+GBR] */
|
nkeynes@1 | 1097 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1098 | UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1099 | break;
|
nkeynes@1 | 1100 | case 14:/* XOR.B imm8, [R0+GBR] */
|
nkeynes@1 | 1101 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1102 | UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1103 | break;
|
nkeynes@1 | 1104 | case 15:/* OR.B imm8, [R0+GBR] */
|
nkeynes@1 | 1105 | MEM_WRITE_BYTE( R0 + sh4r.gbr,
|
nkeynes@1 | 1106 | UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
|
nkeynes@1 | 1107 | break;
|
nkeynes@1 | 1108 | }
|
nkeynes@1 | 1109 | break;
|
nkeynes@1 | 1110 | case 13:/* 1101nnnndddddddd */
|
nkeynes@1 | 1111 | /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
|
nkeynes@1 | 1112 | RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
|
nkeynes@1 | 1113 | break;
|
nkeynes@1 | 1114 | case 14:/* 1110nnnniiiiiiii */
|
nkeynes@1 | 1115 | /* MOV imm8, Rn */
|
nkeynes@1 | 1116 | RN(ir) = IMM8(ir);
|
nkeynes@1 | 1117 | break;
|
nkeynes@1 | 1118 | case 15:/* 1111xxxxxxxxxxxx */
|
nkeynes@1 | 1119 | CHECKFPUEN();
|
nkeynes@1 | 1120 | switch( ir&0x000F ) {
|
nkeynes@1 | 1121 | case 0: /* FADD FRm, FRn */
|
nkeynes@1 | 1122 | FRN(ir) += FRM(ir);
|
nkeynes@1 | 1123 | break;
|
nkeynes@1 | 1124 | case 1: /* FSUB FRm, FRn */
|
nkeynes@1 | 1125 | FRN(ir) -= FRM(ir);
|
nkeynes@1 | 1126 | break;
|
nkeynes@1 | 1127 | case 2: /* FMUL FRm, FRn */
|
nkeynes@1 | 1128 | FRN(ir) = FRN(ir) * FRM(ir);
|
nkeynes@1 | 1129 | break;
|
nkeynes@1 | 1130 | case 3: /* FDIV FRm, FRn */
|
nkeynes@1 | 1131 | FRN(ir) = FRN(ir) / FRM(ir);
|
nkeynes@1 | 1132 | break;
|
nkeynes@1 | 1133 | case 4: /* FCMP/EQ FRm, FRn */
|
nkeynes@1 | 1134 | sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
|
nkeynes@1 | 1135 | break;
|
nkeynes@1 | 1136 | case 5: /* FCMP/GT FRm, FRn */
|
nkeynes@1 | 1137 | sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
|
nkeynes@1 | 1138 | break;
|
nkeynes@1 | 1139 | case 6: /* FMOV.S [Rm+R0], FRn */
|
nkeynes@1 | 1140 | MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
|
nkeynes@1 | 1141 | break;
|
nkeynes@1 | 1142 | case 7: /* FMOV.S FRm, [Rn+R0] */
|
nkeynes@1 | 1143 | MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
|
nkeynes@1 | 1144 | break;
|
nkeynes@1 | 1145 | case 8: /* FMOV.S [Rm], FRn */
|
nkeynes@1 | 1146 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@1 | 1147 | break;
|
nkeynes@1 | 1148 | case 9: /* FMOV.S [Rm++], FRn */
|
nkeynes@1 | 1149 | MEM_FP_READ( RM(ir), FRNn(ir) );
|
nkeynes@1 | 1150 | RM(ir) += FP_WIDTH;
|
nkeynes@1 | 1151 | break;
|
nkeynes@1 | 1152 | case 10:/* FMOV.S FRm, [Rn] */
|
nkeynes@1 | 1153 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@1 | 1154 | break;
|
nkeynes@1 | 1155 | case 11:/* FMOV.S FRm, [--Rn] */
|
nkeynes@1 | 1156 | RN(ir) -= FP_WIDTH;
|
nkeynes@1 | 1157 | MEM_FP_WRITE( RN(ir), FRMn(ir) );
|
nkeynes@1 | 1158 | break;
|
nkeynes@1 | 1159 | case 12:/* FMOV FRm, FRn */
|
nkeynes@1 | 1160 | if( IS_FPU_DOUBLESIZE() ) {
|
nkeynes@1 | 1161 | DRN(ir) = DRM(ir);
|
nkeynes@1 | 1162 | } else {
|
nkeynes@1 | 1163 | FRN(ir) = FRM(ir);
|
nkeynes@1 | 1164 | }
|
nkeynes@1 | 1165 | break;
|
nkeynes@1 | 1166 | case 13:
|
nkeynes@1 | 1167 | switch( (ir&0x00F0) >> 4 ) {
|
nkeynes@1 | 1168 | case 0: /* FSTS FPUL, FRn */
|
nkeynes@1 | 1169 | FRN(ir) = FPULf;
|
nkeynes@1 | 1170 | break;
|
nkeynes@1 | 1171 | case 1: /* FLDS FRn, FPUL */
|
nkeynes@1 | 1172 | FPULf = FRN(ir);
|
nkeynes@1 | 1173 | break;
|
nkeynes@1 | 1174 | case 2: /* FLOAT FPUL, FRn */
|
nkeynes@1 | 1175 | FRN(ir) = (float)FPULi;
|
nkeynes@1 | 1176 | break;
|
nkeynes@1 | 1177 | case 3: /* FTRC FRn, FPUL */
|
nkeynes@1 | 1178 | FPULi = (uint32_t)FRN(ir);
|
nkeynes@1 | 1179 | /* FIXME: is this sufficient? */
|
nkeynes@1 | 1180 | break;
|
nkeynes@1 | 1181 | case 4: /* FNEG FRn */
|
nkeynes@1 | 1182 | FRN(ir) = -FRN(ir);
|
nkeynes@1 | 1183 | break;
|
nkeynes@1 | 1184 | case 5: /* FABS FRn */
|
nkeynes@1 | 1185 | FRN(ir) = fabsf(FRN(ir));
|
nkeynes@1 | 1186 | break;
|
nkeynes@1 | 1187 | case 6: /* FSQRT FRn */
|
nkeynes@1 | 1188 | FRN(ir) = sqrtf(FRN(ir));
|
nkeynes@1 | 1189 | break;
|
nkeynes@2 | 1190 | case 7: /* FSRRA FRn */
|
nkeynes@2 | 1191 | FRN(ir) = 1.0/sqrtf(FRN(ir));
|
nkeynes@2 | 1192 | break;
|
nkeynes@1 | 1193 | case 8: /* FLDI0 FRn */
|
nkeynes@1 | 1194 | FRN(ir) = 0.0;
|
nkeynes@1 | 1195 | break;
|
nkeynes@1 | 1196 | case 9: /* FLDI1 FRn */
|
nkeynes@1 | 1197 | FRN(ir) = 1.0;
|
nkeynes@1 | 1198 | break;
|
nkeynes@1 | 1199 | case 10: /* FCNVSD FPUL, DRn */
|
nkeynes@1 | 1200 | if( IS_FPU_DOUBLEPREC() )
|
nkeynes@1 | 1201 | DRN(ir) = (double)FPULf;
|
nkeynes@1 | 1202 | else UNDEF(ir);
|
nkeynes@1 | 1203 | break;
|
nkeynes@1 | 1204 | case 11: /* FCNVDS DRn, FPUL */
|
nkeynes@1 | 1205 | if( IS_FPU_DOUBLEPREC() )
|
nkeynes@1 | 1206 | FPULf = (float)DRN(ir);
|
nkeynes@1 | 1207 | else UNDEF(ir);
|
nkeynes@1 | 1208 | break;
|
nkeynes@2 | 1209 | case 14:/* FIPR FVm, FVn */
|
nkeynes@2 | 1210 | /* FIXME: This is not going to be entirely accurate
|
nkeynes@2 | 1211 | * as the SH4 instruction is less precise. Also
|
nkeynes@2 | 1212 | * need to check for 0s and infinities.
|
nkeynes@2 | 1213 | */
|
nkeynes@2 | 1214 | {
|
nkeynes@2 | 1215 | float *fr_bank = FR;
|
nkeynes@2 | 1216 | int tmp2 = FVN(ir);
|
nkeynes@2 | 1217 | tmp = FVM(ir);
|
nkeynes@2 | 1218 | fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
|
nkeynes@2 | 1219 | fr_bank[tmp+1]*fr_bank[tmp2+1] +
|
nkeynes@2 | 1220 | fr_bank[tmp+2]*fr_bank[tmp2+2] +
|
nkeynes@2 | 1221 | fr_bank[tmp+3]*fr_bank[tmp2+3];
|
nkeynes@1 | 1222 | break;
|
nkeynes@2 | 1223 | }
|
nkeynes@1 | 1224 | case 15:
|
nkeynes@2 | 1225 | if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
|
nkeynes@2 | 1226 | float *fvout = FR+FVN(ir);
|
nkeynes@2 | 1227 | float *xm = XF;
|
nkeynes@2 | 1228 | float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
|
nkeynes@2 | 1229 | fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
|
nkeynes@2 | 1230 | xm[8]*fv[2] + xm[12]*fv[3];
|
nkeynes@2 | 1231 | fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
|
nkeynes@2 | 1232 | xm[9]*fv[2] + xm[13]*fv[3];
|
nkeynes@2 | 1233 | fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
|
nkeynes@2 | 1234 | xm[10]*fv[2] + xm[14]*fv[3];
|
nkeynes@2 | 1235 | fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
|
nkeynes@2 | 1236 | xm[11]*fv[2] + xm[15]*fv[3];
|
nkeynes@2 | 1237 | break;
|
nkeynes@2 | 1238 | }
|
nkeynes@2 | 1239 | else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
|
nkeynes@2 | 1240 | float angle = (((float)(short)(FPULi>>16)) +
|
nkeynes@2 | 1241 | ((float)(FPULi&16)/65536.0)) *
|
nkeynes@2 | 1242 | 2 * M_PI;
|
nkeynes@2 | 1243 | int reg = FRNn(ir);
|
nkeynes@2 | 1244 | FR[reg] = sinf(angle);
|
nkeynes@2 | 1245 | FR[reg+1] = cosf(angle);
|
nkeynes@2 | 1246 | break;
|
nkeynes@2 | 1247 | }
|
nkeynes@2 | 1248 | else if( ir == 0xFBFD ) {
|
nkeynes@2 | 1249 | /* FRCHG */
|
nkeynes@1 | 1250 | sh4r.fpscr ^= FPSCR_FR;
|
nkeynes@2 | 1251 | break;
|
nkeynes@2 | 1252 | }
|
nkeynes@2 | 1253 | else if( ir == 0xF3FD ) {
|
nkeynes@2 | 1254 | /* FSCHG */
|
nkeynes@1 | 1255 | sh4r.fpscr ^= FPSCR_SZ;
|
nkeynes@2 | 1256 | break;
|
nkeynes@2 | 1257 | }
|
nkeynes@1 | 1258 | default: UNDEF(ir);
|
nkeynes@1 | 1259 | }
|
nkeynes@1 | 1260 | break;
|
nkeynes@1 | 1261 | case 14:/* FMAC FR0, FRm, FRn */
|
nkeynes@1 | 1262 | FRN(ir) += FRM(ir)*FR0;
|
nkeynes@1 | 1263 | break;
|
nkeynes@1 | 1264 | default: UNDEF(ir);
|
nkeynes@1 | 1265 | }
|
nkeynes@1 | 1266 | break;
|
nkeynes@1 | 1267 | }
|
nkeynes@1 | 1268 | sh4r.pc = sh4r.new_pc;
|
nkeynes@1 | 1269 | sh4r.new_pc += 2;
|
nkeynes@2 | 1270 | sh4r.in_delay_slot = 0;
|
nkeynes@1 | 1271 | }
|