nkeynes@31 | 1 | /**
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nkeynes@197 | 2 | * $Id: pvr2.c,v 1.31 2006-08-06 02:47:08 nkeynes Exp $
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nkeynes@31 | 3 | *
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nkeynes@133 | 4 | * PVR2 (Video) Core module implementation and MMIO registers.
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nkeynes@31 | 5 | *
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nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 7 | *
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nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 11 | * (at your option) any later version.
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nkeynes@31 | 12 | *
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nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 16 | * GNU General Public License for more details.
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nkeynes@31 | 17 | */
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nkeynes@35 | 18 | #define MODULE pvr2_module
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nkeynes@31 | 19 |
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nkeynes@1 | 20 | #include "dream.h"
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nkeynes@144 | 21 | #include "display.h"
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nkeynes@1 | 22 | #include "mem.h"
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nkeynes@1 | 23 | #include "asic.h"
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nkeynes@103 | 24 | #include "pvr2/pvr2.h"
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nkeynes@56 | 25 | #include "sh4/sh4core.h"
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nkeynes@1 | 26 | #define MMIO_IMPL
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nkeynes@103 | 27 | #include "pvr2/pvr2mmio.h"
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nkeynes@1 | 28 |
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nkeynes@1 | 29 | char *video_base;
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nkeynes@1 | 30 |
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nkeynes@133 | 31 | static void pvr2_init( void );
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nkeynes@133 | 32 | static void pvr2_reset( void );
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nkeynes@133 | 33 | static uint32_t pvr2_run_slice( uint32_t );
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nkeynes@133 | 34 | static void pvr2_save_state( FILE *f );
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nkeynes@133 | 35 | static int pvr2_load_state( FILE *f );
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nkeynes@133 | 36 |
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nkeynes@94 | 37 | void pvr2_display_frame( void );
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nkeynes@94 | 38 |
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nkeynes@161 | 39 | int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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nkeynes@161 | 40 |
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nkeynes@133 | 41 | struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
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nkeynes@133 | 42 | pvr2_run_slice, NULL,
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nkeynes@133 | 43 | pvr2_save_state, pvr2_load_state };
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nkeynes@133 | 44 |
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nkeynes@103 | 45 |
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nkeynes@144 | 46 | display_driver_t display_driver = NULL;
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nkeynes@15 | 47 |
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nkeynes@103 | 48 | struct video_timing {
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nkeynes@103 | 49 | int fields_per_second;
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nkeynes@103 | 50 | int total_lines;
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nkeynes@108 | 51 | int retrace_lines;
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nkeynes@103 | 52 | int line_time_ns;
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nkeynes@103 | 53 | };
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nkeynes@103 | 54 |
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nkeynes@133 | 55 | struct video_timing pal_timing = { 50, 625, 65, 32000 };
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nkeynes@108 | 56 | struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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nkeynes@103 | 57 |
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nkeynes@133 | 58 | struct pvr2_state {
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nkeynes@133 | 59 | uint32_t frame_count;
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nkeynes@133 | 60 | uint32_t line_count;
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nkeynes@133 | 61 | uint32_t line_remainder;
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nkeynes@133 | 62 | uint32_t irq_vpos1;
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nkeynes@133 | 63 | uint32_t irq_vpos2;
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nkeynes@133 | 64 | gboolean retrace;
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nkeynes@133 | 65 | struct video_timing timing;
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nkeynes@133 | 66 | } pvr2_state;
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nkeynes@15 | 67 |
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nkeynes@133 | 68 | struct video_buffer video_buffer[2];
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nkeynes@133 | 69 | int video_buffer_idx = 0;
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nkeynes@133 | 70 |
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nkeynes@133 | 71 | static void pvr2_init( void )
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nkeynes@1 | 72 | {
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nkeynes@1 | 73 | register_io_region( &mmio_region_PVR2 );
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nkeynes@85 | 74 | register_io_region( &mmio_region_PVR2PAL );
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nkeynes@56 | 75 | register_io_region( &mmio_region_PVR2TA );
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nkeynes@1 | 76 | video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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nkeynes@133 | 77 | texcache_init();
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nkeynes@133 | 78 | pvr2_reset();
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nkeynes@133 | 79 | }
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nkeynes@133 | 80 |
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nkeynes@133 | 81 | static void pvr2_reset( void )
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nkeynes@133 | 82 | {
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nkeynes@133 | 83 | pvr2_state.line_count = 0;
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nkeynes@133 | 84 | pvr2_state.line_remainder = 0;
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nkeynes@133 | 85 | pvr2_state.irq_vpos1 = 0;
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nkeynes@133 | 86 | pvr2_state.irq_vpos2 = 0;
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nkeynes@133 | 87 | pvr2_state.retrace = FALSE;
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nkeynes@133 | 88 | pvr2_state.timing = ntsc_timing;
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nkeynes@133 | 89 | video_buffer_idx = 0;
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nkeynes@133 | 90 |
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nkeynes@133 | 91 | pvr2_ta_init();
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nkeynes@107 | 92 | pvr2_render_init();
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nkeynes@133 | 93 | texcache_flush();
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nkeynes@133 | 94 | }
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nkeynes@133 | 95 |
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nkeynes@133 | 96 | static void pvr2_save_state( FILE *f )
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nkeynes@133 | 97 | {
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nkeynes@133 | 98 | fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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nkeynes@193 | 99 | pvr2_ta_save_state( f );
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nkeynes@133 | 100 | }
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nkeynes@133 | 101 |
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nkeynes@133 | 102 | static int pvr2_load_state( FILE *f )
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nkeynes@133 | 103 | {
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nkeynes@153 | 104 | if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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nkeynes@153 | 105 | return 1;
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nkeynes@193 | 106 | return pvr2_ta_load_state(f);
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nkeynes@133 | 107 | }
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nkeynes@133 | 108 |
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nkeynes@133 | 109 | static uint32_t pvr2_run_slice( uint32_t nanosecs )
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nkeynes@133 | 110 | {
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nkeynes@133 | 111 | pvr2_state.line_remainder += nanosecs;
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nkeynes@133 | 112 | while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
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nkeynes@133 | 113 | pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
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nkeynes@133 | 114 |
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nkeynes@133 | 115 | pvr2_state.line_count++;
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nkeynes@133 | 116 | if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
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nkeynes@133 | 117 | asic_event( EVENT_RETRACE );
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nkeynes@133 | 118 | pvr2_state.line_count = 0;
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nkeynes@133 | 119 | pvr2_state.retrace = TRUE;
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nkeynes@133 | 120 | }
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nkeynes@133 | 121 |
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nkeynes@133 | 122 | if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
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nkeynes@133 | 123 | asic_event( EVENT_SCANLINE1 );
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nkeynes@133 | 124 | }
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nkeynes@133 | 125 | if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
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nkeynes@133 | 126 | asic_event( EVENT_SCANLINE2 );
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nkeynes@133 | 127 | }
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nkeynes@133 | 128 |
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nkeynes@133 | 129 | if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
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nkeynes@133 | 130 | if( pvr2_state.retrace ) {
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nkeynes@133 | 131 | pvr2_display_frame();
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nkeynes@133 | 132 | pvr2_state.retrace = FALSE;
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nkeynes@133 | 133 | }
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nkeynes@133 | 134 | }
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nkeynes@133 | 135 | }
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nkeynes@133 | 136 | return nanosecs;
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nkeynes@133 | 137 | }
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nkeynes@133 | 138 |
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nkeynes@133 | 139 | int pvr2_get_frame_count()
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nkeynes@133 | 140 | {
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nkeynes@133 | 141 | return pvr2_state.frame_count;
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nkeynes@106 | 142 | }
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nkeynes@106 | 143 |
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nkeynes@103 | 144 | /**
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nkeynes@1 | 145 | * Display the next frame, copying the current contents of video ram to
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nkeynes@1 | 146 | * the window. If the video configuration has changed, first recompute the
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nkeynes@1 | 147 | * new frame size/depth.
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nkeynes@1 | 148 | */
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nkeynes@94 | 149 | void pvr2_display_frame( void )
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nkeynes@1 | 150 | {
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nkeynes@197 | 151 | uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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nkeynes@103 | 152 |
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nkeynes@197 | 153 | int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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nkeynes@197 | 154 | int dispmode = MMIO_READ( PVR2, DISP_MODE );
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nkeynes@197 | 155 | int vidcfg = MMIO_READ( PVR2, DISP_CFG );
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nkeynes@94 | 156 | int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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nkeynes@94 | 157 | int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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nkeynes@94 | 158 | int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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nkeynes@103 | 159 | gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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nkeynes@103 | 160 | gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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nkeynes@161 | 161 | video_buffer_t buffer = &video_buffer[video_buffer_idx];
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nkeynes@161 | 162 | video_buffer_idx = !video_buffer_idx;
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nkeynes@161 | 163 | video_buffer_t last = &video_buffer[video_buffer_idx];
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nkeynes@161 | 164 | buffer->rowstride = (vid_ppl + vid_stride) << 2;
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nkeynes@197 | 165 | buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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nkeynes@161 | 166 | buffer->vres = vid_lpf;
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nkeynes@161 | 167 | if( interlaced ) buffer->vres <<= 1;
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nkeynes@161 | 168 | switch( (dispmode & DISPMODE_COL) >> 2 ) {
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nkeynes@161 | 169 | case 0:
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nkeynes@161 | 170 | buffer->colour_format = COLFMT_ARGB1555;
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nkeynes@161 | 171 | buffer->hres = vid_ppl << 1;
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nkeynes@161 | 172 | break;
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nkeynes@161 | 173 | case 1:
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nkeynes@161 | 174 | buffer->colour_format = COLFMT_RGB565;
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nkeynes@161 | 175 | buffer->hres = vid_ppl << 1;
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nkeynes@161 | 176 | break;
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nkeynes@161 | 177 | case 2:
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nkeynes@161 | 178 | buffer->colour_format = COLFMT_RGB888;
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nkeynes@161 | 179 | buffer->hres = (vid_ppl << 2) / 3;
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nkeynes@161 | 180 | break;
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nkeynes@161 | 181 | case 3:
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nkeynes@161 | 182 | buffer->colour_format = COLFMT_ARGB8888;
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nkeynes@161 | 183 | buffer->hres = vid_ppl;
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nkeynes@161 | 184 | break;
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nkeynes@161 | 185 | }
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nkeynes@161 | 186 |
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nkeynes@161 | 187 | if( buffer->hres <=8 )
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nkeynes@161 | 188 | buffer->hres = 640;
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nkeynes@161 | 189 | if( buffer->vres <=8 )
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nkeynes@161 | 190 | buffer->vres = 480;
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nkeynes@161 | 191 | if( display_driver != NULL ) {
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nkeynes@161 | 192 | if( buffer->hres != last->hres ||
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nkeynes@161 | 193 | buffer->vres != last->vres ||
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nkeynes@161 | 194 | buffer->colour_format != last->colour_format) {
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nkeynes@161 | 195 | display_driver->set_display_format( buffer->hres, buffer->vres,
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nkeynes@161 | 196 | buffer->colour_format );
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nkeynes@94 | 197 | }
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nkeynes@161 | 198 | if( !bEnabled ) {
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nkeynes@161 | 199 | display_driver->display_blank_frame( 0 );
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nkeynes@197 | 200 | } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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nkeynes@197 | 201 | uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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nkeynes@161 | 202 | display_driver->display_blank_frame( colour );
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nkeynes@161 | 203 | } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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nkeynes@161 | 204 | display_driver->display_frame( buffer );
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nkeynes@65 | 205 | }
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nkeynes@1 | 206 | }
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nkeynes@133 | 207 | pvr2_state.frame_count++;
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nkeynes@1 | 208 | }
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nkeynes@1 | 209 |
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nkeynes@197 | 210 | /**
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nkeynes@197 | 211 | * This has to handle every single register individually as they all get masked
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nkeynes@197 | 212 | * off differently (and its easier to do it at write time)
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nkeynes@197 | 213 | */
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nkeynes@1 | 214 | void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 215 | {
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nkeynes@1 | 216 | if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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nkeynes@1 | 217 | MMIO_WRITE( PVR2, reg, val );
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nkeynes@1 | 218 | return;
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nkeynes@1 | 219 | }
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nkeynes@1 | 220 |
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nkeynes@1 | 221 | switch(reg) {
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nkeynes@189 | 222 | case PVRID:
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nkeynes@189 | 223 | case PVRVER:
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nkeynes@189 | 224 | case GUNPOS:
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nkeynes@189 | 225 | case TA_POLYPOS:
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nkeynes@189 | 226 | case TA_LISTPOS:
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nkeynes@189 | 227 | /* Readonly registers */
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nkeynes@189 | 228 | break;
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nkeynes@197 | 229 | case PVRRESET:
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nkeynes@197 | 230 | val &= 0x00000007; /* Do stuff? */
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nkeynes@197 | 231 | MMIO_WRITE( PVR2, reg, val );
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nkeynes@197 | 232 | break;
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nkeynes@191 | 233 | case RENDER_START:
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nkeynes@189 | 234 | if( val == 0xFFFFFFFF )
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nkeynes@189 | 235 | pvr2_render_scene();
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nkeynes@189 | 236 | break;
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nkeynes@191 | 237 | case PVRUNK1:
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nkeynes@191 | 238 | MMIO_WRITE( PVR2, reg, val&0x000007FF );
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nkeynes@191 | 239 | break;
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nkeynes@191 | 240 | case RENDER_POLYBASE:
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nkeynes@191 | 241 | MMIO_WRITE( PVR2, reg, val&0x00F00000 );
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nkeynes@191 | 242 | break;
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nkeynes@191 | 243 | case RENDER_TSPCFG:
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nkeynes@191 | 244 | MMIO_WRITE( PVR2, reg, val&0x00010101 );
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nkeynes@191 | 245 | break;
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nkeynes@197 | 246 | case DISP_BORDER:
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nkeynes@191 | 247 | MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
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nkeynes@191 | 248 | break;
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nkeynes@197 | 249 | case DISP_MODE:
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nkeynes@191 | 250 | MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
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nkeynes@191 | 251 | break;
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nkeynes@191 | 252 | case RENDER_MODE:
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nkeynes@191 | 253 | MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
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nkeynes@191 | 254 | break;
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nkeynes@191 | 255 | case RENDER_SIZE:
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nkeynes@191 | 256 | MMIO_WRITE( PVR2, reg, val&0x000001FF );
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nkeynes@191 | 257 | break;
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nkeynes@197 | 258 | case DISP_ADDR1:
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nkeynes@189 | 259 | val &= 0x00FFFFFC;
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nkeynes@189 | 260 | MMIO_WRITE( PVR2, reg, val );
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nkeynes@133 | 261 | if( pvr2_state.retrace ) {
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nkeynes@108 | 262 | pvr2_display_frame();
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nkeynes@133 | 263 | pvr2_state.retrace = FALSE;
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nkeynes@108 | 264 | }
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nkeynes@108 | 265 | break;
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nkeynes@197 | 266 | case DISP_ADDR2:
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nkeynes@191 | 267 | MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
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nkeynes@191 | 268 | break;
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nkeynes@197 | 269 | case DISP_SIZE:
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nkeynes@191 | 270 | MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
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nkeynes@191 | 271 | break;
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nkeynes@191 | 272 | case RENDER_ADDR1:
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nkeynes@191 | 273 | case RENDER_ADDR2:
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nkeynes@191 | 274 | MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
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nkeynes@191 | 275 | break;
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nkeynes@191 | 276 | case RENDER_HCLIP:
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nkeynes@191 | 277 | MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
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nkeynes@189 | 278 | break;
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nkeynes@191 | 279 | case RENDER_VCLIP:
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nkeynes@191 | 280 | MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
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nkeynes@189 | 281 | break;
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nkeynes@197 | 282 | case DISP_HPOSIRQ:
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nkeynes@191 | 283 | MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
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nkeynes@189 | 284 | break;
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nkeynes@197 | 285 | case DISP_VPOSIRQ:
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nkeynes@189 | 286 | val = val & 0x03FF03FF;
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nkeynes@189 | 287 | pvr2_state.irq_vpos1 = (val >> 16);
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nkeynes@133 | 288 | pvr2_state.irq_vpos2 = val & 0x03FF;
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nkeynes@189 | 289 | MMIO_WRITE( PVR2, reg, val );
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nkeynes@103 | 290 | break;
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nkeynes@197 | 291 | case RENDER_NEARCLIP:
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nkeynes@197 | 292 | MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
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nkeynes@197 | 293 | break;
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nkeynes@191 | 294 | case RENDER_SHADOW:
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nkeynes@191 | 295 | MMIO_WRITE( PVR2, reg, val&0x000001FF );
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nkeynes@191 | 296 | break;
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nkeynes@191 | 297 | case RENDER_OBJCFG:
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nkeynes@191 | 298 | MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
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nkeynes@191 | 299 | break;
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nkeynes@197 | 300 | case PVRUNK2:
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nkeynes@197 | 301 | MMIO_WRITE( PVR2, reg, val&0x00000007 );
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nkeynes@197 | 302 | break;
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nkeynes@191 | 303 | case RENDER_TSPCLIP:
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nkeynes@191 | 304 | MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
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nkeynes@191 | 305 | break;
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nkeynes@197 | 306 | case RENDER_FARCLIP:
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nkeynes@197 | 307 | MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
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nkeynes@197 | 308 | break;
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nkeynes@191 | 309 | case RENDER_BGPLANE:
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nkeynes@191 | 310 | MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
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nkeynes@191 | 311 | break;
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nkeynes@191 | 312 | case RENDER_ISPCFG:
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nkeynes@191 | 313 | MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
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nkeynes@191 | 314 | break;
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nkeynes@197 | 315 | case VRAM_CFG1:
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nkeynes@197 | 316 | MMIO_WRITE( PVR2, reg, val&0x000000FF );
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nkeynes@197 | 317 | break;
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nkeynes@197 | 318 | case VRAM_CFG2:
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nkeynes@197 | 319 | MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
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nkeynes@197 | 320 | break;
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nkeynes@197 | 321 | case VRAM_CFG3:
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nkeynes@197 | 322 | MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
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nkeynes@197 | 323 | break;
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nkeynes@197 | 324 | case RENDER_FOGTBLCOL:
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nkeynes@197 | 325 | case RENDER_FOGVRTCOL:
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nkeynes@197 | 326 | MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
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nkeynes@197 | 327 | break;
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nkeynes@197 | 328 | case RENDER_FOGCOEFF:
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nkeynes@197 | 329 | MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
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nkeynes@197 | 330 | break;
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nkeynes@197 | 331 | case RENDER_CLAMPHI:
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nkeynes@197 | 332 | case RENDER_CLAMPLO:
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nkeynes@197 | 333 | MMIO_WRITE( PVR2, reg, val );
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nkeynes@197 | 334 | break;
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nkeynes@197 | 335 | case DISP_CFG:
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nkeynes@197 | 336 | MMIO_WRITE( PVR2, reg, val&0x000003FF );
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nkeynes@197 | 337 | break;
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nkeynes@197 | 338 | case DISP_HBORDER:
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nkeynes@197 | 339 | case DISP_SYNC:
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nkeynes@197 | 340 | case DISP_VBORDER:
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nkeynes@197 | 341 | MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
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nkeynes@197 | 342 | break;
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nkeynes@197 | 343 | case DISP_SYNC2:
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nkeynes@197 | 344 | MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
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nkeynes@197 | 345 | break;
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nkeynes@197 | 346 | case RENDER_TEXSIZE:
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nkeynes@197 | 347 | MMIO_WRITE( PVR2, reg, val&0x00031F1F );
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nkeynes@197 | 348 | break;
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nkeynes@197 | 349 | case DISP_CFG2:
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nkeynes@197 | 350 | MMIO_WRITE( PVR2, reg, val&0x003F01FF );
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nkeynes@197 | 351 | break;
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nkeynes@197 | 352 | case DISP_HPOS:
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nkeynes@197 | 353 | MMIO_WRITE( PVR2, reg, val&0x000003FF );
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nkeynes@197 | 354 | break;
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nkeynes@197 | 355 | case DISP_VPOS:
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nkeynes@197 | 356 | MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
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nkeynes@197 | 357 | break;
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nkeynes@197 | 358 | case SCALERCFG:
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nkeynes@197 | 359 | MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
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nkeynes@197 | 360 | break;
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nkeynes@197 | 361 | case RENDER_PALETTE:
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nkeynes@197 | 362 | MMIO_WRITE( PVR2, reg, val&0x00000003 );
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nkeynes@197 | 363 | break;
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nkeynes@197 | 364 | case PVRUNK3:
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nkeynes@197 | 365 | MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
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nkeynes@197 | 366 | break;
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nkeynes@197 | 367 | case PVRUNK5:
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nkeynes@197 | 368 | MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
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nkeynes@197 | 369 | break;
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nkeynes@197 | 370 | case PVRUNK6:
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nkeynes@197 | 371 | MMIO_WRITE( PVR2, reg, val&0x000000FF );
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nkeynes@197 | 372 | break;
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nkeynes@189 | 373 | case TA_TILEBASE:
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nkeynes@193 | 374 | case TA_LISTEND:
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nkeynes@189 | 375 | case TA_LISTBASE:
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nkeynes@191 | 376 | MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
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nkeynes@189 | 377 | break;
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nkeynes@191 | 378 | case RENDER_TILEBASE:
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nkeynes@189 | 379 | case TA_POLYBASE:
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nkeynes@189 | 380 | case TA_POLYEND:
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nkeynes@191 | 381 | MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
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nkeynes@189 | 382 | break;
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nkeynes@189 | 383 | case TA_TILESIZE:
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nkeynes@191 | 384 | MMIO_WRITE( PVR2, reg, val&0x000F003F );
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nkeynes@189 | 385 | break;
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nkeynes@189 | 386 | case TA_TILECFG:
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nkeynes@191 | 387 | MMIO_WRITE( PVR2, reg, val&0x00133333 );
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nkeynes@189 | 388 | break;
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nkeynes@197 | 389 | case YUV_ADDR:
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nkeynes@197 | 390 | MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
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nkeynes@197 | 391 | break;
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nkeynes@197 | 392 | case YUV_CFG:
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nkeynes@197 | 393 | MMIO_WRITE( PVR2, reg, val&0x01013F3F );
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nkeynes@197 | 394 | break;
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nkeynes@189 | 395 | case TA_INIT:
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nkeynes@100 | 396 | if( val & 0x80000000 )
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nkeynes@100 | 397 | pvr2_ta_init();
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nkeynes@100 | 398 | break;
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nkeynes@197 | 399 | case TA_REINIT:
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nkeynes@197 | 400 | break;
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nkeynes@197 | 401 | case PVRUNK7:
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nkeynes@197 | 402 | MMIO_WRITE( PVR2, reg, val&0x00000001 );
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nkeynes@197 | 403 | break;
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nkeynes@1 | 404 | }
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nkeynes@1 | 405 | }
|
nkeynes@1 | 406 |
|
nkeynes@1 | 407 | MMIO_REGION_READ_FN( PVR2, reg )
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nkeynes@1 | 408 | {
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nkeynes@1 | 409 | switch( reg ) {
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nkeynes@197 | 410 | case DISP_BEAMPOS:
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nkeynes@2 | 411 | return sh4r.icount&0x20 ? 0x2000 : 1;
|
nkeynes@1 | 412 | default:
|
nkeynes@1 | 413 | return MMIO_READ( PVR2, reg );
|
nkeynes@1 | 414 | }
|
nkeynes@1 | 415 | }
|
nkeynes@19 | 416 |
|
nkeynes@85 | 417 | MMIO_REGION_DEFFNS( PVR2PAL )
|
nkeynes@85 | 418 |
|
nkeynes@19 | 419 | void pvr2_set_base_address( uint32_t base )
|
nkeynes@19 | 420 | {
|
nkeynes@197 | 421 | mmio_region_PVR2_write( DISP_ADDR1, base );
|
nkeynes@19 | 422 | }
|
nkeynes@56 | 423 |
|
nkeynes@56 | 424 |
|
nkeynes@65 | 425 |
|
nkeynes@98 | 426 |
|
nkeynes@56 | 427 | int32_t mmio_region_PVR2TA_read( uint32_t reg )
|
nkeynes@56 | 428 | {
|
nkeynes@56 | 429 | return 0xFFFFFFFF;
|
nkeynes@56 | 430 | }
|
nkeynes@56 | 431 |
|
nkeynes@56 | 432 | void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
|
nkeynes@56 | 433 | {
|
nkeynes@189 | 434 | pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
|
nkeynes@56 | 435 | }
|
nkeynes@56 | 436 |
|
nkeynes@85 | 437 |
|
nkeynes@103 | 438 | void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
|
nkeynes@103 | 439 | {
|
nkeynes@103 | 440 | int bank_flag = (destaddr & 0x04) >> 2;
|
nkeynes@103 | 441 | uint32_t *banks[2];
|
nkeynes@103 | 442 | uint32_t *dwsrc;
|
nkeynes@103 | 443 | int i;
|
nkeynes@65 | 444 |
|
nkeynes@103 | 445 | destaddr = destaddr & 0x7FFFFF;
|
nkeynes@103 | 446 | if( destaddr + length > 0x800000 ) {
|
nkeynes@103 | 447 | length = 0x800000 - destaddr;
|
nkeynes@103 | 448 | }
|
nkeynes@103 | 449 |
|
nkeynes@103 | 450 | for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
|
nkeynes@103 | 451 | texcache_invalidate_page( i );
|
nkeynes@103 | 452 | }
|
nkeynes@103 | 453 |
|
nkeynes@108 | 454 | banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
|
nkeynes@103 | 455 | banks[1] = banks[0] + 0x100000;
|
nkeynes@108 | 456 | if( bank_flag )
|
nkeynes@108 | 457 | banks[0]++;
|
nkeynes@103 | 458 |
|
nkeynes@103 | 459 | /* Handle non-aligned start of source */
|
nkeynes@103 | 460 | if( destaddr & 0x03 ) {
|
nkeynes@103 | 461 | char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
|
nkeynes@103 | 462 | for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
|
nkeynes@103 | 463 | *dest++ = *src++;
|
nkeynes@103 | 464 | }
|
nkeynes@103 | 465 | bank_flag = !bank_flag;
|
nkeynes@103 | 466 | }
|
nkeynes@103 | 467 |
|
nkeynes@103 | 468 | dwsrc = (uint32_t *)src;
|
nkeynes@103 | 469 | while( length >= 4 ) {
|
nkeynes@103 | 470 | *banks[bank_flag]++ = *dwsrc++;
|
nkeynes@103 | 471 | bank_flag = !bank_flag;
|
nkeynes@103 | 472 | length -= 4;
|
nkeynes@103 | 473 | }
|
nkeynes@103 | 474 |
|
nkeynes@103 | 475 | /* Handle non-aligned end of source */
|
nkeynes@103 | 476 | if( length ) {
|
nkeynes@103 | 477 | src = (char *)dwsrc;
|
nkeynes@103 | 478 | char *dest = (char *)banks[bank_flag];
|
nkeynes@103 | 479 | while( length-- > 0 ) {
|
nkeynes@103 | 480 | *dest++ = *src++;
|
nkeynes@103 | 481 | }
|
nkeynes@103 | 482 | }
|
nkeynes@103 | 483 |
|
nkeynes@103 | 484 | }
|
nkeynes@103 | 485 |
|
nkeynes@103 | 486 | void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
|
nkeynes@103 | 487 | {
|
nkeynes@103 | 488 | int bank_flag = (srcaddr & 0x04) >> 2;
|
nkeynes@103 | 489 | uint32_t *banks[2];
|
nkeynes@103 | 490 | uint32_t *dwdest;
|
nkeynes@103 | 491 | int i;
|
nkeynes@103 | 492 |
|
nkeynes@103 | 493 | srcaddr = srcaddr & 0x7FFFFF;
|
nkeynes@103 | 494 | if( srcaddr + length > 0x800000 )
|
nkeynes@103 | 495 | length = 0x800000 - srcaddr;
|
nkeynes@103 | 496 |
|
nkeynes@108 | 497 | banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
|
nkeynes@103 | 498 | banks[1] = banks[0] + 0x100000;
|
nkeynes@108 | 499 | if( bank_flag )
|
nkeynes@108 | 500 | banks[0]++;
|
nkeynes@103 | 501 |
|
nkeynes@103 | 502 | /* Handle non-aligned start of source */
|
nkeynes@103 | 503 | if( srcaddr & 0x03 ) {
|
nkeynes@103 | 504 | char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
|
nkeynes@103 | 505 | for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
|
nkeynes@103 | 506 | *dest++ = *src++;
|
nkeynes@103 | 507 | }
|
nkeynes@103 | 508 | bank_flag = !bank_flag;
|
nkeynes@103 | 509 | }
|
nkeynes@103 | 510 |
|
nkeynes@103 | 511 | dwdest = (uint32_t *)dest;
|
nkeynes@103 | 512 | while( length >= 4 ) {
|
nkeynes@103 | 513 | *dwdest++ = *banks[bank_flag]++;
|
nkeynes@103 | 514 | bank_flag = !bank_flag;
|
nkeynes@103 | 515 | length -= 4;
|
nkeynes@103 | 516 | }
|
nkeynes@103 | 517 |
|
nkeynes@103 | 518 | /* Handle non-aligned end of source */
|
nkeynes@103 | 519 | if( length ) {
|
nkeynes@103 | 520 | dest = (char *)dwdest;
|
nkeynes@103 | 521 | char *src = (char *)banks[bank_flag];
|
nkeynes@103 | 522 | while( length-- > 0 ) {
|
nkeynes@103 | 523 | *dest++ = *src++;
|
nkeynes@103 | 524 | }
|
nkeynes@103 | 525 | }
|
nkeynes@103 | 526 | }
|
nkeynes@127 | 527 |
|
nkeynes@127 | 528 | void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f )
|
nkeynes@127 | 529 | {
|
nkeynes@127 | 530 | char tmp[length];
|
nkeynes@127 | 531 | pvr2_vram64_read( tmp, addr, length );
|
nkeynes@127 | 532 | fwrite_dump( tmp, length, f );
|
nkeynes@127 | 533 | }
|