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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 197:f65ff8c8320d
prev193:31151fcc3cb7
next214:7a6501b74fbc
author nkeynes
date Sun Aug 06 02:47:08 2006 +0000 (13 years ago)
permissions -rw-r--r--
last change Add masks on all PVR2 registers
Add missing registers and rename display registers for consistency
file annotate diff log raw
nkeynes@31
     1
/**
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 * $Id: pvr2.c,v 1.31 2006-08-06 02:47:08 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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     9
 * it under the terms of the GNU General Public License as published by
nkeynes@31
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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    15
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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    17
 */
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    18
#define MODULE pvr2_module
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    19
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#include "dream.h"
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#include "display.h"
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#include "mem.h"
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    23
#include "asic.h"
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#include "pvr2/pvr2.h"
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    25
#include "sh4/sh4core.h"
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    26
#define MMIO_IMPL
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    27
#include "pvr2/pvr2mmio.h"
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char *video_base;
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    30
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    31
static void pvr2_init( void );
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    32
static void pvr2_reset( void );
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    33
static uint32_t pvr2_run_slice( uint32_t );
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    34
static void pvr2_save_state( FILE *f );
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    35
static int pvr2_load_state( FILE *f );
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    36
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    37
void pvr2_display_frame( void );
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    38
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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    40
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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    42
					pvr2_run_slice, NULL,
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    43
					pvr2_save_state, pvr2_load_state };
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    44
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    45
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display_driver_t display_driver = NULL;
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    47
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struct video_timing {
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    49
    int fields_per_second;
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    50
    int total_lines;
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    51
    int retrace_lines;
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    52
    int line_time_ns;
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    53
};
nkeynes@103
    54
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    55
struct video_timing pal_timing = { 50, 625, 65, 32000 };
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    56
struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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    57
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struct pvr2_state {
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    59
    uint32_t frame_count;
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    60
    uint32_t line_count;
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    61
    uint32_t line_remainder;
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    62
    uint32_t irq_vpos1;
nkeynes@133
    63
    uint32_t irq_vpos2;
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    64
    gboolean retrace;
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    65
    struct video_timing timing;
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    66
} pvr2_state;
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    67
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    74
    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    84
    pvr2_state.line_remainder = 0;
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    85
    pvr2_state.irq_vpos1 = 0;
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    86
    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.retrace = FALSE;
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    pvr2_state.timing = ntsc_timing;
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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    97
{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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}
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   101
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    return pvr2_ta_load_state(f);
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_state.line_remainder += nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
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	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
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	pvr2_state.line_count++;
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   116
	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
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	    asic_event( EVENT_RETRACE );
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	    pvr2_state.line_count = 0;
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   119
	    pvr2_state.retrace = TRUE;
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   120
	}
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   121
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   122
	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
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   123
	    asic_event( EVENT_SCANLINE1 );
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   124
	} 
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	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
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	    asic_event( EVENT_SCANLINE2 );
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   127
	}
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   128
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	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
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   130
	    if( pvr2_state.retrace ) {
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		pvr2_display_frame();
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		pvr2_state.retrace = FALSE;
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	    }
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   134
	}
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    }
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    return nanosecs;
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   137
}
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   138
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int pvr2_get_frame_count() 
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   140
{
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    return pvr2_state.frame_count;
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   142
}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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   151
    uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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   152
    
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   153
    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_CFG );
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    int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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    buffer->vres = vid_lpf;
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    if( interlaced ) buffer->vres <<= 1;
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    switch( (dispmode & DISPMODE_COL) >> 2 ) {
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    case 0: 
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	buffer->colour_format = COLFMT_ARGB1555;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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	buffer->hres = vid_ppl << 1; 
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	break;
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    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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	break;
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    case 3: 
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	buffer->colour_format = COLFMT_ARGB8888;
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	buffer->hres = vid_ppl; 
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	break;
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    }
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    if( buffer->hres <=8 )
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	buffer->hres = 640;
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    if( buffer->vres <=8 )
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	buffer->vres = 480;
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    if( display_driver != NULL ) {
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	if( buffer->hres != last->hres ||
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	    buffer->vres != last->vres ||
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	    buffer->colour_format != last->colour_format) {
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	    display_driver->set_display_format( buffer->hres, buffer->vres,
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						buffer->colour_format );
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	}
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	if( !bEnabled ) {
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	    display_driver->display_blank_frame( 0 );
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	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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	    display_driver->display_blank_frame( colour );
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	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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	    display_driver->display_frame( buffer );
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	}
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    }
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    pvr2_state.frame_count++;
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}
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/**
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 * This has to handle every single register individually as they all get masked 
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 * off differently (and its easier to do it at write time)
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 */
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void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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{
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    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
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        MMIO_WRITE( PVR2, reg, val );
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        return;
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    }
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    switch(reg) {
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    case PVRID:
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    case PVRVER:
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    case GUNPOS:
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    case TA_POLYPOS:
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    case TA_LISTPOS:
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	/* Readonly registers */
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	break;
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    case PVRRESET:
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	val &= 0x00000007; /* Do stuff? */
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	MMIO_WRITE( PVR2, reg, val );
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	break;
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    case RENDER_START:
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	if( val == 0xFFFFFFFF )
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	    pvr2_render_scene();
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	break;
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   237
    case PVRUNK1:
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    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
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    	break;
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   240
    case RENDER_POLYBASE:
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    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
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    	break;
nkeynes@191
   243
    case RENDER_TSPCFG:
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   244
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
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    	break;
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   246
    case DISP_BORDER:
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   247
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
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    	break;
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   249
    case DISP_MODE:
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   250
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   251
    	break;
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   252
    case RENDER_MODE:
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   253
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
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   254
    	break;
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   255
    case RENDER_SIZE:
nkeynes@191
   256
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
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   257
    	break;
nkeynes@197
   258
    case DISP_ADDR1:
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   259
	val &= 0x00FFFFFC;
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   260
	MMIO_WRITE( PVR2, reg, val );
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   261
	if( pvr2_state.retrace ) {
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   262
	    pvr2_display_frame();
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   263
	    pvr2_state.retrace = FALSE;
nkeynes@108
   264
	}
nkeynes@108
   265
	break;
nkeynes@197
   266
    case DISP_ADDR2:
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   267
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@191
   268
    	break;
nkeynes@197
   269
    case DISP_SIZE:
nkeynes@191
   270
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   271
    	break;
nkeynes@191
   272
    case RENDER_ADDR1:
nkeynes@191
   273
    case RENDER_ADDR2:
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   274
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   275
    	break;
nkeynes@191
   276
    case RENDER_HCLIP:
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   277
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   278
	break;
nkeynes@191
   279
    case RENDER_VCLIP:
nkeynes@191
   280
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   281
	break;
nkeynes@197
   282
    case DISP_HPOSIRQ:
nkeynes@191
   283
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@189
   284
	break;
nkeynes@197
   285
    case DISP_VPOSIRQ:
nkeynes@189
   286
	val = val & 0x03FF03FF;
nkeynes@189
   287
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   288
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@189
   289
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   290
	break;
nkeynes@197
   291
    case RENDER_NEARCLIP:
nkeynes@197
   292
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   293
	break;
nkeynes@191
   294
    case RENDER_SHADOW:
nkeynes@191
   295
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   296
	break;
nkeynes@191
   297
    case RENDER_OBJCFG:
nkeynes@191
   298
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   299
    	break;
nkeynes@197
   300
    case PVRUNK2:
nkeynes@197
   301
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@197
   302
	break;
nkeynes@191
   303
    case RENDER_TSPCLIP:
nkeynes@191
   304
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   305
    	break;
nkeynes@197
   306
    case RENDER_FARCLIP:
nkeynes@197
   307
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   308
	break;
nkeynes@191
   309
    case RENDER_BGPLANE:
nkeynes@191
   310
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   311
    	break;
nkeynes@191
   312
    case RENDER_ISPCFG:
nkeynes@191
   313
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   314
    	break;
nkeynes@197
   315
    case VRAM_CFG1:
nkeynes@197
   316
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   317
	break;
nkeynes@197
   318
    case VRAM_CFG2:
nkeynes@197
   319
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   320
	break;
nkeynes@197
   321
    case VRAM_CFG3:
nkeynes@197
   322
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   323
	break;
nkeynes@197
   324
    case RENDER_FOGTBLCOL:
nkeynes@197
   325
    case RENDER_FOGVRTCOL:
nkeynes@197
   326
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   327
	break;
nkeynes@197
   328
    case RENDER_FOGCOEFF:
nkeynes@197
   329
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   330
	break;
nkeynes@197
   331
    case RENDER_CLAMPHI:
nkeynes@197
   332
    case RENDER_CLAMPLO:
nkeynes@197
   333
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   334
	break;
nkeynes@197
   335
    case DISP_CFG:
nkeynes@197
   336
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@197
   337
	break;
nkeynes@197
   338
    case DISP_HBORDER:
nkeynes@197
   339
    case DISP_SYNC:
nkeynes@197
   340
    case DISP_VBORDER:
nkeynes@197
   341
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   342
	break;
nkeynes@197
   343
    case DISP_SYNC2:
nkeynes@197
   344
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   345
	break;
nkeynes@197
   346
    case RENDER_TEXSIZE:
nkeynes@197
   347
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   348
	break;
nkeynes@197
   349
    case DISP_CFG2:
nkeynes@197
   350
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   351
	break;
nkeynes@197
   352
    case DISP_HPOS:
nkeynes@197
   353
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@197
   354
	break;
nkeynes@197
   355
    case DISP_VPOS:
nkeynes@197
   356
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   357
	break;
nkeynes@197
   358
    case SCALERCFG:
nkeynes@197
   359
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@197
   360
	break;
nkeynes@197
   361
    case RENDER_PALETTE:
nkeynes@197
   362
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@197
   363
	break;
nkeynes@197
   364
    case PVRUNK3:
nkeynes@197
   365
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@197
   366
	break;
nkeynes@197
   367
    case PVRUNK5:
nkeynes@197
   368
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   369
	break;
nkeynes@197
   370
    case PVRUNK6:
nkeynes@197
   371
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   372
	break;
nkeynes@189
   373
    case TA_TILEBASE:
nkeynes@193
   374
    case TA_LISTEND:
nkeynes@189
   375
    case TA_LISTBASE:
nkeynes@191
   376
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   377
	break;
nkeynes@191
   378
    case RENDER_TILEBASE:
nkeynes@189
   379
    case TA_POLYBASE:
nkeynes@189
   380
    case TA_POLYEND:
nkeynes@191
   381
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   382
	break;
nkeynes@189
   383
    case TA_TILESIZE:
nkeynes@191
   384
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   385
	break;
nkeynes@189
   386
    case TA_TILECFG:
nkeynes@191
   387
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   388
	break;
nkeynes@197
   389
    case YUV_ADDR:
nkeynes@197
   390
	MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
nkeynes@197
   391
	break;
nkeynes@197
   392
    case YUV_CFG:
nkeynes@197
   393
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@197
   394
	break;
nkeynes@189
   395
    case TA_INIT:
nkeynes@100
   396
	if( val & 0x80000000 )
nkeynes@100
   397
	    pvr2_ta_init();
nkeynes@100
   398
	break;
nkeynes@197
   399
    case TA_REINIT:
nkeynes@197
   400
	break;
nkeynes@197
   401
    case PVRUNK7:
nkeynes@197
   402
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   403
	break;
nkeynes@1
   404
    }
nkeynes@1
   405
}
nkeynes@1
   406
nkeynes@1
   407
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   408
{
nkeynes@1
   409
    switch( reg ) {
nkeynes@197
   410
        case DISP_BEAMPOS:
nkeynes@2
   411
            return sh4r.icount&0x20 ? 0x2000 : 1;
nkeynes@1
   412
        default:
nkeynes@1
   413
            return MMIO_READ( PVR2, reg );
nkeynes@1
   414
    }
nkeynes@1
   415
}
nkeynes@19
   416
nkeynes@85
   417
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   418
nkeynes@19
   419
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   420
{
nkeynes@197
   421
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   422
}
nkeynes@56
   423
nkeynes@56
   424
nkeynes@65
   425
nkeynes@98
   426
nkeynes@56
   427
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   428
{
nkeynes@56
   429
    return 0xFFFFFFFF;
nkeynes@56
   430
}
nkeynes@56
   431
nkeynes@56
   432
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   433
{
nkeynes@189
   434
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   435
}
nkeynes@56
   436
nkeynes@85
   437
nkeynes@103
   438
void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
nkeynes@103
   439
{
nkeynes@103
   440
    int bank_flag = (destaddr & 0x04) >> 2;
nkeynes@103
   441
    uint32_t *banks[2];
nkeynes@103
   442
    uint32_t *dwsrc;
nkeynes@103
   443
    int i;
nkeynes@65
   444
nkeynes@103
   445
    destaddr = destaddr & 0x7FFFFF;
nkeynes@103
   446
    if( destaddr + length > 0x800000 ) {
nkeynes@103
   447
	length = 0x800000 - destaddr;
nkeynes@103
   448
    }
nkeynes@103
   449
nkeynes@103
   450
    for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
nkeynes@103
   451
	texcache_invalidate_page( i );
nkeynes@103
   452
    }
nkeynes@103
   453
nkeynes@108
   454
    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
nkeynes@103
   455
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   456
    if( bank_flag ) 
nkeynes@108
   457
	banks[0]++;
nkeynes@103
   458
    
nkeynes@103
   459
    /* Handle non-aligned start of source */
nkeynes@103
   460
    if( destaddr & 0x03 ) {
nkeynes@103
   461
	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
nkeynes@103
   462
	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   463
	    *dest++ = *src++;
nkeynes@103
   464
	}
nkeynes@103
   465
	bank_flag = !bank_flag;
nkeynes@103
   466
    }
nkeynes@103
   467
nkeynes@103
   468
    dwsrc = (uint32_t *)src;
nkeynes@103
   469
    while( length >= 4 ) {
nkeynes@103
   470
	*banks[bank_flag]++ = *dwsrc++;
nkeynes@103
   471
	bank_flag = !bank_flag;
nkeynes@103
   472
	length -= 4;
nkeynes@103
   473
    }
nkeynes@103
   474
    
nkeynes@103
   475
    /* Handle non-aligned end of source */
nkeynes@103
   476
    if( length ) {
nkeynes@103
   477
	src = (char *)dwsrc;
nkeynes@103
   478
	char *dest = (char *)banks[bank_flag];
nkeynes@103
   479
	while( length-- > 0 ) {
nkeynes@103
   480
	    *dest++ = *src++;
nkeynes@103
   481
	}
nkeynes@103
   482
    }  
nkeynes@103
   483
nkeynes@103
   484
}
nkeynes@103
   485
nkeynes@103
   486
void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
nkeynes@103
   487
{
nkeynes@103
   488
    int bank_flag = (srcaddr & 0x04) >> 2;
nkeynes@103
   489
    uint32_t *banks[2];
nkeynes@103
   490
    uint32_t *dwdest;
nkeynes@103
   491
    int i;
nkeynes@103
   492
nkeynes@103
   493
    srcaddr = srcaddr & 0x7FFFFF;
nkeynes@103
   494
    if( srcaddr + length > 0x800000 )
nkeynes@103
   495
	length = 0x800000 - srcaddr;
nkeynes@103
   496
nkeynes@108
   497
    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
nkeynes@103
   498
    banks[1] = banks[0] + 0x100000;
nkeynes@108
   499
    if( bank_flag )
nkeynes@108
   500
	banks[0]++;
nkeynes@103
   501
    
nkeynes@103
   502
    /* Handle non-aligned start of source */
nkeynes@103
   503
    if( srcaddr & 0x03 ) {
nkeynes@103
   504
	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
nkeynes@103
   505
	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
nkeynes@103
   506
	    *dest++ = *src++;
nkeynes@103
   507
	}
nkeynes@103
   508
	bank_flag = !bank_flag;
nkeynes@103
   509
    }
nkeynes@103
   510
nkeynes@103
   511
    dwdest = (uint32_t *)dest;
nkeynes@103
   512
    while( length >= 4 ) {
nkeynes@103
   513
	*dwdest++ = *banks[bank_flag]++;
nkeynes@103
   514
	bank_flag = !bank_flag;
nkeynes@103
   515
	length -= 4;
nkeynes@103
   516
    }
nkeynes@103
   517
    
nkeynes@103
   518
    /* Handle non-aligned end of source */
nkeynes@103
   519
    if( length ) {
nkeynes@103
   520
	dest = (char *)dwdest;
nkeynes@103
   521
	char *src = (char *)banks[bank_flag];
nkeynes@103
   522
	while( length-- > 0 ) {
nkeynes@103
   523
	    *dest++ = *src++;
nkeynes@103
   524
	}
nkeynes@103
   525
    }
nkeynes@103
   526
}
nkeynes@127
   527
nkeynes@127
   528
void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
nkeynes@127
   529
{
nkeynes@127
   530
    char tmp[length];
nkeynes@127
   531
    pvr2_vram64_read( tmp, addr, length );
nkeynes@127
   532
    fwrite_dump( tmp, length, f );
nkeynes@127
   533
}
.