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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 401:f79327f39818
prev397:640324505325
next408:af496b734734
author nkeynes
date Thu Sep 20 08:37:19 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Move support routines to sh4.c
file annotate diff log raw
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/**
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 * $Id: sh4x86.c,v 1.14 2007-09-20 08:37:19 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    int exit_code;
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 12 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    NOT_r32( bankreg );
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Update the fr_bank pointer based on the current fpscr value.
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 */
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static inline void update_fr_bank( int fpscrreg )
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{
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    SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
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    store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(arg2b);
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    PUSH_r32(addr);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(arg2a);
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    PUSH_r32(addr);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   352
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   353
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   354
nkeynes@386
   355
#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368
   356
nkeynes@368
   357
nkeynes@359
   358
nkeynes@359
   359
/**
nkeynes@359
   360
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   361
 * SI/DI as required
nkeynes@359
   362
 */
nkeynes@368
   363
void sh4_translate_begin_block() 
nkeynes@368
   364
{
nkeynes@368
   365
    PUSH_r32(R_EBP);
nkeynes@359
   366
    /* mov &sh4r, ebp */
nkeynes@359
   367
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   368
    PUSH_r32(R_EDI);
nkeynes@368
   369
    PUSH_r32(R_ESI);
nkeynes@380
   370
    XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368
   371
    
nkeynes@368
   372
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   373
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   374
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   375
    sh4_x86.backpatch_posn = 0;
nkeynes@388
   376
    sh4_x86.exit_code = 1;
nkeynes@368
   377
}
nkeynes@359
   378
nkeynes@368
   379
/**
nkeynes@368
   380
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   381
 */
nkeynes@374
   382
void exit_block( )
nkeynes@368
   383
{
nkeynes@374
   384
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   385
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   386
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   387
    MUL_r32( R_ESI );
nkeynes@368
   388
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   389
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   390
    load_imm32( R_EAX, sh4_x86.exit_code );
nkeynes@374
   391
    POP_r32(R_ESI);
nkeynes@374
   392
    POP_r32(R_EDI);
nkeynes@374
   393
    POP_r32(R_EBP);
nkeynes@368
   394
    RET();
nkeynes@359
   395
}
nkeynes@359
   396
nkeynes@359
   397
/**
nkeynes@359
   398
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   399
 */
nkeynes@359
   400
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   401
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   402
    // Normal termination - save PC, cycle count
nkeynes@374
   403
    exit_block( );
nkeynes@359
   404
nkeynes@388
   405
    if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388
   406
	uint8_t *end_ptr = xlat_output;
nkeynes@388
   407
	// Exception termination. Jump block for various exception codes:
nkeynes@388
   408
	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388
   409
	JMP_rel8( 33, target1 );
nkeynes@388
   410
	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388
   411
	JMP_rel8( 26, target2 );
nkeynes@388
   412
	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388
   413
	JMP_rel8( 19, target3 );
nkeynes@388
   414
	PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@388
   415
	JMP_rel8( 12, target4 );
nkeynes@388
   416
	PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@388
   417
	JMP_rel8( 5, target5 );
nkeynes@388
   418
	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388
   419
	// target
nkeynes@388
   420
	JMP_TARGET(target1);
nkeynes@388
   421
	JMP_TARGET(target2);
nkeynes@388
   422
	JMP_TARGET(target3);
nkeynes@388
   423
	JMP_TARGET(target4);
nkeynes@388
   424
	JMP_TARGET(target5);
nkeynes@388
   425
	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   426
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   427
	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388
   428
	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388
   429
	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@388
   430
	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   431
	MUL_r32( R_ESI );
nkeynes@388
   432
	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@388
   433
	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388
   434
	
nkeynes@388
   435
	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388
   436
	CALL_r32( R_EAX ); // 2
nkeynes@388
   437
	ADD_imm8s_r32( 4, R_ESP );
nkeynes@388
   438
	POP_r32(R_ESI);
nkeynes@388
   439
	POP_r32(R_EDI);
nkeynes@388
   440
	POP_r32(R_EBP);
nkeynes@388
   441
	RET();
nkeynes@368
   442
nkeynes@388
   443
	sh4_x86_do_backpatch( end_ptr );
nkeynes@388
   444
    }
nkeynes@368
   445
nkeynes@359
   446
}
nkeynes@359
   447
nkeynes@388
   448
nkeynes@388
   449
extern uint16_t *sh4_icache;
nkeynes@388
   450
extern uint32_t sh4_icache_addr;
nkeynes@388
   451
nkeynes@359
   452
/**
nkeynes@359
   453
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   454
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   455
 * 
nkeynes@359
   456
 *
nkeynes@359
   457
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   458
 * (eg a branch or 
nkeynes@359
   459
 */
nkeynes@359
   460
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   461
{
nkeynes@388
   462
    uint32_t ir;
nkeynes@388
   463
    /* Read instruction */
nkeynes@388
   464
    uint32_t pageaddr = pc >> 12;
nkeynes@388
   465
    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388
   466
	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   467
    } else {
nkeynes@388
   468
	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388
   469
	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388
   470
	    /* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388
   471
	     * region, fallback on the full-blown memory read
nkeynes@388
   472
	     */
nkeynes@388
   473
	    sh4_icache = NULL;
nkeynes@388
   474
	    ir = sh4_read_word(pc);
nkeynes@388
   475
	} else {
nkeynes@388
   476
	    sh4_icache_addr = pageaddr;
nkeynes@388
   477
	    ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388
   478
	}
nkeynes@388
   479
    }
nkeynes@388
   480
nkeynes@359
   481
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   482
            case 0x0:
nkeynes@359
   483
                switch( ir&0xF ) {
nkeynes@359
   484
                    case 0x2:
nkeynes@359
   485
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   486
                            case 0x0:
nkeynes@359
   487
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   488
                                    case 0x0:
nkeynes@359
   489
                                        { /* STC SR, Rn */
nkeynes@359
   490
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   491
                                        check_priv();
nkeynes@374
   492
                                        call_func0(sh4_read_sr);
nkeynes@368
   493
                                        store_reg( R_EAX, Rn );
nkeynes@359
   494
                                        }
nkeynes@359
   495
                                        break;
nkeynes@359
   496
                                    case 0x1:
nkeynes@359
   497
                                        { /* STC GBR, Rn */
nkeynes@359
   498
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   499
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   500
                                        store_reg( R_EAX, Rn );
nkeynes@359
   501
                                        }
nkeynes@359
   502
                                        break;
nkeynes@359
   503
                                    case 0x2:
nkeynes@359
   504
                                        { /* STC VBR, Rn */
nkeynes@359
   505
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   506
                                        check_priv();
nkeynes@359
   507
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   508
                                        store_reg( R_EAX, Rn );
nkeynes@359
   509
                                        }
nkeynes@359
   510
                                        break;
nkeynes@359
   511
                                    case 0x3:
nkeynes@359
   512
                                        { /* STC SSR, Rn */
nkeynes@359
   513
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   514
                                        check_priv();
nkeynes@359
   515
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   516
                                        store_reg( R_EAX, Rn );
nkeynes@359
   517
                                        }
nkeynes@359
   518
                                        break;
nkeynes@359
   519
                                    case 0x4:
nkeynes@359
   520
                                        { /* STC SPC, Rn */
nkeynes@359
   521
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   522
                                        check_priv();
nkeynes@359
   523
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   524
                                        store_reg( R_EAX, Rn );
nkeynes@359
   525
                                        }
nkeynes@359
   526
                                        break;
nkeynes@359
   527
                                    default:
nkeynes@359
   528
                                        UNDEF();
nkeynes@359
   529
                                        break;
nkeynes@359
   530
                                }
nkeynes@359
   531
                                break;
nkeynes@359
   532
                            case 0x1:
nkeynes@359
   533
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   534
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
   535
                                check_priv();
nkeynes@374
   536
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   537
                                store_reg( R_EAX, Rn );
nkeynes@359
   538
                                }
nkeynes@359
   539
                                break;
nkeynes@359
   540
                        }
nkeynes@359
   541
                        break;
nkeynes@359
   542
                    case 0x3:
nkeynes@359
   543
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   544
                            case 0x0:
nkeynes@359
   545
                                { /* BSRF Rn */
nkeynes@359
   546
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   547
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   548
                            	SLOTILLEGAL();
nkeynes@374
   549
                                } else {
nkeynes@374
   550
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
   551
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
   552
                            	load_reg( R_EDI, Rn );
nkeynes@374
   553
                            	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
   554
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   555
                            	return 0;
nkeynes@374
   556
                                }
nkeynes@359
   557
                                }
nkeynes@359
   558
                                break;
nkeynes@359
   559
                            case 0x2:
nkeynes@359
   560
                                { /* BRAF Rn */
nkeynes@359
   561
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   562
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   563
                            	SLOTILLEGAL();
nkeynes@374
   564
                                } else {
nkeynes@374
   565
                            	load_reg( R_EDI, Rn );
nkeynes@386
   566
                            	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374
   567
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   568
                            	return 0;
nkeynes@374
   569
                                }
nkeynes@359
   570
                                }
nkeynes@359
   571
                                break;
nkeynes@359
   572
                            case 0x8:
nkeynes@359
   573
                                { /* PREF @Rn */
nkeynes@359
   574
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   575
                                load_reg( R_EAX, Rn );
nkeynes@374
   576
                                PUSH_r32( R_EAX );
nkeynes@374
   577
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   578
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
   579
                                JNE_rel8(7, end);
nkeynes@374
   580
                                call_func0( sh4_flush_store_queue );
nkeynes@380
   581
                                JMP_TARGET(end);
nkeynes@377
   582
                                ADD_imm8s_r32( 4, R_ESP );
nkeynes@359
   583
                                }
nkeynes@359
   584
                                break;
nkeynes@359
   585
                            case 0x9:
nkeynes@359
   586
                                { /* OCBI @Rn */
nkeynes@359
   587
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   588
                                }
nkeynes@359
   589
                                break;
nkeynes@359
   590
                            case 0xA:
nkeynes@359
   591
                                { /* OCBP @Rn */
nkeynes@359
   592
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   593
                                }
nkeynes@359
   594
                                break;
nkeynes@359
   595
                            case 0xB:
nkeynes@359
   596
                                { /* OCBWB @Rn */
nkeynes@359
   597
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   598
                                }
nkeynes@359
   599
                                break;
nkeynes@359
   600
                            case 0xC:
nkeynes@359
   601
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   602
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   603
                                load_reg( R_EAX, 0 );
nkeynes@361
   604
                                load_reg( R_ECX, Rn );
nkeynes@374
   605
                                check_walign32( R_ECX );
nkeynes@361
   606
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   607
                                }
nkeynes@359
   608
                                break;
nkeynes@359
   609
                            default:
nkeynes@359
   610
                                UNDEF();
nkeynes@359
   611
                                break;
nkeynes@359
   612
                        }
nkeynes@359
   613
                        break;
nkeynes@359
   614
                    case 0x4:
nkeynes@359
   615
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   616
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   617
                        load_reg( R_EAX, 0 );
nkeynes@359
   618
                        load_reg( R_ECX, Rn );
nkeynes@359
   619
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   620
                        load_reg( R_EAX, Rm );
nkeynes@359
   621
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   622
                        }
nkeynes@359
   623
                        break;
nkeynes@359
   624
                    case 0x5:
nkeynes@359
   625
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   626
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   627
                        load_reg( R_EAX, 0 );
nkeynes@361
   628
                        load_reg( R_ECX, Rn );
nkeynes@361
   629
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   630
                        check_walign16( R_ECX );
nkeynes@361
   631
                        load_reg( R_EAX, Rm );
nkeynes@361
   632
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   633
                        }
nkeynes@359
   634
                        break;
nkeynes@359
   635
                    case 0x6:
nkeynes@359
   636
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   637
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   638
                        load_reg( R_EAX, 0 );
nkeynes@361
   639
                        load_reg( R_ECX, Rn );
nkeynes@361
   640
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   641
                        check_walign32( R_ECX );
nkeynes@361
   642
                        load_reg( R_EAX, Rm );
nkeynes@361
   643
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   644
                        }
nkeynes@359
   645
                        break;
nkeynes@359
   646
                    case 0x7:
nkeynes@359
   647
                        { /* MUL.L Rm, Rn */
nkeynes@359
   648
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   649
                        load_reg( R_EAX, Rm );
nkeynes@361
   650
                        load_reg( R_ECX, Rn );
nkeynes@361
   651
                        MUL_r32( R_ECX );
nkeynes@361
   652
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   653
                        }
nkeynes@359
   654
                        break;
nkeynes@359
   655
                    case 0x8:
nkeynes@359
   656
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   657
                            case 0x0:
nkeynes@359
   658
                                { /* CLRT */
nkeynes@374
   659
                                CLC();
nkeynes@374
   660
                                SETC_t();
nkeynes@359
   661
                                }
nkeynes@359
   662
                                break;
nkeynes@359
   663
                            case 0x1:
nkeynes@359
   664
                                { /* SETT */
nkeynes@374
   665
                                STC();
nkeynes@374
   666
                                SETC_t();
nkeynes@359
   667
                                }
nkeynes@359
   668
                                break;
nkeynes@359
   669
                            case 0x2:
nkeynes@359
   670
                                { /* CLRMAC */
nkeynes@374
   671
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   672
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   673
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
   674
                                }
nkeynes@359
   675
                                break;
nkeynes@359
   676
                            case 0x3:
nkeynes@359
   677
                                { /* LDTLB */
nkeynes@359
   678
                                }
nkeynes@359
   679
                                break;
nkeynes@359
   680
                            case 0x4:
nkeynes@359
   681
                                { /* CLRS */
nkeynes@374
   682
                                CLC();
nkeynes@374
   683
                                SETC_sh4r(R_S);
nkeynes@359
   684
                                }
nkeynes@359
   685
                                break;
nkeynes@359
   686
                            case 0x5:
nkeynes@359
   687
                                { /* SETS */
nkeynes@374
   688
                                STC();
nkeynes@374
   689
                                SETC_sh4r(R_S);
nkeynes@359
   690
                                }
nkeynes@359
   691
                                break;
nkeynes@359
   692
                            default:
nkeynes@359
   693
                                UNDEF();
nkeynes@359
   694
                                break;
nkeynes@359
   695
                        }
nkeynes@359
   696
                        break;
nkeynes@359
   697
                    case 0x9:
nkeynes@359
   698
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   699
                            case 0x0:
nkeynes@359
   700
                                { /* NOP */
nkeynes@359
   701
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   702
                                }
nkeynes@359
   703
                                break;
nkeynes@359
   704
                            case 0x1:
nkeynes@359
   705
                                { /* DIV0U */
nkeynes@361
   706
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   707
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   708
                                store_spreg( R_EAX, R_M );
nkeynes@361
   709
                                store_spreg( R_EAX, R_T );
nkeynes@359
   710
                                }
nkeynes@359
   711
                                break;
nkeynes@359
   712
                            case 0x2:
nkeynes@359
   713
                                { /* MOVT Rn */
nkeynes@359
   714
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   715
                                load_spreg( R_EAX, R_T );
nkeynes@359
   716
                                store_reg( R_EAX, Rn );
nkeynes@359
   717
                                }
nkeynes@359
   718
                                break;
nkeynes@359
   719
                            default:
nkeynes@359
   720
                                UNDEF();
nkeynes@359
   721
                                break;
nkeynes@359
   722
                        }
nkeynes@359
   723
                        break;
nkeynes@359
   724
                    case 0xA:
nkeynes@359
   725
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   726
                            case 0x0:
nkeynes@359
   727
                                { /* STS MACH, Rn */
nkeynes@359
   728
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   729
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   730
                                store_reg( R_EAX, Rn );
nkeynes@359
   731
                                }
nkeynes@359
   732
                                break;
nkeynes@359
   733
                            case 0x1:
nkeynes@359
   734
                                { /* STS MACL, Rn */
nkeynes@359
   735
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   736
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   737
                                store_reg( R_EAX, Rn );
nkeynes@359
   738
                                }
nkeynes@359
   739
                                break;
nkeynes@359
   740
                            case 0x2:
nkeynes@359
   741
                                { /* STS PR, Rn */
nkeynes@359
   742
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   743
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   744
                                store_reg( R_EAX, Rn );
nkeynes@359
   745
                                }
nkeynes@359
   746
                                break;
nkeynes@359
   747
                            case 0x3:
nkeynes@359
   748
                                { /* STC SGR, Rn */
nkeynes@359
   749
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   750
                                check_priv();
nkeynes@359
   751
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   752
                                store_reg( R_EAX, Rn );
nkeynes@359
   753
                                }
nkeynes@359
   754
                                break;
nkeynes@359
   755
                            case 0x5:
nkeynes@359
   756
                                { /* STS FPUL, Rn */
nkeynes@359
   757
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   758
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   759
                                store_reg( R_EAX, Rn );
nkeynes@359
   760
                                }
nkeynes@359
   761
                                break;
nkeynes@359
   762
                            case 0x6:
nkeynes@359
   763
                                { /* STS FPSCR, Rn */
nkeynes@359
   764
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   765
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   766
                                store_reg( R_EAX, Rn );
nkeynes@359
   767
                                }
nkeynes@359
   768
                                break;
nkeynes@359
   769
                            case 0xF:
nkeynes@359
   770
                                { /* STC DBR, Rn */
nkeynes@359
   771
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
   772
                                check_priv();
nkeynes@359
   773
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   774
                                store_reg( R_EAX, Rn );
nkeynes@359
   775
                                }
nkeynes@359
   776
                                break;
nkeynes@359
   777
                            default:
nkeynes@359
   778
                                UNDEF();
nkeynes@359
   779
                                break;
nkeynes@359
   780
                        }
nkeynes@359
   781
                        break;
nkeynes@359
   782
                    case 0xB:
nkeynes@359
   783
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   784
                            case 0x0:
nkeynes@359
   785
                                { /* RTS */
nkeynes@374
   786
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   787
                            	SLOTILLEGAL();
nkeynes@374
   788
                                } else {
nkeynes@374
   789
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   790
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   791
                            	return 0;
nkeynes@374
   792
                                }
nkeynes@359
   793
                                }
nkeynes@359
   794
                                break;
nkeynes@359
   795
                            case 0x1:
nkeynes@359
   796
                                { /* SLEEP */
nkeynes@388
   797
                                check_priv();
nkeynes@388
   798
                                call_func0( sh4_sleep );
nkeynes@388
   799
                                sh4_x86.exit_code = 0;
nkeynes@388
   800
                                sh4_x86.in_delay_slot = FALSE;
nkeynes@394
   801
                                INC_r32(R_ESI);
nkeynes@388
   802
                                return 1;
nkeynes@359
   803
                                }
nkeynes@359
   804
                                break;
nkeynes@359
   805
                            case 0x2:
nkeynes@359
   806
                                { /* RTE */
nkeynes@374
   807
                                check_priv();
nkeynes@374
   808
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   809
                            	SLOTILLEGAL();
nkeynes@374
   810
                                } else {
nkeynes@386
   811
                            	load_spreg( R_EDI, R_SPC );
nkeynes@374
   812
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   813
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   814
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   815
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   816
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
   817
                            	return 0;
nkeynes@374
   818
                                }
nkeynes@359
   819
                                }
nkeynes@359
   820
                                break;
nkeynes@359
   821
                            default:
nkeynes@359
   822
                                UNDEF();
nkeynes@359
   823
                                break;
nkeynes@359
   824
                        }
nkeynes@359
   825
                        break;
nkeynes@359
   826
                    case 0xC:
nkeynes@359
   827
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   828
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   829
                        load_reg( R_EAX, 0 );
nkeynes@359
   830
                        load_reg( R_ECX, Rm );
nkeynes@359
   831
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   832
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   833
                        store_reg( R_EAX, Rn );
nkeynes@359
   834
                        }
nkeynes@359
   835
                        break;
nkeynes@359
   836
                    case 0xD:
nkeynes@359
   837
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   838
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   839
                        load_reg( R_EAX, 0 );
nkeynes@361
   840
                        load_reg( R_ECX, Rm );
nkeynes@361
   841
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   842
                        check_ralign16( R_ECX );
nkeynes@361
   843
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   844
                        store_reg( R_EAX, Rn );
nkeynes@359
   845
                        }
nkeynes@359
   846
                        break;
nkeynes@359
   847
                    case 0xE:
nkeynes@359
   848
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   849
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   850
                        load_reg( R_EAX, 0 );
nkeynes@361
   851
                        load_reg( R_ECX, Rm );
nkeynes@361
   852
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   853
                        check_ralign32( R_ECX );
nkeynes@361
   854
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   855
                        store_reg( R_EAX, Rn );
nkeynes@359
   856
                        }
nkeynes@359
   857
                        break;
nkeynes@359
   858
                    case 0xF:
nkeynes@359
   859
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   860
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
   861
                        load_reg( R_ECX, Rm );
nkeynes@386
   862
                        check_ralign32( R_ECX );
nkeynes@386
   863
                        load_reg( R_ECX, Rn );
nkeynes@386
   864
                        check_ralign32( R_ECX );
nkeynes@386
   865
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386
   866
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   867
                        PUSH_r32( R_EAX );
nkeynes@386
   868
                        load_reg( R_ECX, Rm );
nkeynes@386
   869
                        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386
   870
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
   871
                        POP_r32( R_ECX );
nkeynes@386
   872
                        IMUL_r32( R_ECX );
nkeynes@386
   873
                        ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   874
                        ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   875
                    
nkeynes@386
   876
                        load_spreg( R_ECX, R_S );
nkeynes@386
   877
                        TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386
   878
                        JE_rel8( 7, nosat );
nkeynes@386
   879
                        call_func0( signsat48 );
nkeynes@386
   880
                        JMP_TARGET( nosat );
nkeynes@359
   881
                        }
nkeynes@359
   882
                        break;
nkeynes@359
   883
                    default:
nkeynes@359
   884
                        UNDEF();
nkeynes@359
   885
                        break;
nkeynes@359
   886
                }
nkeynes@359
   887
                break;
nkeynes@359
   888
            case 0x1:
nkeynes@359
   889
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   890
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   891
                load_reg( R_ECX, Rn );
nkeynes@361
   892
                load_reg( R_EAX, Rm );
nkeynes@361
   893
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   894
                check_walign32( R_ECX );
nkeynes@361
   895
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   896
                }
nkeynes@359
   897
                break;
nkeynes@359
   898
            case 0x2:
nkeynes@359
   899
                switch( ir&0xF ) {
nkeynes@359
   900
                    case 0x0:
nkeynes@359
   901
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   902
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   903
                        load_reg( R_EAX, Rm );
nkeynes@359
   904
                        load_reg( R_ECX, Rn );
nkeynes@359
   905
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   906
                        }
nkeynes@359
   907
                        break;
nkeynes@359
   908
                    case 0x1:
nkeynes@359
   909
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   910
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   911
                        load_reg( R_ECX, Rn );
nkeynes@374
   912
                        check_walign16( R_ECX );
nkeynes@386
   913
                        load_reg( R_EAX, Rm );
nkeynes@386
   914
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   915
                        }
nkeynes@359
   916
                        break;
nkeynes@359
   917
                    case 0x2:
nkeynes@359
   918
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   919
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   920
                        load_reg( R_EAX, Rm );
nkeynes@361
   921
                        load_reg( R_ECX, Rn );
nkeynes@374
   922
                        check_walign32(R_ECX);
nkeynes@361
   923
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   924
                        }
nkeynes@359
   925
                        break;
nkeynes@359
   926
                    case 0x4:
nkeynes@359
   927
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   928
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   929
                        load_reg( R_EAX, Rm );
nkeynes@359
   930
                        load_reg( R_ECX, Rn );
nkeynes@386
   931
                        ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   932
                        store_reg( R_ECX, Rn );
nkeynes@359
   933
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   934
                        }
nkeynes@359
   935
                        break;
nkeynes@359
   936
                    case 0x5:
nkeynes@359
   937
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   938
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   939
                        load_reg( R_ECX, Rn );
nkeynes@374
   940
                        check_walign16( R_ECX );
nkeynes@361
   941
                        load_reg( R_EAX, Rm );
nkeynes@361
   942
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@386
   943
                        store_reg( R_ECX, Rn );
nkeynes@361
   944
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   945
                        }
nkeynes@359
   946
                        break;
nkeynes@359
   947
                    case 0x6:
nkeynes@359
   948
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   949
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   950
                        load_reg( R_EAX, Rm );
nkeynes@361
   951
                        load_reg( R_ECX, Rn );
nkeynes@374
   952
                        check_walign32( R_ECX );
nkeynes@361
   953
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   954
                        store_reg( R_ECX, Rn );
nkeynes@361
   955
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   956
                        }
nkeynes@359
   957
                        break;
nkeynes@359
   958
                    case 0x7:
nkeynes@359
   959
                        { /* DIV0S Rm, Rn */
nkeynes@359
   960
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   961
                        load_reg( R_EAX, Rm );
nkeynes@386
   962
                        load_reg( R_ECX, Rn );
nkeynes@361
   963
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   964
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   965
                        store_spreg( R_EAX, R_M );
nkeynes@361
   966
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   967
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   968
                        SETNE_t();
nkeynes@359
   969
                        }
nkeynes@359
   970
                        break;
nkeynes@359
   971
                    case 0x8:
nkeynes@359
   972
                        { /* TST Rm, Rn */
nkeynes@359
   973
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   974
                        load_reg( R_EAX, Rm );
nkeynes@361
   975
                        load_reg( R_ECX, Rn );
nkeynes@361
   976
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   977
                        SETE_t();
nkeynes@359
   978
                        }
nkeynes@359
   979
                        break;
nkeynes@359
   980
                    case 0x9:
nkeynes@359
   981
                        { /* AND Rm, Rn */
nkeynes@359
   982
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   983
                        load_reg( R_EAX, Rm );
nkeynes@359
   984
                        load_reg( R_ECX, Rn );
nkeynes@359
   985
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   986
                        store_reg( R_ECX, Rn );
nkeynes@359
   987
                        }
nkeynes@359
   988
                        break;
nkeynes@359
   989
                    case 0xA:
nkeynes@359
   990
                        { /* XOR Rm, Rn */
nkeynes@359
   991
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   992
                        load_reg( R_EAX, Rm );
nkeynes@359
   993
                        load_reg( R_ECX, Rn );
nkeynes@359
   994
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   995
                        store_reg( R_ECX, Rn );
nkeynes@359
   996
                        }
nkeynes@359
   997
                        break;
nkeynes@359
   998
                    case 0xB:
nkeynes@359
   999
                        { /* OR Rm, Rn */
nkeynes@359
  1000
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1001
                        load_reg( R_EAX, Rm );
nkeynes@359
  1002
                        load_reg( R_ECX, Rn );
nkeynes@359
  1003
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1004
                        store_reg( R_ECX, Rn );
nkeynes@359
  1005
                        }
nkeynes@359
  1006
                        break;
nkeynes@359
  1007
                    case 0xC:
nkeynes@359
  1008
                        { /* CMP/STR Rm, Rn */
nkeynes@359
  1009
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1010
                        load_reg( R_EAX, Rm );
nkeynes@368
  1011
                        load_reg( R_ECX, Rn );
nkeynes@368
  1012
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
  1013
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@380
  1014
                        JE_rel8(13, target1);
nkeynes@368
  1015
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1016
                        JE_rel8(9, target2);
nkeynes@368
  1017
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
  1018
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
  1019
                        JE_rel8(2, target3);
nkeynes@368
  1020
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
  1021
                        JMP_TARGET(target1);
nkeynes@380
  1022
                        JMP_TARGET(target2);
nkeynes@380
  1023
                        JMP_TARGET(target3);
nkeynes@368
  1024
                        SETE_t();
nkeynes@359
  1025
                        }
nkeynes@359
  1026
                        break;
nkeynes@359
  1027
                    case 0xD:
nkeynes@359
  1028
                        { /* XTRCT Rm, Rn */
nkeynes@359
  1029
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1030
                        load_reg( R_EAX, Rm );
nkeynes@394
  1031
                        load_reg( R_ECX, Rn );
nkeynes@394
  1032
                        SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1033
                        SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1034
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1035
                        store_reg( R_ECX, Rn );
nkeynes@359
  1036
                        }
nkeynes@359
  1037
                        break;
nkeynes@359
  1038
                    case 0xE:
nkeynes@359
  1039
                        { /* MULU.W Rm, Rn */
nkeynes@359
  1040
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1041
                        load_reg16u( R_EAX, Rm );
nkeynes@374
  1042
                        load_reg16u( R_ECX, Rn );
nkeynes@374
  1043
                        MUL_r32( R_ECX );
nkeynes@374
  1044
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1045
                        }
nkeynes@359
  1046
                        break;
nkeynes@359
  1047
                    case 0xF:
nkeynes@359
  1048
                        { /* MULS.W Rm, Rn */
nkeynes@359
  1049
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1050
                        load_reg16s( R_EAX, Rm );
nkeynes@374
  1051
                        load_reg16s( R_ECX, Rn );
nkeynes@374
  1052
                        MUL_r32( R_ECX );
nkeynes@374
  1053
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1054
                        }
nkeynes@359
  1055
                        break;
nkeynes@359
  1056
                    default:
nkeynes@359
  1057
                        UNDEF();
nkeynes@359
  1058
                        break;
nkeynes@359
  1059
                }
nkeynes@359
  1060
                break;
nkeynes@359
  1061
            case 0x3:
nkeynes@359
  1062
                switch( ir&0xF ) {
nkeynes@359
  1063
                    case 0x0:
nkeynes@359
  1064
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
  1065
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1066
                        load_reg( R_EAX, Rm );
nkeynes@359
  1067
                        load_reg( R_ECX, Rn );
nkeynes@359
  1068
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1069
                        SETE_t();
nkeynes@359
  1070
                        }
nkeynes@359
  1071
                        break;
nkeynes@359
  1072
                    case 0x2:
nkeynes@359
  1073
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1074
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1075
                        load_reg( R_EAX, Rm );
nkeynes@359
  1076
                        load_reg( R_ECX, Rn );
nkeynes@359
  1077
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1078
                        SETAE_t();
nkeynes@359
  1079
                        }
nkeynes@359
  1080
                        break;
nkeynes@359
  1081
                    case 0x3:
nkeynes@359
  1082
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1083
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1084
                        load_reg( R_EAX, Rm );
nkeynes@359
  1085
                        load_reg( R_ECX, Rn );
nkeynes@359
  1086
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1087
                        SETGE_t();
nkeynes@359
  1088
                        }
nkeynes@359
  1089
                        break;
nkeynes@359
  1090
                    case 0x4:
nkeynes@359
  1091
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1092
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1093
                        load_spreg( R_ECX, R_M );
nkeynes@386
  1094
                        load_reg( R_EAX, Rn );
nkeynes@374
  1095
                        LDC_t();
nkeynes@386
  1096
                        RCL1_r32( R_EAX );
nkeynes@386
  1097
                        SETC_r8( R_DL ); // Q'
nkeynes@386
  1098
                        CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386
  1099
                        JE_rel8(5, mqequal);
nkeynes@386
  1100
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1101
                        JMP_rel8(3, end);
nkeynes@380
  1102
                        JMP_TARGET(mqequal);
nkeynes@386
  1103
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
  1104
                        JMP_TARGET(end);
nkeynes@386
  1105
                        store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
  1106
                        SETC_r8(R_AL); // tmp1
nkeynes@386
  1107
                        XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
  1108
                        XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
  1109
                        store_spreg( R_ECX, R_Q );
nkeynes@386
  1110
                        XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
  1111
                        MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
  1112
                        store_spreg( R_EAX, R_T );
nkeynes@359
  1113
                        }
nkeynes@359
  1114
                        break;
nkeynes@359
  1115
                    case 0x5:
nkeynes@359
  1116
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1117
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1118
                        load_reg( R_EAX, Rm );
nkeynes@361
  1119
                        load_reg( R_ECX, Rn );
nkeynes@361
  1120
                        MUL_r32(R_ECX);
nkeynes@361
  1121
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1122
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1123
                        }
nkeynes@359
  1124
                        break;
nkeynes@359
  1125
                    case 0x6:
nkeynes@359
  1126
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1127
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1128
                        load_reg( R_EAX, Rm );
nkeynes@359
  1129
                        load_reg( R_ECX, Rn );
nkeynes@359
  1130
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1131
                        SETA_t();
nkeynes@359
  1132
                        }
nkeynes@359
  1133
                        break;
nkeynes@359
  1134
                    case 0x7:
nkeynes@359
  1135
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1136
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1137
                        load_reg( R_EAX, Rm );
nkeynes@359
  1138
                        load_reg( R_ECX, Rn );
nkeynes@359
  1139
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1140
                        SETG_t();
nkeynes@359
  1141
                        }
nkeynes@359
  1142
                        break;
nkeynes@359
  1143
                    case 0x8:
nkeynes@359
  1144
                        { /* SUB Rm, Rn */
nkeynes@359
  1145
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1146
                        load_reg( R_EAX, Rm );
nkeynes@359
  1147
                        load_reg( R_ECX, Rn );
nkeynes@359
  1148
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1149
                        store_reg( R_ECX, Rn );
nkeynes@359
  1150
                        }
nkeynes@359
  1151
                        break;
nkeynes@359
  1152
                    case 0xA:
nkeynes@359
  1153
                        { /* SUBC Rm, Rn */
nkeynes@359
  1154
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1155
                        load_reg( R_EAX, Rm );
nkeynes@359
  1156
                        load_reg( R_ECX, Rn );
nkeynes@359
  1157
                        LDC_t();
nkeynes@359
  1158
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1159
                        store_reg( R_ECX, Rn );
nkeynes@394
  1160
                        SETC_t();
nkeynes@359
  1161
                        }
nkeynes@359
  1162
                        break;
nkeynes@359
  1163
                    case 0xB:
nkeynes@359
  1164
                        { /* SUBV Rm, Rn */
nkeynes@359
  1165
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1166
                        load_reg( R_EAX, Rm );
nkeynes@359
  1167
                        load_reg( R_ECX, Rn );
nkeynes@359
  1168
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1169
                        store_reg( R_ECX, Rn );
nkeynes@359
  1170
                        SETO_t();
nkeynes@359
  1171
                        }
nkeynes@359
  1172
                        break;
nkeynes@359
  1173
                    case 0xC:
nkeynes@359
  1174
                        { /* ADD Rm, Rn */
nkeynes@359
  1175
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1176
                        load_reg( R_EAX, Rm );
nkeynes@359
  1177
                        load_reg( R_ECX, Rn );
nkeynes@359
  1178
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1179
                        store_reg( R_ECX, Rn );
nkeynes@359
  1180
                        }
nkeynes@359
  1181
                        break;
nkeynes@359
  1182
                    case 0xD:
nkeynes@359
  1183
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1184
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1185
                        load_reg( R_EAX, Rm );
nkeynes@361
  1186
                        load_reg( R_ECX, Rn );
nkeynes@361
  1187
                        IMUL_r32(R_ECX);
nkeynes@361
  1188
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1189
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1190
                        }
nkeynes@359
  1191
                        break;
nkeynes@359
  1192
                    case 0xE:
nkeynes@359
  1193
                        { /* ADDC Rm, Rn */
nkeynes@359
  1194
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1195
                        load_reg( R_EAX, Rm );
nkeynes@359
  1196
                        load_reg( R_ECX, Rn );
nkeynes@359
  1197
                        LDC_t();
nkeynes@359
  1198
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1199
                        store_reg( R_ECX, Rn );
nkeynes@359
  1200
                        SETC_t();
nkeynes@359
  1201
                        }
nkeynes@359
  1202
                        break;
nkeynes@359
  1203
                    case 0xF:
nkeynes@359
  1204
                        { /* ADDV Rm, Rn */
nkeynes@359
  1205
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1206
                        load_reg( R_EAX, Rm );
nkeynes@359
  1207
                        load_reg( R_ECX, Rn );
nkeynes@359
  1208
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1209
                        store_reg( R_ECX, Rn );
nkeynes@359
  1210
                        SETO_t();
nkeynes@359
  1211
                        }
nkeynes@359
  1212
                        break;
nkeynes@359
  1213
                    default:
nkeynes@359
  1214
                        UNDEF();
nkeynes@359
  1215
                        break;
nkeynes@359
  1216
                }
nkeynes@359
  1217
                break;
nkeynes@359
  1218
            case 0x4:
nkeynes@359
  1219
                switch( ir&0xF ) {
nkeynes@359
  1220
                    case 0x0:
nkeynes@359
  1221
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1222
                            case 0x0:
nkeynes@359
  1223
                                { /* SHLL Rn */
nkeynes@359
  1224
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1225
                                load_reg( R_EAX, Rn );
nkeynes@359
  1226
                                SHL1_r32( R_EAX );
nkeynes@397
  1227
                                SETC_t();
nkeynes@359
  1228
                                store_reg( R_EAX, Rn );
nkeynes@359
  1229
                                }
nkeynes@359
  1230
                                break;
nkeynes@359
  1231
                            case 0x1:
nkeynes@359
  1232
                                { /* DT Rn */
nkeynes@359
  1233
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1234
                                load_reg( R_EAX, Rn );
nkeynes@386
  1235
                                ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
  1236
                                store_reg( R_EAX, Rn );
nkeynes@359
  1237
                                SETE_t();
nkeynes@359
  1238
                                }
nkeynes@359
  1239
                                break;
nkeynes@359
  1240
                            case 0x2:
nkeynes@359
  1241
                                { /* SHAL Rn */
nkeynes@359
  1242
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1243
                                load_reg( R_EAX, Rn );
nkeynes@359
  1244
                                SHL1_r32( R_EAX );
nkeynes@397
  1245
                                SETC_t();
nkeynes@359
  1246
                                store_reg( R_EAX, Rn );
nkeynes@359
  1247
                                }
nkeynes@359
  1248
                                break;
nkeynes@359
  1249
                            default:
nkeynes@359
  1250
                                UNDEF();
nkeynes@359
  1251
                                break;
nkeynes@359
  1252
                        }
nkeynes@359
  1253
                        break;
nkeynes@359
  1254
                    case 0x1:
nkeynes@359
  1255
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1256
                            case 0x0:
nkeynes@359
  1257
                                { /* SHLR Rn */
nkeynes@359
  1258
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1259
                                load_reg( R_EAX, Rn );
nkeynes@359
  1260
                                SHR1_r32( R_EAX );
nkeynes@397
  1261
                                SETC_t();
nkeynes@359
  1262
                                store_reg( R_EAX, Rn );
nkeynes@359
  1263
                                }
nkeynes@359
  1264
                                break;
nkeynes@359
  1265
                            case 0x1:
nkeynes@359
  1266
                                { /* CMP/PZ Rn */
nkeynes@359
  1267
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1268
                                load_reg( R_EAX, Rn );
nkeynes@359
  1269
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1270
                                SETGE_t();
nkeynes@359
  1271
                                }
nkeynes@359
  1272
                                break;
nkeynes@359
  1273
                            case 0x2:
nkeynes@359
  1274
                                { /* SHAR Rn */
nkeynes@359
  1275
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1276
                                load_reg( R_EAX, Rn );
nkeynes@359
  1277
                                SAR1_r32( R_EAX );
nkeynes@397
  1278
                                SETC_t();
nkeynes@359
  1279
                                store_reg( R_EAX, Rn );
nkeynes@359
  1280
                                }
nkeynes@359
  1281
                                break;
nkeynes@359
  1282
                            default:
nkeynes@359
  1283
                                UNDEF();
nkeynes@359
  1284
                                break;
nkeynes@359
  1285
                        }
nkeynes@359
  1286
                        break;
nkeynes@359
  1287
                    case 0x2:
nkeynes@359
  1288
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1289
                            case 0x0:
nkeynes@359
  1290
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1291
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1292
                                load_reg( R_ECX, Rn );
nkeynes@395
  1293
                                check_walign32( R_ECX );
nkeynes@386
  1294
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1295
                                store_reg( R_ECX, Rn );
nkeynes@359
  1296
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1297
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1298
                                }
nkeynes@359
  1299
                                break;
nkeynes@359
  1300
                            case 0x1:
nkeynes@359
  1301
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1302
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1303
                                load_reg( R_ECX, Rn );
nkeynes@395
  1304
                                check_walign32( R_ECX );
nkeynes@386
  1305
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1306
                                store_reg( R_ECX, Rn );
nkeynes@359
  1307
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1308
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1309
                                }
nkeynes@359
  1310
                                break;
nkeynes@359
  1311
                            case 0x2:
nkeynes@359
  1312
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1313
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1314
                                load_reg( R_ECX, Rn );
nkeynes@395
  1315
                                check_walign32( R_ECX );
nkeynes@386
  1316
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1317
                                store_reg( R_ECX, Rn );
nkeynes@359
  1318
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1319
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1320
                                }
nkeynes@359
  1321
                                break;
nkeynes@359
  1322
                            case 0x3:
nkeynes@359
  1323
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1324
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1325
                                check_priv();
nkeynes@359
  1326
                                load_reg( R_ECX, Rn );
nkeynes@395
  1327
                                check_walign32( R_ECX );
nkeynes@386
  1328
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1329
                                store_reg( R_ECX, Rn );
nkeynes@359
  1330
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1331
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1332
                                }
nkeynes@359
  1333
                                break;
nkeynes@359
  1334
                            case 0x5:
nkeynes@359
  1335
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1336
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1337
                                load_reg( R_ECX, Rn );
nkeynes@395
  1338
                                check_walign32( R_ECX );
nkeynes@386
  1339
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1340
                                store_reg( R_ECX, Rn );
nkeynes@359
  1341
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1342
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1343
                                }
nkeynes@359
  1344
                                break;
nkeynes@359
  1345
                            case 0x6:
nkeynes@359
  1346
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1347
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1348
                                load_reg( R_ECX, Rn );
nkeynes@395
  1349
                                check_walign32( R_ECX );
nkeynes@386
  1350
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1351
                                store_reg( R_ECX, Rn );
nkeynes@359
  1352
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1353
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1354
                                }
nkeynes@359
  1355
                                break;
nkeynes@359
  1356
                            case 0xF:
nkeynes@359
  1357
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1358
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1359
                                check_priv();
nkeynes@359
  1360
                                load_reg( R_ECX, Rn );
nkeynes@395
  1361
                                check_walign32( R_ECX );
nkeynes@386
  1362
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1363
                                store_reg( R_ECX, Rn );
nkeynes@359
  1364
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1365
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1366
                                }
nkeynes@359
  1367
                                break;
nkeynes@359
  1368
                            default:
nkeynes@359
  1369
                                UNDEF();
nkeynes@359
  1370
                                break;
nkeynes@359
  1371
                        }
nkeynes@359
  1372
                        break;
nkeynes@359
  1373
                    case 0x3:
nkeynes@359
  1374
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1375
                            case 0x0:
nkeynes@359
  1376
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1377
                                    case 0x0:
nkeynes@359
  1378
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1379
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1380
                                        check_priv();
nkeynes@395
  1381
                                        call_func0( sh4_read_sr );
nkeynes@374
  1382
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1383
                                        check_walign32( R_ECX );
nkeynes@386
  1384
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1385
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1386
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1387
                                        }
nkeynes@359
  1388
                                        break;
nkeynes@359
  1389
                                    case 0x1:
nkeynes@359
  1390
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1391
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1392
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1393
                                        check_walign32( R_ECX );
nkeynes@386
  1394
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1395
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1396
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1397
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1398
                                        }
nkeynes@359
  1399
                                        break;
nkeynes@359
  1400
                                    case 0x2:
nkeynes@359
  1401
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1402
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1403
                                        check_priv();
nkeynes@359
  1404
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1405
                                        check_walign32( R_ECX );
nkeynes@386
  1406
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1407
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1408
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1409
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1410
                                        }
nkeynes@359
  1411
                                        break;
nkeynes@359
  1412
                                    case 0x3:
nkeynes@359
  1413
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1414
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1415
                                        check_priv();
nkeynes@359
  1416
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1417
                                        check_walign32( R_ECX );
nkeynes@386
  1418
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1419
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1420
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1421
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1422
                                        }
nkeynes@359
  1423
                                        break;
nkeynes@359
  1424
                                    case 0x4:
nkeynes@359
  1425
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1426
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@386
  1427
                                        check_priv();
nkeynes@359
  1428
                                        load_reg( R_ECX, Rn );
nkeynes@395
  1429
                                        check_walign32( R_ECX );
nkeynes@386
  1430
                                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  1431
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1432
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1433
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1434
                                        }
nkeynes@359
  1435
                                        break;
nkeynes@359
  1436
                                    default:
nkeynes@359
  1437
                                        UNDEF();
nkeynes@359
  1438
                                        break;
nkeynes@359
  1439
                                }
nkeynes@359
  1440
                                break;
nkeynes@359
  1441
                            case 0x1:
nkeynes@359
  1442
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1443
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1444
                                check_priv();
nkeynes@374
  1445
                                load_reg( R_ECX, Rn );
nkeynes@395
  1446
                                check_walign32( R_ECX );
nkeynes@386
  1447
                                ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  1448
                                store_reg( R_ECX, Rn );
nkeynes@374
  1449
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1450
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1451
                                }
nkeynes@359
  1452
                                break;
nkeynes@359
  1453
                        }
nkeynes@359
  1454
                        break;
nkeynes@359
  1455
                    case 0x4:
nkeynes@359
  1456
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1457
                            case 0x0:
nkeynes@359
  1458
                                { /* ROTL Rn */
nkeynes@359
  1459
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1460
                                load_reg( R_EAX, Rn );
nkeynes@359
  1461
                                ROL1_r32( R_EAX );
nkeynes@359
  1462
                                store_reg( R_EAX, Rn );
nkeynes@359
  1463
                                SETC_t();
nkeynes@359
  1464
                                }
nkeynes@359
  1465
                                break;
nkeynes@359
  1466
                            case 0x2:
nkeynes@359
  1467
                                { /* ROTCL Rn */
nkeynes@359
  1468
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1469
                                load_reg( R_EAX, Rn );
nkeynes@359
  1470
                                LDC_t();
nkeynes@359
  1471
                                RCL1_r32( R_EAX );
nkeynes@359
  1472
                                store_reg( R_EAX, Rn );
nkeynes@359
  1473
                                SETC_t();
nkeynes@359
  1474
                                }
nkeynes@359
  1475
                                break;
nkeynes@359
  1476
                            default:
nkeynes@359
  1477
                                UNDEF();
nkeynes@359
  1478
                                break;
nkeynes@359
  1479
                        }
nkeynes@359
  1480
                        break;
nkeynes@359
  1481
                    case 0x5:
nkeynes@359
  1482
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1483
                            case 0x0:
nkeynes@359
  1484
                                { /* ROTR Rn */
nkeynes@359
  1485
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1486
                                load_reg( R_EAX, Rn );
nkeynes@359
  1487
                                ROR1_r32( R_EAX );
nkeynes@359
  1488
                                store_reg( R_EAX, Rn );
nkeynes@359
  1489
                                SETC_t();
nkeynes@359
  1490
                                }
nkeynes@359
  1491
                                break;
nkeynes@359
  1492
                            case 0x1:
nkeynes@359
  1493
                                { /* CMP/PL Rn */
nkeynes@359
  1494
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1495
                                load_reg( R_EAX, Rn );
nkeynes@359
  1496
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1497
                                SETG_t();
nkeynes@359
  1498
                                }
nkeynes@359
  1499
                                break;
nkeynes@359
  1500
                            case 0x2:
nkeynes@359
  1501
                                { /* ROTCR Rn */
nkeynes@359
  1502
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1503
                                load_reg( R_EAX, Rn );
nkeynes@359
  1504
                                LDC_t();
nkeynes@359
  1505
                                RCR1_r32( R_EAX );
nkeynes@359
  1506
                                store_reg( R_EAX, Rn );
nkeynes@359
  1507
                                SETC_t();
nkeynes@359
  1508
                                }
nkeynes@359
  1509
                                break;
nkeynes@359
  1510
                            default:
nkeynes@359
  1511
                                UNDEF();
nkeynes@359
  1512
                                break;
nkeynes@359
  1513
                        }
nkeynes@359
  1514
                        break;
nkeynes@359
  1515
                    case 0x6:
nkeynes@359
  1516
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1517
                            case 0x0:
nkeynes@359
  1518
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1519
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1520
                                load_reg( R_EAX, Rm );
nkeynes@395
  1521
                                check_ralign32( R_EAX );
nkeynes@359
  1522
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1523
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1524
                                store_reg( R_EAX, Rm );
nkeynes@359
  1525
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1526
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1527
                                }
nkeynes@359
  1528
                                break;
nkeynes@359
  1529
                            case 0x1:
nkeynes@359
  1530
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1531
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1532
                                load_reg( R_EAX, Rm );
nkeynes@395
  1533
                                check_ralign32( R_EAX );
nkeynes@359
  1534
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1535
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1536
                                store_reg( R_EAX, Rm );
nkeynes@359
  1537
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1538
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1539
                                }
nkeynes@359
  1540
                                break;
nkeynes@359
  1541
                            case 0x2:
nkeynes@359
  1542
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1543
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1544
                                load_reg( R_EAX, Rm );
nkeynes@395
  1545
                                check_ralign32( R_EAX );
nkeynes@359
  1546
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1547
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1548
                                store_reg( R_EAX, Rm );
nkeynes@359
  1549
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1550
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1551
                                }
nkeynes@359
  1552
                                break;
nkeynes@359
  1553
                            case 0x3:
nkeynes@359
  1554
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1555
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1556
                                check_priv();
nkeynes@359
  1557
                                load_reg( R_EAX, Rm );
nkeynes@395
  1558
                                check_ralign32( R_EAX );
nkeynes@359
  1559
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1560
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1561
                                store_reg( R_EAX, Rm );
nkeynes@359
  1562
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1563
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1564
                                }
nkeynes@359
  1565
                                break;
nkeynes@359
  1566
                            case 0x5:
nkeynes@359
  1567
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1568
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1569
                                load_reg( R_EAX, Rm );
nkeynes@395
  1570
                                check_ralign32( R_EAX );
nkeynes@359
  1571
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1572
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1573
                                store_reg( R_EAX, Rm );
nkeynes@359
  1574
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1575
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1576
                                }
nkeynes@359
  1577
                                break;
nkeynes@359
  1578
                            case 0x6:
nkeynes@359
  1579
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1580
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1581
                                load_reg( R_EAX, Rm );
nkeynes@395
  1582
                                check_ralign32( R_EAX );
nkeynes@359
  1583
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1584
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1585
                                store_reg( R_EAX, Rm );
nkeynes@359
  1586
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1587
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1588
                                update_fr_bank( R_EAX );
nkeynes@359
  1589
                                }
nkeynes@359
  1590
                                break;
nkeynes@359
  1591
                            case 0xF:
nkeynes@359
  1592
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1593
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1594
                                check_priv();
nkeynes@359
  1595
                                load_reg( R_EAX, Rm );
nkeynes@395
  1596
                                check_ralign32( R_EAX );
nkeynes@359
  1597
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1598
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1599
                                store_reg( R_EAX, Rm );
nkeynes@359
  1600
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1601
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1602
                                }
nkeynes@359
  1603
                                break;
nkeynes@359
  1604
                            default:
nkeynes@359
  1605
                                UNDEF();
nkeynes@359
  1606
                                break;
nkeynes@359
  1607
                        }
nkeynes@359
  1608
                        break;
nkeynes@359
  1609
                    case 0x7:
nkeynes@359
  1610
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1611
                            case 0x0:
nkeynes@359
  1612
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1613
                                    case 0x0:
nkeynes@359
  1614
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1615
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1616
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1617
                                    	SLOTILLEGAL();
nkeynes@386
  1618
                                        } else {
nkeynes@386
  1619
                                    	check_priv();
nkeynes@386
  1620
                                    	load_reg( R_EAX, Rm );
nkeynes@395
  1621
                                    	check_ralign32( R_EAX );
nkeynes@386
  1622
                                    	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386
  1623
                                    	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386
  1624
                                    	store_reg( R_EAX, Rm );
nkeynes@386
  1625
                                    	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386
  1626
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1627
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1628
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  1629
                                        }
nkeynes@359
  1630
                                        }
nkeynes@359
  1631
                                        break;
nkeynes@359
  1632
                                    case 0x1:
nkeynes@359
  1633
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1634
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1635
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1636
                                        check_ralign32( R_EAX );
nkeynes@359
  1637
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1638
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1639
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1640
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1641
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1642
                                        }
nkeynes@359
  1643
                                        break;
nkeynes@359
  1644
                                    case 0x2:
nkeynes@359
  1645
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1646
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1647
                                        check_priv();
nkeynes@359
  1648
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1649
                                        check_ralign32( R_EAX );
nkeynes@359
  1650
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1651
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1652
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1653
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1654
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1655
                                        }
nkeynes@359
  1656
                                        break;
nkeynes@359
  1657
                                    case 0x3:
nkeynes@359
  1658
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1659
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1660
                                        check_priv();
nkeynes@359
  1661
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1662
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1663
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1664
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1665
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1666
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1667
                                        }
nkeynes@359
  1668
                                        break;
nkeynes@359
  1669
                                    case 0x4:
nkeynes@359
  1670
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1671
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1672
                                        check_priv();
nkeynes@359
  1673
                                        load_reg( R_EAX, Rm );
nkeynes@395
  1674
                                        check_ralign32( R_EAX );
nkeynes@359
  1675
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1676
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1677
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1678
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1679
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1680
                                        }
nkeynes@359
  1681
                                        break;
nkeynes@359
  1682
                                    default:
nkeynes@359
  1683
                                        UNDEF();
nkeynes@359
  1684
                                        break;
nkeynes@359
  1685
                                }
nkeynes@359
  1686
                                break;
nkeynes@359
  1687
                            case 0x1:
nkeynes@359
  1688
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1689
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1690
                                check_priv();
nkeynes@374
  1691
                                load_reg( R_EAX, Rm );
nkeynes@395
  1692
                                check_ralign32( R_EAX );
nkeynes@374
  1693
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1694
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1695
                                store_reg( R_EAX, Rm );
nkeynes@374
  1696
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1697
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1698
                                }
nkeynes@359
  1699
                                break;
nkeynes@359
  1700
                        }
nkeynes@359
  1701
                        break;
nkeynes@359
  1702
                    case 0x8:
nkeynes@359
  1703
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1704
                            case 0x0:
nkeynes@359
  1705
                                { /* SHLL2 Rn */
nkeynes@359
  1706
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1707
                                load_reg( R_EAX, Rn );
nkeynes@359
  1708
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1709
                                store_reg( R_EAX, Rn );
nkeynes@359
  1710
                                }
nkeynes@359
  1711
                                break;
nkeynes@359
  1712
                            case 0x1:
nkeynes@359
  1713
                                { /* SHLL8 Rn */
nkeynes@359
  1714
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1715
                                load_reg( R_EAX, Rn );
nkeynes@359
  1716
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1717
                                store_reg( R_EAX, Rn );
nkeynes@359
  1718
                                }
nkeynes@359
  1719
                                break;
nkeynes@359
  1720
                            case 0x2:
nkeynes@359
  1721
                                { /* SHLL16 Rn */
nkeynes@359
  1722
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1723
                                load_reg( R_EAX, Rn );
nkeynes@359
  1724
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1725
                                store_reg( R_EAX, Rn );
nkeynes@359
  1726
                                }
nkeynes@359
  1727
                                break;
nkeynes@359
  1728
                            default:
nkeynes@359
  1729
                                UNDEF();
nkeynes@359
  1730
                                break;
nkeynes@359
  1731
                        }
nkeynes@359
  1732
                        break;
nkeynes@359
  1733
                    case 0x9:
nkeynes@359
  1734
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1735
                            case 0x0:
nkeynes@359
  1736
                                { /* SHLR2 Rn */
nkeynes@359
  1737
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1738
                                load_reg( R_EAX, Rn );
nkeynes@359
  1739
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1740
                                store_reg( R_EAX, Rn );
nkeynes@359
  1741
                                }
nkeynes@359
  1742
                                break;
nkeynes@359
  1743
                            case 0x1:
nkeynes@359
  1744
                                { /* SHLR8 Rn */
nkeynes@359
  1745
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1746
                                load_reg( R_EAX, Rn );
nkeynes@359
  1747
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1748
                                store_reg( R_EAX, Rn );
nkeynes@359
  1749
                                }
nkeynes@359
  1750
                                break;
nkeynes@359
  1751
                            case 0x2:
nkeynes@359
  1752
                                { /* SHLR16 Rn */
nkeynes@359
  1753
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1754
                                load_reg( R_EAX, Rn );
nkeynes@359
  1755
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1756
                                store_reg( R_EAX, Rn );
nkeynes@359
  1757
                                }
nkeynes@359
  1758
                                break;
nkeynes@359
  1759
                            default:
nkeynes@359
  1760
                                UNDEF();
nkeynes@359
  1761
                                break;
nkeynes@359
  1762
                        }
nkeynes@359
  1763
                        break;
nkeynes@359
  1764
                    case 0xA:
nkeynes@359
  1765
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1766
                            case 0x0:
nkeynes@359
  1767
                                { /* LDS Rm, MACH */
nkeynes@359
  1768
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1769
                                load_reg( R_EAX, Rm );
nkeynes@359
  1770
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1771
                                }
nkeynes@359
  1772
                                break;
nkeynes@359
  1773
                            case 0x1:
nkeynes@359
  1774
                                { /* LDS Rm, MACL */
nkeynes@359
  1775
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1776
                                load_reg( R_EAX, Rm );
nkeynes@359
  1777
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1778
                                }
nkeynes@359
  1779
                                break;
nkeynes@359
  1780
                            case 0x2:
nkeynes@359
  1781
                                { /* LDS Rm, PR */
nkeynes@359
  1782
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1783
                                load_reg( R_EAX, Rm );
nkeynes@359
  1784
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1785
                                }
nkeynes@359
  1786
                                break;
nkeynes@359
  1787
                            case 0x3:
nkeynes@359
  1788
                                { /* LDC Rm, SGR */
nkeynes@359
  1789
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1790
                                check_priv();
nkeynes@359
  1791
                                load_reg( R_EAX, Rm );
nkeynes@359
  1792
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1793
                                }
nkeynes@359
  1794
                                break;
nkeynes@359
  1795
                            case 0x5:
nkeynes@359
  1796
                                { /* LDS Rm, FPUL */
nkeynes@359
  1797
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1798
                                load_reg( R_EAX, Rm );
nkeynes@359
  1799
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1800
                                }
nkeynes@359
  1801
                                break;
nkeynes@359
  1802
                            case 0x6:
nkeynes@359
  1803
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1804
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1805
                                load_reg( R_EAX, Rm );
nkeynes@359
  1806
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@386
  1807
                                update_fr_bank( R_EAX );
nkeynes@359
  1808
                                }
nkeynes@359
  1809
                                break;
nkeynes@359
  1810
                            case 0xF:
nkeynes@359
  1811
                                { /* LDC Rm, DBR */
nkeynes@359
  1812
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1813
                                check_priv();
nkeynes@359
  1814
                                load_reg( R_EAX, Rm );
nkeynes@359
  1815
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1816
                                }
nkeynes@359
  1817
                                break;
nkeynes@359
  1818
                            default:
nkeynes@359
  1819
                                UNDEF();
nkeynes@359
  1820
                                break;
nkeynes@359
  1821
                        }
nkeynes@359
  1822
                        break;
nkeynes@359
  1823
                    case 0xB:
nkeynes@359
  1824
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1825
                            case 0x0:
nkeynes@359
  1826
                                { /* JSR @Rn */
nkeynes@359
  1827
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1828
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1829
                            	SLOTILLEGAL();
nkeynes@374
  1830
                                } else {
nkeynes@374
  1831
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1832
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
  1833
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1834
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1835
                            	return 0;
nkeynes@374
  1836
                                }
nkeynes@359
  1837
                                }
nkeynes@359
  1838
                                break;
nkeynes@359
  1839
                            case 0x1:
nkeynes@359
  1840
                                { /* TAS.B @Rn */
nkeynes@359
  1841
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1842
                                load_reg( R_ECX, Rn );
nkeynes@361
  1843
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1844
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1845
                                SETE_t();
nkeynes@361
  1846
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@386
  1847
                                load_reg( R_ECX, Rn );
nkeynes@361
  1848
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1849
                                }
nkeynes@359
  1850
                                break;
nkeynes@359
  1851
                            case 0x2:
nkeynes@359
  1852
                                { /* JMP @Rn */
nkeynes@359
  1853
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1854
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1855
                            	SLOTILLEGAL();
nkeynes@374
  1856
                                } else {
nkeynes@374
  1857
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1858
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1859
                            	return 0;
nkeynes@374
  1860
                                }
nkeynes@359
  1861
                                }
nkeynes@359
  1862
                                break;
nkeynes@359
  1863
                            default:
nkeynes@359
  1864
                                UNDEF();
nkeynes@359
  1865
                                break;
nkeynes@359
  1866
                        }
nkeynes@359
  1867
                        break;
nkeynes@359
  1868
                    case 0xC:
nkeynes@359
  1869
                        { /* SHAD Rm, Rn */
nkeynes@359
  1870
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1871
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1872
                        load_reg( R_EAX, Rn );
nkeynes@361
  1873
                        load_reg( R_ECX, Rm );
nkeynes@361
  1874
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1875
                        JGE_rel8(16, doshl);
nkeynes@361
  1876
                                        
nkeynes@361
  1877
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1878
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1879
                        JE_rel8( 4, emptysar);     // 2
nkeynes@361
  1880
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@386
  1881
                        JMP_rel8(10, end);          // 2
nkeynes@386
  1882
                    
nkeynes@386
  1883
                        JMP_TARGET(emptysar);
nkeynes@386
  1884
                        SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@386
  1885
                        JMP_rel8(5, end2);
nkeynes@386
  1886
                    
nkeynes@380
  1887
                        JMP_TARGET(doshl);
nkeynes@361
  1888
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1889
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@380
  1890
                        JMP_TARGET(end);
nkeynes@386
  1891
                        JMP_TARGET(end2);
nkeynes@361
  1892
                        store_reg( R_EAX, Rn );
nkeynes@359
  1893
                        }
nkeynes@359
  1894
                        break;
nkeynes@359
  1895
                    case 0xD:
nkeynes@359
  1896
                        { /* SHLD Rm, Rn */
nkeynes@359
  1897
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1898
                        load_reg( R_EAX, Rn );
nkeynes@368
  1899
                        load_reg( R_ECX, Rm );
nkeynes@386
  1900
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@386
  1901
                        JGE_rel8(15, doshl);
nkeynes@368
  1902
                    
nkeynes@386
  1903
                        NEG_r32( R_ECX );      // 2
nkeynes@386
  1904
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1905
                        JE_rel8( 4, emptyshr );
nkeynes@386
  1906
                        SHR_r32_CL( R_EAX );       // 2
nkeynes@386
  1907
                        JMP_rel8(9, end);          // 2
nkeynes@386
  1908
                    
nkeynes@386
  1909
                        JMP_TARGET(emptyshr);
nkeynes@386
  1910
                        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386
  1911
                        JMP_rel8(5, end2);
nkeynes@386
  1912
                    
nkeynes@386
  1913
                        JMP_TARGET(doshl);
nkeynes@386
  1914
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386
  1915
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@386
  1916
                        JMP_TARGET(end);
nkeynes@386
  1917
                        JMP_TARGET(end2);
nkeynes@368
  1918
                        store_reg( R_EAX, Rn );
nkeynes@359
  1919
                        }
nkeynes@359
  1920
                        break;
nkeynes@359
  1921
                    case 0xE:
nkeynes@359
  1922
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1923
                            case 0x0:
nkeynes@359
  1924
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1925
                                    case 0x0:
nkeynes@359
  1926
                                        { /* LDC Rm, SR */
nkeynes@359
  1927
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1928
                                        if( sh4_x86.in_delay_slot ) {
nkeynes@386
  1929
                                    	SLOTILLEGAL();
nkeynes@386
  1930
                                        } else {
nkeynes@386
  1931
                                    	check_priv();
nkeynes@386
  1932
                                    	load_reg( R_EAX, Rm );
nkeynes@386
  1933
                                    	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  1934
                                    	sh4_x86.priv_checked = FALSE;
nkeynes@386
  1935
                                    	sh4_x86.fpuen_checked = FALSE;
nkeynes@386
  1936
                                        }
nkeynes@359
  1937
                                        }
nkeynes@359
  1938
                                        break;
nkeynes@359
  1939
                                    case 0x1:
nkeynes@359
  1940
                                        { /* LDC Rm, GBR */
nkeynes@359
  1941
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1942
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1943
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1944
                                        }
nkeynes@359
  1945
                                        break;
nkeynes@359
  1946
                                    case 0x2:
nkeynes@359
  1947
                                        { /* LDC Rm, VBR */
nkeynes@359
  1948
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1949
                                        check_priv();
nkeynes@359
  1950
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1951
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1952
                                        }
nkeynes@359
  1953
                                        break;
nkeynes@359
  1954
                                    case 0x3:
nkeynes@359
  1955
                                        { /* LDC Rm, SSR */
nkeynes@359
  1956
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1957
                                        check_priv();
nkeynes@359
  1958
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1959
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1960
                                        }
nkeynes@359
  1961
                                        break;
nkeynes@359
  1962
                                    case 0x4:
nkeynes@359
  1963
                                        { /* LDC Rm, SPC */
nkeynes@359
  1964
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@386
  1965
                                        check_priv();
nkeynes@359
  1966
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1967
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1968
                                        }
nkeynes@359
  1969
                                        break;
nkeynes@359
  1970
                                    default:
nkeynes@359
  1971
                                        UNDEF();
nkeynes@359
  1972
                                        break;
nkeynes@359
  1973
                                }
nkeynes@359
  1974
                                break;
nkeynes@359
  1975
                            case 0x1:
nkeynes@359
  1976
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1977
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@386
  1978
                                check_priv();
nkeynes@374
  1979
                                load_reg( R_EAX, Rm );
nkeynes@374
  1980
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1981
                                }
nkeynes@359
  1982
                                break;
nkeynes@359
  1983
                        }
nkeynes@359
  1984
                        break;
nkeynes@359
  1985
                    case 0xF:
nkeynes@359
  1986
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1987
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@386
  1988
                        load_reg( R_ECX, Rm );
nkeynes@386
  1989
                        check_ralign16( R_ECX );
nkeynes@386
  1990
                        load_reg( R_ECX, Rn );
nkeynes@386
  1991
                        check_ralign16( R_ECX );
nkeynes@386
  1992
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386
  1993
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  1994
                        PUSH_r32( R_EAX );
nkeynes@386
  1995
                        load_reg( R_ECX, Rm );
nkeynes@386
  1996
                        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386
  1997
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386
  1998
                        POP_r32( R_ECX );
nkeynes@386
  1999
                        IMUL_r32( R_ECX );
nkeynes@386
  2000
                    
nkeynes@386
  2001
                        load_spreg( R_ECX, R_S );
nkeynes@386
  2002
                        TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386
  2003
                        JE_rel8( 47, nosat );
nkeynes@386
  2004
                    
nkeynes@386
  2005
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2006
                        JNO_rel8( 51, end );            // 2
nkeynes@386
  2007
                        load_imm32( R_EDX, 1 );         // 5
nkeynes@386
  2008
                        store_spreg( R_EDX, R_MACH );   // 6
nkeynes@386
  2009
                        JS_rel8( 13, positive );        // 2
nkeynes@386
  2010
                        load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
  2011
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2012
                        JMP_rel8( 25, end2 );           // 2
nkeynes@386
  2013
                    
nkeynes@386
  2014
                        JMP_TARGET(positive);
nkeynes@386
  2015
                        load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
  2016
                        store_spreg( R_EAX, R_MACL );   // 6
nkeynes@386
  2017
                        JMP_rel8( 12, end3);            // 2
nkeynes@386
  2018
                    
nkeynes@386
  2019
                        JMP_TARGET(nosat);
nkeynes@386
  2020
                        ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
  2021
                        ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
  2022
                        JMP_TARGET(end);
nkeynes@386
  2023
                        JMP_TARGET(end2);
nkeynes@386
  2024
                        JMP_TARGET(end3);
nkeynes@359
  2025
                        }
nkeynes@359
  2026
                        break;
nkeynes@359
  2027
                }
nkeynes@359
  2028
                break;
nkeynes@359
  2029
            case 0x5:
nkeynes@359
  2030
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  2031
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  2032
                load_reg( R_ECX, Rm );
nkeynes@361
  2033
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  2034
                check_ralign32( R_ECX );
nkeynes@361
  2035
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2036
                store_reg( R_EAX, Rn );
nkeynes@359
  2037
                }
nkeynes@359
  2038
                break;
nkeynes@359
  2039
            case 0x6:
nkeynes@359
  2040
                switch( ir&0xF ) {
nkeynes@359
  2041
                    case 0x0:
nkeynes@359
  2042
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  2043
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2044
                        load_reg( R_ECX, Rm );
nkeynes@359
  2045
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386
  2046
                        store_reg( R_EAX, Rn );
nkeynes@359
  2047
                        }
nkeynes@359
  2048
                        break;
nkeynes@359
  2049
                    case 0x1:
nkeynes@359
  2050
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  2051
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2052
                        load_reg( R_ECX, Rm );
nkeynes@374
  2053
                        check_ralign16( R_ECX );
nkeynes@361
  2054
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2055
                        store_reg( R_EAX, Rn );
nkeynes@359
  2056
                        }
nkeynes@359
  2057
                        break;
nkeynes@359
  2058
                    case 0x2:
nkeynes@359
  2059
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  2060
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2061
                        load_reg( R_ECX, Rm );
nkeynes@374
  2062
                        check_ralign32( R_ECX );
nkeynes@361
  2063
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2064
                        store_reg( R_EAX, Rn );
nkeynes@359
  2065
                        }
nkeynes@359
  2066
                        break;
nkeynes@359
  2067
                    case 0x3:
nkeynes@359
  2068
                        { /* MOV Rm, Rn */
nkeynes@359
  2069
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2070
                        load_reg( R_EAX, Rm );
nkeynes@359
  2071
                        store_reg( R_EAX, Rn );
nkeynes@359
  2072
                        }
nkeynes@359
  2073
                        break;
nkeynes@359
  2074
                    case 0x4:
nkeynes@359
  2075
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  2076
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2077
                        load_reg( R_ECX, Rm );
nkeynes@359
  2078
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  2079
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  2080
                        store_reg( R_EAX, Rm );
nkeynes@359
  2081
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2082
                        store_reg( R_EAX, Rn );
nkeynes@359
  2083
                        }
nkeynes@359
  2084
                        break;
nkeynes@359
  2085
                    case 0x5:
nkeynes@359
  2086
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  2087
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2088
                        load_reg( R_EAX, Rm );
nkeynes@374
  2089
                        check_ralign16( R_EAX );
nkeynes@361
  2090
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2091
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  2092
                        store_reg( R_EAX, Rm );
nkeynes@361
  2093
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2094
                        store_reg( R_EAX, Rn );
nkeynes@359
  2095
                        }
nkeynes@359
  2096
                        break;
nkeynes@359
  2097
                    case 0x6:
nkeynes@359
  2098
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  2099
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2100
                        load_reg( R_EAX, Rm );
nkeynes@386
  2101
                        check_ralign32( R_EAX );
nkeynes@361
  2102
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  2103
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  2104
                        store_reg( R_EAX, Rm );
nkeynes@361
  2105
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2106
                        store_reg( R_EAX, Rn );
nkeynes@359
  2107
                        }
nkeynes@359
  2108
                        break;
nkeynes@359
  2109
                    case 0x7:
nkeynes@359
  2110
                        { /* NOT Rm, Rn */
nkeynes@359
  2111
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2112
                        load_reg( R_EAX, Rm );
nkeynes@359
  2113
                        NOT_r32( R_EAX );
nkeynes@359
  2114
                        store_reg( R_EAX, Rn );
nkeynes@359
  2115
                        }
nkeynes@359
  2116
                        break;
nkeynes@359
  2117
                    case 0x8:
nkeynes@359
  2118
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  2119
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2120
                        load_reg( R_EAX, Rm );
nkeynes@359
  2121
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  2122
                        store_reg( R_EAX, Rn );
nkeynes@359
  2123
                        }
nkeynes@359
  2124
                        break;
nkeynes@359
  2125
                    case 0x9:
nkeynes@359
  2126
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  2127
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2128
                        load_reg( R_EAX, Rm );
nkeynes@359
  2129
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2130
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  2131
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  2132
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2133
                        store_reg( R_ECX, Rn );
nkeynes@359
  2134
                        }
nkeynes@359
  2135
                        break;
nkeynes@359
  2136
                    case 0xA:
nkeynes@359
  2137
                        { /* NEGC Rm, Rn */
nkeynes@359
  2138
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2139
                        load_reg( R_EAX, Rm );
nkeynes@359
  2140
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  2141
                        LDC_t();
nkeynes@359
  2142
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2143
                        store_reg( R_ECX, Rn );
nkeynes@359
  2144
                        SETC_t();
nkeynes@359
  2145
                        }
nkeynes@359
  2146
                        break;
nkeynes@359
  2147
                    case 0xB:
nkeynes@359
  2148
                        { /* NEG Rm, Rn */
nkeynes@359
  2149
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2150
                        load_reg( R_EAX, Rm );
nkeynes@359
  2151
                        NEG_r32( R_EAX );
nkeynes@359
  2152
                        store_reg( R_EAX, Rn );
nkeynes@359
  2153
                        }
nkeynes@359
  2154
                        break;
nkeynes@359
  2155
                    case 0xC:
nkeynes@359
  2156
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  2157
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2158
                        load_reg( R_EAX, Rm );
nkeynes@361
  2159
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  2160
                        store_reg( R_EAX, Rn );
nkeynes@359
  2161
                        }
nkeynes@359
  2162
                        break;
nkeynes@359
  2163
                    case 0xD:
nkeynes@359
  2164
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  2165
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2166
                        load_reg( R_EAX, Rm );
nkeynes@361
  2167
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2168
                        store_reg( R_EAX, Rn );
nkeynes@359
  2169
                        }
nkeynes@359
  2170
                        break;
nkeynes@359
  2171
                    case 0xE:
nkeynes@359
  2172
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  2173
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  2174
                        load_reg( R_EAX, Rm );
nkeynes@359
  2175
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  2176
                        store_reg( R_EAX, Rn );
nkeynes@359
  2177
                        }
nkeynes@359
  2178
                        break;
nkeynes@359
  2179
                    case 0xF:
nkeynes@359
  2180
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  2181
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  2182
                        load_reg( R_EAX, Rm );
nkeynes@361
  2183
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  2184
                        store_reg( R_EAX, Rn );
nkeynes@359
  2185
                        }
nkeynes@359
  2186
                        break;
nkeynes@359
  2187
                }
nkeynes@359
  2188
                break;
nkeynes@359
  2189
            case 0x7:
nkeynes@359
  2190
                { /* ADD #imm, Rn */
nkeynes@359
  2191
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2192
                load_reg( R_EAX, Rn );
nkeynes@359
  2193
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2194
                store_reg( R_EAX, Rn );
nkeynes@359
  2195
                }
nkeynes@359
  2196
                break;
nkeynes@359
  2197
            case 0x8:
nkeynes@359
  2198
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2199
                    case 0x0:
nkeynes@359
  2200
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2201
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2202
                        load_reg( R_EAX, 0 );
nkeynes@359
  2203
                        load_reg( R_ECX, Rn );
nkeynes@359
  2204
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2205
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2206
                        }
nkeynes@359
  2207
                        break;
nkeynes@359
  2208
                    case 0x1:
nkeynes@359
  2209
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2210
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2211
                        load_reg( R_ECX, Rn );
nkeynes@361
  2212
                        load_reg( R_EAX, 0 );
nkeynes@361
  2213
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2214
                        check_walign16( R_ECX );
nkeynes@361
  2215
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2216
                        }
nkeynes@359
  2217
                        break;
nkeynes@359
  2218
                    case 0x4:
nkeynes@359
  2219
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2220
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2221
                        load_reg( R_ECX, Rm );
nkeynes@359
  2222
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2223
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2224
                        store_reg( R_EAX, 0 );
nkeynes@359
  2225
                        }
nkeynes@359
  2226
                        break;
nkeynes@359
  2227
                    case 0x5:
nkeynes@359
  2228
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2229
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2230
                        load_reg( R_ECX, Rm );
nkeynes@361
  2231
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2232
                        check_ralign16( R_ECX );
nkeynes@361
  2233
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2234
                        store_reg( R_EAX, 0 );
nkeynes@359
  2235
                        }
nkeynes@359
  2236
                        break;
nkeynes@359
  2237
                    case 0x8:
nkeynes@359
  2238
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2239
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2240
                        load_reg( R_EAX, 0 );
nkeynes@359
  2241
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2242
                        SETE_t();
nkeynes@359
  2243
                        }
nkeynes@359
  2244
                        break;
nkeynes@359
  2245
                    case 0x9:
nkeynes@359
  2246
                        { /* BT disp */
nkeynes@359
  2247
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2248
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2249
                    	SLOTILLEGAL();
nkeynes@374
  2250
                        } else {
nkeynes@374
  2251
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2252
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2253
                    	JE_rel8( 5, nottaken );
nkeynes@374
  2254
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2255
                    	JMP_TARGET(nottaken);
nkeynes@374
  2256
                    	INC_r32(R_ESI);
nkeynes@374
  2257
                    	return 1;
nkeynes@374
  2258
                        }
nkeynes@359
  2259
                        }
nkeynes@359
  2260
                        break;
nkeynes@359
  2261
                    case 0xB:
nkeynes@359
  2262
                        { /* BF disp */
nkeynes@359
  2263
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2264
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2265
                    	SLOTILLEGAL();
nkeynes@374
  2266
                        } else {
nkeynes@374
  2267
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2268
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2269
                    	JNE_rel8( 5, nottaken );
nkeynes@374
  2270
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2271
                    	JMP_TARGET(nottaken);
nkeynes@374
  2272
                    	INC_r32(R_ESI);
nkeynes@374
  2273
                    	return 1;
nkeynes@374
  2274
                        }
nkeynes@359
  2275
                        }
nkeynes@359
  2276
                        break;
nkeynes@359
  2277
                    case 0xD:
nkeynes@359
  2278
                        { /* BT/S disp */
nkeynes@359
  2279
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2280
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2281
                    	SLOTILLEGAL();
nkeynes@374
  2282
                        } else {
nkeynes@386
  2283
                    	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  2284
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2285
                    	JE_rel8( 5, nottaken );
nkeynes@374
  2286
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2287
                    	JMP_TARGET(nottaken);
nkeynes@374
  2288
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2289
                    	return 0;
nkeynes@374
  2290
                        }
nkeynes@359
  2291
                        }
nkeynes@359
  2292
                        break;
nkeynes@359
  2293
                    case 0xF:
nkeynes@359
  2294
                        { /* BF/S disp */
nkeynes@359
  2295
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2296
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2297
                    	SLOTILLEGAL();
nkeynes@374
  2298
                        } else {
nkeynes@386
  2299
                    	load_imm32( R_EDI, pc + 4 );
nkeynes@374
  2300
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  2301
                    	JNE_rel8( 5, nottaken );
nkeynes@374
  2302
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  2303
                    	JMP_TARGET(nottaken);
nkeynes@374
  2304
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2305
                    	return 0;
nkeynes@374
  2306
                        }
nkeynes@359
  2307
                        }
nkeynes@359
  2308
                        break;
nkeynes@359
  2309
                    default:
nkeynes@359
  2310
                        UNDEF();
nkeynes@359
  2311
                        break;
nkeynes@359
  2312
                }
nkeynes@359
  2313
                break;
nkeynes@359
  2314
            case 0x9:
nkeynes@359
  2315
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2316
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2317
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2318
            	SLOTILLEGAL();
nkeynes@374
  2319
                } else {
nkeynes@374
  2320
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2321
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2322
            	store_reg( R_EAX, Rn );
nkeynes@374
  2323
                }
nkeynes@359
  2324
                }
nkeynes@359
  2325
                break;
nkeynes@359
  2326
            case 0xA:
nkeynes@359
  2327
                { /* BRA disp */
nkeynes@359
  2328
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2329
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2330
            	SLOTILLEGAL();
nkeynes@374
  2331
                } else {
nkeynes@374
  2332
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2333
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2334
            	return 0;
nkeynes@374
  2335
                }
nkeynes@359
  2336
                }
nkeynes@359
  2337
                break;
nkeynes@359
  2338
            case 0xB:
nkeynes@359
  2339
                { /* BSR disp */
nkeynes@359
  2340
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2341
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2342
            	SLOTILLEGAL();
nkeynes@374
  2343
                } else {
nkeynes@374
  2344
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2345
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2346
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2347
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2348
            	return 0;
nkeynes@374
  2349
                }
nkeynes@359
  2350
                }
nkeynes@359
  2351
                break;
nkeynes@359
  2352
            case 0xC:
nkeynes@359
  2353
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2354
                    case 0x0:
nkeynes@359
  2355
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2356
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2357
                        load_reg( R_EAX, 0 );
nkeynes@359
  2358
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2359
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2360
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2361
                        }
nkeynes@359
  2362
                        break;
nkeynes@359
  2363
                    case 0x1:
nkeynes@359
  2364
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2365
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2366
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2367
                        load_reg( R_EAX, 0 );
nkeynes@361
  2368
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2369
                        check_walign16( R_ECX );
nkeynes@361
  2370
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2371
                        }
nkeynes@359
  2372
                        break;
nkeynes@359
  2373
                    case 0x2:
nkeynes@359
  2374
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2375
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2376
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2377
                        load_reg( R_EAX, 0 );
nkeynes@361
  2378
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2379
                        check_walign32( R_ECX );
nkeynes@361
  2380
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2381
                        }
nkeynes@359
  2382
                        break;
nkeynes@359
  2383
                    case 0x3:
nkeynes@359
  2384
                        { /* TRAPA #imm */
nkeynes@359
  2385
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2386
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2387
                    	SLOTILLEGAL();
nkeynes@374
  2388
                        } else {
nkeynes@388
  2389
                    	PUSH_imm32( imm );
nkeynes@388
  2390
                    	call_func0( sh4_raise_trap );
nkeynes@388
  2391
                    	ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2392
                        }
nkeynes@359
  2393
                        }
nkeynes@359
  2394
                        break;
nkeynes@359
  2395
                    case 0x4:
nkeynes@359
  2396
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2397
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2398
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2399
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2400
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2401
                        store_reg( R_EAX, 0 );
nkeynes@359
  2402
                        }
nkeynes@359
  2403
                        break;
nkeynes@359
  2404
                    case 0x5:
nkeynes@359
  2405
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2406
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2407
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2408
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2409
                        check_ralign16( R_ECX );
nkeynes@361
  2410
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2411
                        store_reg( R_EAX, 0 );
nkeynes@359
  2412
                        }
nkeynes@359
  2413
                        break;
nkeynes@359
  2414
                    case 0x6:
nkeynes@359
  2415
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2416
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2417
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2418
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2419
                        check_ralign32( R_ECX );
nkeynes@361
  2420
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2421
                        store_reg( R_EAX, 0 );
nkeynes@359
  2422
                        }
nkeynes@359
  2423
                        break;
nkeynes@359
  2424
                    case 0x7:
nkeynes@359
  2425
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2426
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2427
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2428
                    	SLOTILLEGAL();
nkeynes@374
  2429
                        } else {
nkeynes@374
  2430
                    	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2431
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2432
                        }
nkeynes@359
  2433
                        }
nkeynes@359
  2434
                        break;
nkeynes@359
  2435
                    case 0x8:
nkeynes@359
  2436
                        { /* TST #imm, R0 */
nkeynes@359
  2437
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2438
                        load_reg( R_EAX, 0 );
nkeynes@368
  2439
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2440
                        SETE_t();
nkeynes@359
  2441
                        }
nkeynes@359
  2442
                        break;
nkeynes@359
  2443
                    case 0x9:
nkeynes@359
  2444
                        { /* AND #imm, R0 */
nkeynes@359
  2445
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2446
                        load_reg( R_EAX, 0 );
nkeynes@359
  2447
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2448
                        store_reg( R_EAX, 0 );
nkeynes@359
  2449
                        }
nkeynes@359
  2450
                        break;
nkeynes@359
  2451
                    case 0xA:
nkeynes@359
  2452
                        { /* XOR #imm, R0 */
nkeynes@359
  2453
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2454
                        load_reg( R_EAX, 0 );
nkeynes@359
  2455
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2456
                        store_reg( R_EAX, 0 );
nkeynes@359
  2457
                        }
nkeynes@359
  2458
                        break;
nkeynes@359
  2459
                    case 0xB:
nkeynes@359
  2460
                        { /* OR #imm, R0 */
nkeynes@359
  2461
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2462
                        load_reg( R_EAX, 0 );
nkeynes@359
  2463
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2464
                        store_reg( R_EAX, 0 );
nkeynes@359
  2465
                        }
nkeynes@359
  2466
                        break;
nkeynes@359
  2467
                    case 0xC:
nkeynes@359
  2468
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2469
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2470
                        load_reg( R_EAX, 0);
nkeynes@368
  2471
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2472
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2473
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@394
  2474
                        TEST_imm8_r8( imm, R_AL );
nkeynes@368
  2475
                        SETE_t();
nkeynes@359
  2476
                        }
nkeynes@359
  2477
                        break;
nkeynes@359
  2478
                    case 0xD:
nkeynes@359
  2479
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2480
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2481
                        load_reg( R_EAX, 0 );
nkeynes@359
  2482
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2483
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2484
                        PUSH_r32(R_ECX);
nkeynes@386
  2485
                        call_func0(sh4_read_byte);
nkeynes@386
  2486
                        POP_r32(R_ECX);
nkeynes@386
  2487
                        AND_imm32_r32(imm, R_EAX );
nkeynes@359
  2488
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2489
                        }
nkeynes@359
  2490
                        break;
nkeynes@359
  2491
                    case 0xE:
nkeynes@359
  2492
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2493
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2494
                        load_reg( R_EAX, 0 );
nkeynes@359
  2495
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2496
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2497
                        PUSH_r32(R_ECX);
nkeynes@386
  2498
                        call_func0(sh4_read_byte);
nkeynes@386
  2499
                        POP_r32(R_ECX);
nkeynes@359
  2500
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2501
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2502
                        }
nkeynes@359
  2503
                        break;
nkeynes@359
  2504
                    case 0xF:
nkeynes@359
  2505
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2506
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2507
                        load_reg( R_EAX, 0 );
nkeynes@374
  2508
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2509
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386
  2510
                        PUSH_r32(R_ECX);
nkeynes@386
  2511
                        call_func0(sh4_read_byte);
nkeynes@386
  2512
                        POP_r32(R_ECX);
nkeynes@386
  2513
                        OR_imm32_r32(imm, R_EAX );
nkeynes@374
  2514
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2515
                        }
nkeynes@359
  2516
                        break;
nkeynes@359
  2517
                }
nkeynes@359
  2518
                break;
nkeynes@359
  2519
            case 0xD:
nkeynes@359
  2520
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2521
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2522
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2523
            	SLOTILLEGAL();
nkeynes@374
  2524
                } else {
nkeynes@388
  2525
            	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388
  2526
            	char *ptr = mem_get_region(target);
nkeynes@388
  2527
            	if( ptr != NULL ) {
nkeynes@388
  2528
            	    MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388
  2529
            	} else {
nkeynes@388
  2530
            	    load_imm32( R_ECX, target );
nkeynes@388
  2531
            	    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388
  2532
            	}
nkeynes@386
  2533
            	store_reg( R_EAX, Rn );
nkeynes@374
  2534
                }
nkeynes@359
  2535
                }
nkeynes@359
  2536
                break;
nkeynes@359
  2537
            case 0xE:
nkeynes@359
  2538
                { /* MOV #imm, Rn */
nkeynes@359
  2539
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2540
                load_imm32( R_EAX, imm );
nkeynes@359
  2541
                store_reg( R_EAX, Rn );
nkeynes@359
  2542
                }
nkeynes@359
  2543
                break;
nkeynes@359
  2544
            case 0xF:
nkeynes@359
  2545
                switch( ir&0xF ) {
nkeynes@359
  2546
                    case 0x0:
nkeynes@359
  2547
                        { /* FADD FRm, FRn */
nkeynes@359
  2548
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2549
                        check_fpuen();
nkeynes@377
  2550
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2551
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2552
                        load_fr_bank( R_EDX );
nkeynes@380
  2553
                        JNE_rel8(13,doubleprec);
nkeynes@377
  2554
                        push_fr(R_EDX, FRm);
nkeynes@377
  2555
                        push_fr(R_EDX, FRn);
nkeynes@377
  2556
                        FADDP_st(1);
nkeynes@377
  2557
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2558
                        JMP_rel8(11,end);
nkeynes@380
  2559
                        JMP_TARGET(doubleprec);
nkeynes@377
  2560
                        push_dr(R_EDX, FRm);
nkeynes@377
  2561
                        push_dr(R_EDX, FRn);
nkeynes@377
  2562
                        FADDP_st(1);
nkeynes@377
  2563
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2564
                        JMP_TARGET(end);
nkeynes@359
  2565
                        }
nkeynes@359
  2566
                        break;
nkeynes@359
  2567
                    case 0x1:
nkeynes@359
  2568
                        { /* FSUB FRm, FRn */
nkeynes@359
  2569
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2570
                        check_fpuen();
nkeynes@377
  2571
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2572
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2573
                        load_fr_bank( R_EDX );
nkeynes@380
  2574
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2575
                        push_fr(R_EDX, FRn);
nkeynes@377
  2576
                        push_fr(R_EDX, FRm);
nkeynes@388
  2577
                        FSUBP_st(1);
nkeynes@377
  2578
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2579
                        JMP_rel8(11, end);
nkeynes@380
  2580
                        JMP_TARGET(doubleprec);
nkeynes@377
  2581
                        push_dr(R_EDX, FRn);
nkeynes@377
  2582
                        push_dr(R_EDX, FRm);
nkeynes@388
  2583
                        FSUBP_st(1);
nkeynes@377
  2584
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2585
                        JMP_TARGET(end);
nkeynes@359
  2586
                        }
nkeynes@359
  2587
                        break;
nkeynes@359
  2588
                    case 0x2:
nkeynes@359
  2589
                        { /* FMUL FRm, FRn */
nkeynes@359
  2590
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2591
                        check_fpuen();
nkeynes@377
  2592
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2593
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2594
                        load_fr_bank( R_EDX );
nkeynes@380
  2595
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2596
                        push_fr(R_EDX, FRm);
nkeynes@377
  2597
                        push_fr(R_EDX, FRn);
nkeynes@377
  2598
                        FMULP_st(1);
nkeynes@377
  2599
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2600
                        JMP_rel8(11, end);
nkeynes@380
  2601
                        JMP_TARGET(doubleprec);
nkeynes@377
  2602
                        push_dr(R_EDX, FRm);
nkeynes@377
  2603
                        push_dr(R_EDX, FRn);
nkeynes@377
  2604
                        FMULP_st(1);
nkeynes@377
  2605
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2606
                        JMP_TARGET(end);
nkeynes@359
  2607
                        }
nkeynes@359
  2608
                        break;
nkeynes@359
  2609
                    case 0x3:
nkeynes@359
  2610
                        { /* FDIV FRm, FRn */
nkeynes@359
  2611
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2612
                        check_fpuen();
nkeynes@377
  2613
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2614
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2615
                        load_fr_bank( R_EDX );
nkeynes@380
  2616
                        JNE_rel8(13, doubleprec);
nkeynes@377
  2617
                        push_fr(R_EDX, FRn);
nkeynes@377
  2618
                        push_fr(R_EDX, FRm);
nkeynes@377
  2619
                        FDIVP_st(1);
nkeynes@377
  2620
                        pop_fr(R_EDX, FRn);
nkeynes@380
  2621
                        JMP_rel8(11, end);
nkeynes@380
  2622
                        JMP_TARGET(doubleprec);
nkeynes@377
  2623
                        push_dr(R_EDX, FRn);
nkeynes@377
  2624
                        push_dr(R_EDX, FRm);
nkeynes@377
  2625
                        FDIVP_st(1);
nkeynes@377
  2626
                        pop_dr(R_EDX, FRn);
nkeynes@380
  2627
                        JMP_TARGET(end);
nkeynes@359
  2628
                        }
nkeynes@359
  2629
                        break;
nkeynes@359
  2630
                    case 0x4:
nkeynes@359
  2631
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  2632
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2633
                        check_fpuen();
nkeynes@377
  2634
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2635
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2636
                        load_fr_bank( R_EDX );
nkeynes@380
  2637
                        JNE_rel8(8, doubleprec);
nkeynes@377
  2638
                        push_fr(R_EDX, FRm);
nkeynes@377
  2639
                        push_fr(R_EDX, FRn);
nkeynes@380
  2640
                        JMP_rel8(6, end);
nkeynes@380
  2641
                        JMP_TARGET(doubleprec);
nkeynes@377
  2642
                        push_dr(R_EDX, FRm);
nkeynes@377
  2643
                        push_dr(R_EDX, FRn);
nkeynes@386
  2644
                        JMP_TARGET(end);
nkeynes@377
  2645
                        FCOMIP_st(1);
nkeynes@377
  2646
                        SETE_t();
nkeynes@377
  2647
                        FPOP_st();
nkeynes@359
  2648
                        }
nkeynes@359
  2649
                        break;
nkeynes@359
  2650
                    case 0x5:
nkeynes@359
  2651
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  2652
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2653
                        check_fpuen();
nkeynes@377
  2654
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2655
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2656
                        load_fr_bank( R_EDX );
nkeynes@380
  2657
                        JNE_rel8(8, doubleprec);
nkeynes@377
  2658
                        push_fr(R_EDX, FRm);
nkeynes@377
  2659
                        push_fr(R_EDX, FRn);
nkeynes@380
  2660
                        JMP_rel8(6, end);
nkeynes@380
  2661
                        JMP_TARGET(doubleprec);
nkeynes@377
  2662
                        push_dr(R_EDX, FRm);
nkeynes@377
  2663
                        push_dr(R_EDX, FRn);
nkeynes@380
  2664
                        JMP_TARGET(end);
nkeynes@377
  2665
                        FCOMIP_st(1);
nkeynes@377
  2666
                        SETA_t();
nkeynes@377
  2667
                        FPOP_st();
nkeynes@359
  2668
                        }
nkeynes@359
  2669
                        break;
nkeynes@359
  2670
                    case 0x6:
nkeynes@359
  2671
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  2672
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2673
                        check_fpuen();
nkeynes@375
  2674
                        load_reg( R_EDX, Rm );
nkeynes@377
  2675
                        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@375
  2676
                        check_ralign32( R_EDX );
nkeynes@375
  2677
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2678
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  2679
                        JNE_rel8(19, doublesize);
nkeynes@375
  2680
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  2681
                        load_fr_bank( R_ECX );
nkeynes@375
  2682
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  2683
                        if( FRn&1 ) {
nkeynes@386
  2684
                    	JMP_rel8(48, end);
nkeynes@380
  2685
                    	JMP_TARGET(doublesize);
nkeynes@375
  2686
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  2687
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  2688
                    	load_xf_bank( R_ECX );
nkeynes@380
  2689
                    	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  2690
                    	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  2691
                    	JMP_TARGET(end);
nkeynes@375
  2692
                        } else {
nkeynes@380
  2693
                    	JMP_rel8(36, end);
nkeynes@380
  2694
                    	JMP_TARGET(doublesize);
nkeynes@375
  2695
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2696
                    	load_fr_bank( R_ECX );
nkeynes@380
  2697
                    	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  2698
                    	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  2699
                    	JMP_TARGET(end);
nkeynes@377
  2700
                        }
nkeynes@377
  2701
                        }
nkeynes@377
  2702
                        break;
nkeynes@377
  2703
                    case 0x7:
nkeynes@377
  2704
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@377
  2705
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2706
                        check_fpuen();
nkeynes@377
  2707
                        load_reg( R_EDX, Rn );
nkeynes@377
  2708
                        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  2709
                        check_walign32( R_EDX );
nkeynes@377
  2710
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2711
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  2712
                        JNE_rel8(20, doublesize);
nkeynes@377
  2713
                        load_fr_bank( R_ECX );
nkeynes@377
  2714
                        load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2715
                        MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  2716
                        if( FRm&1 ) {
nkeynes@386
  2717
                    	JMP_rel8( 48, end );
nkeynes@380
  2718
                    	JMP_TARGET(doublesize);
nkeynes@377
  2719
                    	load_xf_bank( R_ECX );
nkeynes@380
  2720
                    	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  2721
                    	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  2722
                    	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );