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lxdream.org :: lxdream/test/sh4/excslot.s
lxdream 0.9.1
released Jun 29
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filename test/sh4/excslot.s
changeset 233:f8333b94f503
prev231:a9e61a96a885
next357:3592a10b3242
author nkeynes
date Wed Sep 27 10:21:34 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add user mode/system mode switch
Add undefined instruction tests
file annotate diff log raw
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.section .text
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.include "sh4/inc.s"
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!
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! Test for all cases that raise a slot-illegal exception (according to the SH4
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! manual). See Page 103 of the Hitachi manual
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.global _test_slot_illegal
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_test_slot_illegal:	
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	start_test
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! First the easy ones - instructions not permitted in delay slots at any
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! time:
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! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
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! LDC (to SR), MOV pcrel, MOVA
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!
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! Note that the tests use BSR as the branch instruction, and assume it
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! functions correctly.
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test_slot_1:	!JMP
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_1_pc:	
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	bsr test_slot_fail
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	jmp @r3
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	assert_exc_caught test_slot_str_k1 test_slot_1_pc
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test_slot_2:	! JSR
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_2_pc:
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	bsr test_slot_fail
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	jsr @r3
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	assert_exc_caught test_slot_str_k1 test_slot_2_pc
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test_slot_3:	! BRA
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_3_pc:
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	bsr test_slot_fail
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	bra test_slot_fail
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	assert_exc_caught test_slot_str_k1 test_slot_3_pc
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test_slot_4:	! BRAF
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_4_pc:
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	bsr test_slot_fail
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	braf r3
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	assert_exc_caught test_slot_str_k test_slot_4_pc
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test_slot_5:	! BSR
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_5_pc:
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	bsr test_slot_fail
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	bsr test_slot_fail
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	assert_exc_caught test_slot_str_k test_slot_5_pc
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test_slot_6:	! BSRF
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_6_pc:
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	bsr test_slot_fail
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	bsrf r3
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	assert_exc_caught test_slot_str_k test_slot_6_pc
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test_slot_7:	! BF
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_7_pc:
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	bsr test_slot_fail
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	bf test_slot_7_fail
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test_slot_7_fail:	
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	assert_exc_caught test_slot_str_k test_slot_7_pc
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test_slot_8:	! BT
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_8_pc:
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	bsr test_slot_fail
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	bt test_slot_8_fail
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test_slot_8_fail:	
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	assert_exc_caught test_slot_str_k test_slot_8_pc
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test_slot_9:	! BF/S
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_9_pc:
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	bsr test_slot_fail
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	bf/s test_slot_9_fail
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test_slot_9_fail:	
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	assert_exc_caught test_slot_str_k test_slot_9_pc
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test_slot_10:	! BT/S
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_10_pc:
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	bsr test_slot_fail
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	bt/s test_slot_10_fail
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test_slot_10_fail:	
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	assert_exc_caught test_slot_str_k test_slot_10_pc
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	bra test_slot_11
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	nop
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test_slot_str_k1:
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	.long test_slot_str
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test_slot_11:	! TRAPA
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_11_pc:
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	bsr test_slot_fail
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	trapa #12
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	assert_exc_caught test_slot_str_k test_slot_11_pc
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test_slot_12:	! LDC r0, sr
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	add #1, r12
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	expect_exc 0x000001A0
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	stc sr, r0
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test_slot_12_pc:
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	bsr test_slot_fail
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	ldc r0, sr
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	assert_exc_caught test_slot_str_k test_slot_12_pc
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test_slot_13:	! LDC @r0, sr
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	add #1, r12
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	expect_exc 0x000001A0
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	stc sr, r1
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	mova test_slot_13_temp, r0
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	mov.l r1, @r0
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test_slot_13_pc:
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	bsr test_slot_fail
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	ldc.l @r0+, sr
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	assert_exc_caught test_slot_str_k test_slot_13_pc
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	bra test_slot_14
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	nop
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test_slot_13_temp:
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	.long 0
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test_slot_14:	! MOVA
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_14_pc:
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	bsr test_slot_fail
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	mova test_slot_15, r0
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	assert_exc_caught test_slot_str_k test_slot_14_pc
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test_slot_15:	! MOV.W pcrel, Rn
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_15_pc:
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	bsr test_slot_fail
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	mov.w test_slot_16, r0
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	assert_exc_caught test_slot_str_k test_slot_15_pc
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test_slot_16:	! MOV.L pcrel, Rn
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_16_pc:
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	bsr test_slot_fail
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	mov.l test_slot_str_k, r0
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	assert_exc_caught test_slot_str_k test_slot_16_pc
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test_slot_17:	! "Undefined" 0xFFFD
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	add #1, r12
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	expect_exc 0x000001A0
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test_slot_17_pc:
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	bsr test_slot_fail
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	.word 0xFFFD
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	assert_exc_caught test_slot_str_k test_slot_17_pc
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!
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! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
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! in a delay slot (otherwise it's GENERAL_ILLEGAL)
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test_slot_18:   ! LDC Rn, SPC in user mode
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	add #1, r12
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	expect_exc 0x000001A0
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	stc spc, r4
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	usermode
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test_slot_18_pc:
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	bsr test_slot_fail
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	ldc r4, spc
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	systemmode
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	assert_exc_caught test_slot_str_k test_slot_18_pc
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test_slot_end:
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	end_test test_slot_str_k
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! Returns after the delay slot, which should hit the "no exception" test
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test_slot_fail:
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	rts
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	nop
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test_slot_str_k:
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	.long test_slot_str
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test_slot_str:
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	.string "SLOT-ILLEGAL"
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