Search
lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/sh4/sh4x86.c
changeset 377:fa18743f6905
prev375:4627600f7f8e
next380:2e8166bf6832
author nkeynes
date Wed Sep 12 09:17:52 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fill in most of the FP operations and fix the stack adjustments
file annotate diff log raw
nkeynes@359
     1
/**
nkeynes@377
     2
 * $Id: sh4x86.c,v 1.6 2007-09-12 09:17:52 nkeynes Exp $
nkeynes@359
     3
 * 
nkeynes@359
     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
nkeynes@359
     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
nkeynes@359
    10
 * This program is free software; you can redistribute it and/or modify
nkeynes@359
    11
 * it under the terms of the GNU General Public License as published by
nkeynes@359
    12
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@359
    13
 * (at your option) any later version.
nkeynes@359
    14
 *
nkeynes@359
    15
 * This program is distributed in the hope that it will be useful,
nkeynes@359
    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359
    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@359
    18
 * GNU General Public License for more details.
nkeynes@359
    19
 */
nkeynes@359
    20
nkeynes@368
    21
#include <assert.h>
nkeynes@368
    22
nkeynes@368
    23
#include "sh4/sh4core.h"
nkeynes@368
    24
#include "sh4/sh4trans.h"
nkeynes@368
    25
#include "sh4/x86op.h"
nkeynes@368
    26
#include "clock.h"
nkeynes@368
    27
nkeynes@368
    28
#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368
    29
nkeynes@368
    30
/** 
nkeynes@368
    31
 * Struct to manage internal translation state. This state is not saved -
nkeynes@368
    32
 * it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368
    33
 * sh4_translate_end_block()
nkeynes@368
    34
 */
nkeynes@368
    35
struct sh4_x86_state {
nkeynes@368
    36
    gboolean in_delay_slot;
nkeynes@368
    37
    gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368
    38
    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@368
    39
nkeynes@368
    40
    /* Allocated memory for the (block-wide) back-patch list */
nkeynes@368
    41
    uint32_t **backpatch_list;
nkeynes@368
    42
    uint32_t backpatch_posn;
nkeynes@368
    43
    uint32_t backpatch_size;
nkeynes@368
    44
};
nkeynes@368
    45
nkeynes@368
    46
#define EXIT_DATA_ADDR_READ 0
nkeynes@368
    47
#define EXIT_DATA_ADDR_WRITE 7
nkeynes@368
    48
#define EXIT_ILLEGAL 14
nkeynes@368
    49
#define EXIT_SLOT_ILLEGAL 21
nkeynes@368
    50
#define EXIT_FPU_DISABLED 28
nkeynes@368
    51
#define EXIT_SLOT_FPU_DISABLED 35
nkeynes@368
    52
nkeynes@368
    53
static struct sh4_x86_state sh4_x86;
nkeynes@368
    54
nkeynes@368
    55
void sh4_x86_init()
nkeynes@368
    56
{
nkeynes@368
    57
    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@368
    58
    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
nkeynes@368
    59
}
nkeynes@368
    60
nkeynes@368
    61
nkeynes@368
    62
static void sh4_x86_add_backpatch( uint8_t *ptr )
nkeynes@368
    63
{
nkeynes@368
    64
    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368
    65
	sh4_x86.backpatch_size <<= 1;
nkeynes@368
    66
	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
nkeynes@368
    67
	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368
    68
    }
nkeynes@368
    69
    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
nkeynes@368
    70
}
nkeynes@368
    71
nkeynes@368
    72
static void sh4_x86_do_backpatch( uint8_t *reloc_base )
nkeynes@368
    73
{
nkeynes@368
    74
    unsigned int i;
nkeynes@368
    75
    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
nkeynes@374
    76
	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
nkeynes@368
    77
    }
nkeynes@368
    78
}
nkeynes@368
    79
nkeynes@368
    80
#ifndef NDEBUG
nkeynes@368
    81
#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
nkeynes@368
    82
#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
nkeynes@368
    83
#else
nkeynes@368
    84
#define MARK_JMP(x,n)
nkeynes@368
    85
#define CHECK_JMP(x)
nkeynes@368
    86
#endif
nkeynes@368
    87
nkeynes@359
    88
nkeynes@359
    89
/**
nkeynes@359
    90
 * Emit an instruction to load an SH4 reg into a real register
nkeynes@359
    91
 */
nkeynes@359
    92
static inline void load_reg( int x86reg, int sh4reg ) 
nkeynes@359
    93
{
nkeynes@359
    94
    /* mov [bp+n], reg */
nkeynes@361
    95
    OP(0x8B);
nkeynes@361
    96
    OP(0x45 + (x86reg<<3));
nkeynes@359
    97
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
    98
}
nkeynes@359
    99
nkeynes@374
   100
static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368
   101
{
nkeynes@374
   102
    OP(0x0F);
nkeynes@374
   103
    OP(0xBF);
nkeynes@374
   104
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368
   105
}
nkeynes@368
   106
nkeynes@374
   107
static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368
   108
{
nkeynes@374
   109
    OP(0x0F);
nkeynes@374
   110
    OP(0xB7);
nkeynes@374
   111
    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374
   112
nkeynes@368
   113
}
nkeynes@368
   114
nkeynes@359
   115
static inline void load_spreg( int x86reg, int regoffset )
nkeynes@359
   116
{
nkeynes@359
   117
    /* mov [bp+n], reg */
nkeynes@361
   118
    OP(0x8B);
nkeynes@361
   119
    OP(0x45 + (x86reg<<3));
nkeynes@359
   120
    OP(regoffset);
nkeynes@359
   121
}
nkeynes@359
   122
nkeynes@359
   123
/**
nkeynes@359
   124
 * Emit an instruction to load an immediate value into a register
nkeynes@359
   125
 */
nkeynes@359
   126
static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359
   127
    /* mov #value, reg */
nkeynes@359
   128
    OP(0xB8 + x86reg);
nkeynes@359
   129
    OP32(value);
nkeynes@359
   130
}
nkeynes@359
   131
nkeynes@359
   132
/**
nkeynes@359
   133
 * Emit an instruction to store an SH4 reg (RN)
nkeynes@359
   134
 */
nkeynes@359
   135
void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359
   136
    /* mov reg, [bp+n] */
nkeynes@361
   137
    OP(0x89);
nkeynes@361
   138
    OP(0x45 + (x86reg<<3));
nkeynes@359
   139
    OP(REG_OFFSET(r[sh4reg]));
nkeynes@359
   140
}
nkeynes@359
   141
void static inline store_spreg( int x86reg, int regoffset ) {
nkeynes@359
   142
    /* mov reg, [bp+n] */
nkeynes@361
   143
    OP(0x89);
nkeynes@361
   144
    OP(0x45 + (x86reg<<3));
nkeynes@359
   145
    OP(regoffset);
nkeynes@359
   146
}
nkeynes@359
   147
nkeynes@374
   148
nkeynes@374
   149
#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374
   150
nkeynes@375
   151
/**
nkeynes@375
   152
 * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375
   153
 * register (eg for register-to-register moves)
nkeynes@375
   154
 */
nkeynes@375
   155
void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375
   156
{
nkeynes@375
   157
    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375
   158
}
nkeynes@375
   159
nkeynes@375
   160
/**
nkeynes@375
   161
 * Store an FR register (single-precision floating point) into an integer x86
nkeynes@375
   162
 * register (eg for register-to-register moves)
nkeynes@375
   163
 */
nkeynes@375
   164
void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375
   165
{
nkeynes@375
   166
    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375
   167
}
nkeynes@375
   168
nkeynes@375
   169
nkeynes@375
   170
/**
nkeynes@375
   171
 * Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375
   172
 * bankreg must have been previously loaded with FPSCR.
nkeynes@375
   173
 * NB: 10 bytes
nkeynes@375
   174
 */
nkeynes@374
   175
static inline void load_xf_bank( int bankreg )
nkeynes@374
   176
{
nkeynes@374
   177
    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374
   178
    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
nkeynes@374
   179
    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374
   180
}
nkeynes@374
   181
nkeynes@375
   182
/**
nkeynes@377
   183
 * Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377
   184
 */
nkeynes@377
   185
static inline void push_fpul( )
nkeynes@377
   186
{
nkeynes@377
   187
    OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377
   188
}
nkeynes@377
   189
nkeynes@377
   190
/**
nkeynes@377
   191
 * Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377
   192
 */
nkeynes@377
   193
static inline void pop_fpul( )
nkeynes@377
   194
{
nkeynes@377
   195
    OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377
   196
}
nkeynes@377
   197
nkeynes@377
   198
/**
nkeynes@375
   199
 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375
   200
 * with the location of the current fp bank.
nkeynes@375
   201
 */
nkeynes@374
   202
static inline void push_fr( int bankreg, int frm ) 
nkeynes@374
   203
{
nkeynes@374
   204
    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
nkeynes@374
   205
}
nkeynes@374
   206
nkeynes@375
   207
/**
nkeynes@375
   208
 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
nkeynes@375
   209
 * with bankreg previously loaded with the location of the current fp bank.
nkeynes@375
   210
 */
nkeynes@374
   211
static inline void pop_fr( int bankreg, int frm )
nkeynes@374
   212
{
nkeynes@374
   213
    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374
   214
}
nkeynes@374
   215
nkeynes@375
   216
/**
nkeynes@375
   217
 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375
   218
 * with the location of the current fp bank.
nkeynes@375
   219
 */
nkeynes@374
   220
static inline void push_dr( int bankreg, int frm )
nkeynes@374
   221
{
nkeynes@377
   222
    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374
   223
}
nkeynes@374
   224
nkeynes@374
   225
static inline void pop_dr( int bankreg, int frm )
nkeynes@374
   226
{
nkeynes@377
   227
    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374
   228
}
nkeynes@374
   229
nkeynes@361
   230
/**
nkeynes@361
   231
 * Note: clobbers EAX to make the indirect call - this isn't usually
nkeynes@361
   232
 * a problem since the callee will usually clobber it anyway.
nkeynes@361
   233
 */
nkeynes@361
   234
static inline void call_func0( void *ptr )
nkeynes@361
   235
{
nkeynes@361
   236
    load_imm32(R_EAX, (uint32_t)ptr);
nkeynes@368
   237
    CALL_r32(R_EAX);
nkeynes@361
   238
}
nkeynes@361
   239
nkeynes@361
   240
static inline void call_func1( void *ptr, int arg1 )
nkeynes@361
   241
{
nkeynes@361
   242
    PUSH_r32(arg1);
nkeynes@361
   243
    call_func0(ptr);
nkeynes@377
   244
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@361
   245
}
nkeynes@361
   246
nkeynes@361
   247
static inline void call_func2( void *ptr, int arg1, int arg2 )
nkeynes@361
   248
{
nkeynes@361
   249
    PUSH_r32(arg2);
nkeynes@361
   250
    PUSH_r32(arg1);
nkeynes@361
   251
    call_func0(ptr);
nkeynes@377
   252
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   253
}
nkeynes@375
   254
nkeynes@375
   255
/**
nkeynes@375
   256
 * Write a double (64-bit) value into memory, with the first word in arg2a, and
nkeynes@375
   257
 * the second in arg2b
nkeynes@375
   258
 * NB: 30 bytes
nkeynes@375
   259
 */
nkeynes@375
   260
static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375
   261
{
nkeynes@375
   262
    ADD_imm8s_r32( 4, addr );
nkeynes@375
   263
    PUSH_r32(addr);
nkeynes@375
   264
    PUSH_r32(arg2b);
nkeynes@375
   265
    ADD_imm8s_r32( -4, addr );
nkeynes@375
   266
    PUSH_r32(addr);
nkeynes@375
   267
    PUSH_r32(arg2a);
nkeynes@375
   268
    call_func0(sh4_write_long);
nkeynes@377
   269
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   270
    call_func0(sh4_write_long);
nkeynes@377
   271
    ADD_imm8s_r32( 8, R_ESP );
nkeynes@375
   272
}
nkeynes@375
   273
nkeynes@375
   274
/**
nkeynes@375
   275
 * Read a double (64-bit) value from memory, writing the first word into arg2a
nkeynes@375
   276
 * and the second into arg2b. The addr must not be in EAX
nkeynes@375
   277
 * NB: 27 bytes
nkeynes@375
   278
 */
nkeynes@375
   279
static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375
   280
{
nkeynes@375
   281
    PUSH_r32(addr);
nkeynes@375
   282
    call_func0(sh4_read_long);
nkeynes@375
   283
    POP_r32(addr);
nkeynes@375
   284
    PUSH_r32(R_EAX);
nkeynes@375
   285
    ADD_imm8s_r32( 4, addr );
nkeynes@375
   286
    PUSH_r32(addr);
nkeynes@375
   287
    call_func0(sh4_read_long);
nkeynes@377
   288
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@375
   289
    MOV_r32_r32( R_EAX, arg2b );
nkeynes@375
   290
    POP_r32(arg2a);
nkeynes@361
   291
}
nkeynes@361
   292
nkeynes@368
   293
/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@368
   294
static void check_priv( )
nkeynes@368
   295
{
nkeynes@368
   296
    if( !sh4_x86.priv_checked ) {
nkeynes@368
   297
	sh4_x86.priv_checked = TRUE;
nkeynes@368
   298
	load_spreg( R_EAX, R_SR );
nkeynes@368
   299
	AND_imm32_r32( SR_MD, R_EAX );
nkeynes@368
   300
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   301
	    JE_exit( EXIT_SLOT_ILLEGAL );
nkeynes@368
   302
	} else {
nkeynes@368
   303
	    JE_exit( EXIT_ILLEGAL );
nkeynes@368
   304
	}
nkeynes@368
   305
    }
nkeynes@368
   306
}
nkeynes@368
   307
nkeynes@368
   308
static void check_fpuen( )
nkeynes@368
   309
{
nkeynes@368
   310
    if( !sh4_x86.fpuen_checked ) {
nkeynes@368
   311
	sh4_x86.fpuen_checked = TRUE;
nkeynes@368
   312
	load_spreg( R_EAX, R_SR );
nkeynes@368
   313
	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368
   314
	if( sh4_x86.in_delay_slot ) {
nkeynes@368
   315
	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368
   316
	} else {
nkeynes@368
   317
	    JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368
   318
	}
nkeynes@368
   319
    }
nkeynes@368
   320
}
nkeynes@368
   321
nkeynes@368
   322
static void check_ralign16( int x86reg )
nkeynes@368
   323
{
nkeynes@368
   324
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   325
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   326
}
nkeynes@368
   327
nkeynes@368
   328
static void check_walign16( int x86reg )
nkeynes@368
   329
{
nkeynes@368
   330
    TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368
   331
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   332
}
nkeynes@368
   333
nkeynes@368
   334
static void check_ralign32( int x86reg )
nkeynes@368
   335
{
nkeynes@368
   336
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   337
    JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368
   338
}
nkeynes@368
   339
static void check_walign32( int x86reg )
nkeynes@368
   340
{
nkeynes@368
   341
    TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368
   342
    JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368
   343
}
nkeynes@368
   344
nkeynes@368
   345
nkeynes@361
   346
#define UNDEF()
nkeynes@361
   347
#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361
   348
#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   349
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   350
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361
   351
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361
   352
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361
   353
#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361
   354
nkeynes@368
   355
#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
nkeynes@374
   356
#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
nkeynes@368
   357
nkeynes@368
   358
nkeynes@359
   359
nkeynes@359
   360
/**
nkeynes@359
   361
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   362
 * SI/DI as required
nkeynes@359
   363
 */
nkeynes@368
   364
void sh4_translate_begin_block() 
nkeynes@368
   365
{
nkeynes@368
   366
    PUSH_r32(R_EBP);
nkeynes@359
   367
    /* mov &sh4r, ebp */
nkeynes@359
   368
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   369
    PUSH_r32(R_EDI);
nkeynes@368
   370
    PUSH_r32(R_ESI);
nkeynes@368
   371
    
nkeynes@368
   372
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   373
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   374
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   375
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   376
}
nkeynes@359
   377
nkeynes@368
   378
/**
nkeynes@368
   379
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   380
 */
nkeynes@374
   381
void exit_block( )
nkeynes@368
   382
{
nkeynes@374
   383
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   384
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   385
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   386
    MUL_r32( R_ESI );
nkeynes@368
   387
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   388
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   389
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@374
   390
    POP_r32(R_ESI);
nkeynes@374
   391
    POP_r32(R_EDI);
nkeynes@374
   392
    POP_r32(R_EBP);
nkeynes@368
   393
    RET();
nkeynes@359
   394
}
nkeynes@359
   395
nkeynes@359
   396
/**
nkeynes@359
   397
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   398
 */
nkeynes@359
   399
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   400
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   401
    // Normal termination - save PC, cycle count
nkeynes@374
   402
    exit_block( );
nkeynes@359
   403
nkeynes@368
   404
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   405
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   406
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@368
   407
    JMP_rel8( 33 );
nkeynes@368
   408
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@368
   409
    JMP_rel8( 26 );
nkeynes@368
   410
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@368
   411
    JMP_rel8( 19 );
nkeynes@368
   412
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@368
   413
    JMP_rel8( 12 );
nkeynes@368
   414
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@368
   415
    JMP_rel8( 5 );                 
nkeynes@368
   416
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   417
    // target
nkeynes@368
   418
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   419
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   420
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   421
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   422
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   423
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   424
    MUL_r32( R_ESI );
nkeynes@368
   425
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   426
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   427
nkeynes@368
   428
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   429
    CALL_r32( R_EAX ); // 2
nkeynes@368
   430
    POP_r32(R_EBP);
nkeynes@368
   431
    RET();
nkeynes@368
   432
nkeynes@368
   433
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   434
}
nkeynes@359
   435
nkeynes@359
   436
/**
nkeynes@359
   437
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   438
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   439
 * 
nkeynes@359
   440
 *
nkeynes@359
   441
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   442
 * (eg a branch or 
nkeynes@359
   443
 */
nkeynes@359
   444
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   445
{
nkeynes@361
   446
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   447
    
nkeynes@359
   448
        switch( (ir&0xF000) >> 12 ) {
nkeynes@359
   449
            case 0x0:
nkeynes@359
   450
                switch( ir&0xF ) {
nkeynes@359
   451
                    case 0x2:
nkeynes@359
   452
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   453
                            case 0x0:
nkeynes@359
   454
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   455
                                    case 0x0:
nkeynes@359
   456
                                        { /* STC SR, Rn */
nkeynes@359
   457
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   458
                                        call_func0(sh4_read_sr);
nkeynes@368
   459
                                        store_reg( R_EAX, Rn );
nkeynes@359
   460
                                        }
nkeynes@359
   461
                                        break;
nkeynes@359
   462
                                    case 0x1:
nkeynes@359
   463
                                        { /* STC GBR, Rn */
nkeynes@359
   464
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   465
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   466
                                        store_reg( R_EAX, Rn );
nkeynes@359
   467
                                        }
nkeynes@359
   468
                                        break;
nkeynes@359
   469
                                    case 0x2:
nkeynes@359
   470
                                        { /* STC VBR, Rn */
nkeynes@359
   471
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   472
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   473
                                        store_reg( R_EAX, Rn );
nkeynes@359
   474
                                        }
nkeynes@359
   475
                                        break;
nkeynes@359
   476
                                    case 0x3:
nkeynes@359
   477
                                        { /* STC SSR, Rn */
nkeynes@359
   478
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   479
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   480
                                        store_reg( R_EAX, Rn );
nkeynes@359
   481
                                        }
nkeynes@359
   482
                                        break;
nkeynes@359
   483
                                    case 0x4:
nkeynes@359
   484
                                        { /* STC SPC, Rn */
nkeynes@359
   485
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   486
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   487
                                        store_reg( R_EAX, Rn );
nkeynes@359
   488
                                        }
nkeynes@359
   489
                                        break;
nkeynes@359
   490
                                    default:
nkeynes@359
   491
                                        UNDEF();
nkeynes@359
   492
                                        break;
nkeynes@359
   493
                                }
nkeynes@359
   494
                                break;
nkeynes@359
   495
                            case 0x1:
nkeynes@359
   496
                                { /* STC Rm_BANK, Rn */
nkeynes@359
   497
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@374
   498
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
   499
                                store_reg( R_EAX, Rn );
nkeynes@359
   500
                                }
nkeynes@359
   501
                                break;
nkeynes@359
   502
                        }
nkeynes@359
   503
                        break;
nkeynes@359
   504
                    case 0x3:
nkeynes@359
   505
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   506
                            case 0x0:
nkeynes@359
   507
                                { /* BSRF Rn */
nkeynes@359
   508
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   509
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   510
                            	SLOTILLEGAL();
nkeynes@374
   511
                                } else {
nkeynes@374
   512
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
   513
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
   514
                            	load_reg( R_EDI, Rn );
nkeynes@374
   515
                            	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
   516
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   517
                            	INC_r32(R_ESI);
nkeynes@374
   518
                            	return 0;
nkeynes@374
   519
                                }
nkeynes@359
   520
                                }
nkeynes@359
   521
                                break;
nkeynes@359
   522
                            case 0x2:
nkeynes@359
   523
                                { /* BRAF Rn */
nkeynes@359
   524
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   525
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   526
                            	SLOTILLEGAL();
nkeynes@374
   527
                                } else {
nkeynes@374
   528
                            	load_reg( R_EDI, Rn );
nkeynes@374
   529
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   530
                            	INC_r32(R_ESI);
nkeynes@374
   531
                            	return 0;
nkeynes@374
   532
                                }
nkeynes@359
   533
                                }
nkeynes@359
   534
                                break;
nkeynes@359
   535
                            case 0x8:
nkeynes@359
   536
                                { /* PREF @Rn */
nkeynes@359
   537
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
   538
                                load_reg( R_EAX, Rn );
nkeynes@374
   539
                                PUSH_r32( R_EAX );
nkeynes@374
   540
                                AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
   541
                                CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@374
   542
                                JNE_rel8(8);
nkeynes@374
   543
                                call_func0( sh4_flush_store_queue );
nkeynes@377
   544
                                ADD_imm8s_r32( 4, R_ESP );
nkeynes@359
   545
                                }
nkeynes@359
   546
                                break;
nkeynes@359
   547
                            case 0x9:
nkeynes@359
   548
                                { /* OCBI @Rn */
nkeynes@359
   549
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   550
                                }
nkeynes@359
   551
                                break;
nkeynes@359
   552
                            case 0xA:
nkeynes@359
   553
                                { /* OCBP @Rn */
nkeynes@359
   554
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   555
                                }
nkeynes@359
   556
                                break;
nkeynes@359
   557
                            case 0xB:
nkeynes@359
   558
                                { /* OCBWB @Rn */
nkeynes@359
   559
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   560
                                }
nkeynes@359
   561
                                break;
nkeynes@359
   562
                            case 0xC:
nkeynes@359
   563
                                { /* MOVCA.L R0, @Rn */
nkeynes@359
   564
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
   565
                                load_reg( R_EAX, 0 );
nkeynes@361
   566
                                load_reg( R_ECX, Rn );
nkeynes@374
   567
                                check_walign32( R_ECX );
nkeynes@361
   568
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   569
                                }
nkeynes@359
   570
                                break;
nkeynes@359
   571
                            default:
nkeynes@359
   572
                                UNDEF();
nkeynes@359
   573
                                break;
nkeynes@359
   574
                        }
nkeynes@359
   575
                        break;
nkeynes@359
   576
                    case 0x4:
nkeynes@359
   577
                        { /* MOV.B Rm, @(R0, Rn) */
nkeynes@359
   578
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   579
                        load_reg( R_EAX, 0 );
nkeynes@359
   580
                        load_reg( R_ECX, Rn );
nkeynes@359
   581
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   582
                        load_reg( R_EAX, Rm );
nkeynes@359
   583
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   584
                        }
nkeynes@359
   585
                        break;
nkeynes@359
   586
                    case 0x5:
nkeynes@359
   587
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   588
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   589
                        load_reg( R_EAX, 0 );
nkeynes@361
   590
                        load_reg( R_ECX, Rn );
nkeynes@361
   591
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   592
                        check_walign16( R_ECX );
nkeynes@361
   593
                        load_reg( R_EAX, Rm );
nkeynes@361
   594
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   595
                        }
nkeynes@359
   596
                        break;
nkeynes@359
   597
                    case 0x6:
nkeynes@359
   598
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   599
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   600
                        load_reg( R_EAX, 0 );
nkeynes@361
   601
                        load_reg( R_ECX, Rn );
nkeynes@361
   602
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   603
                        check_walign32( R_ECX );
nkeynes@361
   604
                        load_reg( R_EAX, Rm );
nkeynes@361
   605
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   606
                        }
nkeynes@359
   607
                        break;
nkeynes@359
   608
                    case 0x7:
nkeynes@359
   609
                        { /* MUL.L Rm, Rn */
nkeynes@359
   610
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   611
                        load_reg( R_EAX, Rm );
nkeynes@361
   612
                        load_reg( R_ECX, Rn );
nkeynes@361
   613
                        MUL_r32( R_ECX );
nkeynes@361
   614
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   615
                        }
nkeynes@359
   616
                        break;
nkeynes@359
   617
                    case 0x8:
nkeynes@359
   618
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   619
                            case 0x0:
nkeynes@359
   620
                                { /* CLRT */
nkeynes@374
   621
                                CLC();
nkeynes@374
   622
                                SETC_t();
nkeynes@359
   623
                                }
nkeynes@359
   624
                                break;
nkeynes@359
   625
                            case 0x1:
nkeynes@359
   626
                                { /* SETT */
nkeynes@374
   627
                                STC();
nkeynes@374
   628
                                SETC_t();
nkeynes@359
   629
                                }
nkeynes@359
   630
                                break;
nkeynes@359
   631
                            case 0x2:
nkeynes@359
   632
                                { /* CLRMAC */
nkeynes@374
   633
                                XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
   634
                                store_spreg( R_EAX, R_MACL );
nkeynes@374
   635
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
   636
                                }
nkeynes@359
   637
                                break;
nkeynes@359
   638
                            case 0x3:
nkeynes@359
   639
                                { /* LDTLB */
nkeynes@359
   640
                                }
nkeynes@359
   641
                                break;
nkeynes@359
   642
                            case 0x4:
nkeynes@359
   643
                                { /* CLRS */
nkeynes@374
   644
                                CLC();
nkeynes@374
   645
                                SETC_sh4r(R_S);
nkeynes@359
   646
                                }
nkeynes@359
   647
                                break;
nkeynes@359
   648
                            case 0x5:
nkeynes@359
   649
                                { /* SETS */
nkeynes@374
   650
                                STC();
nkeynes@374
   651
                                SETC_sh4r(R_S);
nkeynes@359
   652
                                }
nkeynes@359
   653
                                break;
nkeynes@359
   654
                            default:
nkeynes@359
   655
                                UNDEF();
nkeynes@359
   656
                                break;
nkeynes@359
   657
                        }
nkeynes@359
   658
                        break;
nkeynes@359
   659
                    case 0x9:
nkeynes@359
   660
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   661
                            case 0x0:
nkeynes@359
   662
                                { /* NOP */
nkeynes@359
   663
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   664
                                }
nkeynes@359
   665
                                break;
nkeynes@359
   666
                            case 0x1:
nkeynes@359
   667
                                { /* DIV0U */
nkeynes@361
   668
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   669
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   670
                                store_spreg( R_EAX, R_M );
nkeynes@361
   671
                                store_spreg( R_EAX, R_T );
nkeynes@359
   672
                                }
nkeynes@359
   673
                                break;
nkeynes@359
   674
                            case 0x2:
nkeynes@359
   675
                                { /* MOVT Rn */
nkeynes@359
   676
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   677
                                load_spreg( R_EAX, R_T );
nkeynes@359
   678
                                store_reg( R_EAX, Rn );
nkeynes@359
   679
                                }
nkeynes@359
   680
                                break;
nkeynes@359
   681
                            default:
nkeynes@359
   682
                                UNDEF();
nkeynes@359
   683
                                break;
nkeynes@359
   684
                        }
nkeynes@359
   685
                        break;
nkeynes@359
   686
                    case 0xA:
nkeynes@359
   687
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   688
                            case 0x0:
nkeynes@359
   689
                                { /* STS MACH, Rn */
nkeynes@359
   690
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   691
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   692
                                store_reg( R_EAX, Rn );
nkeynes@359
   693
                                }
nkeynes@359
   694
                                break;
nkeynes@359
   695
                            case 0x1:
nkeynes@359
   696
                                { /* STS MACL, Rn */
nkeynes@359
   697
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   698
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   699
                                store_reg( R_EAX, Rn );
nkeynes@359
   700
                                }
nkeynes@359
   701
                                break;
nkeynes@359
   702
                            case 0x2:
nkeynes@359
   703
                                { /* STS PR, Rn */
nkeynes@359
   704
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   705
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   706
                                store_reg( R_EAX, Rn );
nkeynes@359
   707
                                }
nkeynes@359
   708
                                break;
nkeynes@359
   709
                            case 0x3:
nkeynes@359
   710
                                { /* STC SGR, Rn */
nkeynes@359
   711
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   712
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   713
                                store_reg( R_EAX, Rn );
nkeynes@359
   714
                                }
nkeynes@359
   715
                                break;
nkeynes@359
   716
                            case 0x5:
nkeynes@359
   717
                                { /* STS FPUL, Rn */
nkeynes@359
   718
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   719
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   720
                                store_reg( R_EAX, Rn );
nkeynes@359
   721
                                }
nkeynes@359
   722
                                break;
nkeynes@359
   723
                            case 0x6:
nkeynes@359
   724
                                { /* STS FPSCR, Rn */
nkeynes@359
   725
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   726
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   727
                                store_reg( R_EAX, Rn );
nkeynes@359
   728
                                }
nkeynes@359
   729
                                break;
nkeynes@359
   730
                            case 0xF:
nkeynes@359
   731
                                { /* STC DBR, Rn */
nkeynes@359
   732
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   733
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   734
                                store_reg( R_EAX, Rn );
nkeynes@359
   735
                                }
nkeynes@359
   736
                                break;
nkeynes@359
   737
                            default:
nkeynes@359
   738
                                UNDEF();
nkeynes@359
   739
                                break;
nkeynes@359
   740
                        }
nkeynes@359
   741
                        break;
nkeynes@359
   742
                    case 0xB:
nkeynes@359
   743
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   744
                            case 0x0:
nkeynes@359
   745
                                { /* RTS */
nkeynes@374
   746
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   747
                            	SLOTILLEGAL();
nkeynes@374
   748
                                } else {
nkeynes@374
   749
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   750
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
   751
                            	INC_r32(R_ESI);
nkeynes@374
   752
                            	return 0;
nkeynes@374
   753
                                }
nkeynes@359
   754
                                }
nkeynes@359
   755
                                break;
nkeynes@359
   756
                            case 0x1:
nkeynes@359
   757
                                { /* SLEEP */
nkeynes@374
   758
                                /* TODO */
nkeynes@359
   759
                                }
nkeynes@359
   760
                                break;
nkeynes@359
   761
                            case 0x2:
nkeynes@359
   762
                                { /* RTE */
nkeynes@374
   763
                                check_priv();
nkeynes@374
   764
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
   765
                            	SLOTILLEGAL();
nkeynes@374
   766
                                } else {
nkeynes@374
   767
                            	load_spreg( R_EDI, R_PR );
nkeynes@374
   768
                            	load_spreg( R_EAX, R_SSR );
nkeynes@374
   769
                            	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
   770
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
   771
                            	sh4_x86.priv_checked = FALSE;
nkeynes@377
   772
                            	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
   773
                            	INC_r32(R_ESI);
nkeynes@374
   774
                            	return 0;
nkeynes@374
   775
                                }
nkeynes@359
   776
                                }
nkeynes@359
   777
                                break;
nkeynes@359
   778
                            default:
nkeynes@359
   779
                                UNDEF();
nkeynes@359
   780
                                break;
nkeynes@359
   781
                        }
nkeynes@359
   782
                        break;
nkeynes@359
   783
                    case 0xC:
nkeynes@359
   784
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   785
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   786
                        load_reg( R_EAX, 0 );
nkeynes@359
   787
                        load_reg( R_ECX, Rm );
nkeynes@359
   788
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   789
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   790
                        store_reg( R_EAX, Rn );
nkeynes@359
   791
                        }
nkeynes@359
   792
                        break;
nkeynes@359
   793
                    case 0xD:
nkeynes@359
   794
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   795
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   796
                        load_reg( R_EAX, 0 );
nkeynes@361
   797
                        load_reg( R_ECX, Rm );
nkeynes@361
   798
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   799
                        check_ralign16( R_ECX );
nkeynes@361
   800
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   801
                        store_reg( R_EAX, Rn );
nkeynes@359
   802
                        }
nkeynes@359
   803
                        break;
nkeynes@359
   804
                    case 0xE:
nkeynes@359
   805
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   806
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   807
                        load_reg( R_EAX, 0 );
nkeynes@361
   808
                        load_reg( R_ECX, Rm );
nkeynes@361
   809
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   810
                        check_ralign32( R_ECX );
nkeynes@361
   811
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   812
                        store_reg( R_EAX, Rn );
nkeynes@359
   813
                        }
nkeynes@359
   814
                        break;
nkeynes@359
   815
                    case 0xF:
nkeynes@359
   816
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   817
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   818
                        }
nkeynes@359
   819
                        break;
nkeynes@359
   820
                    default:
nkeynes@359
   821
                        UNDEF();
nkeynes@359
   822
                        break;
nkeynes@359
   823
                }
nkeynes@359
   824
                break;
nkeynes@359
   825
            case 0x1:
nkeynes@359
   826
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   827
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   828
                load_reg( R_ECX, Rn );
nkeynes@361
   829
                load_reg( R_EAX, Rm );
nkeynes@361
   830
                ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   831
                check_walign32( R_ECX );
nkeynes@361
   832
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   833
                }
nkeynes@359
   834
                break;
nkeynes@359
   835
            case 0x2:
nkeynes@359
   836
                switch( ir&0xF ) {
nkeynes@359
   837
                    case 0x0:
nkeynes@359
   838
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   839
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   840
                        load_reg( R_EAX, Rm );
nkeynes@359
   841
                        load_reg( R_ECX, Rn );
nkeynes@359
   842
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   843
                        }
nkeynes@359
   844
                        break;
nkeynes@359
   845
                    case 0x1:
nkeynes@359
   846
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   847
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   848
                        load_reg( R_ECX, Rn );
nkeynes@374
   849
                        check_walign16( R_ECX );
nkeynes@361
   850
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   851
                        store_reg( R_EAX, Rn );
nkeynes@359
   852
                        }
nkeynes@359
   853
                        break;
nkeynes@359
   854
                    case 0x2:
nkeynes@359
   855
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   856
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   857
                        load_reg( R_EAX, Rm );
nkeynes@361
   858
                        load_reg( R_ECX, Rn );
nkeynes@374
   859
                        check_walign32(R_ECX);
nkeynes@361
   860
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   861
                        }
nkeynes@359
   862
                        break;
nkeynes@359
   863
                    case 0x4:
nkeynes@359
   864
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   865
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   866
                        load_reg( R_EAX, Rm );
nkeynes@359
   867
                        load_reg( R_ECX, Rn );
nkeynes@359
   868
                        ADD_imm8s_r32( -1, Rn );
nkeynes@359
   869
                        store_reg( R_ECX, Rn );
nkeynes@359
   870
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   871
                        }
nkeynes@359
   872
                        break;
nkeynes@359
   873
                    case 0x5:
nkeynes@359
   874
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   875
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   876
                        load_reg( R_ECX, Rn );
nkeynes@374
   877
                        check_walign16( R_ECX );
nkeynes@361
   878
                        load_reg( R_EAX, Rm );
nkeynes@361
   879
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   880
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   881
                        }
nkeynes@359
   882
                        break;
nkeynes@359
   883
                    case 0x6:
nkeynes@359
   884
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   885
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   886
                        load_reg( R_EAX, Rm );
nkeynes@361
   887
                        load_reg( R_ECX, Rn );
nkeynes@374
   888
                        check_walign32( R_ECX );
nkeynes@361
   889
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   890
                        store_reg( R_ECX, Rn );
nkeynes@361
   891
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   892
                        }
nkeynes@359
   893
                        break;
nkeynes@359
   894
                    case 0x7:
nkeynes@359
   895
                        { /* DIV0S Rm, Rn */
nkeynes@359
   896
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   897
                        load_reg( R_EAX, Rm );
nkeynes@361
   898
                        load_reg( R_ECX, Rm );
nkeynes@361
   899
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   900
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   901
                        store_spreg( R_EAX, R_M );
nkeynes@361
   902
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   903
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   904
                        SETE_t();
nkeynes@359
   905
                        }
nkeynes@359
   906
                        break;
nkeynes@359
   907
                    case 0x8:
nkeynes@359
   908
                        { /* TST Rm, Rn */
nkeynes@359
   909
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   910
                        load_reg( R_EAX, Rm );
nkeynes@361
   911
                        load_reg( R_ECX, Rn );
nkeynes@361
   912
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   913
                        SETE_t();
nkeynes@359
   914
                        }
nkeynes@359
   915
                        break;
nkeynes@359
   916
                    case 0x9:
nkeynes@359
   917
                        { /* AND Rm, Rn */
nkeynes@359
   918
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   919
                        load_reg( R_EAX, Rm );
nkeynes@359
   920
                        load_reg( R_ECX, Rn );
nkeynes@359
   921
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   922
                        store_reg( R_ECX, Rn );
nkeynes@359
   923
                        }
nkeynes@359
   924
                        break;
nkeynes@359
   925
                    case 0xA:
nkeynes@359
   926
                        { /* XOR Rm, Rn */
nkeynes@359
   927
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   928
                        load_reg( R_EAX, Rm );
nkeynes@359
   929
                        load_reg( R_ECX, Rn );
nkeynes@359
   930
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   931
                        store_reg( R_ECX, Rn );
nkeynes@359
   932
                        }
nkeynes@359
   933
                        break;
nkeynes@359
   934
                    case 0xB:
nkeynes@359
   935
                        { /* OR Rm, Rn */
nkeynes@359
   936
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   937
                        load_reg( R_EAX, Rm );
nkeynes@359
   938
                        load_reg( R_ECX, Rn );
nkeynes@359
   939
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   940
                        store_reg( R_ECX, Rn );
nkeynes@359
   941
                        }
nkeynes@359
   942
                        break;
nkeynes@359
   943
                    case 0xC:
nkeynes@359
   944
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   945
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
   946
                        load_reg( R_EAX, Rm );
nkeynes@368
   947
                        load_reg( R_ECX, Rn );
nkeynes@368
   948
                        XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   949
                        TEST_r8_r8( R_AL, R_AL );
nkeynes@368
   950
                        JE_rel8(13);
nkeynes@368
   951
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   952
                        JE_rel8(9);
nkeynes@368
   953
                        SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   954
                        TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@368
   955
                        JE_rel8(2);
nkeynes@368
   956
                        TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   957
                        SETE_t();
nkeynes@359
   958
                        }
nkeynes@359
   959
                        break;
nkeynes@359
   960
                    case 0xD:
nkeynes@359
   961
                        { /* XTRCT Rm, Rn */
nkeynes@359
   962
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   963
                        load_reg( R_EAX, Rm );
nkeynes@361
   964
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   965
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   966
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   967
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   968
                        store_reg( R_ECX, Rn );
nkeynes@359
   969
                        }
nkeynes@359
   970
                        break;
nkeynes@359
   971
                    case 0xE:
nkeynes@359
   972
                        { /* MULU.W Rm, Rn */
nkeynes@359
   973
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   974
                        load_reg16u( R_EAX, Rm );
nkeynes@374
   975
                        load_reg16u( R_ECX, Rn );
nkeynes@374
   976
                        MUL_r32( R_ECX );
nkeynes@374
   977
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   978
                        }
nkeynes@359
   979
                        break;
nkeynes@359
   980
                    case 0xF:
nkeynes@359
   981
                        { /* MULS.W Rm, Rn */
nkeynes@359
   982
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
   983
                        load_reg16s( R_EAX, Rm );
nkeynes@374
   984
                        load_reg16s( R_ECX, Rn );
nkeynes@374
   985
                        MUL_r32( R_ECX );
nkeynes@374
   986
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   987
                        }
nkeynes@359
   988
                        break;
nkeynes@359
   989
                    default:
nkeynes@359
   990
                        UNDEF();
nkeynes@359
   991
                        break;
nkeynes@359
   992
                }
nkeynes@359
   993
                break;
nkeynes@359
   994
            case 0x3:
nkeynes@359
   995
                switch( ir&0xF ) {
nkeynes@359
   996
                    case 0x0:
nkeynes@359
   997
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   998
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   999
                        load_reg( R_EAX, Rm );
nkeynes@359
  1000
                        load_reg( R_ECX, Rn );
nkeynes@359
  1001
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1002
                        SETE_t();
nkeynes@359
  1003
                        }
nkeynes@359
  1004
                        break;
nkeynes@359
  1005
                    case 0x2:
nkeynes@359
  1006
                        { /* CMP/HS Rm, Rn */
nkeynes@359
  1007
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1008
                        load_reg( R_EAX, Rm );
nkeynes@359
  1009
                        load_reg( R_ECX, Rn );
nkeynes@359
  1010
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1011
                        SETAE_t();
nkeynes@359
  1012
                        }
nkeynes@359
  1013
                        break;
nkeynes@359
  1014
                    case 0x3:
nkeynes@359
  1015
                        { /* CMP/GE Rm, Rn */
nkeynes@359
  1016
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1017
                        load_reg( R_EAX, Rm );
nkeynes@359
  1018
                        load_reg( R_ECX, Rn );
nkeynes@359
  1019
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1020
                        SETGE_t();
nkeynes@359
  1021
                        }
nkeynes@359
  1022
                        break;
nkeynes@359
  1023
                    case 0x4:
nkeynes@359
  1024
                        { /* DIV1 Rm, Rn */
nkeynes@359
  1025
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@374
  1026
                        load_reg( R_ECX, Rn );
nkeynes@374
  1027
                        LDC_t();
nkeynes@374
  1028
                        RCL1_r32( R_ECX ); // OP2
nkeynes@374
  1029
                        SETC_r32( R_EDX ); // Q
nkeynes@374
  1030
                        load_spreg( R_EAX, R_Q );
nkeynes@374
  1031
                        CMP_sh4r_r32( R_M, R_EAX );
nkeynes@374
  1032
                        JE_rel8(8);
nkeynes@374
  1033
                        ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
  1034
                        JMP_rel8(3);
nkeynes@374
  1035
                        SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
  1036
                        // TODO
nkeynes@359
  1037
                        }
nkeynes@359
  1038
                        break;
nkeynes@359
  1039
                    case 0x5:
nkeynes@359
  1040
                        { /* DMULU.L Rm, Rn */
nkeynes@359
  1041
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1042
                        load_reg( R_EAX, Rm );
nkeynes@361
  1043
                        load_reg( R_ECX, Rn );
nkeynes@361
  1044
                        MUL_r32(R_ECX);
nkeynes@361
  1045
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1046
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1047
                        }
nkeynes@359
  1048
                        break;
nkeynes@359
  1049
                    case 0x6:
nkeynes@359
  1050
                        { /* CMP/HI Rm, Rn */
nkeynes@359
  1051
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1052
                        load_reg( R_EAX, Rm );
nkeynes@359
  1053
                        load_reg( R_ECX, Rn );
nkeynes@359
  1054
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1055
                        SETA_t();
nkeynes@359
  1056
                        }
nkeynes@359
  1057
                        break;
nkeynes@359
  1058
                    case 0x7:
nkeynes@359
  1059
                        { /* CMP/GT Rm, Rn */
nkeynes@359
  1060
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1061
                        load_reg( R_EAX, Rm );
nkeynes@359
  1062
                        load_reg( R_ECX, Rn );
nkeynes@359
  1063
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1064
                        SETG_t();
nkeynes@359
  1065
                        }
nkeynes@359
  1066
                        break;
nkeynes@359
  1067
                    case 0x8:
nkeynes@359
  1068
                        { /* SUB Rm, Rn */
nkeynes@359
  1069
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1070
                        load_reg( R_EAX, Rm );
nkeynes@359
  1071
                        load_reg( R_ECX, Rn );
nkeynes@359
  1072
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1073
                        store_reg( R_ECX, Rn );
nkeynes@359
  1074
                        }
nkeynes@359
  1075
                        break;
nkeynes@359
  1076
                    case 0xA:
nkeynes@359
  1077
                        { /* SUBC Rm, Rn */
nkeynes@359
  1078
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1079
                        load_reg( R_EAX, Rm );
nkeynes@359
  1080
                        load_reg( R_ECX, Rn );
nkeynes@359
  1081
                        LDC_t();
nkeynes@359
  1082
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1083
                        store_reg( R_ECX, Rn );
nkeynes@359
  1084
                        }
nkeynes@359
  1085
                        break;
nkeynes@359
  1086
                    case 0xB:
nkeynes@359
  1087
                        { /* SUBV Rm, Rn */
nkeynes@359
  1088
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1089
                        load_reg( R_EAX, Rm );
nkeynes@359
  1090
                        load_reg( R_ECX, Rn );
nkeynes@359
  1091
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1092
                        store_reg( R_ECX, Rn );
nkeynes@359
  1093
                        SETO_t();
nkeynes@359
  1094
                        }
nkeynes@359
  1095
                        break;
nkeynes@359
  1096
                    case 0xC:
nkeynes@359
  1097
                        { /* ADD Rm, Rn */
nkeynes@359
  1098
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1099
                        load_reg( R_EAX, Rm );
nkeynes@359
  1100
                        load_reg( R_ECX, Rn );
nkeynes@359
  1101
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1102
                        store_reg( R_ECX, Rn );
nkeynes@359
  1103
                        }
nkeynes@359
  1104
                        break;
nkeynes@359
  1105
                    case 0xD:
nkeynes@359
  1106
                        { /* DMULS.L Rm, Rn */
nkeynes@359
  1107
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1108
                        load_reg( R_EAX, Rm );
nkeynes@361
  1109
                        load_reg( R_ECX, Rn );
nkeynes@361
  1110
                        IMUL_r32(R_ECX);
nkeynes@361
  1111
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
  1112
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
  1113
                        }
nkeynes@359
  1114
                        break;
nkeynes@359
  1115
                    case 0xE:
nkeynes@359
  1116
                        { /* ADDC Rm, Rn */
nkeynes@359
  1117
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1118
                        load_reg( R_EAX, Rm );
nkeynes@359
  1119
                        load_reg( R_ECX, Rn );
nkeynes@359
  1120
                        LDC_t();
nkeynes@359
  1121
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1122
                        store_reg( R_ECX, Rn );
nkeynes@359
  1123
                        SETC_t();
nkeynes@359
  1124
                        }
nkeynes@359
  1125
                        break;
nkeynes@359
  1126
                    case 0xF:
nkeynes@359
  1127
                        { /* ADDV Rm, Rn */
nkeynes@359
  1128
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1129
                        load_reg( R_EAX, Rm );
nkeynes@359
  1130
                        load_reg( R_ECX, Rn );
nkeynes@359
  1131
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1132
                        store_reg( R_ECX, Rn );
nkeynes@359
  1133
                        SETO_t();
nkeynes@359
  1134
                        }
nkeynes@359
  1135
                        break;
nkeynes@359
  1136
                    default:
nkeynes@359
  1137
                        UNDEF();
nkeynes@359
  1138
                        break;
nkeynes@359
  1139
                }
nkeynes@359
  1140
                break;
nkeynes@359
  1141
            case 0x4:
nkeynes@359
  1142
                switch( ir&0xF ) {
nkeynes@359
  1143
                    case 0x0:
nkeynes@359
  1144
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1145
                            case 0x0:
nkeynes@359
  1146
                                { /* SHLL Rn */
nkeynes@359
  1147
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1148
                                load_reg( R_EAX, Rn );
nkeynes@359
  1149
                                SHL1_r32( R_EAX );
nkeynes@359
  1150
                                store_reg( R_EAX, Rn );
nkeynes@359
  1151
                                }
nkeynes@359
  1152
                                break;
nkeynes@359
  1153
                            case 0x1:
nkeynes@359
  1154
                                { /* DT Rn */
nkeynes@359
  1155
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1156
                                load_reg( R_EAX, Rn );
nkeynes@359
  1157
                                ADD_imm8s_r32( -1, Rn );
nkeynes@359
  1158
                                store_reg( R_EAX, Rn );
nkeynes@359
  1159
                                SETE_t();
nkeynes@359
  1160
                                }
nkeynes@359
  1161
                                break;
nkeynes@359
  1162
                            case 0x2:
nkeynes@359
  1163
                                { /* SHAL Rn */
nkeynes@359
  1164
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1165
                                load_reg( R_EAX, Rn );
nkeynes@359
  1166
                                SHL1_r32( R_EAX );
nkeynes@359
  1167
                                store_reg( R_EAX, Rn );
nkeynes@359
  1168
                                }
nkeynes@359
  1169
                                break;
nkeynes@359
  1170
                            default:
nkeynes@359
  1171
                                UNDEF();
nkeynes@359
  1172
                                break;
nkeynes@359
  1173
                        }
nkeynes@359
  1174
                        break;
nkeynes@359
  1175
                    case 0x1:
nkeynes@359
  1176
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1177
                            case 0x0:
nkeynes@359
  1178
                                { /* SHLR Rn */
nkeynes@359
  1179
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1180
                                load_reg( R_EAX, Rn );
nkeynes@359
  1181
                                SHR1_r32( R_EAX );
nkeynes@359
  1182
                                store_reg( R_EAX, Rn );
nkeynes@359
  1183
                                }
nkeynes@359
  1184
                                break;
nkeynes@359
  1185
                            case 0x1:
nkeynes@359
  1186
                                { /* CMP/PZ Rn */
nkeynes@359
  1187
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1188
                                load_reg( R_EAX, Rn );
nkeynes@359
  1189
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1190
                                SETGE_t();
nkeynes@359
  1191
                                }
nkeynes@359
  1192
                                break;
nkeynes@359
  1193
                            case 0x2:
nkeynes@359
  1194
                                { /* SHAR Rn */
nkeynes@359
  1195
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1196
                                load_reg( R_EAX, Rn );
nkeynes@359
  1197
                                SAR1_r32( R_EAX );
nkeynes@359
  1198
                                store_reg( R_EAX, Rn );
nkeynes@359
  1199
                                }
nkeynes@359
  1200
                                break;
nkeynes@359
  1201
                            default:
nkeynes@359
  1202
                                UNDEF();
nkeynes@359
  1203
                                break;
nkeynes@359
  1204
                        }
nkeynes@359
  1205
                        break;
nkeynes@359
  1206
                    case 0x2:
nkeynes@359
  1207
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1208
                            case 0x0:
nkeynes@359
  1209
                                { /* STS.L MACH, @-Rn */
nkeynes@359
  1210
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1211
                                load_reg( R_ECX, Rn );
nkeynes@359
  1212
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1213
                                store_reg( R_ECX, Rn );
nkeynes@359
  1214
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
  1215
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1216
                                }
nkeynes@359
  1217
                                break;
nkeynes@359
  1218
                            case 0x1:
nkeynes@359
  1219
                                { /* STS.L MACL, @-Rn */
nkeynes@359
  1220
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1221
                                load_reg( R_ECX, Rn );
nkeynes@359
  1222
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1223
                                store_reg( R_ECX, Rn );
nkeynes@359
  1224
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
  1225
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1226
                                }
nkeynes@359
  1227
                                break;
nkeynes@359
  1228
                            case 0x2:
nkeynes@359
  1229
                                { /* STS.L PR, @-Rn */
nkeynes@359
  1230
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1231
                                load_reg( R_ECX, Rn );
nkeynes@359
  1232
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1233
                                store_reg( R_ECX, Rn );
nkeynes@359
  1234
                                load_spreg( R_EAX, R_PR );
nkeynes@359
  1235
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1236
                                }
nkeynes@359
  1237
                                break;
nkeynes@359
  1238
                            case 0x3:
nkeynes@359
  1239
                                { /* STC.L SGR, @-Rn */
nkeynes@359
  1240
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1241
                                load_reg( R_ECX, Rn );
nkeynes@359
  1242
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1243
                                store_reg( R_ECX, Rn );
nkeynes@359
  1244
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
  1245
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1246
                                }
nkeynes@359
  1247
                                break;
nkeynes@359
  1248
                            case 0x5:
nkeynes@359
  1249
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
  1250
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1251
                                load_reg( R_ECX, Rn );
nkeynes@359
  1252
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1253
                                store_reg( R_ECX, Rn );
nkeynes@359
  1254
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
  1255
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1256
                                }
nkeynes@359
  1257
                                break;
nkeynes@359
  1258
                            case 0x6:
nkeynes@359
  1259
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
  1260
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1261
                                load_reg( R_ECX, Rn );
nkeynes@359
  1262
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1263
                                store_reg( R_ECX, Rn );
nkeynes@359
  1264
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1265
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1266
                                }
nkeynes@359
  1267
                                break;
nkeynes@359
  1268
                            case 0xF:
nkeynes@359
  1269
                                { /* STC.L DBR, @-Rn */
nkeynes@359
  1270
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1271
                                load_reg( R_ECX, Rn );
nkeynes@359
  1272
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1273
                                store_reg( R_ECX, Rn );
nkeynes@359
  1274
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
  1275
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1276
                                }
nkeynes@359
  1277
                                break;
nkeynes@359
  1278
                            default:
nkeynes@359
  1279
                                UNDEF();
nkeynes@359
  1280
                                break;
nkeynes@359
  1281
                        }
nkeynes@359
  1282
                        break;
nkeynes@359
  1283
                    case 0x3:
nkeynes@359
  1284
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1285
                            case 0x0:
nkeynes@359
  1286
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1287
                                    case 0x0:
nkeynes@359
  1288
                                        { /* STC.L SR, @-Rn */
nkeynes@359
  1289
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1290
                                        load_reg( R_ECX, Rn );
nkeynes@374
  1291
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1292
                                        store_reg( R_ECX, Rn );
nkeynes@374
  1293
                                        call_func0( sh4_read_sr );
nkeynes@374
  1294
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1295
                                        }
nkeynes@359
  1296
                                        break;
nkeynes@359
  1297
                                    case 0x1:
nkeynes@359
  1298
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
  1299
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1300
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1301
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1302
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1303
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
  1304
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1305
                                        }
nkeynes@359
  1306
                                        break;
nkeynes@359
  1307
                                    case 0x2:
nkeynes@359
  1308
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
  1309
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1310
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1311
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1312
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1313
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
  1314
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1315
                                        }
nkeynes@359
  1316
                                        break;
nkeynes@359
  1317
                                    case 0x3:
nkeynes@359
  1318
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
  1319
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1320
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1321
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1322
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1323
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
  1324
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1325
                                        }
nkeynes@359
  1326
                                        break;
nkeynes@359
  1327
                                    case 0x4:
nkeynes@359
  1328
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
  1329
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1330
                                        load_reg( R_ECX, Rn );
nkeynes@359
  1331
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1332
                                        store_reg( R_ECX, Rn );
nkeynes@359
  1333
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
  1334
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1335
                                        }
nkeynes@359
  1336
                                        break;
nkeynes@359
  1337
                                    default:
nkeynes@359
  1338
                                        UNDEF();
nkeynes@359
  1339
                                        break;
nkeynes@359
  1340
                                }
nkeynes@359
  1341
                                break;
nkeynes@359
  1342
                            case 0x1:
nkeynes@359
  1343
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
  1344
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1345
                                load_reg( R_ECX, Rn );
nkeynes@374
  1346
                                ADD_imm8s_r32( -4, Rn );
nkeynes@374
  1347
                                store_reg( R_ECX, Rn );
nkeynes@374
  1348
                                load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1349
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1350
                                }
nkeynes@359
  1351
                                break;
nkeynes@359
  1352
                        }
nkeynes@359
  1353
                        break;
nkeynes@359
  1354
                    case 0x4:
nkeynes@359
  1355
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1356
                            case 0x0:
nkeynes@359
  1357
                                { /* ROTL Rn */
nkeynes@359
  1358
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1359
                                load_reg( R_EAX, Rn );
nkeynes@359
  1360
                                ROL1_r32( R_EAX );
nkeynes@359
  1361
                                store_reg( R_EAX, Rn );
nkeynes@359
  1362
                                SETC_t();
nkeynes@359
  1363
                                }
nkeynes@359
  1364
                                break;
nkeynes@359
  1365
                            case 0x2:
nkeynes@359
  1366
                                { /* ROTCL Rn */
nkeynes@359
  1367
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1368
                                load_reg( R_EAX, Rn );
nkeynes@359
  1369
                                LDC_t();
nkeynes@359
  1370
                                RCL1_r32( R_EAX );
nkeynes@359
  1371
                                store_reg( R_EAX, Rn );
nkeynes@359
  1372
                                SETC_t();
nkeynes@359
  1373
                                }
nkeynes@359
  1374
                                break;
nkeynes@359
  1375
                            default:
nkeynes@359
  1376
                                UNDEF();
nkeynes@359
  1377
                                break;
nkeynes@359
  1378
                        }
nkeynes@359
  1379
                        break;
nkeynes@359
  1380
                    case 0x5:
nkeynes@359
  1381
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1382
                            case 0x0:
nkeynes@359
  1383
                                { /* ROTR Rn */
nkeynes@359
  1384
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1385
                                load_reg( R_EAX, Rn );
nkeynes@359
  1386
                                ROR1_r32( R_EAX );
nkeynes@359
  1387
                                store_reg( R_EAX, Rn );
nkeynes@359
  1388
                                SETC_t();
nkeynes@359
  1389
                                }
nkeynes@359
  1390
                                break;
nkeynes@359
  1391
                            case 0x1:
nkeynes@359
  1392
                                { /* CMP/PL Rn */
nkeynes@359
  1393
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1394
                                load_reg( R_EAX, Rn );
nkeynes@359
  1395
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
  1396
                                SETG_t();
nkeynes@359
  1397
                                }
nkeynes@359
  1398
                                break;
nkeynes@359
  1399
                            case 0x2:
nkeynes@359
  1400
                                { /* ROTCR Rn */
nkeynes@359
  1401
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1402
                                load_reg( R_EAX, Rn );
nkeynes@359
  1403
                                LDC_t();
nkeynes@359
  1404
                                RCR1_r32( R_EAX );
nkeynes@359
  1405
                                store_reg( R_EAX, Rn );
nkeynes@359
  1406
                                SETC_t();
nkeynes@359
  1407
                                }
nkeynes@359
  1408
                                break;
nkeynes@359
  1409
                            default:
nkeynes@359
  1410
                                UNDEF();
nkeynes@359
  1411
                                break;
nkeynes@359
  1412
                        }
nkeynes@359
  1413
                        break;
nkeynes@359
  1414
                    case 0x6:
nkeynes@359
  1415
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1416
                            case 0x0:
nkeynes@359
  1417
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1418
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1419
                                load_reg( R_EAX, Rm );
nkeynes@359
  1420
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1421
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1422
                                store_reg( R_EAX, Rm );
nkeynes@359
  1423
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1424
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1425
                                }
nkeynes@359
  1426
                                break;
nkeynes@359
  1427
                            case 0x1:
nkeynes@359
  1428
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1429
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1430
                                load_reg( R_EAX, Rm );
nkeynes@359
  1431
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1432
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1433
                                store_reg( R_EAX, Rm );
nkeynes@359
  1434
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1435
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1436
                                }
nkeynes@359
  1437
                                break;
nkeynes@359
  1438
                            case 0x2:
nkeynes@359
  1439
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1440
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1441
                                load_reg( R_EAX, Rm );
nkeynes@359
  1442
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1443
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1444
                                store_reg( R_EAX, Rm );
nkeynes@359
  1445
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1446
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1447
                                }
nkeynes@359
  1448
                                break;
nkeynes@359
  1449
                            case 0x3:
nkeynes@359
  1450
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1451
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1452
                                load_reg( R_EAX, Rm );
nkeynes@359
  1453
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1454
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1455
                                store_reg( R_EAX, Rm );
nkeynes@359
  1456
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1457
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1458
                                }
nkeynes@359
  1459
                                break;
nkeynes@359
  1460
                            case 0x5:
nkeynes@359
  1461
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1462
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1463
                                load_reg( R_EAX, Rm );
nkeynes@359
  1464
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1465
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1466
                                store_reg( R_EAX, Rm );
nkeynes@359
  1467
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1468
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1469
                                }
nkeynes@359
  1470
                                break;
nkeynes@359
  1471
                            case 0x6:
nkeynes@359
  1472
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1473
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1474
                                load_reg( R_EAX, Rm );
nkeynes@359
  1475
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1476
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1477
                                store_reg( R_EAX, Rm );
nkeynes@359
  1478
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1479
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1480
                                }
nkeynes@359
  1481
                                break;
nkeynes@359
  1482
                            case 0xF:
nkeynes@359
  1483
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1484
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1485
                                load_reg( R_EAX, Rm );
nkeynes@359
  1486
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1487
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1488
                                store_reg( R_EAX, Rm );
nkeynes@359
  1489
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1490
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1491
                                }
nkeynes@359
  1492
                                break;
nkeynes@359
  1493
                            default:
nkeynes@359
  1494
                                UNDEF();
nkeynes@359
  1495
                                break;
nkeynes@359
  1496
                        }
nkeynes@359
  1497
                        break;
nkeynes@359
  1498
                    case 0x7:
nkeynes@359
  1499
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1500
                            case 0x0:
nkeynes@359
  1501
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1502
                                    case 0x0:
nkeynes@359
  1503
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1504
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1505
                                        load_reg( R_EAX, Rm );
nkeynes@368
  1506
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1507
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1508
                                        store_reg( R_EAX, Rm );
nkeynes@368
  1509
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1510
                                        call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1511
                                        sh4_x86.priv_checked = FALSE;
nkeynes@377
  1512
                                        sh4_x86.fpuen_checked = FALSE;
nkeynes@359
  1513
                                        }
nkeynes@359
  1514
                                        break;
nkeynes@359
  1515
                                    case 0x1:
nkeynes@359
  1516
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1517
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1518
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1519
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1520
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1521
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1522
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1523
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1524
                                        }
nkeynes@359
  1525
                                        break;
nkeynes@359
  1526
                                    case 0x2:
nkeynes@359
  1527
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1528
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1529
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1530
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1531
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1532
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1533
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1534
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1535
                                        }
nkeynes@359
  1536
                                        break;
nkeynes@359
  1537
                                    case 0x3:
nkeynes@359
  1538
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1539
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1540
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1541
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1542
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1543
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1544
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1545
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1546
                                        }
nkeynes@359
  1547
                                        break;
nkeynes@359
  1548
                                    case 0x4:
nkeynes@359
  1549
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1550
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1551
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1552
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1553
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1554
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1555
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1556
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1557
                                        }
nkeynes@359
  1558
                                        break;
nkeynes@359
  1559
                                    default:
nkeynes@359
  1560
                                        UNDEF();
nkeynes@359
  1561
                                        break;
nkeynes@359
  1562
                                }
nkeynes@359
  1563
                                break;
nkeynes@359
  1564
                            case 0x1:
nkeynes@359
  1565
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1566
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1567
                                load_reg( R_EAX, Rm );
nkeynes@374
  1568
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1569
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1570
                                store_reg( R_EAX, Rm );
nkeynes@374
  1571
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1572
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1573
                                }
nkeynes@359
  1574
                                break;
nkeynes@359
  1575
                        }
nkeynes@359
  1576
                        break;
nkeynes@359
  1577
                    case 0x8:
nkeynes@359
  1578
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1579
                            case 0x0:
nkeynes@359
  1580
                                { /* SHLL2 Rn */
nkeynes@359
  1581
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1582
                                load_reg( R_EAX, Rn );
nkeynes@359
  1583
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1584
                                store_reg( R_EAX, Rn );
nkeynes@359
  1585
                                }
nkeynes@359
  1586
                                break;
nkeynes@359
  1587
                            case 0x1:
nkeynes@359
  1588
                                { /* SHLL8 Rn */
nkeynes@359
  1589
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1590
                                load_reg( R_EAX, Rn );
nkeynes@359
  1591
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1592
                                store_reg( R_EAX, Rn );
nkeynes@359
  1593
                                }
nkeynes@359
  1594
                                break;
nkeynes@359
  1595
                            case 0x2:
nkeynes@359
  1596
                                { /* SHLL16 Rn */
nkeynes@359
  1597
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1598
                                load_reg( R_EAX, Rn );
nkeynes@359
  1599
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1600
                                store_reg( R_EAX, Rn );
nkeynes@359
  1601
                                }
nkeynes@359
  1602
                                break;
nkeynes@359
  1603
                            default:
nkeynes@359
  1604
                                UNDEF();
nkeynes@359
  1605
                                break;
nkeynes@359
  1606
                        }
nkeynes@359
  1607
                        break;
nkeynes@359
  1608
                    case 0x9:
nkeynes@359
  1609
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1610
                            case 0x0:
nkeynes@359
  1611
                                { /* SHLR2 Rn */
nkeynes@359
  1612
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1613
                                load_reg( R_EAX, Rn );
nkeynes@359
  1614
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1615
                                store_reg( R_EAX, Rn );
nkeynes@359
  1616
                                }
nkeynes@359
  1617
                                break;
nkeynes@359
  1618
                            case 0x1:
nkeynes@359
  1619
                                { /* SHLR8 Rn */
nkeynes@359
  1620
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1621
                                load_reg( R_EAX, Rn );
nkeynes@359
  1622
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1623
                                store_reg( R_EAX, Rn );
nkeynes@359
  1624
                                }
nkeynes@359
  1625
                                break;
nkeynes@359
  1626
                            case 0x2:
nkeynes@359
  1627
                                { /* SHLR16 Rn */
nkeynes@359
  1628
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1629
                                load_reg( R_EAX, Rn );
nkeynes@359
  1630
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1631
                                store_reg( R_EAX, Rn );
nkeynes@359
  1632
                                }
nkeynes@359
  1633
                                break;
nkeynes@359
  1634
                            default:
nkeynes@359
  1635
                                UNDEF();
nkeynes@359
  1636
                                break;
nkeynes@359
  1637
                        }
nkeynes@359
  1638
                        break;
nkeynes@359
  1639
                    case 0xA:
nkeynes@359
  1640
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1641
                            case 0x0:
nkeynes@359
  1642
                                { /* LDS Rm, MACH */
nkeynes@359
  1643
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1644
                                load_reg( R_EAX, Rm );
nkeynes@359
  1645
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1646
                                }
nkeynes@359
  1647
                                break;
nkeynes@359
  1648
                            case 0x1:
nkeynes@359
  1649
                                { /* LDS Rm, MACL */
nkeynes@359
  1650
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1651
                                load_reg( R_EAX, Rm );
nkeynes@359
  1652
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1653
                                }
nkeynes@359
  1654
                                break;
nkeynes@359
  1655
                            case 0x2:
nkeynes@359
  1656
                                { /* LDS Rm, PR */
nkeynes@359
  1657
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1658
                                load_reg( R_EAX, Rm );
nkeynes@359
  1659
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1660
                                }
nkeynes@359
  1661
                                break;
nkeynes@359
  1662
                            case 0x3:
nkeynes@359
  1663
                                { /* LDC Rm, SGR */
nkeynes@359
  1664
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1665
                                load_reg( R_EAX, Rm );
nkeynes@359
  1666
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1667
                                }
nkeynes@359
  1668
                                break;
nkeynes@359
  1669
                            case 0x5:
nkeynes@359
  1670
                                { /* LDS Rm, FPUL */
nkeynes@359
  1671
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1672
                                load_reg( R_EAX, Rm );
nkeynes@359
  1673
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1674
                                }
nkeynes@359
  1675
                                break;
nkeynes@359
  1676
                            case 0x6:
nkeynes@359
  1677
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1678
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1679
                                load_reg( R_EAX, Rm );
nkeynes@359
  1680
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1681
                                }
nkeynes@359
  1682
                                break;
nkeynes@359
  1683
                            case 0xF:
nkeynes@359
  1684
                                { /* LDC Rm, DBR */
nkeynes@359
  1685
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1686
                                load_reg( R_EAX, Rm );
nkeynes@359
  1687
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1688
                                }
nkeynes@359
  1689
                                break;
nkeynes@359
  1690
                            default:
nkeynes@359
  1691
                                UNDEF();
nkeynes@359
  1692
                                break;
nkeynes@359
  1693
                        }
nkeynes@359
  1694
                        break;
nkeynes@359
  1695
                    case 0xB:
nkeynes@359
  1696
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1697
                            case 0x0:
nkeynes@359
  1698
                                { /* JSR @Rn */
nkeynes@359
  1699
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1700
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1701
                            	SLOTILLEGAL();
nkeynes@374
  1702
                                } else {
nkeynes@374
  1703
                            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1704
                            	store_spreg( R_EAX, R_PR );
nkeynes@374
  1705
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1706
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1707
                            	INC_r32(R_ESI);
nkeynes@374
  1708
                            	return 0;
nkeynes@374
  1709
                                }
nkeynes@359
  1710
                                }
nkeynes@359
  1711
                                break;
nkeynes@359
  1712
                            case 0x1:
nkeynes@359
  1713
                                { /* TAS.B @Rn */
nkeynes@359
  1714
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1715
                                load_reg( R_ECX, Rn );
nkeynes@361
  1716
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1717
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1718
                                SETE_t();
nkeynes@361
  1719
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@361
  1720
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1721
                                }
nkeynes@359
  1722
                                break;
nkeynes@359
  1723
                            case 0x2:
nkeynes@359
  1724
                                { /* JMP @Rn */
nkeynes@359
  1725
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@374
  1726
                                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1727
                            	SLOTILLEGAL();
nkeynes@374
  1728
                                } else {
nkeynes@374
  1729
                            	load_reg( R_EDI, Rn );
nkeynes@374
  1730
                            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1731
                            	INC_r32(R_ESI);
nkeynes@374
  1732
                            	return 0;
nkeynes@374
  1733
                                }
nkeynes@359
  1734
                                }
nkeynes@359
  1735
                                break;
nkeynes@359
  1736
                            default:
nkeynes@359
  1737
                                UNDEF();
nkeynes@359
  1738
                                break;
nkeynes@359
  1739
                        }
nkeynes@359
  1740
                        break;
nkeynes@359
  1741
                    case 0xC:
nkeynes@359
  1742
                        { /* SHAD Rm, Rn */
nkeynes@359
  1743
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1744
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1745
                        load_reg( R_EAX, Rn );
nkeynes@361
  1746
                        load_reg( R_ECX, Rm );
nkeynes@361
  1747
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@361
  1748
                        JAE_rel8(9);
nkeynes@361
  1749
                                        
nkeynes@361
  1750
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1751
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1752
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@361
  1753
                        JMP_rel8(5);               // 2
nkeynes@361
  1754
                        
nkeynes@361
  1755
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1756
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@361
  1757
                                        
nkeynes@361
  1758
                        store_reg( R_EAX, Rn );
nkeynes@359
  1759
                        }
nkeynes@359
  1760
                        break;
nkeynes@359
  1761
                    case 0xD:
nkeynes@359
  1762
                        { /* SHLD Rm, Rn */
nkeynes@359
  1763
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@368
  1764
                        load_reg( R_EAX, Rn );
nkeynes@368
  1765
                        load_reg( R_ECX, Rm );
nkeynes@368
  1766
                    
nkeynes@368
  1767
                        MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
  1768
                        SHL_r32_CL( R_EAX );
nkeynes@368
  1769
                        NEG_r32( R_ECX );
nkeynes@368
  1770
                        SHR_r32_CL( R_EDX );
nkeynes@368
  1771
                        CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
  1772
                        CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
  1773
                        store_reg( R_EAX, Rn );
nkeynes@359
  1774
                        }
nkeynes@359
  1775
                        break;
nkeynes@359
  1776
                    case 0xE:
nkeynes@359
  1777
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1778
                            case 0x0:
nkeynes@359
  1779
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1780
                                    case 0x0:
nkeynes@359
  1781
                                        { /* LDC Rm, SR */
nkeynes@359
  1782
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@368
  1783
                                        load_reg( R_EAX, Rm );
nkeynes@374
  1784
                                        call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1785
                                        sh4_x86.priv_checked = FALSE;
nkeynes@377
  1786
                                        sh4_x86.fpuen_checked = FALSE;
nkeynes@359
  1787
                                        }
nkeynes@359
  1788
                                        break;
nkeynes@359
  1789
                                    case 0x1:
nkeynes@359
  1790
                                        { /* LDC Rm, GBR */
nkeynes@359
  1791
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1792
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1793
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1794
                                        }
nkeynes@359
  1795
                                        break;
nkeynes@359
  1796
                                    case 0x2:
nkeynes@359
  1797
                                        { /* LDC Rm, VBR */
nkeynes@359
  1798
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1799
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1800
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1801
                                        }
nkeynes@359
  1802
                                        break;
nkeynes@359
  1803
                                    case 0x3:
nkeynes@359
  1804
                                        { /* LDC Rm, SSR */
nkeynes@359
  1805
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1806
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1807
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1808
                                        }
nkeynes@359
  1809
                                        break;
nkeynes@359
  1810
                                    case 0x4:
nkeynes@359
  1811
                                        { /* LDC Rm, SPC */
nkeynes@359
  1812
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1813
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1814
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1815
                                        }
nkeynes@359
  1816
                                        break;
nkeynes@359
  1817
                                    default:
nkeynes@359
  1818
                                        UNDEF();
nkeynes@359
  1819
                                        break;
nkeynes@359
  1820
                                }
nkeynes@359
  1821
                                break;
nkeynes@359
  1822
                            case 0x1:
nkeynes@359
  1823
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1824
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@374
  1825
                                load_reg( R_EAX, Rm );
nkeynes@374
  1826
                                store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1827
                                }
nkeynes@359
  1828
                                break;
nkeynes@359
  1829
                        }
nkeynes@359
  1830
                        break;
nkeynes@359
  1831
                    case 0xF:
nkeynes@359
  1832
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1833
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1834
                        }
nkeynes@359
  1835
                        break;
nkeynes@359
  1836
                }
nkeynes@359
  1837
                break;
nkeynes@359
  1838
            case 0x5:
nkeynes@359
  1839
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1840
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1841
                load_reg( R_ECX, Rm );
nkeynes@361
  1842
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1843
                check_ralign32( R_ECX );
nkeynes@361
  1844
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1845
                store_reg( R_EAX, Rn );
nkeynes@359
  1846
                }
nkeynes@359
  1847
                break;
nkeynes@359
  1848
            case 0x6:
nkeynes@359
  1849
                switch( ir&0xF ) {
nkeynes@359
  1850
                    case 0x0:
nkeynes@359
  1851
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1852
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1853
                        load_reg( R_ECX, Rm );
nkeynes@359
  1854
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1855
                        store_reg( R_ECX, Rn );
nkeynes@359
  1856
                        }
nkeynes@359
  1857
                        break;
nkeynes@359
  1858
                    case 0x1:
nkeynes@359
  1859
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  1860
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1861
                        load_reg( R_ECX, Rm );
nkeynes@374
  1862
                        check_ralign16( R_ECX );
nkeynes@361
  1863
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1864
                        store_reg( R_EAX, Rn );
nkeynes@359
  1865
                        }
nkeynes@359
  1866
                        break;
nkeynes@359
  1867
                    case 0x2:
nkeynes@359
  1868
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  1869
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1870
                        load_reg( R_ECX, Rm );
nkeynes@374
  1871
                        check_ralign32( R_ECX );
nkeynes@361
  1872
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1873
                        store_reg( R_EAX, Rn );
nkeynes@359
  1874
                        }
nkeynes@359
  1875
                        break;
nkeynes@359
  1876
                    case 0x3:
nkeynes@359
  1877
                        { /* MOV Rm, Rn */
nkeynes@359
  1878
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1879
                        load_reg( R_EAX, Rm );
nkeynes@359
  1880
                        store_reg( R_EAX, Rn );
nkeynes@359
  1881
                        }
nkeynes@359
  1882
                        break;
nkeynes@359
  1883
                    case 0x4:
nkeynes@359
  1884
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  1885
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1886
                        load_reg( R_ECX, Rm );
nkeynes@359
  1887
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1888
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1889
                        store_reg( R_EAX, Rm );
nkeynes@359
  1890
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1891
                        store_reg( R_EAX, Rn );
nkeynes@359
  1892
                        }
nkeynes@359
  1893
                        break;
nkeynes@359
  1894
                    case 0x5:
nkeynes@359
  1895
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  1896
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1897
                        load_reg( R_EAX, Rm );
nkeynes@374
  1898
                        check_ralign16( R_EAX );
nkeynes@361
  1899
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1900
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1901
                        store_reg( R_EAX, Rm );
nkeynes@361
  1902
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1903
                        store_reg( R_EAX, Rn );
nkeynes@359
  1904
                        }
nkeynes@359
  1905
                        break;
nkeynes@359
  1906
                    case 0x6:
nkeynes@359
  1907
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  1908
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1909
                        load_reg( R_EAX, Rm );
nkeynes@374
  1910
                        check_ralign32( R_ECX );
nkeynes@361
  1911
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1912
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1913
                        store_reg( R_EAX, Rm );
nkeynes@361
  1914
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1915
                        store_reg( R_EAX, Rn );
nkeynes@359
  1916
                        }
nkeynes@359
  1917
                        break;
nkeynes@359
  1918
                    case 0x7:
nkeynes@359
  1919
                        { /* NOT Rm, Rn */
nkeynes@359
  1920
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1921
                        load_reg( R_EAX, Rm );
nkeynes@359
  1922
                        NOT_r32( R_EAX );
nkeynes@359
  1923
                        store_reg( R_EAX, Rn );
nkeynes@359
  1924
                        }
nkeynes@359
  1925
                        break;
nkeynes@359
  1926
                    case 0x8:
nkeynes@359
  1927
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  1928
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1929
                        load_reg( R_EAX, Rm );
nkeynes@359
  1930
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1931
                        store_reg( R_EAX, Rn );
nkeynes@359
  1932
                        }
nkeynes@359
  1933
                        break;
nkeynes@359
  1934
                    case 0x9:
nkeynes@359
  1935
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  1936
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1937
                        load_reg( R_EAX, Rm );
nkeynes@359
  1938
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1939
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1940
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1941
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1942
                        store_reg( R_ECX, Rn );
nkeynes@359
  1943
                        }
nkeynes@359
  1944
                        break;
nkeynes@359
  1945
                    case 0xA:
nkeynes@359
  1946
                        { /* NEGC Rm, Rn */
nkeynes@359
  1947
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1948
                        load_reg( R_EAX, Rm );
nkeynes@359
  1949
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1950
                        LDC_t();
nkeynes@359
  1951
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1952
                        store_reg( R_ECX, Rn );
nkeynes@359
  1953
                        SETC_t();
nkeynes@359
  1954
                        }
nkeynes@359
  1955
                        break;
nkeynes@359
  1956
                    case 0xB:
nkeynes@359
  1957
                        { /* NEG Rm, Rn */
nkeynes@359
  1958
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1959
                        load_reg( R_EAX, Rm );
nkeynes@359
  1960
                        NEG_r32( R_EAX );
nkeynes@359
  1961
                        store_reg( R_EAX, Rn );
nkeynes@359
  1962
                        }
nkeynes@359
  1963
                        break;
nkeynes@359
  1964
                    case 0xC:
nkeynes@359
  1965
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  1966
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1967
                        load_reg( R_EAX, Rm );
nkeynes@361
  1968
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  1969
                        store_reg( R_EAX, Rn );
nkeynes@359
  1970
                        }
nkeynes@359
  1971
                        break;
nkeynes@359
  1972
                    case 0xD:
nkeynes@359
  1973
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  1974
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1975
                        load_reg( R_EAX, Rm );
nkeynes@361
  1976
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1977
                        store_reg( R_EAX, Rn );
nkeynes@359
  1978
                        }
nkeynes@359
  1979
                        break;
nkeynes@359
  1980
                    case 0xE:
nkeynes@359
  1981
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  1982
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1983
                        load_reg( R_EAX, Rm );
nkeynes@359
  1984
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  1985
                        store_reg( R_EAX, Rn );
nkeynes@359
  1986
                        }
nkeynes@359
  1987
                        break;
nkeynes@359
  1988
                    case 0xF:
nkeynes@359
  1989
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  1990
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1991
                        load_reg( R_EAX, Rm );
nkeynes@361
  1992
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1993
                        store_reg( R_EAX, Rn );
nkeynes@359
  1994
                        }
nkeynes@359
  1995
                        break;
nkeynes@359
  1996
                }
nkeynes@359
  1997
                break;
nkeynes@359
  1998
            case 0x7:
nkeynes@359
  1999
                { /* ADD #imm, Rn */
nkeynes@359
  2000
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2001
                load_reg( R_EAX, Rn );
nkeynes@359
  2002
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  2003
                store_reg( R_EAX, Rn );
nkeynes@359
  2004
                }
nkeynes@359
  2005
                break;
nkeynes@359
  2006
            case 0x8:
nkeynes@359
  2007
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2008
                    case 0x0:
nkeynes@359
  2009
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  2010
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2011
                        load_reg( R_EAX, 0 );
nkeynes@359
  2012
                        load_reg( R_ECX, Rn );
nkeynes@359
  2013
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2014
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2015
                        }
nkeynes@359
  2016
                        break;
nkeynes@359
  2017
                    case 0x1:
nkeynes@359
  2018
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  2019
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2020
                        load_reg( R_ECX, Rn );
nkeynes@361
  2021
                        load_reg( R_EAX, 0 );
nkeynes@361
  2022
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2023
                        check_walign16( R_ECX );
nkeynes@361
  2024
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2025
                        }
nkeynes@359
  2026
                        break;
nkeynes@359
  2027
                    case 0x4:
nkeynes@359
  2028
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  2029
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  2030
                        load_reg( R_ECX, Rm );
nkeynes@359
  2031
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2032
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2033
                        store_reg( R_EAX, 0 );
nkeynes@359
  2034
                        }
nkeynes@359
  2035
                        break;
nkeynes@359
  2036
                    case 0x5:
nkeynes@359
  2037
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  2038
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  2039
                        load_reg( R_ECX, Rm );
nkeynes@361
  2040
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2041
                        check_ralign16( R_ECX );
nkeynes@361
  2042
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2043
                        store_reg( R_EAX, 0 );
nkeynes@359
  2044
                        }
nkeynes@359
  2045
                        break;
nkeynes@359
  2046
                    case 0x8:
nkeynes@359
  2047
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  2048
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2049
                        load_reg( R_EAX, 0 );
nkeynes@359
  2050
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  2051
                        SETE_t();
nkeynes@359
  2052
                        }
nkeynes@359
  2053
                        break;
nkeynes@359
  2054
                    case 0x9:
nkeynes@359
  2055
                        { /* BT disp */
nkeynes@359
  2056
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2057
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2058
                    	SLOTILLEGAL();
nkeynes@374
  2059
                        } else {
nkeynes@374
  2060
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2061
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2062
                    	JE_rel8( 5 );
nkeynes@374
  2063
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2064
                    	INC_r32(R_ESI);
nkeynes@374
  2065
                    	return 1;
nkeynes@374
  2066
                        }
nkeynes@359
  2067
                        }
nkeynes@359
  2068
                        break;
nkeynes@359
  2069
                    case 0xB:
nkeynes@359
  2070
                        { /* BF disp */
nkeynes@359
  2071
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2072
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2073
                    	SLOTILLEGAL();
nkeynes@374
  2074
                        } else {
nkeynes@374
  2075
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2076
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2077
                    	JNE_rel8( 5 );
nkeynes@374
  2078
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2079
                    	INC_r32(R_ESI);
nkeynes@374
  2080
                    	return 1;
nkeynes@374
  2081
                        }
nkeynes@359
  2082
                        }
nkeynes@359
  2083
                        break;
nkeynes@359
  2084
                    case 0xD:
nkeynes@359
  2085
                        { /* BT/S disp */
nkeynes@359
  2086
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2087
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2088
                    	SLOTILLEGAL();
nkeynes@374
  2089
                        } else {
nkeynes@374
  2090
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2091
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2092
                    	JE_rel8( 5 );
nkeynes@374
  2093
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2094
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2095
                    	INC_r32(R_ESI);
nkeynes@374
  2096
                    	return 0;
nkeynes@374
  2097
                        }
nkeynes@359
  2098
                        }
nkeynes@359
  2099
                        break;
nkeynes@359
  2100
                    case 0xF:
nkeynes@359
  2101
                        { /* BF/S disp */
nkeynes@359
  2102
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@374
  2103
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2104
                    	SLOTILLEGAL();
nkeynes@374
  2105
                        } else {
nkeynes@374
  2106
                    	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  2107
                    	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  2108
                    	JNE_rel8( 5 );
nkeynes@374
  2109
                    	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2110
                    	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2111
                    	INC_r32(R_ESI);
nkeynes@374
  2112
                    	return 0;
nkeynes@374
  2113
                        }
nkeynes@359
  2114
                        }
nkeynes@359
  2115
                        break;
nkeynes@359
  2116
                    default:
nkeynes@359
  2117
                        UNDEF();
nkeynes@359
  2118
                        break;
nkeynes@359
  2119
                }
nkeynes@359
  2120
                break;
nkeynes@359
  2121
            case 0x9:
nkeynes@359
  2122
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  2123
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@374
  2124
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2125
            	SLOTILLEGAL();
nkeynes@374
  2126
                } else {
nkeynes@374
  2127
            	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  2128
            	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  2129
            	store_reg( R_EAX, Rn );
nkeynes@374
  2130
                }
nkeynes@359
  2131
                }
nkeynes@359
  2132
                break;
nkeynes@359
  2133
            case 0xA:
nkeynes@359
  2134
                { /* BRA disp */
nkeynes@359
  2135
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2136
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2137
            	SLOTILLEGAL();
nkeynes@374
  2138
                } else {
nkeynes@374
  2139
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2140
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2141
            	INC_r32(R_ESI);
nkeynes@374
  2142
            	return 0;
nkeynes@374
  2143
                }
nkeynes@359
  2144
                }
nkeynes@359
  2145
                break;
nkeynes@359
  2146
            case 0xB:
nkeynes@359
  2147
                { /* BSR disp */
nkeynes@359
  2148
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@374
  2149
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2150
            	SLOTILLEGAL();
nkeynes@374
  2151
                } else {
nkeynes@374
  2152
            	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  2153
            	store_spreg( R_EAX, R_PR );
nkeynes@374
  2154
            	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  2155
            	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  2156
            	INC_r32(R_ESI);
nkeynes@374
  2157
            	return 0;
nkeynes@374
  2158
                }
nkeynes@359
  2159
                }
nkeynes@359
  2160
                break;
nkeynes@359
  2161
            case 0xC:
nkeynes@359
  2162
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  2163
                    case 0x0:
nkeynes@359
  2164
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  2165
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2166
                        load_reg( R_EAX, 0 );
nkeynes@359
  2167
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2168
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2169
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2170
                        }
nkeynes@359
  2171
                        break;
nkeynes@359
  2172
                    case 0x1:
nkeynes@359
  2173
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  2174
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2175
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2176
                        load_reg( R_EAX, 0 );
nkeynes@361
  2177
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2178
                        check_walign16( R_ECX );
nkeynes@361
  2179
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  2180
                        }
nkeynes@359
  2181
                        break;
nkeynes@359
  2182
                    case 0x2:
nkeynes@359
  2183
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  2184
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2185
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2186
                        load_reg( R_EAX, 0 );
nkeynes@361
  2187
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2188
                        check_walign32( R_ECX );
nkeynes@361
  2189
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2190
                        }
nkeynes@359
  2191
                        break;
nkeynes@359
  2192
                    case 0x3:
nkeynes@359
  2193
                        { /* TRAPA #imm */
nkeynes@359
  2194
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2195
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2196
                    	SLOTILLEGAL();
nkeynes@374
  2197
                        } else {
nkeynes@374
  2198
                    	// TODO: Write TRA 
nkeynes@374
  2199
                    	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  2200
                        }
nkeynes@359
  2201
                        }
nkeynes@359
  2202
                        break;
nkeynes@359
  2203
                    case 0x4:
nkeynes@359
  2204
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  2205
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  2206
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2207
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  2208
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2209
                        store_reg( R_EAX, 0 );
nkeynes@359
  2210
                        }
nkeynes@359
  2211
                        break;
nkeynes@359
  2212
                    case 0x5:
nkeynes@359
  2213
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  2214
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  2215
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2216
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2217
                        check_ralign16( R_ECX );
nkeynes@361
  2218
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  2219
                        store_reg( R_EAX, 0 );
nkeynes@359
  2220
                        }
nkeynes@359
  2221
                        break;
nkeynes@359
  2222
                    case 0x6:
nkeynes@359
  2223
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  2224
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  2225
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  2226
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  2227
                        check_ralign32( R_ECX );
nkeynes@361
  2228
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  2229
                        store_reg( R_EAX, 0 );
nkeynes@359
  2230
                        }
nkeynes@359
  2231
                        break;
nkeynes@359
  2232
                    case 0x7:
nkeynes@359
  2233
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  2234
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2235
                        if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2236
                    	SLOTILLEGAL();
nkeynes@374
  2237
                        } else {
nkeynes@374
  2238
                    	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2239
                    	store_reg( R_ECX, 0 );
nkeynes@374
  2240
                        }
nkeynes@359
  2241
                        }
nkeynes@359
  2242
                        break;
nkeynes@359
  2243
                    case 0x8:
nkeynes@359
  2244
                        { /* TST #imm, R0 */
nkeynes@359
  2245
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2246
                        load_reg( R_EAX, 0 );
nkeynes@368
  2247
                        TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  2248
                        SETE_t();
nkeynes@359
  2249
                        }
nkeynes@359
  2250
                        break;
nkeynes@359
  2251
                    case 0x9:
nkeynes@359
  2252
                        { /* AND #imm, R0 */
nkeynes@359
  2253
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2254
                        load_reg( R_EAX, 0 );
nkeynes@359
  2255
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  2256
                        store_reg( R_EAX, 0 );
nkeynes@359
  2257
                        }
nkeynes@359
  2258
                        break;
nkeynes@359
  2259
                    case 0xA:
nkeynes@359
  2260
                        { /* XOR #imm, R0 */
nkeynes@359
  2261
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2262
                        load_reg( R_EAX, 0 );
nkeynes@359
  2263
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2264
                        store_reg( R_EAX, 0 );
nkeynes@359
  2265
                        }
nkeynes@359
  2266
                        break;
nkeynes@359
  2267
                    case 0xB:
nkeynes@359
  2268
                        { /* OR #imm, R0 */
nkeynes@359
  2269
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2270
                        load_reg( R_EAX, 0 );
nkeynes@359
  2271
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  2272
                        store_reg( R_EAX, 0 );
nkeynes@359
  2273
                        }
nkeynes@359
  2274
                        break;
nkeynes@359
  2275
                    case 0xC:
nkeynes@359
  2276
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  2277
                        uint32_t imm = (ir&0xFF); 
nkeynes@368
  2278
                        load_reg( R_EAX, 0);
nkeynes@368
  2279
                        load_reg( R_ECX, R_GBR);
nkeynes@368
  2280
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
  2281
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
  2282
                        TEST_imm8_r8( imm, R_EAX );
nkeynes@368
  2283
                        SETE_t();
nkeynes@359
  2284
                        }
nkeynes@359
  2285
                        break;
nkeynes@359
  2286
                    case 0xD:
nkeynes@359
  2287
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  2288
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2289
                        load_reg( R_EAX, 0 );
nkeynes@359
  2290
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2291
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2292
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2293
                        AND_imm32_r32(imm, R_ECX );
nkeynes@359
  2294
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2295
                        }
nkeynes@359
  2296
                        break;
nkeynes@359
  2297
                    case 0xE:
nkeynes@359
  2298
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  2299
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  2300
                        load_reg( R_EAX, 0 );
nkeynes@359
  2301
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  2302
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  2303
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  2304
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  2305
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2306
                        }
nkeynes@359
  2307
                        break;
nkeynes@359
  2308
                    case 0xF:
nkeynes@359
  2309
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  2310
                        uint32_t imm = (ir&0xFF); 
nkeynes@374
  2311
                        load_reg( R_EAX, 0 );
nkeynes@374
  2312
                        load_spreg( R_ECX, R_GBR );
nkeynes@374
  2313
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  2314
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
  2315
                        OR_imm32_r32(imm, R_ECX );
nkeynes@374
  2316
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  2317
                        }
nkeynes@359
  2318
                        break;
nkeynes@359
  2319
                }
nkeynes@359
  2320
                break;
nkeynes@359
  2321
            case 0xD:
nkeynes@359
  2322
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  2323
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@374
  2324
                if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2325
            	SLOTILLEGAL();
nkeynes@374
  2326
                } else {
nkeynes@374
  2327
            	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  2328
            	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  2329
            	store_reg( R_EAX, 0 );
nkeynes@374
  2330
                }
nkeynes@359
  2331
                }
nkeynes@359
  2332
                break;
nkeynes@359
  2333
            case 0xE:
nkeynes@359
  2334
                { /* MOV #imm, Rn */
nkeynes@359
  2335
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  2336
                load_imm32( R_EAX, imm );
nkeynes@359
  2337
                store_reg( R_EAX, Rn );
nkeynes@359
  2338
                }
nkeynes@359
  2339
                break;
nkeynes@359
  2340
            case 0xF:
nkeynes@359
  2341
                switch( ir&0xF ) {
nkeynes@359
  2342
                    case 0x0:
nkeynes@359
  2343
                        { /* FADD FRm, FRn */
nkeynes@359
  2344
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2345
                        check_fpuen();
nkeynes@377
  2346
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2347
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2348
                        load_fr_bank( R_EDX );
nkeynes@377
  2349
                        JNE_rel8(13);
nkeynes@377
  2350
                        push_fr(R_EDX, FRm);
nkeynes@377
  2351
                        push_fr(R_EDX, FRn);
nkeynes@377
  2352
                        FADDP_st(1);
nkeynes@377
  2353
                        pop_fr(R_EDX, FRn);
nkeynes@377
  2354
                        JMP_rel8(11);
nkeynes@377
  2355
                        push_dr(R_EDX, FRm);
nkeynes@377
  2356
                        push_dr(R_EDX, FRn);
nkeynes@377
  2357
                        FADDP_st(1);
nkeynes@377
  2358
                        pop_dr(R_EDX, FRn);
nkeynes@359
  2359
                        }
nkeynes@359
  2360
                        break;
nkeynes@359
  2361
                    case 0x1:
nkeynes@359
  2362
                        { /* FSUB FRm, FRn */
nkeynes@359
  2363
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2364
                        check_fpuen();
nkeynes@377
  2365
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2366
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2367
                        load_fr_bank( R_EDX );
nkeynes@377
  2368
                        JNE_rel8(13);
nkeynes@377
  2369
                        push_fr(R_EDX, FRn);
nkeynes@377
  2370
                        push_fr(R_EDX, FRm);
nkeynes@377
  2371
                        FMULP_st(1);
nkeynes@377
  2372
                        pop_fr(R_EDX, FRn);
nkeynes@377
  2373
                        JMP_rel8(11);
nkeynes@377
  2374
                        push_dr(R_EDX, FRn);
nkeynes@377
  2375
                        push_dr(R_EDX, FRm);
nkeynes@377
  2376
                        FMULP_st(1);
nkeynes@377
  2377
                        pop_dr(R_EDX, FRn);
nkeynes@359
  2378
                        }
nkeynes@359
  2379
                        break;
nkeynes@359
  2380
                    case 0x2:
nkeynes@359
  2381
                        { /* FMUL FRm, FRn */
nkeynes@359
  2382
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2383
                        check_fpuen();
nkeynes@377
  2384
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2385
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2386
                        load_fr_bank( R_EDX );
nkeynes@377
  2387
                        JNE_rel8(13);
nkeynes@377
  2388
                        push_fr(R_EDX, FRm);
nkeynes@377
  2389
                        push_fr(R_EDX, FRn);
nkeynes@377
  2390
                        FMULP_st(1);
nkeynes@377
  2391
                        pop_fr(R_EDX, FRn);
nkeynes@377
  2392
                        JMP_rel8(11);
nkeynes@377
  2393
                        push_dr(R_EDX, FRm);
nkeynes@377
  2394
                        push_dr(R_EDX, FRn);
nkeynes@377
  2395
                        FMULP_st(1);
nkeynes@377
  2396
                        pop_dr(R_EDX, FRn);
nkeynes@359
  2397
                        }
nkeynes@359
  2398
                        break;
nkeynes@359
  2399
                    case 0x3:
nkeynes@359
  2400
                        { /* FDIV FRm, FRn */
nkeynes@359
  2401
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2402
                        check_fpuen();
nkeynes@377
  2403
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2404
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2405
                        load_fr_bank( R_EDX );
nkeynes@377
  2406
                        JNE_rel8(13);
nkeynes@377
  2407
                        push_fr(R_EDX, FRn);
nkeynes@377
  2408
                        push_fr(R_EDX, FRm);
nkeynes@377
  2409
                        FDIVP_st(1);
nkeynes@377
  2410
                        pop_fr(R_EDX, FRn);
nkeynes@377
  2411
                        JMP_rel8(11);
nkeynes@377
  2412
                        push_dr(R_EDX, FRn);
nkeynes@377
  2413
                        push_dr(R_EDX, FRm);
nkeynes@377
  2414
                        FDIVP_st(1);
nkeynes@377
  2415
                        pop_dr(R_EDX, FRn);
nkeynes@359
  2416
                        }
nkeynes@359
  2417
                        break;
nkeynes@359
  2418
                    case 0x4:
nkeynes@359
  2419
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  2420
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2421
                        check_fpuen();
nkeynes@377
  2422
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2423
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2424
                        load_fr_bank( R_EDX );
nkeynes@377
  2425
                        JNE_rel8(8);
nkeynes@377
  2426
                        push_fr(R_EDX, FRm);
nkeynes@377
  2427
                        push_fr(R_EDX, FRn);
nkeynes@377
  2428
                        JMP_rel8(6);
nkeynes@377
  2429
                        push_dr(R_EDX, FRm);
nkeynes@377
  2430
                        push_dr(R_EDX, FRn);
nkeynes@377
  2431
                        FCOMIP_st(1);
nkeynes@377
  2432
                        SETE_t();
nkeynes@377
  2433
                        FPOP_st();
nkeynes@359
  2434
                        }
nkeynes@359
  2435
                        break;
nkeynes@359
  2436
                    case 0x5:
nkeynes@359
  2437
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  2438
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2439
                        check_fpuen();
nkeynes@377
  2440
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2441
                        TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2442
                        load_fr_bank( R_EDX );
nkeynes@377
  2443
                        JNE_rel8(8);
nkeynes@377
  2444
                        push_fr(R_EDX, FRm);
nkeynes@377
  2445
                        push_fr(R_EDX, FRn);
nkeynes@377
  2446
                        JMP_rel8(6);
nkeynes@377
  2447
                        push_dr(R_EDX, FRm);
nkeynes@377
  2448
                        push_dr(R_EDX, FRn);
nkeynes@377
  2449
                        FCOMIP_st(1);
nkeynes@377
  2450
                        SETA_t();
nkeynes@377
  2451
                        FPOP_st();
nkeynes@359
  2452
                        }
nkeynes@359
  2453
                        break;
nkeynes@359
  2454
                    case 0x6:
nkeynes@359
  2455
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  2456
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2457
                        check_fpuen();
nkeynes@375
  2458
                        load_reg( R_EDX, Rm );
nkeynes@377
  2459
                        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@375
  2460
                        check_ralign32( R_EDX );
nkeynes@375
  2461
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2462
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  2463
                        JNE_rel8(19);
nkeynes@375
  2464
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  2465
                        load_fr_bank( R_ECX );
nkeynes@375
  2466
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  2467
                        if( FRn&1 ) {
nkeynes@375
  2468
                    	JMP_rel8(46);
nkeynes@375
  2469
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  2470
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  2471
                    	load_xf_bank( R_ECX );
nkeynes@375
  2472
                        } else {
nkeynes@375
  2473
                    	JMP_rel8(36);
nkeynes@375
  2474
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2475
                    	load_fr_bank( R_ECX );
nkeynes@377
  2476
                        }
nkeynes@377
  2477
                        store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@377
  2478
                        store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@377
  2479
                        }
nkeynes@377
  2480
                        break;
nkeynes@377
  2481
                    case 0x7:
nkeynes@377
  2482
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@377
  2483
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2484
                        check_fpuen();
nkeynes@377
  2485
                        load_reg( R_EDX, Rn );
nkeynes@377
  2486
                        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  2487
                        check_walign32( R_EDX );
nkeynes@377
  2488
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2489
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2490
                        JNE_rel8(20);
nkeynes@377
  2491
                        load_fr_bank( R_ECX );
nkeynes@377
  2492
                        load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2493
                        MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  2494
                        if( FRm&1 ) {
nkeynes@377
  2495
                    	JMP_rel8( 46 );
nkeynes@377
  2496
                    	load_xf_bank( R_ECX );
nkeynes@377
  2497
                        } else {
nkeynes@377
  2498
                    	JMP_rel8( 39 );
nkeynes@377
  2499
                    	load_fr_bank( R_ECX );
nkeynes@377
  2500
                        }
nkeynes@377
  2501
                        load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@377
  2502
                        load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@377
  2503
                        MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@377
  2504
                        }
nkeynes@377
  2505
                        break;
nkeynes@377
  2506
                    case 0x8:
nkeynes@377
  2507
                        { /* FMOV @Rm, FRn */
nkeynes@377
  2508
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2509
                        check_fpuen();
nkeynes@377
  2510
                        load_reg( R_EDX, Rm );
nkeynes@377
  2511
                        check_ralign32( R_EDX );
nkeynes@377
  2512
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2513
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2514
                        JNE_rel8(19);
nkeynes@377
  2515
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  2516
                        load_fr_bank( R_ECX );
nkeynes@377
  2517
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  2518
                        if( FRn&1 ) {
nkeynes@377
  2519
                    	JMP_rel8(46);
nkeynes@377
  2520
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2521
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  2522
                    	load_xf_bank( R_ECX );
nkeynes@377
  2523
                        } else {
nkeynes@377
  2524
                    	JMP_rel8(36);
nkeynes@377
  2525
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2526
                    	load_fr_bank( R_ECX );
nkeynes@375
  2527
                        }
nkeynes@375
  2528
                        store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@375
  2529
                        store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@359
  2530
                        }
nkeynes@359
  2531
                        break;
nkeynes@359
  2532
                    case 0x9:
nkeynes@359
  2533
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  2534
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@377
  2535
                        check_fpuen();
nkeynes@377
  2536
                        load_reg( R_EDX, Rm );
nkeynes@377
  2537
                        check_ralign32( R_EDX );
nkeynes@377
  2538
                        MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  2539
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2540
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2541
                        JNE_rel8(25);
nkeynes@377
  2542
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  2543
                        store_reg( R_EAX, Rm );
nkeynes@377
  2544
                        MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  2545
                        load_fr_bank( R_ECX );
nkeynes@377
  2546
                        store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  2547
                        if( FRn&1 ) {
nkeynes@377
  2548
                    	JMP_rel8(52);
nkeynes@377
  2549
                    	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  2550
                    	store_reg(R_EAX, Rm);
nkeynes@377
  2551
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2552
                    	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  2553
                    	load_xf_bank( R_ECX );
nkeynes@377
  2554
                        } else {
nkeynes@377
  2555
                    	JMP_rel8(42);
nkeynes@377
  2556
                    	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  2557
                    	store_reg(R_EAX, Rm);
nkeynes@377
  2558
                    	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  2559
                    	load_fr_bank( R_ECX );
nkeynes@377
  2560
                        }
nkeynes@377
  2561
                        store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@377
  2562
                        store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@359
  2563
                        }
nkeynes@359
  2564
                        break;
nkeynes@359
  2565
                    case 0xA:
nkeynes@359
  2566
                        { /* FMOV FRm, @Rn */
nkeynes@359
  2567
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2568
                        check_fpuen();
nkeynes@375
  2569
                        load_reg( R_EDX, Rn );
nkeynes@375
  2570
                        check_walign32( R_EDX );
nkeynes@375
  2571
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  2572
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  2573
                        JNE_rel8(20);
nkeynes@377
  2574
                        load_fr_bank( R_ECX );
nkeynes@375
  2575
                        load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  2576
                        MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  2577
                        if( FRm&1 ) {
nkeynes@375
  2578
                    	JMP_rel8( 46 );
nkeynes@375
  2579
                    	load_xf_bank( R_ECX );
nkeynes@375
  2580
                        } else {
nkeynes@375
  2581
                    	JMP_rel8( 39 );
nkeynes@377
  2582
                    	load_fr_bank( R_ECX );
nkeynes@375
  2583
                        }
nkeynes@375
  2584
                        load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@375
  2585
                        load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@375
  2586
                        MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@359
  2587
                        }
nkeynes@359
  2588
                        break;
nkeynes@359
  2589
                    case 0xB:
nkeynes@359
  2590
                        { /* FMOV FRm, @-Rn */
nkeynes@359
  2591
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@377
  2592
                        check_fpuen();
nkeynes@377
  2593
                        load_reg( R_EDX, Rn );
nkeynes@377
  2594
                        check_walign32( R_EDX );
nkeynes@377
  2595
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2596
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2597
                        JNE_rel8(20);
nkeynes@377
  2598
                        load_fr_bank( R_ECX );
nkeynes@377
  2599
                        load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2600
                        ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  2601
                        store_reg( R_EDX, Rn );
nkeynes@377
  2602
                        MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  2603
                        if( FRm&1 ) {
nkeynes@377
  2604
                    	JMP_rel8( 46 );
nkeynes@377
  2605
                    	load_xf_bank( R_ECX );
nkeynes@377
  2606
                        } else {
nkeynes@377
  2607
                    	JMP_rel8( 39 );
nkeynes@377
  2608
                    	load_fr_bank( R_ECX );
nkeynes@377
  2609
                        }
nkeynes@377
  2610
                        load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@377
  2611
                        load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@377
  2612
                        ADD_imm8s_r32(-8,R_EDX);
nkeynes@377
  2613
                        store_reg( R_EDX, Rn );
nkeynes@377
  2614
                        MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@359
  2615
                        }
nkeynes@359
  2616
                        break;
nkeynes@359
  2617
                    case 0xC:
nkeynes@359
  2618
                        { /* FMOV FRm, FRn */
nkeynes@359
  2619
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@375
  2620
                        /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  2621
                         * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  2622
                         * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  2623
                         * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  2624
                         * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  2625
                         * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  2626
                         */
nkeynes@377
  2627
                        check_fpuen();
nkeynes@375
  2628
                        load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2629
                        load_fr_bank( R_EDX );
nkeynes@375
  2630
                        TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  2631
                        JNE_rel8(8);
nkeynes@375
  2632
                        load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  2633
                        store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  2634
                        if( FRm&1 ) {
nkeynes@375
  2635
                    	JMP_rel8(22);
nkeynes@375
  2636
                    	load_xf_bank( R_ECX ); 
nkeynes@375
  2637
                    	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  2638
                    	if( FRn&1 ) {
nkeynes@375
  2639
                    	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  2640
                    	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  2641
                    	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  2642
                    	} else /* FRn&1 == 0 */ {
nkeynes@375
  2643
                    	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@375
  2644
                    	    store_fr( R_EDX, R_EAX, FRn-1 );
nkeynes@375
  2645
                    	    store_fr( R_EDX, R_ECX, FRn );
nkeynes@375
  2646
                    	}
nkeynes@375
  2647
                        } else /* FRm&1 == 0 */ {
nkeynes@375
  2648
                    	if( FRn&1 ) {
nkeynes@375
  2649
                    	    JMP_rel8(22);
nkeynes@375
  2650
                    	    load_xf_bank( R_ECX );
nkeynes@375
  2651
                    	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  2652
                    	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  2653
                    	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  2654
                    	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  2655
                    	} else /* FRn&1 == 0 */ {
nkeynes@375
  2656
                    	    JMP_rel8(12);
nkeynes@375
  2657
                    	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  2658
                    	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  2659
                    	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  2660
                    	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  2661
                    	}
nkeynes@375
  2662
                        }
nkeynes@359
  2663
                        }
nkeynes@359
  2664
                        break;
nkeynes@359
  2665
                    case 0xD:
nkeynes@359
  2666
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  2667
                            case 0x0:
nkeynes@359
  2668
                                { /* FSTS FPUL, FRn */
nkeynes@359
  2669
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@377
  2670
                                check_fpuen();
nkeynes@377
  2671
                                load_fr_bank( R_ECX );
nkeynes@377
  2672
                                load_spreg( R_EAX, R_FPUL );
nkeynes@377
  2673
                                store_fr( R_ECX, R_EAX, FRn );
nkeynes@359
  2674
                                }
nkeynes@359
  2675
                                break;
nkeynes@359
  2676
                            case 0x1:
nkeynes@359
  2677
                                { /* FLDS FRm, FPUL */
nkeynes@359
  2678
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@377
  2679
                                check_fpuen();
nkeynes@377
  2680
                                load_fr_bank( R_ECX );
nkeynes@377
  2681
                                load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  2682
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2683
                                }
nkeynes@359
  2684
                                break;
nkeynes@359
  2685
                            case 0x2:
nkeynes@359
  2686
                                { /* FLOAT FPUL, FRn */
nkeynes@359
  2687
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@377
  2688
                                check_fpuen();
nkeynes@377
  2689
                                load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2690
                                load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  2691
                                FILD_sh4r(R_FPUL);
nkeynes@377
  2692
                                TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  2693
                                JNE_rel8(5);
nkeynes@377
  2694
                                pop_fr( R_EDX, FRn );
nkeynes@377
  2695
                                JMP_rel8(3);
nkeynes@377
  2696
                                pop_dr( R_EDX, FRn );
nkeynes@359
  2697
                                }
nkeynes@359
  2698
                                break;
nkeynes@359
  2699
                            case 0x3:
nkeynes@359
  2700
                                { /* FTRC FRm, FPUL */
nkeynes@359
  2701
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@377
  2702
                                check_fpuen();
nkeynes@377