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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 377:fa18743f6905
prev375:4627600f7f8e
next380:2e8166bf6832
author nkeynes
date Wed Sep 12 09:17:52 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fill in most of the FP operations and fix the stack adjustments
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.6 2007-09-12 09:17:24 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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#ifndef NDEBUG
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#define MARK_JMP(x,n) uint8_t *_mark_jmp_##x = xlat_output + n
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#define CHECK_JMP(x) assert( _mark_jmp_##x == xlat_output )
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#else
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#define MARK_JMP(x,n)
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#define CHECK_JMP(x)
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#endif
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_spreg( int x86reg, int regoffset )
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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void static inline store_spreg( int x86reg, int regoffset ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(regoffset);
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 10 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2b);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2a);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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   356
#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); return 1
nkeynes@368
   357
nkeynes@368
   358
nkeynes@359
   359
nkeynes@359
   360
/**
nkeynes@359
   361
 * Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359
   362
 * SI/DI as required
nkeynes@359
   363
 */
nkeynes@368
   364
void sh4_translate_begin_block() 
nkeynes@368
   365
{
nkeynes@368
   366
    PUSH_r32(R_EBP);
nkeynes@359
   367
    /* mov &sh4r, ebp */
nkeynes@359
   368
    load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374
   369
    PUSH_r32(R_EDI);
nkeynes@368
   370
    PUSH_r32(R_ESI);
nkeynes@368
   371
    
nkeynes@368
   372
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   373
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   374
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   375
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   376
}
nkeynes@359
   377
nkeynes@368
   378
/**
nkeynes@368
   379
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   380
 */
nkeynes@374
   381
void exit_block( )
nkeynes@368
   382
{
nkeynes@374
   383
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   384
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   385
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   386
    MUL_r32( R_ESI );
nkeynes@368
   387
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   388
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   389
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@374
   390
    POP_r32(R_ESI);
nkeynes@374
   391
    POP_r32(R_EDI);
nkeynes@374
   392
    POP_r32(R_EBP);
nkeynes@368
   393
    RET();
nkeynes@359
   394
}
nkeynes@359
   395
nkeynes@359
   396
/**
nkeynes@359
   397
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   398
 */
nkeynes@359
   399
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   400
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   401
    // Normal termination - save PC, cycle count
nkeynes@374
   402
    exit_block( );
nkeynes@359
   403
nkeynes@368
   404
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   405
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   406
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@368
   407
    JMP_rel8( 33 );
nkeynes@368
   408
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@368
   409
    JMP_rel8( 26 );
nkeynes@368
   410
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@368
   411
    JMP_rel8( 19 );
nkeynes@368
   412
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@368
   413
    JMP_rel8( 12 );
nkeynes@368
   414
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@368
   415
    JMP_rel8( 5 );                 
nkeynes@368
   416
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   417
    // target
nkeynes@368
   418
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   419
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   420
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   421
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   422
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   423
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   424
    MUL_r32( R_ESI );
nkeynes@368
   425
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   426
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   427
nkeynes@368
   428
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   429
    CALL_r32( R_EAX ); // 2
nkeynes@368
   430
    POP_r32(R_EBP);
nkeynes@368
   431
    RET();
nkeynes@368
   432
nkeynes@368
   433
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   434
}
nkeynes@359
   435
nkeynes@359
   436
/**
nkeynes@359
   437
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   438
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   439
 * 
nkeynes@359
   440
 *
nkeynes@359
   441
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   442
 * (eg a branch or 
nkeynes@359
   443
 */
nkeynes@359
   444
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   445
{
nkeynes@361
   446
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   447
    
nkeynes@359
   448
%%
nkeynes@359
   449
/* ALU operations */
nkeynes@359
   450
ADD Rm, Rn {:
nkeynes@359
   451
    load_reg( R_EAX, Rm );
nkeynes@359
   452
    load_reg( R_ECX, Rn );
nkeynes@359
   453
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   454
    store_reg( R_ECX, Rn );
nkeynes@359
   455
:}
nkeynes@359
   456
ADD #imm, Rn {:  
nkeynes@359
   457
    load_reg( R_EAX, Rn );
nkeynes@359
   458
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   459
    store_reg( R_EAX, Rn );
nkeynes@359
   460
:}
nkeynes@359
   461
ADDC Rm, Rn {:
nkeynes@359
   462
    load_reg( R_EAX, Rm );
nkeynes@359
   463
    load_reg( R_ECX, Rn );
nkeynes@359
   464
    LDC_t();
nkeynes@359
   465
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   466
    store_reg( R_ECX, Rn );
nkeynes@359
   467
    SETC_t();
nkeynes@359
   468
:}
nkeynes@359
   469
ADDV Rm, Rn {:
nkeynes@359
   470
    load_reg( R_EAX, Rm );
nkeynes@359
   471
    load_reg( R_ECX, Rn );
nkeynes@359
   472
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   473
    store_reg( R_ECX, Rn );
nkeynes@359
   474
    SETO_t();
nkeynes@359
   475
:}
nkeynes@359
   476
AND Rm, Rn {:
nkeynes@359
   477
    load_reg( R_EAX, Rm );
nkeynes@359
   478
    load_reg( R_ECX, Rn );
nkeynes@359
   479
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   480
    store_reg( R_ECX, Rn );
nkeynes@359
   481
:}
nkeynes@359
   482
AND #imm, R0 {:  
nkeynes@359
   483
    load_reg( R_EAX, 0 );
nkeynes@359
   484
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   485
    store_reg( R_EAX, 0 );
nkeynes@359
   486
:}
nkeynes@359
   487
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   488
    load_reg( R_EAX, 0 );
nkeynes@359
   489
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   490
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   491
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   492
    AND_imm32_r32(imm, R_ECX );
nkeynes@359
   493
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   494
:}
nkeynes@359
   495
CMP/EQ Rm, Rn {:  
nkeynes@359
   496
    load_reg( R_EAX, Rm );
nkeynes@359
   497
    load_reg( R_ECX, Rn );
nkeynes@359
   498
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   499
    SETE_t();
nkeynes@359
   500
:}
nkeynes@359
   501
CMP/EQ #imm, R0 {:  
nkeynes@359
   502
    load_reg( R_EAX, 0 );
nkeynes@359
   503
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   504
    SETE_t();
nkeynes@359
   505
:}
nkeynes@359
   506
CMP/GE Rm, Rn {:  
nkeynes@359
   507
    load_reg( R_EAX, Rm );
nkeynes@359
   508
    load_reg( R_ECX, Rn );
nkeynes@359
   509
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   510
    SETGE_t();
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/GT Rm, Rn {: 
nkeynes@359
   513
    load_reg( R_EAX, Rm );
nkeynes@359
   514
    load_reg( R_ECX, Rn );
nkeynes@359
   515
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   516
    SETG_t();
nkeynes@359
   517
:}
nkeynes@359
   518
CMP/HI Rm, Rn {:  
nkeynes@359
   519
    load_reg( R_EAX, Rm );
nkeynes@359
   520
    load_reg( R_ECX, Rn );
nkeynes@359
   521
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   522
    SETA_t();
nkeynes@359
   523
:}
nkeynes@359
   524
CMP/HS Rm, Rn {: 
nkeynes@359
   525
    load_reg( R_EAX, Rm );
nkeynes@359
   526
    load_reg( R_ECX, Rn );
nkeynes@359
   527
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   528
    SETAE_t();
nkeynes@359
   529
 :}
nkeynes@359
   530
CMP/PL Rn {: 
nkeynes@359
   531
    load_reg( R_EAX, Rn );
nkeynes@359
   532
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   533
    SETG_t();
nkeynes@359
   534
:}
nkeynes@359
   535
CMP/PZ Rn {:  
nkeynes@359
   536
    load_reg( R_EAX, Rn );
nkeynes@359
   537
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   538
    SETGE_t();
nkeynes@359
   539
:}
nkeynes@361
   540
CMP/STR Rm, Rn {:  
nkeynes@368
   541
    load_reg( R_EAX, Rm );
nkeynes@368
   542
    load_reg( R_ECX, Rn );
nkeynes@368
   543
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   544
    TEST_r8_r8( R_AL, R_AL );
nkeynes@368
   545
    JE_rel8(13);
nkeynes@368
   546
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   547
    JE_rel8(9);
nkeynes@368
   548
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   549
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@368
   550
    JE_rel8(2);
nkeynes@368
   551
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@368
   552
    SETE_t();
nkeynes@361
   553
:}
nkeynes@361
   554
DIV0S Rm, Rn {:
nkeynes@361
   555
    load_reg( R_EAX, Rm );
nkeynes@361
   556
    load_reg( R_ECX, Rm );
nkeynes@361
   557
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   558
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   559
    store_spreg( R_EAX, R_M );
nkeynes@361
   560
    store_spreg( R_ECX, R_Q );
nkeynes@361
   561
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   562
    SETE_t();
nkeynes@361
   563
:}
nkeynes@361
   564
DIV0U {:  
nkeynes@361
   565
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   566
    store_spreg( R_EAX, R_Q );
nkeynes@361
   567
    store_spreg( R_EAX, R_M );
nkeynes@361
   568
    store_spreg( R_EAX, R_T );
nkeynes@361
   569
:}
nkeynes@374
   570
DIV1 Rm, Rn {:  
nkeynes@374
   571
    load_reg( R_ECX, Rn );
nkeynes@374
   572
    LDC_t();
nkeynes@374
   573
    RCL1_r32( R_ECX ); // OP2
nkeynes@374
   574
    SETC_r32( R_EDX ); // Q
nkeynes@374
   575
    load_spreg( R_EAX, R_Q );
nkeynes@374
   576
    CMP_sh4r_r32( R_M, R_EAX );
nkeynes@374
   577
    JE_rel8(8);
nkeynes@374
   578
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
   579
    JMP_rel8(3);
nkeynes@374
   580
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@374
   581
    // TODO
nkeynes@374
   582
:}
nkeynes@361
   583
DMULS.L Rm, Rn {:  
nkeynes@361
   584
    load_reg( R_EAX, Rm );
nkeynes@361
   585
    load_reg( R_ECX, Rn );
nkeynes@361
   586
    IMUL_r32(R_ECX);
nkeynes@361
   587
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   588
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   589
:}
nkeynes@361
   590
DMULU.L Rm, Rn {:  
nkeynes@361
   591
    load_reg( R_EAX, Rm );
nkeynes@361
   592
    load_reg( R_ECX, Rn );
nkeynes@361
   593
    MUL_r32(R_ECX);
nkeynes@361
   594
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   595
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   596
:}
nkeynes@359
   597
DT Rn {:  
nkeynes@359
   598
    load_reg( R_EAX, Rn );
nkeynes@359
   599
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   600
    store_reg( R_EAX, Rn );
nkeynes@359
   601
    SETE_t();
nkeynes@359
   602
:}
nkeynes@359
   603
EXTS.B Rm, Rn {:  
nkeynes@359
   604
    load_reg( R_EAX, Rm );
nkeynes@359
   605
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   606
    store_reg( R_EAX, Rn );
nkeynes@359
   607
:}
nkeynes@361
   608
EXTS.W Rm, Rn {:  
nkeynes@361
   609
    load_reg( R_EAX, Rm );
nkeynes@361
   610
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   611
    store_reg( R_EAX, Rn );
nkeynes@361
   612
:}
nkeynes@361
   613
EXTU.B Rm, Rn {:  
nkeynes@361
   614
    load_reg( R_EAX, Rm );
nkeynes@361
   615
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   616
    store_reg( R_EAX, Rn );
nkeynes@361
   617
:}
nkeynes@361
   618
EXTU.W Rm, Rn {:  
nkeynes@361
   619
    load_reg( R_EAX, Rm );
nkeynes@361
   620
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   621
    store_reg( R_EAX, Rn );
nkeynes@361
   622
:}
nkeynes@359
   623
MAC.L @Rm+, @Rn+ {:  :}
nkeynes@359
   624
MAC.W @Rm+, @Rn+ {:  :}
nkeynes@359
   625
MOVT Rn {:  
nkeynes@359
   626
    load_spreg( R_EAX, R_T );
nkeynes@359
   627
    store_reg( R_EAX, Rn );
nkeynes@359
   628
:}
nkeynes@361
   629
MUL.L Rm, Rn {:  
nkeynes@361
   630
    load_reg( R_EAX, Rm );
nkeynes@361
   631
    load_reg( R_ECX, Rn );
nkeynes@361
   632
    MUL_r32( R_ECX );
nkeynes@361
   633
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   634
:}
nkeynes@374
   635
MULS.W Rm, Rn {:
nkeynes@374
   636
    load_reg16s( R_EAX, Rm );
nkeynes@374
   637
    load_reg16s( R_ECX, Rn );
nkeynes@374
   638
    MUL_r32( R_ECX );
nkeynes@374
   639
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   640
:}
nkeynes@374
   641
MULU.W Rm, Rn {:  
nkeynes@374
   642
    load_reg16u( R_EAX, Rm );
nkeynes@374
   643
    load_reg16u( R_ECX, Rn );
nkeynes@374
   644
    MUL_r32( R_ECX );
nkeynes@374
   645
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   646
:}
nkeynes@359
   647
NEG Rm, Rn {:
nkeynes@359
   648
    load_reg( R_EAX, Rm );
nkeynes@359
   649
    NEG_r32( R_EAX );
nkeynes@359
   650
    store_reg( R_EAX, Rn );
nkeynes@359
   651
:}
nkeynes@359
   652
NEGC Rm, Rn {:  
nkeynes@359
   653
    load_reg( R_EAX, Rm );
nkeynes@359
   654
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   655
    LDC_t();
nkeynes@359
   656
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   657
    store_reg( R_ECX, Rn );
nkeynes@359
   658
    SETC_t();
nkeynes@359
   659
:}
nkeynes@359
   660
NOT Rm, Rn {:  
nkeynes@359
   661
    load_reg( R_EAX, Rm );
nkeynes@359
   662
    NOT_r32( R_EAX );
nkeynes@359
   663
    store_reg( R_EAX, Rn );
nkeynes@359
   664
:}
nkeynes@359
   665
OR Rm, Rn {:  
nkeynes@359
   666
    load_reg( R_EAX, Rm );
nkeynes@359
   667
    load_reg( R_ECX, Rn );
nkeynes@359
   668
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   669
    store_reg( R_ECX, Rn );
nkeynes@359
   670
:}
nkeynes@359
   671
OR #imm, R0 {:
nkeynes@359
   672
    load_reg( R_EAX, 0 );
nkeynes@359
   673
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   674
    store_reg( R_EAX, 0 );
nkeynes@359
   675
:}
nkeynes@374
   676
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   677
    load_reg( R_EAX, 0 );
nkeynes@374
   678
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   679
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   680
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
   681
    OR_imm32_r32(imm, R_ECX );
nkeynes@374
   682
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   683
:}
nkeynes@359
   684
ROTCL Rn {:
nkeynes@359
   685
    load_reg( R_EAX, Rn );
nkeynes@359
   686
    LDC_t();
nkeynes@359
   687
    RCL1_r32( R_EAX );
nkeynes@359
   688
    store_reg( R_EAX, Rn );
nkeynes@359
   689
    SETC_t();
nkeynes@359
   690
:}
nkeynes@359
   691
ROTCR Rn {:  
nkeynes@359
   692
    load_reg( R_EAX, Rn );
nkeynes@359
   693
    LDC_t();
nkeynes@359
   694
    RCR1_r32( R_EAX );
nkeynes@359
   695
    store_reg( R_EAX, Rn );
nkeynes@359
   696
    SETC_t();
nkeynes@359
   697
:}
nkeynes@359
   698
ROTL Rn {:  
nkeynes@359
   699
    load_reg( R_EAX, Rn );
nkeynes@359
   700
    ROL1_r32( R_EAX );
nkeynes@359
   701
    store_reg( R_EAX, Rn );
nkeynes@359
   702
    SETC_t();
nkeynes@359
   703
:}
nkeynes@359
   704
ROTR Rn {:  
nkeynes@359
   705
    load_reg( R_EAX, Rn );
nkeynes@359
   706
    ROR1_r32( R_EAX );
nkeynes@359
   707
    store_reg( R_EAX, Rn );
nkeynes@359
   708
    SETC_t();
nkeynes@359
   709
:}
nkeynes@359
   710
SHAD Rm, Rn {:
nkeynes@359
   711
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   712
    load_reg( R_EAX, Rn );
nkeynes@361
   713
    load_reg( R_ECX, Rm );
nkeynes@361
   714
    CMP_imm32_r32( 0, R_ECX );
nkeynes@361
   715
    JAE_rel8(9);
nkeynes@361
   716
                    
nkeynes@361
   717
    NEG_r32( R_ECX );      // 2
nkeynes@361
   718
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   719
    SAR_r32_CL( R_EAX );       // 2
nkeynes@361
   720
    JMP_rel8(5);               // 2
nkeynes@361
   721
    
nkeynes@361
   722
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   723
    SHL_r32_CL( R_EAX );       // 2
nkeynes@361
   724
                    
nkeynes@361
   725
    store_reg( R_EAX, Rn );
nkeynes@359
   726
:}
nkeynes@359
   727
SHLD Rm, Rn {:  
nkeynes@368
   728
    load_reg( R_EAX, Rn );
nkeynes@368
   729
    load_reg( R_ECX, Rm );
nkeynes@368
   730
nkeynes@368
   731
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@368
   732
    SHL_r32_CL( R_EAX );
nkeynes@368
   733
    NEG_r32( R_ECX );
nkeynes@368
   734
    SHR_r32_CL( R_EDX );
nkeynes@368
   735
    CMP_imm8s_r32( 0, R_ECX );
nkeynes@368
   736
    CMOVAE_r32_r32( R_EDX,  R_EAX );
nkeynes@368
   737
    store_reg( R_EAX, Rn );
nkeynes@359
   738
:}
nkeynes@359
   739
SHAL Rn {: 
nkeynes@359
   740
    load_reg( R_EAX, Rn );
nkeynes@359
   741
    SHL1_r32( R_EAX );
nkeynes@359
   742
    store_reg( R_EAX, Rn );
nkeynes@359
   743
:}
nkeynes@359
   744
SHAR Rn {:  
nkeynes@359
   745
    load_reg( R_EAX, Rn );
nkeynes@359
   746
    SAR1_r32( R_EAX );
nkeynes@359
   747
    store_reg( R_EAX, Rn );
nkeynes@359
   748
:}
nkeynes@359
   749
SHLL Rn {:  
nkeynes@359
   750
    load_reg( R_EAX, Rn );
nkeynes@359
   751
    SHL1_r32( R_EAX );
nkeynes@359
   752
    store_reg( R_EAX, Rn );
nkeynes@359
   753
:}
nkeynes@359
   754
SHLL2 Rn {:
nkeynes@359
   755
    load_reg( R_EAX, Rn );
nkeynes@359
   756
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   757
    store_reg( R_EAX, Rn );
nkeynes@359
   758
:}
nkeynes@359
   759
SHLL8 Rn {:  
nkeynes@359
   760
    load_reg( R_EAX, Rn );
nkeynes@359
   761
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   762
    store_reg( R_EAX, Rn );
nkeynes@359
   763
:}
nkeynes@359
   764
SHLL16 Rn {:  
nkeynes@359
   765
    load_reg( R_EAX, Rn );
nkeynes@359
   766
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   767
    store_reg( R_EAX, Rn );
nkeynes@359
   768
:}
nkeynes@359
   769
SHLR Rn {:  
nkeynes@359
   770
    load_reg( R_EAX, Rn );
nkeynes@359
   771
    SHR1_r32( R_EAX );
nkeynes@359
   772
    store_reg( R_EAX, Rn );
nkeynes@359
   773
:}
nkeynes@359
   774
SHLR2 Rn {:  
nkeynes@359
   775
    load_reg( R_EAX, Rn );
nkeynes@359
   776
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   777
    store_reg( R_EAX, Rn );
nkeynes@359
   778
:}
nkeynes@359
   779
SHLR8 Rn {:  
nkeynes@359
   780
    load_reg( R_EAX, Rn );
nkeynes@359
   781
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   782
    store_reg( R_EAX, Rn );
nkeynes@359
   783
:}
nkeynes@359
   784
SHLR16 Rn {:  
nkeynes@359
   785
    load_reg( R_EAX, Rn );
nkeynes@359
   786
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   787
    store_reg( R_EAX, Rn );
nkeynes@359
   788
:}
nkeynes@359
   789
SUB Rm, Rn {:  
nkeynes@359
   790
    load_reg( R_EAX, Rm );
nkeynes@359
   791
    load_reg( R_ECX, Rn );
nkeynes@359
   792
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   793
    store_reg( R_ECX, Rn );
nkeynes@359
   794
:}
nkeynes@359
   795
SUBC Rm, Rn {:  
nkeynes@359
   796
    load_reg( R_EAX, Rm );
nkeynes@359
   797
    load_reg( R_ECX, Rn );
nkeynes@359
   798
    LDC_t();
nkeynes@359
   799
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   800
    store_reg( R_ECX, Rn );
nkeynes@359
   801
:}
nkeynes@359
   802
SUBV Rm, Rn {:  
nkeynes@359
   803
    load_reg( R_EAX, Rm );
nkeynes@359
   804
    load_reg( R_ECX, Rn );
nkeynes@359
   805
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   806
    store_reg( R_ECX, Rn );
nkeynes@359
   807
    SETO_t();
nkeynes@359
   808
:}
nkeynes@359
   809
SWAP.B Rm, Rn {:  
nkeynes@359
   810
    load_reg( R_EAX, Rm );
nkeynes@359
   811
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   812
    store_reg( R_EAX, Rn );
nkeynes@359
   813
:}
nkeynes@359
   814
SWAP.W Rm, Rn {:  
nkeynes@359
   815
    load_reg( R_EAX, Rm );
nkeynes@359
   816
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   817
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   818
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   819
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   820
    store_reg( R_ECX, Rn );
nkeynes@359
   821
:}
nkeynes@361
   822
TAS.B @Rn {:  
nkeynes@361
   823
    load_reg( R_ECX, Rn );
nkeynes@361
   824
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   825
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   826
    SETE_t();
nkeynes@361
   827
    OR_imm8_r8( 0x80, R_AL );
nkeynes@361
   828
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   829
:}
nkeynes@361
   830
TST Rm, Rn {:  
nkeynes@361
   831
    load_reg( R_EAX, Rm );
nkeynes@361
   832
    load_reg( R_ECX, Rn );
nkeynes@361
   833
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   834
    SETE_t();
nkeynes@361
   835
:}
nkeynes@368
   836
TST #imm, R0 {:  
nkeynes@368
   837
    load_reg( R_EAX, 0 );
nkeynes@368
   838
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   839
    SETE_t();
nkeynes@368
   840
:}
nkeynes@368
   841
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   842
    load_reg( R_EAX, 0);
nkeynes@368
   843
    load_reg( R_ECX, R_GBR);
nkeynes@368
   844
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   845
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
   846
    TEST_imm8_r8( imm, R_EAX );
nkeynes@368
   847
    SETE_t();
nkeynes@368
   848
:}
nkeynes@359
   849
XOR Rm, Rn {:  
nkeynes@359
   850
    load_reg( R_EAX, Rm );
nkeynes@359
   851
    load_reg( R_ECX, Rn );
nkeynes@359
   852
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   853
    store_reg( R_ECX, Rn );
nkeynes@359
   854
:}
nkeynes@359
   855
XOR #imm, R0 {:  
nkeynes@359
   856
    load_reg( R_EAX, 0 );
nkeynes@359
   857
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   858
    store_reg( R_EAX, 0 );
nkeynes@359
   859
:}
nkeynes@359
   860
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   861
    load_reg( R_EAX, 0 );
nkeynes@359
   862
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   863
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   864
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   865
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   866
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   867
:}
nkeynes@361
   868
XTRCT Rm, Rn {:
nkeynes@361
   869
    load_reg( R_EAX, Rm );
nkeynes@361
   870
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   871
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   872
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   873
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   874
    store_reg( R_ECX, Rn );
nkeynes@359
   875
:}
nkeynes@359
   876
nkeynes@359
   877
/* Data move instructions */
nkeynes@359
   878
MOV Rm, Rn {:  
nkeynes@359
   879
    load_reg( R_EAX, Rm );
nkeynes@359
   880
    store_reg( R_EAX, Rn );
nkeynes@359
   881
:}
nkeynes@359
   882
MOV #imm, Rn {:  
nkeynes@359
   883
    load_imm32( R_EAX, imm );
nkeynes@359
   884
    store_reg( R_EAX, Rn );
nkeynes@359
   885
:}
nkeynes@359
   886
MOV.B Rm, @Rn {:  
nkeynes@359
   887
    load_reg( R_EAX, Rm );
nkeynes@359
   888
    load_reg( R_ECX, Rn );
nkeynes@359
   889
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   890
:}
nkeynes@359
   891
MOV.B Rm, @-Rn {:  
nkeynes@359
   892
    load_reg( R_EAX, Rm );
nkeynes@359
   893
    load_reg( R_ECX, Rn );
nkeynes@359
   894
    ADD_imm8s_r32( -1, Rn );
nkeynes@359
   895
    store_reg( R_ECX, Rn );
nkeynes@359
   896
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   897
:}
nkeynes@359
   898
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   899
    load_reg( R_EAX, 0 );
nkeynes@359
   900
    load_reg( R_ECX, Rn );
nkeynes@359
   901
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   902
    load_reg( R_EAX, Rm );
nkeynes@359
   903
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   904
:}
nkeynes@359
   905
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   906
    load_reg( R_EAX, 0 );
nkeynes@359
   907
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   908
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   909
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   910
:}
nkeynes@359
   911
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
   912
    load_reg( R_EAX, 0 );
nkeynes@359
   913
    load_reg( R_ECX, Rn );
nkeynes@359
   914
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   915
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   916
:}
nkeynes@359
   917
MOV.B @Rm, Rn {:  
nkeynes@359
   918
    load_reg( R_ECX, Rm );
nkeynes@359
   919
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   920
    store_reg( R_ECX, Rn );
nkeynes@359
   921
:}
nkeynes@359
   922
MOV.B @Rm+, Rn {:  
nkeynes@359
   923
    load_reg( R_ECX, Rm );
nkeynes@359
   924
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
   925
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
   926
    store_reg( R_EAX, Rm );
nkeynes@359
   927
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   928
    store_reg( R_EAX, Rn );
nkeynes@359
   929
:}
nkeynes@359
   930
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
   931
    load_reg( R_EAX, 0 );
nkeynes@359
   932
    load_reg( R_ECX, Rm );
nkeynes@359
   933
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   934
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   935
    store_reg( R_EAX, Rn );
nkeynes@359
   936
:}
nkeynes@359
   937
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
   938
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   939
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   940
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   941
    store_reg( R_EAX, 0 );
nkeynes@359
   942
:}
nkeynes@359
   943
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
   944
    load_reg( R_ECX, Rm );
nkeynes@359
   945
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   946
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   947
    store_reg( R_EAX, 0 );
nkeynes@359
   948
:}
nkeynes@374
   949
MOV.L Rm, @Rn {:
nkeynes@361
   950
    load_reg( R_EAX, Rm );
nkeynes@361
   951
    load_reg( R_ECX, Rn );
nkeynes@374
   952
    check_walign32(R_ECX);
nkeynes@361
   953
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   954
:}
nkeynes@361
   955
MOV.L Rm, @-Rn {:  
nkeynes@361
   956
    load_reg( R_EAX, Rm );
nkeynes@361
   957
    load_reg( R_ECX, Rn );
nkeynes@374
   958
    check_walign32( R_ECX );
nkeynes@361
   959
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   960
    store_reg( R_ECX, Rn );
nkeynes@361
   961
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   962
:}
nkeynes@361
   963
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
   964
    load_reg( R_EAX, 0 );
nkeynes@361
   965
    load_reg( R_ECX, Rn );
nkeynes@361
   966
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   967
    check_walign32( R_ECX );
nkeynes@361
   968
    load_reg( R_EAX, Rm );
nkeynes@361
   969
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   970
:}
nkeynes@361
   971
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
   972
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   973
    load_reg( R_EAX, 0 );
nkeynes@361
   974
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   975
    check_walign32( R_ECX );
nkeynes@361
   976
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   977
:}
nkeynes@361
   978
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
   979
    load_reg( R_ECX, Rn );
nkeynes@361
   980
    load_reg( R_EAX, Rm );
nkeynes@361
   981
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   982
    check_walign32( R_ECX );
nkeynes@361
   983
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   984
:}
nkeynes@361
   985
MOV.L @Rm, Rn {:  
nkeynes@361
   986
    load_reg( R_ECX, Rm );
nkeynes@374
   987
    check_ralign32( R_ECX );
nkeynes@361
   988
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   989
    store_reg( R_EAX, Rn );
nkeynes@361
   990
:}
nkeynes@361
   991
MOV.L @Rm+, Rn {:  
nkeynes@361
   992
    load_reg( R_EAX, Rm );
nkeynes@374
   993
    check_ralign32( R_ECX );
nkeynes@361
   994
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   995
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
   996
    store_reg( R_EAX, Rm );
nkeynes@361
   997
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   998
    store_reg( R_EAX, Rn );
nkeynes@361
   999
:}
nkeynes@361
  1000
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1001
    load_reg( R_EAX, 0 );
nkeynes@361
  1002
    load_reg( R_ECX, Rm );
nkeynes@361
  1003
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1004
    check_ralign32( R_ECX );
nkeynes@361
  1005
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1006
    store_reg( R_EAX, Rn );
nkeynes@361
  1007
:}
nkeynes@361
  1008
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1009
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1010
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1011
    check_ralign32( R_ECX );
nkeynes@361
  1012
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1013
    store_reg( R_EAX, 0 );
nkeynes@361
  1014
:}
nkeynes@361
  1015
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1016
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1017
	SLOTILLEGAL();
nkeynes@374
  1018
    } else {
nkeynes@374
  1019
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1020
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1021
	store_reg( R_EAX, 0 );
nkeynes@374
  1022
    }
nkeynes@361
  1023
:}
nkeynes@361
  1024
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1025
    load_reg( R_ECX, Rm );
nkeynes@361
  1026
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1027
    check_ralign32( R_ECX );
nkeynes@361
  1028
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1029
    store_reg( R_EAX, Rn );
nkeynes@361
  1030
:}
nkeynes@361
  1031
MOV.W Rm, @Rn {:  
nkeynes@361
  1032
    load_reg( R_ECX, Rn );
nkeynes@374
  1033
    check_walign16( R_ECX );
nkeynes@361
  1034
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1035
    store_reg( R_EAX, Rn );
nkeynes@361
  1036
:}
nkeynes@361
  1037
MOV.W Rm, @-Rn {:  
nkeynes@361
  1038
    load_reg( R_ECX, Rn );
nkeynes@374
  1039
    check_walign16( R_ECX );
nkeynes@361
  1040
    load_reg( R_EAX, Rm );
nkeynes@361
  1041
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
  1042
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1043
:}
nkeynes@361
  1044
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1045
    load_reg( R_EAX, 0 );
nkeynes@361
  1046
    load_reg( R_ECX, Rn );
nkeynes@361
  1047
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1048
    check_walign16( R_ECX );
nkeynes@361
  1049
    load_reg( R_EAX, Rm );
nkeynes@361
  1050
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1051
:}
nkeynes@361
  1052
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1053
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1054
    load_reg( R_EAX, 0 );
nkeynes@361
  1055
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1056
    check_walign16( R_ECX );
nkeynes@361
  1057
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1058
:}
nkeynes@361
  1059
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1060
    load_reg( R_ECX, Rn );
nkeynes@361
  1061
    load_reg( R_EAX, 0 );
nkeynes@361
  1062
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1063
    check_walign16( R_ECX );
nkeynes@361
  1064
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1065
:}
nkeynes@361
  1066
MOV.W @Rm, Rn {:  
nkeynes@361
  1067
    load_reg( R_ECX, Rm );
nkeynes@374
  1068
    check_ralign16( R_ECX );
nkeynes@361
  1069
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1070
    store_reg( R_EAX, Rn );
nkeynes@361
  1071
:}
nkeynes@361
  1072
MOV.W @Rm+, Rn {:  
nkeynes@361
  1073
    load_reg( R_EAX, Rm );
nkeynes@374
  1074
    check_ralign16( R_EAX );
nkeynes@361
  1075
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1076
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1077
    store_reg( R_EAX, Rm );
nkeynes@361
  1078
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1079
    store_reg( R_EAX, Rn );
nkeynes@361
  1080
:}
nkeynes@361
  1081
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1082
    load_reg( R_EAX, 0 );
nkeynes@361
  1083
    load_reg( R_ECX, Rm );
nkeynes@361
  1084
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1085
    check_ralign16( R_ECX );
nkeynes@361
  1086
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1087
    store_reg( R_EAX, Rn );
nkeynes@361
  1088
:}
nkeynes@361
  1089
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1090
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1091
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1092
    check_ralign16( R_ECX );
nkeynes@361
  1093
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1094
    store_reg( R_EAX, 0 );
nkeynes@361
  1095
:}
nkeynes@361
  1096
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1097
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1098
	SLOTILLEGAL();
nkeynes@374
  1099
    } else {
nkeynes@374
  1100
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1101
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1102
	store_reg( R_EAX, Rn );
nkeynes@374
  1103
    }
nkeynes@361
  1104
:}
nkeynes@361
  1105
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1106
    load_reg( R_ECX, Rm );
nkeynes@361
  1107
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1108
    check_ralign16( R_ECX );
nkeynes@361
  1109
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1110
    store_reg( R_EAX, 0 );
nkeynes@361
  1111
:}
nkeynes@361
  1112
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1113
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1114
	SLOTILLEGAL();
nkeynes@374
  1115
    } else {
nkeynes@374
  1116
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1117
	store_reg( R_ECX, 0 );
nkeynes@374
  1118
    }
nkeynes@361
  1119
:}
nkeynes@361
  1120
MOVCA.L R0, @Rn {:  
nkeynes@361
  1121
    load_reg( R_EAX, 0 );
nkeynes@361
  1122
    load_reg( R_ECX, Rn );
nkeynes@374
  1123
    check_walign32( R_ECX );
nkeynes@361
  1124
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1125
:}
nkeynes@359
  1126
nkeynes@359
  1127
/* Control transfer instructions */
nkeynes@374
  1128
BF disp {:
nkeynes@374
  1129
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1130
	SLOTILLEGAL();
nkeynes@374
  1131
    } else {
nkeynes@374
  1132
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1133
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1134
	JNE_rel8( 5 );
nkeynes@374
  1135
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1136
	INC_r32(R_ESI);
nkeynes@374
  1137
	return 1;
nkeynes@374
  1138
    }
nkeynes@374
  1139
:}
nkeynes@374
  1140
BF/S disp {:
nkeynes@374
  1141
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1142
	SLOTILLEGAL();
nkeynes@374
  1143
    } else {
nkeynes@374
  1144
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1145
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1146
	JNE_rel8( 5 );
nkeynes@374
  1147
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1148
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1149
	INC_r32(R_ESI);
nkeynes@374
  1150
	return 0;
nkeynes@374
  1151
    }
nkeynes@374
  1152
:}
nkeynes@374
  1153
BRA disp {:  
nkeynes@374
  1154
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1155
	SLOTILLEGAL();
nkeynes@374
  1156
    } else {
nkeynes@374
  1157
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1158
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1159
	INC_r32(R_ESI);
nkeynes@374
  1160
	return 0;
nkeynes@374
  1161
    }
nkeynes@374
  1162
:}
nkeynes@374
  1163
BRAF Rn {:  
nkeynes@374
  1164
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1165
	SLOTILLEGAL();
nkeynes@374
  1166
    } else {
nkeynes@374
  1167
	load_reg( R_EDI, Rn );
nkeynes@374
  1168
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1169
	INC_r32(R_ESI);
nkeynes@374
  1170
	return 0;
nkeynes@374
  1171
    }
nkeynes@374
  1172
:}
nkeynes@374
  1173
BSR disp {:  
nkeynes@374
  1174
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1175
	SLOTILLEGAL();
nkeynes@374
  1176
    } else {
nkeynes@374
  1177
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1178
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1179
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1180
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1181
	INC_r32(R_ESI);
nkeynes@374
  1182
	return 0;
nkeynes@374
  1183
    }
nkeynes@374
  1184
:}
nkeynes@374
  1185
BSRF Rn {:  
nkeynes@374
  1186
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1187
	SLOTILLEGAL();
nkeynes@374
  1188
    } else {
nkeynes@374
  1189
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1190
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1191
	load_reg( R_EDI, Rn );
nkeynes@374
  1192
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1193
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1194
	INC_r32(R_ESI);
nkeynes@374
  1195
	return 0;
nkeynes@374
  1196
    }
nkeynes@374
  1197
:}
nkeynes@374
  1198
BT disp {:
nkeynes@374
  1199
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1200
	SLOTILLEGAL();
nkeynes@374
  1201
    } else {
nkeynes@374
  1202
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1203
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1204
	JE_rel8( 5 );
nkeynes@374
  1205
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1206
	INC_r32(R_ESI);
nkeynes@374
  1207
	return 1;
nkeynes@374
  1208
    }
nkeynes@374
  1209
:}
nkeynes@374
  1210
BT/S disp {:
nkeynes@374
  1211
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1212
	SLOTILLEGAL();
nkeynes@374
  1213
    } else {
nkeynes@374
  1214
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1215
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@374
  1216
	JE_rel8( 5 );
nkeynes@374
  1217
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1218
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1219
	INC_r32(R_ESI);
nkeynes@374
  1220
	return 0;
nkeynes@374
  1221
    }
nkeynes@374
  1222
:}
nkeynes@374
  1223
JMP @Rn {:  
nkeynes@374
  1224
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1225
	SLOTILLEGAL();
nkeynes@374
  1226
    } else {
nkeynes@374
  1227
	load_reg( R_EDI, Rn );
nkeynes@374
  1228
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1229
	INC_r32(R_ESI);
nkeynes@374
  1230
	return 0;
nkeynes@374
  1231
    }
nkeynes@374
  1232
:}
nkeynes@374
  1233
JSR @Rn {:  
nkeynes@374
  1234
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1235
	SLOTILLEGAL();
nkeynes@374
  1236
    } else {
nkeynes@374
  1237
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1238
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1239
	load_reg( R_EDI, Rn );
nkeynes@374
  1240
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1241
	INC_r32(R_ESI);
nkeynes@374
  1242
	return 0;
nkeynes@374
  1243
    }
nkeynes@374
  1244
:}
nkeynes@374
  1245
RTE {:  
nkeynes@374
  1246
    check_priv();
nkeynes@374
  1247
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1248
	SLOTILLEGAL();
nkeynes@374
  1249
    } else {
nkeynes@374
  1250
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1251
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1252
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1253
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1254
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1255
	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
  1256
	INC_r32(R_ESI);
nkeynes@374
  1257
	return 0;
nkeynes@374
  1258
    }
nkeynes@374
  1259
:}
nkeynes@374
  1260
RTS {:  
nkeynes@374
  1261
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1262
	SLOTILLEGAL();
nkeynes@374
  1263
    } else {
nkeynes@374
  1264
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1265
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1266
	INC_r32(R_ESI);
nkeynes@374
  1267
	return 0;
nkeynes@374
  1268
    }
nkeynes@374
  1269
:}
nkeynes@374
  1270
TRAPA #imm {:  
nkeynes@374
  1271
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1272
	SLOTILLEGAL();
nkeynes@374
  1273
    } else {
nkeynes@374
  1274
	// TODO: Write TRA 
nkeynes@374
  1275
	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  1276
    }
nkeynes@374
  1277
:}
nkeynes@374
  1278
UNDEF {:  
nkeynes@374
  1279
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1280
	RAISE_EXCEPTION(EXC_SLOT_ILLEGAL);
nkeynes@374
  1281
    } else {
nkeynes@374
  1282
	RAISE_EXCEPTION(EXC_ILLEGAL);
nkeynes@374
  1283
    }
nkeynes@368
  1284
    return 1;
nkeynes@368
  1285
:}
nkeynes@374
  1286
nkeynes@374
  1287
CLRMAC {:  
nkeynes@374
  1288
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1289
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1290
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1291
:}
nkeynes@374
  1292
CLRS {:
nkeynes@374
  1293
    CLC();
nkeynes@374
  1294
    SETC_sh4r(R_S);
nkeynes@368
  1295
:}
nkeynes@374
  1296
CLRT {:  
nkeynes@374
  1297
    CLC();
nkeynes@374
  1298
    SETC_t();
nkeynes@359
  1299
:}
nkeynes@374
  1300
SETS {:  
nkeynes@374
  1301
    STC();
nkeynes@374
  1302
    SETC_sh4r(R_S);
nkeynes@359
  1303
:}
nkeynes@374
  1304
SETT {:  
nkeynes@374
  1305
    STC();
nkeynes@374
  1306
    SETC_t();
nkeynes@374
  1307
:}
nkeynes@359
  1308
nkeynes@375
  1309
/* Floating point moves */
nkeynes@375
  1310
FMOV FRm, FRn {:  
nkeynes@375
  1311
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1312
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1313
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1314
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1315
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1316
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1317
     */
nkeynes@377
  1318
    check_fpuen();
nkeynes@375
  1319
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1320
    load_fr_bank( R_EDX );
nkeynes@375
  1321
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  1322
    JNE_rel8(8);
nkeynes@375
  1323
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1324
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1325
    if( FRm&1 ) {
nkeynes@375
  1326
	JMP_rel8(22);
nkeynes@375
  1327
	load_xf_bank( R_ECX ); 
nkeynes@375
  1328
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1329
	if( FRn&1 ) {
nkeynes@375
  1330
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1331
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1332
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1333
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1334
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@375
  1335
	    store_fr( R_EDX, R_EAX, FRn-1 );
nkeynes@375
  1336
	    store_fr( R_EDX, R_ECX, FRn );
nkeynes@375
  1337
	}
nkeynes@375
  1338
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1339
	if( FRn&1 ) {
nkeynes@375
  1340
	    JMP_rel8(22);
nkeynes@375
  1341
	    load_xf_bank( R_ECX );
nkeynes@375
  1342
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1343
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1344
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1345
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1346
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1347
	    JMP_rel8(12);
nkeynes@375
  1348
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1349
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1350
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1351
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375
  1352
	}
nkeynes@375
  1353
    }
nkeynes@375
  1354
:}
nkeynes@375
  1355
FMOV FRm, @Rn {:  
nkeynes@377
  1356
    check_fpuen();
nkeynes@375
  1357
    load_reg( R_EDX, Rn );
nkeynes@375
  1358
    check_walign32( R_EDX );
nkeynes@375
  1359
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1360
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  1361
    JNE_rel8(20);
nkeynes@377
  1362
    load_fr_bank( R_ECX );
nkeynes@375
  1363
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1364
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1365
    if( FRm&1 ) {
nkeynes@375
  1366
	JMP_rel8( 46 );
nkeynes@375
  1367
	load_xf_bank( R_ECX );
nkeynes@375
  1368
    } else {
nkeynes@375
  1369
	JMP_rel8( 39 );
nkeynes@377
  1370
	load_fr_bank( R_ECX );
nkeynes@375
  1371
    }
nkeynes@375
  1372
    load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@375
  1373
    load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@375
  1374
    MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@375
  1375
:}
nkeynes@375
  1376
FMOV @Rm, FRn {:  
nkeynes@377
  1377
    check_fpuen();
nkeynes@375
  1378
    load_reg( R_EDX, Rm );
nkeynes@375
  1379
    check_ralign32( R_EDX );
nkeynes@375
  1380
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1381
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@375
  1382
    JNE_rel8(19);
nkeynes@375
  1383
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1384
    load_fr_bank( R_ECX );
nkeynes@375
  1385
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1386
    if( FRn&1 ) {
nkeynes@375
  1387
	JMP_rel8(46);
nkeynes@375
  1388
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1389
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1390
	load_xf_bank( R_ECX );
nkeynes@375
  1391
    } else {
nkeynes@375
  1392
	JMP_rel8(36);
nkeynes@375
  1393
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1394
	load_fr_bank( R_ECX );
nkeynes@375
  1395
    }
nkeynes@375
  1396
    store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@375
  1397
    store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@375
  1398
:}
nkeynes@377
  1399
FMOV FRm, @-Rn {:  
nkeynes@377
  1400
    check_fpuen();
nkeynes@377
  1401
    load_reg( R_EDX, Rn );
nkeynes@377
  1402
    check_walign32( R_EDX );
nkeynes@377
  1403
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1404
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1405
    JNE_rel8(20);
nkeynes@377
  1406
    load_fr_bank( R_ECX );
nkeynes@377
  1407
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1408
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1409
    store_reg( R_EDX, Rn );
nkeynes@377
  1410
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1411
    if( FRm&1 ) {
nkeynes@377
  1412
	JMP_rel8( 46 );
nkeynes@377
  1413
	load_xf_bank( R_ECX );
nkeynes@377
  1414
    } else {
nkeynes@377
  1415
	JMP_rel8( 39 );
nkeynes@377
  1416
	load_fr_bank( R_ECX );
nkeynes@377
  1417
    }
nkeynes@377
  1418
    load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@377
  1419
    load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@377
  1420
    ADD_imm8s_r32(-8,R_EDX);
nkeynes@377
  1421
    store_reg( R_EDX, Rn );
nkeynes@377
  1422
    MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@377
  1423
:}
nkeynes@377
  1424
FMOV @Rm+, FRn {:  
nkeynes@377
  1425
    check_fpuen();
nkeynes@377
  1426
    load_reg( R_EDX, Rm );
nkeynes@377
  1427
    check_ralign32( R_EDX );
nkeynes@377
  1428
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1429
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1430
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1431
    JNE_rel8(25);
nkeynes@377
  1432
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1433
    store_reg( R_EAX, Rm );
nkeynes@377
  1434
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1435
    load_fr_bank( R_ECX );
nkeynes@377
  1436
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1437
    if( FRn&1 ) {
nkeynes@377
  1438
	JMP_rel8(52);
nkeynes@377
  1439
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1440
	store_reg(R_EAX, Rm);
nkeynes@377
  1441
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1442
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1443
	load_xf_bank( R_ECX );
nkeynes@377
  1444
    } else {
nkeynes@377
  1445
	JMP_rel8(42);
nkeynes@377
  1446
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1447
	store_reg(R_EAX, Rm);
nkeynes@377
  1448
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1449
	load_fr_bank( R_ECX );
nkeynes@377
  1450
    }
nkeynes@377
  1451
    store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@377
  1452
    store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@377
  1453
:}
nkeynes@377
  1454
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1455
    check_fpuen();
nkeynes@377
  1456
    load_reg( R_EDX, Rn );
nkeynes@377
  1457
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1458
    check_walign32( R_EDX );
nkeynes@377
  1459
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1460
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1461
    JNE_rel8(20);
nkeynes@377
  1462
    load_fr_bank( R_ECX );
nkeynes@377
  1463
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1464
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1465
    if( FRm&1 ) {
nkeynes@377
  1466
	JMP_rel8( 46 );
nkeynes@377
  1467
	load_xf_bank( R_ECX );
nkeynes@377
  1468
    } else {
nkeynes@377
  1469
	JMP_rel8( 39 );
nkeynes@377
  1470
	load_fr_bank( R_ECX );
nkeynes@377
  1471
    }
nkeynes@377
  1472
    load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@377
  1473
    load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@377
  1474
    MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@377
  1475
:}
nkeynes@377
  1476
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1477
    check_fpuen();
nkeynes@377
  1478
    load_reg( R_EDX, Rm );
nkeynes@377
  1479
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1480
    check_ralign32( R_EDX );
nkeynes@377
  1481
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1482
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1483
    JNE_rel8(19);
nkeynes@377
  1484
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1485
    load_fr_bank( R_ECX );
nkeynes@377
  1486
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1487
    if( FRn&1 ) {
nkeynes@377
  1488
	JMP_rel8(46);
nkeynes@377
  1489
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1490
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1491
	load_xf_bank( R_ECX );
nkeynes@377
  1492
    } else {
nkeynes@377
  1493
	JMP_rel8(36);
nkeynes@377
  1494
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1495
	load_fr_bank( R_ECX );
nkeynes@377
  1496
    }
nkeynes@377
  1497
    store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@377
  1498
    store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@377
  1499
:}
nkeynes@377
  1500
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1501
    check_fpuen();
nkeynes@377
  1502
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1503
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1504
    JNE_rel8(8);
nkeynes@377
  1505
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1506
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1507
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1508
:}
nkeynes@377
  1509
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1510
    check_fpuen();
nkeynes@377
  1511
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1512
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1513
    JNE_rel8(11);
nkeynes@377
  1514
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1515
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1516
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1517
:}
nkeynes@377
  1518
nkeynes@377
  1519
FLOAT FPUL, FRn {:  
nkeynes@377
  1520
    check_fpuen();
nkeynes@377
  1521
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1522
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1523
    FILD_sh4r(R_FPUL);
nkeynes@377
  1524
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1525
    JNE_rel8(5);
nkeynes@377
  1526
    pop_fr( R_EDX, FRn );
nkeynes@377
  1527
    JMP_rel8(3);
nkeynes@377
  1528
    pop_dr( R_EDX, FRn );
nkeynes@377
  1529
:}
nkeynes@377
  1530
FTRC FRm, FPUL {:  
nkeynes@377
  1531
    check_fpuen();
nkeynes@377
  1532
    // TODO
nkeynes@377
  1533
:}
nkeynes@377
  1534
FLDS FRm, FPUL {:  
nkeynes@377
  1535
    check_fpuen();
nkeynes@377
  1536
    load_fr_bank( R_ECX );
nkeynes@377
  1537
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1538
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1539
:}
nkeynes@377
  1540
FSTS FPUL, FRn {:  
nkeynes@377
  1541
    check_fpuen();
nkeynes@377
  1542
    load_fr_bank( R_ECX );
nkeynes@377
  1543
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1544
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1545
:}
nkeynes@377
  1546
FCNVDS FRm, FPUL {:  
nkeynes@377
  1547
    check_fpuen();
nkeynes@377
  1548
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1549
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1550
    JE_rel8(9); // only when PR=1
nkeynes@377
  1551
    load_fr_bank( R_ECX );
nkeynes@377
  1552
    push_dr( R_ECX, FRm );
nkeynes@377
  1553
    pop_fpul();
nkeynes@377
  1554
:}
nkeynes@377
  1555
FCNVSD FPUL, FRn {:  
nkeynes@377
  1556
    check_fpuen();
nkeynes@377
  1557
    check_fpuen();
nkeynes@377
  1558
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1559
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1560
    JE_rel8(9); // only when PR=1
nkeynes@377
  1561
    load_fr_bank( R_ECX );
nkeynes@377
  1562
    push_fpul();
nkeynes@377
  1563
    pop_dr( R_ECX, FRn );
nkeynes@377
  1564
:}
nkeynes@375
  1565
nkeynes@359
  1566
/* Floating point instructions */
nkeynes@374
  1567
FABS FRn {:  
nkeynes@377
  1568
    check_fpuen();
nkeynes@374
  1569
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1570
    load_fr_bank( R_EDX );
nkeynes@374
  1571
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@374
  1572
    JNE_rel8(10);
nkeynes@374
  1573
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1574
    FABS_st0(); // 2
nkeynes@374
  1575
    pop_fr( R_EDX, FRn); //3
nkeynes@374
  1576
    JMP_rel8(8); // 2
nkeynes@374
  1577
    push_dr(R_EDX, FRn);
nkeynes@374
  1578
    FABS_st0();
nkeynes@374
  1579
    pop_dr(R_EDX, FRn);
nkeynes@374
  1580
:}
nkeynes@377
  1581
FADD FRm, FRn {:  
nkeynes@377
  1582
    check_fpuen();
nkeynes@375
  1583
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1584
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1585
    load_fr_bank( R_EDX );
nkeynes@377
  1586
    JNE_rel8(13);
nkeynes@377
  1587
    push_fr(R_EDX, FRm);
nkeynes@377
  1588
    push_fr(R_EDX, FRn);
nkeynes@377
  1589
    FADDP_st(1);
nkeynes@377
  1590
    pop_fr(R_EDX, FRn);
nkeynes@377
  1591
    JMP_rel8(11);
nkeynes@377
  1592
    push_dr(R_EDX, FRm);
nkeynes@377
  1593
    push_dr(R_EDX, FRn);
nkeynes@377
  1594
    FADDP_st(1);
nkeynes@377
  1595
    pop_dr(R_EDX, FRn);
nkeynes@375
  1596
:}
nkeynes@377
  1597
FDIV FRm, FRn {:  
nkeynes@377
  1598
    check_fpuen();
nkeynes@375
  1599
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1600
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1601
    load_fr_bank( R_EDX );
nkeynes@377
  1602
    JNE_rel8(13);
nkeynes@377
  1603
    push_fr(R_EDX, FRn);
nkeynes@377
  1604
    push_fr(R_EDX, FRm);
nkeynes@377
  1605
    FDIVP_st(1);
nkeynes@377
  1606
    pop_fr(R_EDX, FRn);
nkeynes@377
  1607
    JMP_rel8(11);
nkeynes@377
  1608
    push_dr(R_EDX, FRn);
nkeynes@377
  1609
    push_dr(R_EDX, FRm);
nkeynes@377
  1610
    FDIVP_st(1);
nkeynes@377
  1611
    pop_dr(R_EDX, FRn);
nkeynes@375
  1612
:}
nkeynes@375
  1613
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1614
    check_fpuen();
nkeynes@375
  1615
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1616
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1617
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@375
  1618
    JNE_rel8(18);
nkeynes@375
  1619
    push_fr( R_EDX, 0 );
nkeynes@375
  1620
    push_fr( R_EDX, FRm );
nkeynes@375
  1621
    FMULP_st(1);
nkeynes@375
  1622
    push_fr( R_EDX, FRn );
nkeynes@375
  1623
    FADDP_st(1);
nkeynes@375
  1624
    pop_fr( R_EDX, FRn );
nkeynes@375
  1625
    JMP_rel8(16);
nkeynes@375
  1626
    push_dr( R_EDX, 0 );
nkeynes@375
  1627
    push_dr( R_EDX, FRm );
nkeynes@375
  1628
    FMULP_st(1);
nkeynes@375
  1629
    push_dr( R_EDX, FRn );
nkeynes@375
  1630
    FADDP_st(1);
nkeynes@375
  1631
    pop_dr( R_EDX, FRn );
nkeynes@375
  1632
:}
nkeynes@375
  1633
nkeynes@377
  1634
FMUL FRm, FRn {:  
nkeynes@377
  1635
    check_fpuen();
nkeynes@377
  1636
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1637
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1638
    load_fr_bank( R_EDX );
nkeynes@377
  1639
    JNE_rel8(13);
nkeynes@377
  1640
    push_fr(R_EDX, FRm);
nkeynes@377
  1641
    push_fr(R_EDX, FRn);
nkeynes@377
  1642
    FMULP_st(1);
nkeynes@377
  1643
    pop_fr(R_EDX, FRn);
nkeynes@377
  1644
    JMP_rel8(11);
nkeynes@377
  1645
    push_dr(R_EDX, FRm);
nkeynes@377
  1646
    push_dr(R_EDX, FRn);
nkeynes@377
  1647
    FMULP_st(1);
nkeynes@377
  1648
    pop_dr(R_EDX, FRn);
nkeynes@377
  1649
:}
nkeynes@377
  1650
FNEG FRn {:  
nkeynes@377
  1651
    check_fpuen();
nkeynes@377
  1652
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1653
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1654
    load_fr_bank( R_EDX );
nkeynes@377
  1655
    JNE_rel8(10);
nkeynes@377
  1656
    push_fr(R_EDX, FRn);
nkeynes@377
  1657
    FCHS_st0();
nkeynes@377
  1658
    pop_fr(R_EDX, FRn);
nkeynes@377
  1659
    JMP_rel8(8);
nkeynes@377
  1660
    push_dr(R_EDX, FRn);
nkeynes@377
  1661
    FCHS_st0();
nkeynes@377
  1662
    pop_dr(R_EDX, FRn);
nkeynes@377
  1663
:}
nkeynes@377
  1664
FSRRA FRn {:  
nkeynes@377
  1665
    check_fpuen();
nkeynes@377
  1666
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1667
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1668
    load_fr_bank( R_EDX );
nkeynes@377
  1669
    JNE_rel8(12); // PR=0 only
nkeynes@377
  1670
    FLD1_st0();
nkeynes@377
  1671
    push_fr(R_EDX, FRn);
nkeynes@377
  1672
    FSQRT_st0();
nkeynes@377
  1673
    FDIVP_st(1);
nkeynes@377
  1674
    pop_fr(R_EDX, FRn);
nkeynes@377
  1675
:}
nkeynes@377
  1676
FSQRT FRn {:  
nkeynes@377
  1677
    check_fpuen();
nkeynes@377
  1678
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1679
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1680
    load_fr_bank( R_EDX );
nkeynes@377
  1681
    JNE_rel8(10);
nkeynes@377
  1682
    push_fr(R_EDX, FRn);
nkeynes@377
  1683
    FSQRT_st0();
nkeynes@377
  1684
    pop_fr(R_EDX, FRn);
nkeynes@377
  1685
    JMP_rel8(8);
nkeynes@377
  1686
    push_dr(R_EDX, FRn);
nkeynes@377
  1687
    FSQRT_st0();
nkeynes@377
  1688
    pop_dr(R_EDX, FRn);
nkeynes@377
  1689
:}
nkeynes@377
  1690
FSUB FRm, FRn {:  
nkeynes@377
  1691
    check_fpuen();
nkeynes@377
  1692
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1693
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1694
    load_fr_bank( R_EDX );
nkeynes@377
  1695
    JNE_rel8(13);
nkeynes@377
  1696
    push_fr(R_EDX, FRn);
nkeynes@377
  1697
    push_fr(R_EDX, FRm);
nkeynes@377
  1698
    FMULP_st(1);
nkeynes@377
  1699
    pop_fr(R_EDX, FRn);
nkeynes@377
  1700
    JMP_rel8(11);
nkeynes@377
  1701
    push_dr(R_EDX, FRn);
nkeynes@377
  1702
    push_dr(R_EDX, FRm);
nkeynes@377
  1703
    FMULP_st(1);
nkeynes@377
  1704
    pop_dr(R_EDX, FRn);
nkeynes@377
  1705
:}
nkeynes@377
  1706
nkeynes@377
  1707
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1708
    check_fpuen();
nkeynes@377
  1709
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1710
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1711
    load_fr_bank( R_EDX );
nkeynes@377
  1712
    JNE_rel8(8);
nkeynes@377
  1713
    push_fr(R_EDX, FRm);
nkeynes@377
  1714
    push_fr(R_EDX, FRn);
nkeynes@377
  1715
    JMP_rel8(6);
nkeynes@377
  1716
    push_dr(R_EDX, FRm);
nkeynes@377
  1717
    push_dr(R_EDX, FRn);
nkeynes@377
  1718
    FCOMIP_st(1);
nkeynes@377
  1719
    SETE_t();
nkeynes@377
  1720
    FPOP_st();
nkeynes@377
  1721
:}
nkeynes@377
  1722
FCMP/GT FRm, FRn {:  
nkeynes@377
  1723
    check_fpuen();
nkeynes@377
  1724
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1725
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1726
    load_fr_bank( R_EDX );
nkeynes@377
  1727
    JNE_rel8(8);
nkeynes@377
  1728
    push_fr(R_EDX, FRm);
nkeynes@377
  1729
    push_fr(R_EDX, FRn);
nkeynes@377
  1730
    JMP_rel8(6);
nkeynes@377
  1731
    push_dr(R_EDX, FRm);
nkeynes@377
  1732
    push_dr(R_EDX, FRn);
nkeynes@377
  1733
    FCOMIP_st(1);
nkeynes@377
  1734
    SETA_t();
nkeynes@377
  1735
    FPOP_st();
nkeynes@377
  1736
:}
nkeynes@377
  1737
nkeynes@377
  1738
FSCA FPUL, FRn {:  
nkeynes@377
  1739
    check_fpuen();
nkeynes@377
  1740
:}
nkeynes@377
  1741
FIPR FVm, FVn {:  
nkeynes@377
  1742
    check_fpuen();
nkeynes@377
  1743
:}
nkeynes@377
  1744
FTRV XMTRX, FVn {:  
nkeynes@377
  1745
    check_fpuen();
nkeynes@377
  1746
:}
nkeynes@377
  1747
nkeynes@377
  1748
FRCHG {:  
nkeynes@377
  1749
    check_fpuen();
nkeynes@377
  1750
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1751
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  1752
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1753
    
nkeynes@377
  1754
:}
nkeynes@377
  1755
FSCHG {:  
nkeynes@377
  1756
    check_fpuen();
nkeynes@377
  1757
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1758
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1759
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1760
:}
nkeynes@359
  1761
nkeynes@359
  1762
/* Processor control instructions */
nkeynes@368
  1763
LDC Rm, SR {:
nkeynes@368
  1764
    load_reg( R_EAX, Rm );
nkeynes@374
  1765
    call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1766
    sh4_x86.priv_checked = FALSE;
nkeynes@377
  1767
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
  1768
:}
nkeynes@359
  1769
LDC Rm, GBR {: 
nkeynes@359
  1770
    load_reg( R_EAX, Rm );
nkeynes@359
  1771
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1772
:}
nkeynes@359
  1773
LDC Rm, VBR {:  
nkeynes@359
  1774
    load_reg( R_EAX, Rm );
nkeynes@359
  1775
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1776
:}
nkeynes@359
  1777
LDC Rm, SSR {:  
nkeynes@359
  1778
    load_reg( R_EAX, Rm );
nkeynes@359
  1779
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1780
:}
nkeynes@359
  1781
LDC Rm, SGR {:  
nkeynes@359
  1782
    load_reg( R_EAX, Rm );
nkeynes@359
  1783
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1784
:}
nkeynes@359
  1785
LDC Rm, SPC {:  
nkeynes@359
  1786
    load_reg( R_EAX, Rm );
nkeynes@359
  1787
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1788
:}
nkeynes@359
  1789
LDC Rm, DBR {:  
nkeynes@359
  1790
    load_reg( R_EAX, Rm );
nkeynes@359
  1791
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1792
:}
nkeynes@374
  1793
LDC Rm, Rn_BANK {:  
nkeynes@374
  1794
    load_reg( R_EAX, Rm );
nkeynes@374
  1795
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  1796
:}
nkeynes@359
  1797
LDC.L @Rm+, GBR {:  
nkeynes@359
  1798
    load_reg( R_EAX, Rm );
nkeynes@359
  1799
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1800
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1801
    store_reg( R_EAX, Rm );
nkeynes@359
  1802
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1803
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1804
:}
nkeynes@368
  1805
LDC.L @Rm+, SR {:
nkeynes@368
  1806
    load_reg( R_EAX, Rm );
nkeynes@368
  1807
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1808
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1809
    store_reg( R_EAX, Rm );
nkeynes@368
  1810
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1811
    call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1812
    sh4_x86.priv_checked = FALSE;
nkeynes@377
  1813
    sh4_x86.fpuen_checked = FALSE;
nkeynes@359
  1814
:}
nkeynes@359
  1815
LDC.L @Rm+, VBR {:  
nkeynes@359
  1816
    load_reg( R_EAX, Rm );
nkeynes@359
  1817
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1818
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1819
    store_reg( R_EAX, Rm );
nkeynes@359
  1820
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1821
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1822
:}
nkeynes@359
  1823
LDC.L @Rm+, SSR {:
nkeynes@359
  1824
    load_reg( R_EAX, Rm );
nkeynes@359
  1825
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1826
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1827
    store_reg( R_EAX, Rm );
nkeynes@359
  1828
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1829
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1830
:}
nkeynes@359
  1831
LDC.L @Rm+, SGR {:  
nkeynes@359
  1832
    load_reg( R_EAX, Rm );
nkeynes@359
  1833
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1834
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1835
    store_reg( R_EAX, Rm );
nkeynes@359
  1836
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1837
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1838
:}
nkeynes@359
  1839
LDC.L @Rm+, SPC {:  
nkeynes@359
  1840
    load_reg( R_EAX, Rm );
nkeynes@359
  1841
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1842
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1843
    store_reg( R_EAX, Rm );
nkeynes@359
  1844
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1845
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1846
:}
nkeynes@359
  1847
LDC.L @Rm+, DBR {:  
nkeynes@359
  1848
    load_reg( R_EAX, Rm );
nkeynes@359
  1849
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1850
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1851
    store_reg( R_EAX, Rm );
nkeynes@359
  1852
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1853
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1854
:}
nkeynes@359
  1855
LDC.L @Rm+, Rn_BANK {:  
nkeynes@374
  1856
    load_reg( R_EAX, Rm );
nkeynes@374
  1857
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1858
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1859
    store_reg( R_EAX, Rm );
nkeynes@374
  1860
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1861
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1862
:}
nkeynes@359
  1863
LDS Rm, FPSCR {:  
nkeynes@359
  1864
    load_reg( R_EAX, Rm );
nkeynes@359
  1865
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1866
:}
nkeynes@359
  1867
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  1868
    load_reg( R_EAX, Rm );
nkeynes@359
  1869
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1870
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1871
    store_reg( R_EAX, Rm );
nkeynes@359
  1872
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1873
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1874
:}
nkeynes@359
  1875
LDS Rm, FPUL {:  
nkeynes@359
  1876
    load_reg( R_EAX, Rm );
nkeynes@359
  1877
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1878
:}
nkeynes@359
  1879
LDS.L @Rm+, FPUL {:  
nkeynes@359
  1880
    load_reg( R_EAX, Rm );
nkeynes@359
  1881
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1882
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1883
    store_reg( R_EAX, Rm );
nkeynes@359
  1884
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1885
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1886
:}
nkeynes@359
  1887
LDS Rm, MACH {: 
nkeynes@359
  1888
    load_reg( R_EAX, Rm );
nkeynes@359
  1889
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1890
:}
nkeynes@359
  1891
LDS.L @Rm+, MACH {:  
nkeynes@359
  1892
    load_reg( R_EAX, Rm );
nkeynes@359
  1893
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1894
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1895
    store_reg( R_EAX, Rm );
nkeynes@359
  1896
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1897
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1898
:}
nkeynes@359
  1899
LDS Rm, MACL {:  
nkeynes@359
  1900
    load_reg( R_EAX, Rm );
nkeynes@359
  1901
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1902
:}
nkeynes@359
  1903
LDS.L @Rm+, MACL {:  
nkeynes@359
  1904
    load_reg( R_EAX, Rm );
nkeynes@359
  1905
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1906
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1907
    store_reg( R_EAX, Rm );
nkeynes@359
  1908
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1909
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1910
:}
nkeynes@359
  1911
LDS Rm, PR {:  
nkeynes@359
  1912
    load_reg( R_EAX, Rm );
nkeynes@359
  1913
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1914
:}
nkeynes@359
  1915
LDS.L @Rm+, PR {:  
nkeynes@359
  1916
    load_reg( R_EAX, Rm );
nkeynes@359
  1917
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1918
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1919
    store_reg( R_EAX, Rm );
nkeynes@359
  1920
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1921
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1922
:}
nkeynes@359
  1923
LDTLB {:  :}
nkeynes@359
  1924
OCBI @Rn {:  :}
nkeynes@359
  1925
OCBP @Rn {:  :}
nkeynes@359
  1926
OCBWB @Rn {:  :}
nkeynes@374
  1927
PREF @Rn {:
nkeynes@374
  1928
    load_reg( R_EAX, Rn );
nkeynes@374
  1929
    PUSH_r32( R_EAX );
nkeynes@374
  1930
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  1931
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@374
  1932
    JNE_rel8(8);
nkeynes@374
  1933
    call_func0( sh4_flush_store_queue );
nkeynes@377
  1934
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  1935
:}
nkeynes@374
  1936
 SLEEP {: /* TODO */ :}
nkeynes@368
  1937
 STC SR, Rn {:
nkeynes@374
  1938
     call_func0(sh4_read_sr);
nkeynes@368
  1939
     store_reg( R_EAX, Rn );
nkeynes@359
  1940
:}
nkeynes@359
  1941
STC GBR, Rn {:  
nkeynes@359
  1942
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  1943
    store_reg( R_EAX, Rn );
nkeynes@359
  1944
:}
nkeynes@359
  1945
STC VBR, Rn {:  
nkeynes@359
  1946
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  1947
    store_reg( R_EAX, Rn );
nkeynes@359
  1948
:}
nkeynes@359
  1949
STC SSR, Rn {:  
nkeynes@359
  1950
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  1951
    store_reg( R_EAX, Rn );
nkeynes@359
  1952
:}
nkeynes@359
  1953
STC SPC, Rn {:  
nkeynes@359
  1954
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  1955
    store_reg( R_EAX, Rn );
nkeynes@359
  1956
:}
nkeynes@359
  1957
STC SGR, Rn {:  
nkeynes@359
  1958
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  1959
    store_reg( R_EAX, Rn );
nkeynes@359
  1960
:}
nkeynes@359
  1961
STC DBR, Rn {:  
nkeynes@359
  1962
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  1963
    store_reg( R_EAX, Rn );
nkeynes@359
  1964
:}
nkeynes@374
  1965
STC Rm_BANK, Rn {:
nkeynes@374
  1966
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  1967
    store_reg( R_EAX, Rn );
nkeynes@359
  1968
:}
nkeynes@374
  1969
STC.L SR, @-Rn {:
nkeynes@368
  1970
    load_reg( R_ECX, Rn );
nkeynes@368
  1971
    ADD_imm8s_r32( -4, Rn );
nkeynes@368
  1972
    store_reg( R_ECX, Rn );
nkeynes@374
  1973
    call_func0( sh4_read_sr );
nkeynes@368
  1974
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1975
:}
nkeynes@359
  1976
STC.L VBR, @-Rn {:  
nkeynes@359
  1977
    load_reg( R_ECX, Rn );
nkeynes@359
  1978
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1979
    store_reg( R_ECX, Rn );
nkeynes@359
  1980
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  1981
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1982
:}
nkeynes@359
  1983
STC.L SSR, @-Rn {:  
nkeynes@359
  1984
    load_reg( R_ECX, Rn );
nkeynes@359
  1985
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1986
    store_reg( R_ECX, Rn );
nkeynes@359
  1987
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  1988
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1989
:}
nkeynes@359
  1990
STC.L SPC, @-Rn {:  
nkeynes@359
  1991
    load_reg( R_ECX, Rn );
nkeynes@359
  1992
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  1993
    store_reg( R_ECX, Rn );
nkeynes@359
  1994
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  1995
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1996
:}
nkeynes@359
  1997
STC.L SGR, @-Rn {:  
nkeynes@359
  1998
    load_reg( R_ECX, Rn );
nkeynes@359
  1999
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2000
    store_reg( R_ECX, Rn );
nkeynes@359
  2001
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2002
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2003
:}
nkeynes@359
  2004
STC.L DBR, @-Rn {:  
nkeynes@359
  2005
    load_reg( R_ECX, Rn );
nkeynes@359
  2006
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2007
    store_reg( R_ECX, Rn );
nkeynes@359
  2008
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2009
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2010
:}
nkeynes@374
  2011
STC.L Rm_BANK, @-Rn {:  
nkeynes@374
  2012
    load_reg( R_ECX, Rn );
nkeynes@374
  2013
    ADD_imm8s_r32( -4, Rn );
nkeynes@374
  2014
    store_reg( R_ECX, Rn );
nkeynes@374
  2015
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2016
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2017
:}
nkeynes@359
  2018
STC.L GBR, @-Rn {:  
nkeynes@359
  2019
    load_reg( R_ECX, Rn );
nkeynes@359
  2020
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2021
    store_reg( R_ECX, Rn );
nkeynes@359
  2022
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2023
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2024
:}
nkeynes@359
  2025
STS FPSCR, Rn {:  
nkeynes@359
  2026
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2027
    store_reg( R_EAX, Rn );
nkeynes@359
  2028
:}
nkeynes@359
  2029
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2030
    load_reg( R_ECX, Rn );
nkeynes@359
  2031
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2032
    store_reg( R_ECX, Rn );
nkeynes@359
  2033
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2034
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2035
:}
nkeynes@359
  2036
STS FPUL, Rn {:  
nkeynes@359
  2037
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2038
    store_reg( R_EAX, Rn );
nkeynes@359
  2039
:}
nkeynes@359
  2040
STS.L FPUL, @-Rn {:  
nkeynes@359
  2041
    load_reg( R_ECX, Rn );
nkeynes@359
  2042
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2043
    store_reg( R_ECX, Rn );
nkeynes@359
  2044
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2045
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2046
:}
nkeynes@359
  2047
STS MACH, Rn {:  
nkeynes@359
  2048
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2049
    store_reg( R_EAX, Rn );
nkeynes@359
  2050
:}
nkeynes@359
  2051
STS.L MACH, @-Rn {:  
nkeynes@359
  2052
    load_reg( R_ECX, Rn );
nkeynes@359
  2053
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2054
    store_reg( R_ECX, Rn );
nkeynes@359
  2055
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2056
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2057
:}
nkeynes@359
  2058
STS MACL, Rn {:  
nkeynes@359
  2059
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2060
    store_reg( R_EAX, Rn );
nkeynes@359
  2061
:}
nkeynes@359
  2062
STS.L MACL, @-Rn {:  
nkeynes@359
  2063
    load_reg( R_ECX, Rn );
nkeynes@359
  2064
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2065
    store_reg( R_ECX, Rn );
nkeynes@359
  2066
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2067
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2068
:}
nkeynes@359
  2069
STS PR, Rn {:  
nkeynes@359
  2070
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2071
    store_reg( R_EAX, Rn );
nkeynes@359
  2072
:}
nkeynes@359
  2073
STS.L PR, @-Rn {:  
nkeynes@359
  2074
    load_reg( R_ECX, Rn );
nkeynes@359
  2075
    ADD_imm8s_r32( -4, Rn );
nkeynes@359
  2076
    store_reg( R_ECX, Rn );
nkeynes@359
  2077
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2078
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2079
:}
nkeynes@359
  2080
nkeynes@359
  2081
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2082
%%
nkeynes@368
  2083
    INC_r32(R_ESI);
nkeynes@374
  2084
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2085
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2086
	return 1;
nkeynes@374
  2087
    }
nkeynes@359
  2088
    return 0;
nkeynes@359
  2089
}
.