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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 335:fb890e1814c0
prev304:2855cf8709a5
next337:cdd757aa8e8c
author nkeynes
date Sat Jan 27 12:03:53 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Start working towards more thorough interlaced support
file annotate diff log raw
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/**
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 * $Id: pvr2.c,v 1.42 2007-01-27 12:03:53 nkeynes Exp $
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "sh4/sh4core.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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char *video_base;
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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					pvr2_run_slice, NULL,
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					pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct video_timing {
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    int fields_per_second;
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    int total_lines;
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    int retrace_lines;
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    int line_time_ns;
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};
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struct video_timing pal_timing = { 50, 625, 65, 31945 };
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struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    gchar *save_next_render_filename;
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    gboolean interlaced;
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    struct video_timing timing;
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} pvr2_state;
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struct video_buffer video_buffer[2];
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int video_buffer_idx = 0;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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	}
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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				  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_init( void )
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{
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    pvr2_state.save_next_render_filename = NULL;
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}
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static void pvr2_reset( void )
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{
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.timing = ntsc_timing;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    video_buffer_idx = 0;
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    pvr2_ta_init();
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    pvr2_render_init();
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    texcache_flush();
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}
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static void pvr2_save_state( FILE *f )
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{
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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static int pvr2_load_state( FILE *f )
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{
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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	return 1;
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    if( pvr2_ta_load_state(f) ) {
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	return 1;
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    }
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    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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	return; /* do nothing */
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    }
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    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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	pvr2_state.line_count ++;
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	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
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    }
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    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
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	pvr2_state.line_count -= pvr2_state.total_lines;
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	if( pvr2_state.interlaced ) {
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	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
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	}
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    }
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    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
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	(old_line_count < pvr2_state.retrace_end_line ||
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	 old_line_count > pvr2_state.line_count) ) {
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	pvr2_display_frame();
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    }
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}
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static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
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{
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    pvr2_update_raster_posn( nanosecs );
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    pvr2_state.cycles_run = 0;
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    return nanosecs;
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}
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int pvr2_get_frame_count() 
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{
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    return pvr2_state.frame_count;
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}
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gboolean pvr2_save_next_scene( const gchar *filename )
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{
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    if( pvr2_state.save_next_render_filename != NULL ) {
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	g_free( pvr2_state.save_next_render_filename );
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    } 
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    pvr2_state.save_next_render_filename = g_strdup(filename);
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    return TRUE;
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}
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/**
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 * Display the next frame, copying the current contents of video ram to
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 * the window. If the video configuration has changed, first recompute the
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 * new frame size/depth.
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 */
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void pvr2_display_frame( void )
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{
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    uint32_t display_addr;
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    int dispsize = MMIO_READ( PVR2, DISP_SIZE );
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    int dispmode = MMIO_READ( PVR2, DISP_MODE );
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    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
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    int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
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    int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
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    int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
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    gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
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    gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
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    video_buffer_t buffer = &video_buffer[video_buffer_idx];
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    video_buffer_idx = !video_buffer_idx;
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    video_buffer_t last = &video_buffer[video_buffer_idx];
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    buffer->rowstride = (vid_ppl + vid_stride) << 2;
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    buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
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    buffer->line_double = (dispmode & DISPMODE_LINEDOUBLE) ? TRUE : FALSE;
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    buffer->vres = vid_lpf;
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    if( interlaced ) {
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	if( vid_ppl == vid_stride ) { /* Magic deinterlace */
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	    buffer->vres <<= 1;
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	    buffer->rowstride = vid_ppl << 2;
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	    display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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	} else { /* Just display the field as is, folks */
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	    if( pvr2_state.odd_even_field ) {
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		display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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	    } else {
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		display_addr = MMIO_READ( PVR2, DISP_ADDR2 );
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	    }
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	}
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    } else {
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	display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
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    }
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   272
    switch( (dispmode & DISPMODE_COLFMT) >> 2 ) {
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    case 0: 
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   274
	buffer->colour_format = COLFMT_ARGB1555;
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   275
	buffer->hres = vid_ppl << 1; 
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   276
	break;
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    case 1: 
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	buffer->colour_format = COLFMT_RGB565;
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   279
	buffer->hres = vid_ppl << 1; 
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   280
	break;
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   281
    case 2:
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	buffer->colour_format = COLFMT_RGB888;
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	buffer->hres = (vid_ppl << 2) / 3; 
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   284
	break;
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   285
    case 3: 
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   286
	buffer->colour_format = COLFMT_ARGB8888;
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   287
	buffer->hres = vid_ppl; 
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   288
	break;
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   289
    }
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   290
	
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   291
    if( buffer->hres <=8 )
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   292
	buffer->hres = 640;
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   293
    if( buffer->vres <=8 )
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   294
	buffer->vres = 480;
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   295
    if( display_driver != NULL ) {
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   296
	if( buffer->hres != last->hres ||
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   297
	    buffer->vres != last->vres ||
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   298
	    buffer->colour_format != last->colour_format) {
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   299
	    display_driver->set_display_format( buffer->hres, buffer->vres,
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   300
						buffer->colour_format );
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	}
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   302
	if( !bEnabled ) {
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   303
	    display_driver->display_blank_frame( 0 );
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   304
	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
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   305
	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
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   306
	    display_driver->display_blank_frame( colour );
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   307
	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
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   308
	    display_driver->display_frame( buffer );
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   309
	}
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   310
    }
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   311
    pvr2_state.frame_count++;
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   312
}
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   313
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   314
/**
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 * This has to handle every single register individually as they all get masked 
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 * off differently (and its easier to do it at write time)
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   317
 */
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   318
void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
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   319
{
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   320
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   321
        MMIO_WRITE( PVR2, reg, val );
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   322
        return;
nkeynes@1
   323
    }
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   324
    
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   325
    switch(reg) {
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   326
    case PVRID:
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   327
    case PVRVER:
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   328
    case GUNPOS: /* Read only registers */
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   329
	break;
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   330
    case PVRRESET:
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   331
	val &= 0x00000007; /* Do stuff? */
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   332
	MMIO_WRITE( PVR2, reg, val );
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   333
	break;
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   334
    case RENDER_START: /* Don't really care what value */
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   335
	if( pvr2_state.save_next_render_filename != NULL ) {
nkeynes@295
   336
	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
nkeynes@295
   337
		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
nkeynes@295
   338
	    }
nkeynes@295
   339
	    g_free( pvr2_state.save_next_render_filename );
nkeynes@295
   340
	    pvr2_state.save_next_render_filename = NULL;
nkeynes@295
   341
	}
nkeynes@295
   342
	pvr2_render_scene();
nkeynes@189
   343
	break;
nkeynes@191
   344
    case RENDER_POLYBASE:
nkeynes@191
   345
    	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@191
   346
    	break;
nkeynes@191
   347
    case RENDER_TSPCFG:
nkeynes@191
   348
    	MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@191
   349
    	break;
nkeynes@197
   350
    case DISP_BORDER:
nkeynes@191
   351
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@191
   352
    	break;
nkeynes@197
   353
    case DISP_MODE:
nkeynes@191
   354
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@191
   355
    	break;
nkeynes@191
   356
    case RENDER_MODE:
nkeynes@191
   357
    	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@191
   358
    	break;
nkeynes@191
   359
    case RENDER_SIZE:
nkeynes@191
   360
    	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   361
    	break;
nkeynes@197
   362
    case DISP_ADDR1:
nkeynes@189
   363
	val &= 0x00FFFFFC;
nkeynes@189
   364
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   365
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   366
	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||
nkeynes@265
   367
	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {
nkeynes@108
   368
	    pvr2_display_frame();
nkeynes@108
   369
	}
nkeynes@108
   370
	break;
nkeynes@197
   371
    case DISP_ADDR2:
nkeynes@191
   372
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@191
   373
    	break;
nkeynes@197
   374
    case DISP_SIZE:
nkeynes@191
   375
    	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@191
   376
    	break;
nkeynes@191
   377
    case RENDER_ADDR1:
nkeynes@191
   378
    case RENDER_ADDR2:
nkeynes@191
   379
    	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@191
   380
    	break;
nkeynes@191
   381
    case RENDER_HCLIP:
nkeynes@191
   382
	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@189
   383
	break;
nkeynes@191
   384
    case RENDER_VCLIP:
nkeynes@191
   385
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@189
   386
	break;
nkeynes@197
   387
    case DISP_HPOSIRQ:
nkeynes@191
   388
	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@304
   389
	pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@304
   390
	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@304
   391
	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@304
   392
	switch( pvr2_state.irq_hpos_mode ) {
nkeynes@304
   393
	case 3: /* Reserved - treat as 0 */
nkeynes@304
   394
	case 0: /* Once per frame at specified line */
nkeynes@304
   395
	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@304
   396
	    break;
nkeynes@304
   397
	case 2: /* Once per line - as per-line-count */
nkeynes@304
   398
	    pvr2_state.irq_hpos_line = 1;
nkeynes@304
   399
	    pvr2_state.irq_hpos_mode = 1;
nkeynes@304
   400
	case 1: /* Once per N lines */
nkeynes@304
   401
	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@304
   402
	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@304
   403
		pvr2_state.irq_hpos_line_count;
nkeynes@304
   404
	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@304
   405
		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@304
   406
	    }
nkeynes@304
   407
	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@304
   408
	}
nkeynes@304
   409
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@304
   410
					  pvr2_state.irq_hpos_time_ns );
nkeynes@189
   411
	break;
nkeynes@197
   412
    case DISP_VPOSIRQ:
nkeynes@189
   413
	val = val & 0x03FF03FF;
nkeynes@189
   414
	pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@133
   415
	pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@265
   416
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@304
   417
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   418
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@189
   419
	MMIO_WRITE( PVR2, reg, val );
nkeynes@103
   420
	break;
nkeynes@197
   421
    case RENDER_NEARCLIP:
nkeynes@197
   422
	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@197
   423
	break;
nkeynes@191
   424
    case RENDER_SHADOW:
nkeynes@191
   425
	MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@191
   426
	break;
nkeynes@191
   427
    case RENDER_OBJCFG:
nkeynes@191
   428
    	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@191
   429
    	break;
nkeynes@191
   430
    case RENDER_TSPCLIP:
nkeynes@191
   431
    	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@191
   432
    	break;
nkeynes@197
   433
    case RENDER_FARCLIP:
nkeynes@197
   434
	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@197
   435
	break;
nkeynes@191
   436
    case RENDER_BGPLANE:
nkeynes@191
   437
    	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@191
   438
    	break;
nkeynes@191
   439
    case RENDER_ISPCFG:
nkeynes@191
   440
    	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@191
   441
    	break;
nkeynes@197
   442
    case VRAM_CFG1:
nkeynes@197
   443
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   444
	break;
nkeynes@197
   445
    case VRAM_CFG2:
nkeynes@197
   446
	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@197
   447
	break;
nkeynes@197
   448
    case VRAM_CFG3:
nkeynes@197
   449
	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@197
   450
	break;
nkeynes@197
   451
    case RENDER_FOGTBLCOL:
nkeynes@197
   452
    case RENDER_FOGVRTCOL:
nkeynes@197
   453
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@197
   454
	break;
nkeynes@197
   455
    case RENDER_FOGCOEFF:
nkeynes@197
   456
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@197
   457
	break;
nkeynes@197
   458
    case RENDER_CLAMPHI:
nkeynes@197
   459
    case RENDER_CLAMPLO:
nkeynes@197
   460
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   461
	break;
nkeynes@261
   462
    case RENDER_TEXSIZE:
nkeynes@261
   463
	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@197
   464
	break;
nkeynes@261
   465
    case RENDER_PALETTE:
nkeynes@261
   466
	MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@261
   467
	break;
nkeynes@261
   468
nkeynes@261
   469
	/********** CRTC registers *************/
nkeynes@197
   470
    case DISP_HBORDER:
nkeynes@197
   471
    case DISP_VBORDER:
nkeynes@197
   472
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   473
	break;
nkeynes@261
   474
    case DISP_TOTAL:
nkeynes@261
   475
	val = val & 0x03FF03FF;
nkeynes@261
   476
	MMIO_WRITE( PVR2, reg, val );
nkeynes@265
   477
	pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@261
   478
	pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@261
   479
	pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@261
   480
	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@265
   481
	pvr2_state.retrace_end_line = 0x2A;
nkeynes@265
   482
	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@304
   483
	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@304
   484
	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@304
   485
	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@304
   486
					  pvr2_state.irq_hpos_time_ns );
nkeynes@261
   487
	break;
nkeynes@261
   488
    case DISP_SYNCCFG:
nkeynes@261
   489
	MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@261
   490
	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@261
   491
	break;
nkeynes@261
   492
    case DISP_SYNCTIME:
nkeynes@261
   493
	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@269
   494
	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@197
   495
	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@197
   496
	break;
nkeynes@197
   497
    case DISP_CFG2:
nkeynes@197
   498
	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@197
   499
	break;
nkeynes@197
   500
    case DISP_HPOS:
nkeynes@261
   501
	val = val & 0x03FF;
nkeynes@261
   502
	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@261
   503
	MMIO_WRITE( PVR2, reg, val );
nkeynes@197
   504
	break;
nkeynes@197
   505
    case DISP_VPOS:
nkeynes@197
   506
	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@197
   507
	break;
nkeynes@261
   508
nkeynes@261
   509
	/*********** Tile accelerator registers ***********/
nkeynes@261
   510
    case TA_POLYPOS:
nkeynes@261
   511
    case TA_LISTPOS:
nkeynes@261
   512
	/* Readonly registers */
nkeynes@197
   513
	break;
nkeynes@189
   514
    case TA_TILEBASE:
nkeynes@193
   515
    case TA_LISTEND:
nkeynes@189
   516
    case TA_LISTBASE:
nkeynes@191
   517
	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@189
   518
	break;
nkeynes@191
   519
    case RENDER_TILEBASE:
nkeynes@189
   520
    case TA_POLYBASE:
nkeynes@189
   521
    case TA_POLYEND:
nkeynes@191
   522
	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@189
   523
	break;
nkeynes@189
   524
    case TA_TILESIZE:
nkeynes@191
   525
	MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@189
   526
	break;
nkeynes@189
   527
    case TA_TILECFG:
nkeynes@191
   528
	MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@189
   529
	break;
nkeynes@261
   530
    case TA_INIT:
nkeynes@261
   531
	if( val & 0x80000000 )
nkeynes@261
   532
	    pvr2_ta_init();
nkeynes@261
   533
	break;
nkeynes@261
   534
    case TA_REINIT:
nkeynes@261
   535
	break;
nkeynes@261
   536
	/**************** Scaler registers? ****************/
nkeynes@335
   537
    case RENDER_SCALER:
nkeynes@261
   538
	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@261
   539
	break;
nkeynes@261
   540
nkeynes@197
   541
    case YUV_ADDR:
nkeynes@284
   542
	val = val & 0x00FFFFF8;
nkeynes@284
   543
	MMIO_WRITE( PVR2, reg, val );
nkeynes@284
   544
	pvr2_yuv_init( val );
nkeynes@197
   545
	break;
nkeynes@197
   546
    case YUV_CFG:
nkeynes@197
   547
	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@284
   548
	pvr2_yuv_set_config(val);
nkeynes@197
   549
	break;
nkeynes@261
   550
nkeynes@261
   551
	/**************** Unknowns ***************/
nkeynes@261
   552
    case PVRUNK1:
nkeynes@261
   553
    	MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@261
   554
    	break;
nkeynes@261
   555
    case PVRUNK2:
nkeynes@261
   556
	MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@100
   557
	break;
nkeynes@261
   558
    case PVRUNK3:
nkeynes@261
   559
	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@261
   560
	break;
nkeynes@261
   561
    case PVRUNK5:
nkeynes@261
   562
	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@261
   563
	break;
nkeynes@261
   564
    case PVRUNK6:
nkeynes@261
   565
	MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@197
   566
	break;
nkeynes@197
   567
    case PVRUNK7:
nkeynes@197
   568
	MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@197
   569
	break;
nkeynes@1
   570
    }
nkeynes@1
   571
}
nkeynes@1
   572
nkeynes@261
   573
/**
nkeynes@261
   574
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   575
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   576
 * The register reads (LSB to MSB) as:
nkeynes@261
   577
 *     0..9  Current scan line
nkeynes@261
   578
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   579
 *     11    Display active (including border and overscan)
nkeynes@261
   580
 *     12    Horizontal sync off
nkeynes@261
   581
 *     13    Vertical sync off
nkeynes@261
   582
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   583
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   584
 */
nkeynes@261
   585
uint32_t pvr2_get_sync_status()
nkeynes@261
   586
{
nkeynes@265
   587
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   588
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   589
nkeynes@265
   590
    if( pvr2_state.odd_even_field ) {
nkeynes@261
   591
	result |= 0x0400;
nkeynes@261
   592
    }
nkeynes@265
   593
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@265
   594
	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@261
   595
	    result |= 0x1000; /* !HSYNC */
nkeynes@261
   596
	}
nkeynes@265
   597
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@265
   598
	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@261
   599
		result |= 0x2800; /* Display active */
nkeynes@261
   600
	    } else {
nkeynes@261
   601
		result |= 0x2000; /* Front porch */
nkeynes@261
   602
	    }
nkeynes@261
   603
	}
nkeynes@261
   604
    } else {
nkeynes@269
   605
	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@269
   606
	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@269
   607
		result |= 0x3800; /* Display active */
nkeynes@269
   608
	    } else {
nkeynes@269
   609
		result |= 0x3000;
nkeynes@269
   610
	    }
nkeynes@261
   611
	} else {
nkeynes@261
   612
	    result |= 0x1000; /* Back porch */
nkeynes@261
   613
	}
nkeynes@261
   614
    }
nkeynes@261
   615
    return result;
nkeynes@261
   616
}
nkeynes@261
   617
nkeynes@265
   618
/**
nkeynes@265
   619
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   620
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   621
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   622
 * The raster position should be updated before calling this
nkeynes@265
   623
 * method.
nkeynes@304
   624
 * @param eventid Event to fire at the specified time
nkeynes@304
   625
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   626
 *  displays). 
nkeynes@304
   627
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   628
 */
nkeynes@304
   629
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   630
{
nkeynes@265
   631
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   632
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@265
   633
	field = !field;
nkeynes@265
   634
    }
nkeynes@304
   635
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@304
   636
	hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   637
    }
nkeynes@265
   638
nkeynes@265
   639
    line <<= 1;
nkeynes@265
   640
    if( field ) {
nkeynes@265
   641
	line += 1;
nkeynes@265
   642
    }
nkeynes@274
   643
    
nkeynes@274
   644
    if( line < pvr2_state.total_lines ) {
nkeynes@274
   645
	uint32_t lines;
nkeynes@274
   646
	uint32_t time;
nkeynes@274
   647
	if( line <= pvr2_state.line_count ) {
nkeynes@274
   648
	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@274
   649
	} else {
nkeynes@274
   650
	    lines = (line - pvr2_state.line_count);
nkeynes@274
   651
	}
nkeynes@274
   652
	if( lines <= minimum_lines ) {
nkeynes@274
   653
	    lines += pvr2_state.total_lines;
nkeynes@274
   654
	}
nkeynes@304
   655
	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@274
   656
	event_schedule( eventid, time );
nkeynes@274
   657
    } else {
nkeynes@274
   658
	event_cancel( eventid );
nkeynes@274
   659
    }
nkeynes@265
   660
}
nkeynes@265
   661
nkeynes@1
   662
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   663
{
nkeynes@1
   664
    switch( reg ) {
nkeynes@261
   665
        case DISP_SYNCSTAT:
nkeynes@261
   666
            return pvr2_get_sync_status();
nkeynes@1
   667
        default:
nkeynes@1
   668
            return MMIO_READ( PVR2, reg );
nkeynes@1
   669
    }
nkeynes@1
   670
}
nkeynes@19
   671
nkeynes@85
   672
MMIO_REGION_DEFFNS( PVR2PAL )
nkeynes@85
   673
nkeynes@19
   674
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   675
{
nkeynes@197
   676
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   677
}
nkeynes@56
   678
nkeynes@56
   679
nkeynes@65
   680
nkeynes@98
   681
nkeynes@56
   682
int32_t mmio_region_PVR2TA_read( uint32_t reg )
nkeynes@56
   683
{
nkeynes@56
   684
    return 0xFFFFFFFF;
nkeynes@56
   685
}
nkeynes@56
   686
nkeynes@56
   687
void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
nkeynes@56
   688
{
nkeynes@189
   689
    pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
nkeynes@56
   690
}
nkeynes@56
   691
.