Search
lxdream.org :: lxdream/src/aica/armcore.h
lxdream 0.9.1
released Jun 29
Download Now
filename src/aica/armcore.h
changeset 14:fc481a638848
prev11:0a82ef380c45
next30:89b30313d757
author nkeynes
date Mon Dec 12 10:37:41 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Use cpu-specific is_valid_page function
file annotate diff log raw
nkeynes@2
     1
nkeynes@2
     2
#ifndef dream_armcore_H
nkeynes@2
     3
#define dream_armcore_H 1
nkeynes@2
     4
nkeynes@2
     5
#include "dream.h"
nkeynes@2
     6
#include <stdint.h>
nkeynes@2
     7
nkeynes@7
     8
#define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
nkeynes@2
     9
nkeynes@2
    10
struct arm_registers {
nkeynes@11
    11
    uint32_t r[16]; /* Current register bank */
nkeynes@11
    12
    
nkeynes@11
    13
    uint32_t cpsr;
nkeynes@11
    14
    uint32_t spsr;
nkeynes@11
    15
    
nkeynes@11
    16
    /* Various banked versions of the registers. */
nkeynes@11
    17
    uint32_t fiq_r[7]; /* FIQ bank 8..14 */
nkeynes@11
    18
    uint32_t irq_r[2]; /* IRQ bank 13..14 */
nkeynes@11
    19
    uint32_t und_r[2]; /* UND bank 13..14 */
nkeynes@11
    20
    uint32_t abt_r[2]; /* ABT bank 13..14 */
nkeynes@11
    21
    uint32_t svc_r[2]; /* SVC bank 13..14 */
nkeynes@11
    22
    uint32_t user_r[7]; /* User/System bank 8..14 */
nkeynes@11
    23
    
nkeynes@11
    24
    uint32_t c,n,z,v,t;
nkeynes@11
    25
    
nkeynes@11
    26
    /* "fake" registers */
nkeynes@11
    27
    uint32_t shift_c;  /* used for temporary storage of shifter results */
nkeynes@11
    28
    uint32_t icount; /* Instruction counter */
nkeynes@2
    29
};
nkeynes@2
    30
nkeynes@2
    31
#define CPSR_N 0x80000000 /* Negative flag */
nkeynes@2
    32
#define CPSR_Z 0x40000000 /* Zero flag */
nkeynes@2
    33
#define CPSR_C 0x20000000 /* Carry flag */
nkeynes@2
    34
#define CPSR_V 0x10000000 /* Overflow flag */
nkeynes@2
    35
#define CPSR_I 0x00000080 /* Interrupt disable bit */ 
nkeynes@2
    36
#define CPSR_F 0x00000040 /* Fast interrupt disable bit */
nkeynes@2
    37
#define CPSR_T 0x00000020 /* Thumb mode */
nkeynes@2
    38
#define CPSR_MODE 0x0000001F /* Current execution mode */
nkeynes@2
    39
nkeynes@2
    40
#define MODE_USER 0x00 /* User mode */
nkeynes@2
    41
#define MODE_FIQ   0x01 /* Fast IRQ mode */
nkeynes@2
    42
#define MODE_IRQ  0x02 /* IRQ mode */
nkeynes@2
    43
#define MODE_SV   0x03 /* Supervisor mode */
nkeynes@2
    44
#define MODE_ABT 0x07 /* Abort mode */
nkeynes@2
    45
#define MODE_UND 0x0B /* Undefined mode */
nkeynes@2
    46
#define MODE_SYS 0x0F /* System mode */
nkeynes@2
    47
nkeynes@2
    48
extern struct arm_registers armr;
nkeynes@2
    49
nkeynes@5
    50
#define CARRY_FLAG (armr.cpsr&CPSR_C)
nkeynes@2
    51
nkeynes@11
    52
/* ARM Memory */
nkeynes@11
    53
int32_t arm_read_long( uint32_t addr );
nkeynes@11
    54
int32_t arm_read_word( uint32_t addr );
nkeynes@11
    55
int32_t arm_read_byte( uint32_t addr );
nkeynes@11
    56
void arm_write_long( uint32_t addr, uint32_t val );
nkeynes@11
    57
void arm_write_word( uint32_t addr, uint32_t val );
nkeynes@11
    58
void arm_write_byte( uint32_t addr, uint32_t val );
nkeynes@11
    59
int32_t arm_read_phys_word( uint32_t addr );
nkeynes@14
    60
int arm_has_page( uint32_t addr );
nkeynes@11
    61
nkeynes@2
    62
#endif /* !dream_armcore_H */
.