Search
lxdream.org :: lxdream/src/tst1.c
lxdream 0.9.1
released Jun 29
Download Now
filename src/tst1.c
changeset 1:eea311cfd33e
author nkeynes
date Mon Dec 12 10:37:41 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Use cpu-specific is_valid_page function
file annotate diff log raw
nkeynes@1
     1
#include <stdint.h>
nkeynes@1
     2
nkeynes@1
     3
#define PORT_R 1
nkeynes@1
     4
#define PORT_W 2
nkeynes@1
     5
#define PORT_MEM 4 /* store written value */
nkeynes@1
     6
#define PORT_RW 3
nkeynes@1
     7
#define PORT_MRW 7
nkeynes@1
     8
#define UNDEFINED 0
nkeynes@1
     9
nkeynes@1
    10
struct mmio_region {
nkeynes@1
    11
    char *id, *desc;
nkeynes@1
    12
    uint32_t base;
nkeynes@1
    13
    char *mem;
nkeynes@1
    14
    struct mmio_port {
nkeynes@1
    15
        char *id, *desc;
nkeynes@1
    16
        int width;
nkeynes@1
    17
        uint32_t offset;
nkeynes@1
    18
        uint32_t default;
nkeynes@1
    19
        int flags;
nkeynes@1
    20
    } *ports;
nkeynes@1
    21
};
nkeynes@1
    22
nkeynes@1
    23
#define _MACROIZE #define
nkeynes@1
    24
nkeynes@1
    25
#define MMIO_REGION_BEGIN(b,id,d) struct mmio_region mmio_region_##id = { #id, d, b, NULL, 
nkeynes@1
    26
#define LONG_PORT( o,id,f,def,d ) { #id, desc, 32, o, def, f }, \
nkeynes@1
    27
_MACROIZE port_##id o \
nkeynes@1
    28
_MACROIZE reg_##id  (*(uint32_t *)(mmio_region_##id.mem + o))
nkeynes@1
    29
#define WORD_PORT( o,id,f,def,d ) { #id, desc, 16, o, def, f },
nkeynes@1
    30
#define BYTE_PORT( o,id,f,def,d ) { #id, desc, 8, o, def, f },
nkeynes@1
    31
#define MMIO_REGION_END {NULL, NULL, 0, 0, 0} };
nkeynes@1
    32
nkeynes@1
    33
MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
nkeynes@1
    34
    LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" ),
nkeynes@1
    35
    LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" ),
nkeynes@1
    36
MMIO_REGION_END
nkeynes@1
    37
nkeynes@1
    38
MMIO_REGION_BEGIN( BSC, 0xFF800000, "I/O Port Registers" )
nkeynes@1
    39
    LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "" ),
nkeynes@1
    40
    WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "" ),
nkeynes@1
    41
    LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "" ),
nkeynes@1
    42
    LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "" ),
nkeynes@1
    43
    LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "" ),
nkeynes@1
    44
    LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" ),
nkeynes@1
    45
    WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" ),
nkeynes@1
    46
    LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" ),
nkeynes@1
    47
    WORD_PORT( 0x044, PCTRB, PORT_RW, UNDEFINED, "Port data register B" ),
nkeynes@1
    48
    WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
nkeynes@1
    49
MMIO_REGION_END
nkeynes@1
    50
nkeynes@1
    51
MMIO_REGION_BEGIN( SCI, 0xFFE00000, "Serial Controller Registers" )
nkeynes@1
    52
    
nkeynes@1
    53
MMIO_REGION_END
nkeynes@1
    54
nkeynes@1
    55
MMIO_REGIN_BEGIN( SCIF, 0xFFE80000, "Serial Controller (FIFO) Registers" )
nkeynes@1
    56
MMIO_REGION_END
nkeynes@1
    57
.