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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 382:fce3f4da92ab
prev381:aade6c9aca4d
next386:6fb10951326a
author nkeynes
date Thu Sep 13 08:28:01 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Fix exception handling
Fix various instruction bugs
file annotate diff log raw
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/**
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 * $Id: sh4x86.in,v 1.9 2007-09-13 08:28:01 nkeynes Exp $
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    gboolean in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    /* Allocated memory for the (block-wide) back-patch list */
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    uint32_t **backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define EXIT_DATA_ADDR_READ 0
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#define EXIT_DATA_ADDR_WRITE 7
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#define EXIT_ILLEGAL 14
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#define EXIT_SLOT_ILLEGAL 21
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#define EXIT_FPU_DISABLED 28
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#define EXIT_SLOT_FPU_DISABLED 35
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static struct sh4_x86_state sh4_x86;
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void sh4_x86_init()
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
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}
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static void sh4_x86_add_backpatch( uint8_t *ptr )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
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}
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static void sh4_x86_do_backpatch( uint8_t *reloc_base )
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{
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    unsigned int i;
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    for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
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	*sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
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    }
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline load_fr( int bankreg, int x86reg, int frm )
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{
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    OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
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}
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/**
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 * Store an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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void static inline store_fr( int bankreg, int x86reg, int frn )
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{
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    OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
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}
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/**
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 * Load a pointer to the back fp back into the specified x86 register. The
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 * bankreg must have been previously loaded with FPSCR.
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 * NB: 10 bytes
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 */
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static inline void load_xf_bank( int bankreg )
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{
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    SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
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    AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
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    OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
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}
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/**
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 * Push FPUL (as a 32-bit float) onto the FPU stack
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 */
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static inline void push_fpul( )
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{
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    OP(0xD9); OP(0x45); OP(R_FPUL);
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}
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/**
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 * Pop FPUL (as a 32-bit float) from the FPU stack
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 */
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static inline void pop_fpul( )
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{
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    OP(0xD9); OP(0x5D); OP(R_FPUL);
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}
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/**
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 * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_fr( int bankreg, int frm ) 
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{
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    OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
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}
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/**
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 * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
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 * with bankreg previously loaded with the location of the current fp bank.
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 */
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static inline void pop_fr( int bankreg, int frm )
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{
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    OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
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}
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/**
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 * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
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 * with the location of the current fp bank.
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 */
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static inline void push_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
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}
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static inline void pop_dr( int bankreg, int frm )
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{
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    OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
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}
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/**
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 * Note: clobbers EAX to make the indirect call - this isn't usually
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 * a problem since the callee will usually clobber it anyway.
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 */
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static inline void call_func0( void *ptr )
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{
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    load_imm32(R_EAX, (uint32_t)ptr);
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    CALL_r32(R_EAX);
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}
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static inline void call_func1( void *ptr, int arg1 )
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{
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 4, R_ESP );
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}
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static inline void call_func2( void *ptr, int arg1, int arg2 )
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{
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    PUSH_r32(arg2);
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    PUSH_r32(arg1);
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    call_func0(ptr);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Write a double (64-bit) value into memory, with the first word in arg2a, and
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 * the second in arg2b
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 * NB: 30 bytes
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 */
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static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2b);
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    ADD_imm8s_r32( -4, addr );
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    PUSH_r32(addr);
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    PUSH_r32(arg2a);
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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    call_func0(sh4_write_long);
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    ADD_imm8s_r32( 8, R_ESP );
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}
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/**
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 * Read a double (64-bit) value from memory, writing the first word into arg2a
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 * and the second into arg2b. The addr must not be in EAX
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 * NB: 27 bytes
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 */
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static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
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{
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    POP_r32(addr);
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    PUSH_r32(R_EAX);
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    ADD_imm8s_r32( 4, addr );
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    PUSH_r32(addr);
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    call_func0(sh4_read_long);
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    ADD_imm8s_r32( 4, R_ESP );
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    MOV_r32_r32( R_EAX, arg2b );
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    POP_r32(arg2a);
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}
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/* Exception checks - Note that all exception checks will clobber EAX */
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static void check_priv( )
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{
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    if( !sh4_x86.priv_checked ) {
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	sh4_x86.priv_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_MD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JE_exit( EXIT_SLOT_ILLEGAL );
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	} else {
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	    JE_exit( EXIT_ILLEGAL );
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	}
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    }
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}
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static void check_fpuen( )
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{
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    if( !sh4_x86.fpuen_checked ) {
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	sh4_x86.fpuen_checked = TRUE;
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	load_spreg( R_EAX, R_SR );
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	AND_imm32_r32( SR_FD, R_EAX );
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	if( sh4_x86.in_delay_slot ) {
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	    JNE_exit(EXIT_SLOT_FPU_DISABLED);
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	} else {
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	    JNE_exit(EXIT_FPU_DISABLED);
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	}
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    }
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}
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static void check_ralign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign16( int x86reg )
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{
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    TEST_imm32_r32( 0x00000001, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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static void check_ralign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_READ);
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}
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static void check_walign32( int x86reg )
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{
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    TEST_imm32_r32( 0x00000003, x86reg );
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    JNE_exit(EXIT_DATA_ADDR_WRITE);
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}
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#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#define RAISE_EXCEPTION( exc ) call_func1(sh4_raise_exception, exc);
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#define SLOTILLEGAL() RAISE_EXCEPTION(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() 
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{
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    PUSH_r32(R_EBP);
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    /* mov &sh4r, ebp */
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    load_imm32( R_EBP, (uint32_t)&sh4r );
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    PUSH_r32(R_EDI);
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    PUSH_r32(R_ESI);
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    XOR_r32_r32(R_ESI, R_ESI);
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nkeynes@368
   355
    sh4_x86.in_delay_slot = FALSE;
nkeynes@368
   356
    sh4_x86.priv_checked = FALSE;
nkeynes@368
   357
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
   358
    sh4_x86.backpatch_posn = 0;
nkeynes@368
   359
}
nkeynes@359
   360
nkeynes@368
   361
/**
nkeynes@368
   362
 * Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368
   363
 */
nkeynes@374
   364
void exit_block( )
nkeynes@368
   365
{
nkeynes@374
   366
    store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368
   367
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   368
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   369
    MUL_r32( R_ESI );
nkeynes@368
   370
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   371
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@381
   372
    load_imm32( R_EAX, 1 );
nkeynes@374
   373
    POP_r32(R_ESI);
nkeynes@374
   374
    POP_r32(R_EDI);
nkeynes@374
   375
    POP_r32(R_EBP);
nkeynes@368
   376
    RET();
nkeynes@359
   377
}
nkeynes@359
   378
nkeynes@359
   379
/**
nkeynes@359
   380
 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359
   381
 */
nkeynes@359
   382
void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368
   383
    assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368
   384
    // Normal termination - save PC, cycle count
nkeynes@374
   385
    exit_block( );
nkeynes@359
   386
nkeynes@368
   387
    uint8_t *end_ptr = xlat_output;
nkeynes@368
   388
    // Exception termination. Jump block for various exception codes:
nkeynes@368
   389
    PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@380
   390
    JMP_rel8( 33, target1 );
nkeynes@368
   391
    PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@380
   392
    JMP_rel8( 26, target2 );
nkeynes@368
   393
    PUSH_imm32( EXC_ILLEGAL );
nkeynes@380
   394
    JMP_rel8( 19, target3 );
nkeynes@368
   395
    PUSH_imm32( EXC_SLOT_ILLEGAL ); 
nkeynes@380
   396
    JMP_rel8( 12, target4 );
nkeynes@368
   397
    PUSH_imm32( EXC_FPU_DISABLED ); 
nkeynes@380
   398
    JMP_rel8( 5, target5 );
nkeynes@368
   399
    PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@368
   400
    // target
nkeynes@380
   401
    JMP_TARGET(target1);
nkeynes@380
   402
    JMP_TARGET(target2);
nkeynes@380
   403
    JMP_TARGET(target3);
nkeynes@380
   404
    JMP_TARGET(target4);
nkeynes@380
   405
    JMP_TARGET(target5);
nkeynes@368
   406
    load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   407
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   408
    ADD_r32_r32( R_ESI, R_ECX );
nkeynes@368
   409
    store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@368
   410
    MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368
   411
    load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   412
    MUL_r32( R_ESI );
nkeynes@368
   413
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   414
    store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368
   415
nkeynes@368
   416
    load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@368
   417
    CALL_r32( R_EAX ); // 2
nkeynes@382
   418
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@382
   419
    POP_r32(R_ESI);
nkeynes@382
   420
    POP_r32(R_EDI);
nkeynes@368
   421
    POP_r32(R_EBP);
nkeynes@368
   422
    RET();
nkeynes@368
   423
nkeynes@368
   424
    sh4_x86_do_backpatch( end_ptr );
nkeynes@359
   425
}
nkeynes@359
   426
nkeynes@359
   427
/**
nkeynes@359
   428
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   429
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   430
 * 
nkeynes@359
   431
 *
nkeynes@359
   432
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   433
 * (eg a branch or 
nkeynes@359
   434
 */
nkeynes@359
   435
uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359
   436
{
nkeynes@361
   437
    uint16_t ir = sh4_read_word( pc );
nkeynes@368
   438
    
nkeynes@359
   439
%%
nkeynes@359
   440
/* ALU operations */
nkeynes@359
   441
ADD Rm, Rn {:
nkeynes@359
   442
    load_reg( R_EAX, Rm );
nkeynes@359
   443
    load_reg( R_ECX, Rn );
nkeynes@359
   444
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   445
    store_reg( R_ECX, Rn );
nkeynes@359
   446
:}
nkeynes@359
   447
ADD #imm, Rn {:  
nkeynes@359
   448
    load_reg( R_EAX, Rn );
nkeynes@359
   449
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   450
    store_reg( R_EAX, Rn );
nkeynes@359
   451
:}
nkeynes@359
   452
ADDC Rm, Rn {:
nkeynes@359
   453
    load_reg( R_EAX, Rm );
nkeynes@359
   454
    load_reg( R_ECX, Rn );
nkeynes@359
   455
    LDC_t();
nkeynes@359
   456
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   457
    store_reg( R_ECX, Rn );
nkeynes@359
   458
    SETC_t();
nkeynes@359
   459
:}
nkeynes@359
   460
ADDV Rm, Rn {:
nkeynes@359
   461
    load_reg( R_EAX, Rm );
nkeynes@359
   462
    load_reg( R_ECX, Rn );
nkeynes@359
   463
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   464
    store_reg( R_ECX, Rn );
nkeynes@359
   465
    SETO_t();
nkeynes@359
   466
:}
nkeynes@359
   467
AND Rm, Rn {:
nkeynes@359
   468
    load_reg( R_EAX, Rm );
nkeynes@359
   469
    load_reg( R_ECX, Rn );
nkeynes@359
   470
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   471
    store_reg( R_ECX, Rn );
nkeynes@359
   472
:}
nkeynes@359
   473
AND #imm, R0 {:  
nkeynes@359
   474
    load_reg( R_EAX, 0 );
nkeynes@359
   475
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   476
    store_reg( R_EAX, 0 );
nkeynes@359
   477
:}
nkeynes@359
   478
AND.B #imm, @(R0, GBR) {: 
nkeynes@359
   479
    load_reg( R_EAX, 0 );
nkeynes@359
   480
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   481
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   482
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   483
    AND_imm32_r32(imm, R_ECX );
nkeynes@359
   484
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   485
:}
nkeynes@359
   486
CMP/EQ Rm, Rn {:  
nkeynes@359
   487
    load_reg( R_EAX, Rm );
nkeynes@359
   488
    load_reg( R_ECX, Rn );
nkeynes@359
   489
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   490
    SETE_t();
nkeynes@359
   491
:}
nkeynes@359
   492
CMP/EQ #imm, R0 {:  
nkeynes@359
   493
    load_reg( R_EAX, 0 );
nkeynes@359
   494
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   495
    SETE_t();
nkeynes@359
   496
:}
nkeynes@359
   497
CMP/GE Rm, Rn {:  
nkeynes@359
   498
    load_reg( R_EAX, Rm );
nkeynes@359
   499
    load_reg( R_ECX, Rn );
nkeynes@359
   500
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   501
    SETGE_t();
nkeynes@359
   502
:}
nkeynes@359
   503
CMP/GT Rm, Rn {: 
nkeynes@359
   504
    load_reg( R_EAX, Rm );
nkeynes@359
   505
    load_reg( R_ECX, Rn );
nkeynes@359
   506
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   507
    SETG_t();
nkeynes@359
   508
:}
nkeynes@359
   509
CMP/HI Rm, Rn {:  
nkeynes@359
   510
    load_reg( R_EAX, Rm );
nkeynes@359
   511
    load_reg( R_ECX, Rn );
nkeynes@359
   512
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   513
    SETA_t();
nkeynes@359
   514
:}
nkeynes@359
   515
CMP/HS Rm, Rn {: 
nkeynes@359
   516
    load_reg( R_EAX, Rm );
nkeynes@359
   517
    load_reg( R_ECX, Rn );
nkeynes@359
   518
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   519
    SETAE_t();
nkeynes@359
   520
 :}
nkeynes@359
   521
CMP/PL Rn {: 
nkeynes@359
   522
    load_reg( R_EAX, Rn );
nkeynes@359
   523
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   524
    SETG_t();
nkeynes@359
   525
:}
nkeynes@359
   526
CMP/PZ Rn {:  
nkeynes@359
   527
    load_reg( R_EAX, Rn );
nkeynes@359
   528
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   529
    SETGE_t();
nkeynes@359
   530
:}
nkeynes@361
   531
CMP/STR Rm, Rn {:  
nkeynes@368
   532
    load_reg( R_EAX, Rm );
nkeynes@368
   533
    load_reg( R_ECX, Rn );
nkeynes@368
   534
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   535
    TEST_r8_r8( R_AL, R_AL );
nkeynes@380
   536
    JE_rel8(13, target1);
nkeynes@368
   537
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   538
    JE_rel8(9, target2);
nkeynes@368
   539
    SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368
   540
    TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380
   541
    JE_rel8(2, target3);
nkeynes@368
   542
    TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380
   543
    JMP_TARGET(target1);
nkeynes@380
   544
    JMP_TARGET(target2);
nkeynes@380
   545
    JMP_TARGET(target3);
nkeynes@368
   546
    SETE_t();
nkeynes@361
   547
:}
nkeynes@361
   548
DIV0S Rm, Rn {:
nkeynes@361
   549
    load_reg( R_EAX, Rm );
nkeynes@361
   550
    load_reg( R_ECX, Rm );
nkeynes@361
   551
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   552
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   553
    store_spreg( R_EAX, R_M );
nkeynes@361
   554
    store_spreg( R_ECX, R_Q );
nkeynes@361
   555
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   556
    SETE_t();
nkeynes@361
   557
:}
nkeynes@361
   558
DIV0U {:  
nkeynes@361
   559
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   560
    store_spreg( R_EAX, R_Q );
nkeynes@361
   561
    store_spreg( R_EAX, R_M );
nkeynes@361
   562
    store_spreg( R_EAX, R_T );
nkeynes@361
   563
:}
nkeynes@374
   564
DIV1 Rm, Rn {:  
nkeynes@374
   565
    load_reg( R_ECX, Rn );
nkeynes@374
   566
    LDC_t();
nkeynes@374
   567
    RCL1_r32( R_ECX ); // OP2
nkeynes@374
   568
    SETC_r32( R_EDX ); // Q
nkeynes@374
   569
    load_spreg( R_EAX, R_Q );
nkeynes@374
   570
    CMP_sh4r_r32( R_M, R_EAX );
nkeynes@380
   571
    JE_rel8(8,mqequal);
nkeynes@374
   572
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@380
   573
    JMP_rel8(3, mqnotequal);
nkeynes@380
   574
    JMP_TARGET(mqequal);
nkeynes@374
   575
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_ECX );
nkeynes@380
   576
    JMP_TARGET(mqnotequal);
nkeynes@374
   577
    // TODO
nkeynes@374
   578
:}
nkeynes@361
   579
DMULS.L Rm, Rn {:  
nkeynes@361
   580
    load_reg( R_EAX, Rm );
nkeynes@361
   581
    load_reg( R_ECX, Rn );
nkeynes@361
   582
    IMUL_r32(R_ECX);
nkeynes@361
   583
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   584
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   585
:}
nkeynes@361
   586
DMULU.L Rm, Rn {:  
nkeynes@361
   587
    load_reg( R_EAX, Rm );
nkeynes@361
   588
    load_reg( R_ECX, Rn );
nkeynes@361
   589
    MUL_r32(R_ECX);
nkeynes@361
   590
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   591
    store_spreg( R_EAX, R_MACL );    
nkeynes@361
   592
:}
nkeynes@359
   593
DT Rn {:  
nkeynes@359
   594
    load_reg( R_EAX, Rn );
nkeynes@382
   595
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   596
    store_reg( R_EAX, Rn );
nkeynes@359
   597
    SETE_t();
nkeynes@359
   598
:}
nkeynes@359
   599
EXTS.B Rm, Rn {:  
nkeynes@359
   600
    load_reg( R_EAX, Rm );
nkeynes@359
   601
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   602
    store_reg( R_EAX, Rn );
nkeynes@359
   603
:}
nkeynes@361
   604
EXTS.W Rm, Rn {:  
nkeynes@361
   605
    load_reg( R_EAX, Rm );
nkeynes@361
   606
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   607
    store_reg( R_EAX, Rn );
nkeynes@361
   608
:}
nkeynes@361
   609
EXTU.B Rm, Rn {:  
nkeynes@361
   610
    load_reg( R_EAX, Rm );
nkeynes@361
   611
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   612
    store_reg( R_EAX, Rn );
nkeynes@361
   613
:}
nkeynes@361
   614
EXTU.W Rm, Rn {:  
nkeynes@361
   615
    load_reg( R_EAX, Rm );
nkeynes@361
   616
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   617
    store_reg( R_EAX, Rn );
nkeynes@361
   618
:}
nkeynes@359
   619
MAC.L @Rm+, @Rn+ {:  :}
nkeynes@359
   620
MAC.W @Rm+, @Rn+ {:  :}
nkeynes@359
   621
MOVT Rn {:  
nkeynes@359
   622
    load_spreg( R_EAX, R_T );
nkeynes@359
   623
    store_reg( R_EAX, Rn );
nkeynes@359
   624
:}
nkeynes@361
   625
MUL.L Rm, Rn {:  
nkeynes@361
   626
    load_reg( R_EAX, Rm );
nkeynes@361
   627
    load_reg( R_ECX, Rn );
nkeynes@361
   628
    MUL_r32( R_ECX );
nkeynes@361
   629
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   630
:}
nkeynes@374
   631
MULS.W Rm, Rn {:
nkeynes@374
   632
    load_reg16s( R_EAX, Rm );
nkeynes@374
   633
    load_reg16s( R_ECX, Rn );
nkeynes@374
   634
    MUL_r32( R_ECX );
nkeynes@374
   635
    store_spreg( R_EAX, R_MACL );
nkeynes@361
   636
:}
nkeynes@374
   637
MULU.W Rm, Rn {:  
nkeynes@374
   638
    load_reg16u( R_EAX, Rm );
nkeynes@374
   639
    load_reg16u( R_ECX, Rn );
nkeynes@374
   640
    MUL_r32( R_ECX );
nkeynes@374
   641
    store_spreg( R_EAX, R_MACL );
nkeynes@374
   642
:}
nkeynes@359
   643
NEG Rm, Rn {:
nkeynes@359
   644
    load_reg( R_EAX, Rm );
nkeynes@359
   645
    NEG_r32( R_EAX );
nkeynes@359
   646
    store_reg( R_EAX, Rn );
nkeynes@359
   647
:}
nkeynes@359
   648
NEGC Rm, Rn {:  
nkeynes@359
   649
    load_reg( R_EAX, Rm );
nkeynes@359
   650
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   651
    LDC_t();
nkeynes@359
   652
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   653
    store_reg( R_ECX, Rn );
nkeynes@359
   654
    SETC_t();
nkeynes@359
   655
:}
nkeynes@359
   656
NOT Rm, Rn {:  
nkeynes@359
   657
    load_reg( R_EAX, Rm );
nkeynes@359
   658
    NOT_r32( R_EAX );
nkeynes@359
   659
    store_reg( R_EAX, Rn );
nkeynes@359
   660
:}
nkeynes@359
   661
OR Rm, Rn {:  
nkeynes@359
   662
    load_reg( R_EAX, Rm );
nkeynes@359
   663
    load_reg( R_ECX, Rn );
nkeynes@359
   664
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   665
    store_reg( R_ECX, Rn );
nkeynes@359
   666
:}
nkeynes@359
   667
OR #imm, R0 {:
nkeynes@359
   668
    load_reg( R_EAX, 0 );
nkeynes@359
   669
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   670
    store_reg( R_EAX, 0 );
nkeynes@359
   671
:}
nkeynes@374
   672
OR.B #imm, @(R0, GBR) {:  
nkeynes@374
   673
    load_reg( R_EAX, 0 );
nkeynes@374
   674
    load_spreg( R_ECX, R_GBR );
nkeynes@374
   675
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   676
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@374
   677
    OR_imm32_r32(imm, R_ECX );
nkeynes@374
   678
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@374
   679
:}
nkeynes@359
   680
ROTCL Rn {:
nkeynes@359
   681
    load_reg( R_EAX, Rn );
nkeynes@359
   682
    LDC_t();
nkeynes@359
   683
    RCL1_r32( R_EAX );
nkeynes@359
   684
    store_reg( R_EAX, Rn );
nkeynes@359
   685
    SETC_t();
nkeynes@359
   686
:}
nkeynes@359
   687
ROTCR Rn {:  
nkeynes@359
   688
    load_reg( R_EAX, Rn );
nkeynes@359
   689
    LDC_t();
nkeynes@359
   690
    RCR1_r32( R_EAX );
nkeynes@359
   691
    store_reg( R_EAX, Rn );
nkeynes@359
   692
    SETC_t();
nkeynes@359
   693
:}
nkeynes@359
   694
ROTL Rn {:  
nkeynes@359
   695
    load_reg( R_EAX, Rn );
nkeynes@359
   696
    ROL1_r32( R_EAX );
nkeynes@359
   697
    store_reg( R_EAX, Rn );
nkeynes@359
   698
    SETC_t();
nkeynes@359
   699
:}
nkeynes@359
   700
ROTR Rn {:  
nkeynes@359
   701
    load_reg( R_EAX, Rn );
nkeynes@359
   702
    ROR1_r32( R_EAX );
nkeynes@359
   703
    store_reg( R_EAX, Rn );
nkeynes@359
   704
    SETC_t();
nkeynes@359
   705
:}
nkeynes@359
   706
SHAD Rm, Rn {:
nkeynes@359
   707
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   708
    load_reg( R_EAX, Rn );
nkeynes@361
   709
    load_reg( R_ECX, Rm );
nkeynes@361
   710
    CMP_imm32_r32( 0, R_ECX );
nkeynes@382
   711
    JGE_rel8(9, doshl);
nkeynes@361
   712
                    
nkeynes@361
   713
    NEG_r32( R_ECX );      // 2
nkeynes@361
   714
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   715
    SAR_r32_CL( R_EAX );       // 2
nkeynes@380
   716
    JMP_rel8(5, end);          // 2
nkeynes@382
   717
nkeynes@380
   718
    JMP_TARGET(doshl);
nkeynes@361
   719
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   720
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   721
    JMP_TARGET(end);
nkeynes@361
   722
    store_reg( R_EAX, Rn );
nkeynes@359
   723
:}
nkeynes@359
   724
SHLD Rm, Rn {:  
nkeynes@368
   725
    load_reg( R_EAX, Rn );
nkeynes@368
   726
    load_reg( R_ECX, Rm );
nkeynes@382
   727
    CMP_imm32_r32( 0, R_ECX );
nkeynes@382
   728
    JGE_rel8(9, doshl);
nkeynes@368
   729
nkeynes@382
   730
    NEG_r32( R_ECX );      // 2
nkeynes@382
   731
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   732
    SHR_r32_CL( R_EAX );       // 2
nkeynes@382
   733
    JMP_rel8(5, end);          // 2
nkeynes@382
   734
nkeynes@382
   735
    JMP_TARGET(doshl);
nkeynes@382
   736
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   737
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   738
    JMP_TARGET(end);
nkeynes@368
   739
    store_reg( R_EAX, Rn );
nkeynes@359
   740
:}
nkeynes@359
   741
SHAL Rn {: 
nkeynes@359
   742
    load_reg( R_EAX, Rn );
nkeynes@359
   743
    SHL1_r32( R_EAX );
nkeynes@359
   744
    store_reg( R_EAX, Rn );
nkeynes@359
   745
:}
nkeynes@359
   746
SHAR Rn {:  
nkeynes@359
   747
    load_reg( R_EAX, Rn );
nkeynes@359
   748
    SAR1_r32( R_EAX );
nkeynes@359
   749
    store_reg( R_EAX, Rn );
nkeynes@359
   750
:}
nkeynes@359
   751
SHLL Rn {:  
nkeynes@359
   752
    load_reg( R_EAX, Rn );
nkeynes@359
   753
    SHL1_r32( R_EAX );
nkeynes@359
   754
    store_reg( R_EAX, Rn );
nkeynes@359
   755
:}
nkeynes@359
   756
SHLL2 Rn {:
nkeynes@359
   757
    load_reg( R_EAX, Rn );
nkeynes@359
   758
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   759
    store_reg( R_EAX, Rn );
nkeynes@359
   760
:}
nkeynes@359
   761
SHLL8 Rn {:  
nkeynes@359
   762
    load_reg( R_EAX, Rn );
nkeynes@359
   763
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   764
    store_reg( R_EAX, Rn );
nkeynes@359
   765
:}
nkeynes@359
   766
SHLL16 Rn {:  
nkeynes@359
   767
    load_reg( R_EAX, Rn );
nkeynes@359
   768
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   769
    store_reg( R_EAX, Rn );
nkeynes@359
   770
:}
nkeynes@359
   771
SHLR Rn {:  
nkeynes@359
   772
    load_reg( R_EAX, Rn );
nkeynes@359
   773
    SHR1_r32( R_EAX );
nkeynes@359
   774
    store_reg( R_EAX, Rn );
nkeynes@359
   775
:}
nkeynes@359
   776
SHLR2 Rn {:  
nkeynes@359
   777
    load_reg( R_EAX, Rn );
nkeynes@359
   778
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   779
    store_reg( R_EAX, Rn );
nkeynes@359
   780
:}
nkeynes@359
   781
SHLR8 Rn {:  
nkeynes@359
   782
    load_reg( R_EAX, Rn );
nkeynes@359
   783
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   784
    store_reg( R_EAX, Rn );
nkeynes@359
   785
:}
nkeynes@359
   786
SHLR16 Rn {:  
nkeynes@359
   787
    load_reg( R_EAX, Rn );
nkeynes@359
   788
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   789
    store_reg( R_EAX, Rn );
nkeynes@359
   790
:}
nkeynes@359
   791
SUB Rm, Rn {:  
nkeynes@359
   792
    load_reg( R_EAX, Rm );
nkeynes@359
   793
    load_reg( R_ECX, Rn );
nkeynes@359
   794
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   795
    store_reg( R_ECX, Rn );
nkeynes@359
   796
:}
nkeynes@359
   797
SUBC Rm, Rn {:  
nkeynes@359
   798
    load_reg( R_EAX, Rm );
nkeynes@359
   799
    load_reg( R_ECX, Rn );
nkeynes@359
   800
    LDC_t();
nkeynes@359
   801
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   802
    store_reg( R_ECX, Rn );
nkeynes@359
   803
:}
nkeynes@359
   804
SUBV Rm, Rn {:  
nkeynes@359
   805
    load_reg( R_EAX, Rm );
nkeynes@359
   806
    load_reg( R_ECX, Rn );
nkeynes@359
   807
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   808
    store_reg( R_ECX, Rn );
nkeynes@359
   809
    SETO_t();
nkeynes@359
   810
:}
nkeynes@359
   811
SWAP.B Rm, Rn {:  
nkeynes@359
   812
    load_reg( R_EAX, Rm );
nkeynes@359
   813
    XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
   814
    store_reg( R_EAX, Rn );
nkeynes@359
   815
:}
nkeynes@359
   816
SWAP.W Rm, Rn {:  
nkeynes@359
   817
    load_reg( R_EAX, Rm );
nkeynes@359
   818
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
   819
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
   820
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   821
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   822
    store_reg( R_ECX, Rn );
nkeynes@359
   823
:}
nkeynes@361
   824
TAS.B @Rn {:  
nkeynes@361
   825
    load_reg( R_ECX, Rn );
nkeynes@361
   826
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
   827
    TEST_r8_r8( R_AL, R_AL );
nkeynes@361
   828
    SETE_t();
nkeynes@361
   829
    OR_imm8_r8( 0x80, R_AL );
nkeynes@361
   830
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@361
   831
:}
nkeynes@361
   832
TST Rm, Rn {:  
nkeynes@361
   833
    load_reg( R_EAX, Rm );
nkeynes@361
   834
    load_reg( R_ECX, Rn );
nkeynes@361
   835
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   836
    SETE_t();
nkeynes@361
   837
:}
nkeynes@368
   838
TST #imm, R0 {:  
nkeynes@368
   839
    load_reg( R_EAX, 0 );
nkeynes@368
   840
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
   841
    SETE_t();
nkeynes@368
   842
:}
nkeynes@368
   843
TST.B #imm, @(R0, GBR) {:  
nkeynes@368
   844
    load_reg( R_EAX, 0);
nkeynes@368
   845
    load_reg( R_ECX, R_GBR);
nkeynes@368
   846
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368
   847
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368
   848
    TEST_imm8_r8( imm, R_EAX );
nkeynes@368
   849
    SETE_t();
nkeynes@368
   850
:}
nkeynes@359
   851
XOR Rm, Rn {:  
nkeynes@359
   852
    load_reg( R_EAX, Rm );
nkeynes@359
   853
    load_reg( R_ECX, Rn );
nkeynes@359
   854
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   855
    store_reg( R_ECX, Rn );
nkeynes@359
   856
:}
nkeynes@359
   857
XOR #imm, R0 {:  
nkeynes@359
   858
    load_reg( R_EAX, 0 );
nkeynes@359
   859
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   860
    store_reg( R_EAX, 0 );
nkeynes@359
   861
:}
nkeynes@359
   862
XOR.B #imm, @(R0, GBR) {:  
nkeynes@359
   863
    load_reg( R_EAX, 0 );
nkeynes@359
   864
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   865
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   866
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   867
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
   868
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   869
:}
nkeynes@361
   870
XTRCT Rm, Rn {:
nkeynes@361
   871
    load_reg( R_EAX, Rm );
nkeynes@361
   872
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   873
    SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   874
    SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   875
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   876
    store_reg( R_ECX, Rn );
nkeynes@359
   877
:}
nkeynes@359
   878
nkeynes@359
   879
/* Data move instructions */
nkeynes@359
   880
MOV Rm, Rn {:  
nkeynes@359
   881
    load_reg( R_EAX, Rm );
nkeynes@359
   882
    store_reg( R_EAX, Rn );
nkeynes@359
   883
:}
nkeynes@359
   884
MOV #imm, Rn {:  
nkeynes@359
   885
    load_imm32( R_EAX, imm );
nkeynes@359
   886
    store_reg( R_EAX, Rn );
nkeynes@359
   887
:}
nkeynes@359
   888
MOV.B Rm, @Rn {:  
nkeynes@359
   889
    load_reg( R_EAX, Rm );
nkeynes@359
   890
    load_reg( R_ECX, Rn );
nkeynes@359
   891
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   892
:}
nkeynes@359
   893
MOV.B Rm, @-Rn {:  
nkeynes@359
   894
    load_reg( R_EAX, Rm );
nkeynes@359
   895
    load_reg( R_ECX, Rn );
nkeynes@382
   896
    ADD_imm8s_r32( -1, R_ECX );
nkeynes@359
   897
    store_reg( R_ECX, Rn );
nkeynes@359
   898
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   899
:}
nkeynes@359
   900
MOV.B Rm, @(R0, Rn) {:  
nkeynes@359
   901
    load_reg( R_EAX, 0 );
nkeynes@359
   902
    load_reg( R_ECX, Rn );
nkeynes@359
   903
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   904
    load_reg( R_EAX, Rm );
nkeynes@359
   905
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   906
:}
nkeynes@359
   907
MOV.B R0, @(disp, GBR) {:  
nkeynes@359
   908
    load_reg( R_EAX, 0 );
nkeynes@359
   909
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   910
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   911
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   912
:}
nkeynes@359
   913
MOV.B R0, @(disp, Rn) {:  
nkeynes@359
   914
    load_reg( R_EAX, 0 );
nkeynes@359
   915
    load_reg( R_ECX, Rn );
nkeynes@359
   916
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   917
    MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   918
:}
nkeynes@359
   919
MOV.B @Rm, Rn {:  
nkeynes@359
   920
    load_reg( R_ECX, Rm );
nkeynes@359
   921
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   922
    store_reg( R_ECX, Rn );
nkeynes@359
   923
:}
nkeynes@359
   924
MOV.B @Rm+, Rn {:  
nkeynes@359
   925
    load_reg( R_ECX, Rm );
nkeynes@359
   926
    MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
   927
    ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
   928
    store_reg( R_EAX, Rm );
nkeynes@359
   929
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   930
    store_reg( R_EAX, Rn );
nkeynes@359
   931
:}
nkeynes@359
   932
MOV.B @(R0, Rm), Rn {:  
nkeynes@359
   933
    load_reg( R_EAX, 0 );
nkeynes@359
   934
    load_reg( R_ECX, Rm );
nkeynes@359
   935
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   936
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   937
    store_reg( R_EAX, Rn );
nkeynes@359
   938
:}
nkeynes@359
   939
MOV.B @(disp, GBR), R0 {:  
nkeynes@359
   940
    load_spreg( R_ECX, R_GBR );
nkeynes@359
   941
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   942
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   943
    store_reg( R_EAX, 0 );
nkeynes@359
   944
:}
nkeynes@359
   945
MOV.B @(disp, Rm), R0 {:  
nkeynes@359
   946
    load_reg( R_ECX, Rm );
nkeynes@359
   947
    ADD_imm32_r32( disp, R_ECX );
nkeynes@359
   948
    MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   949
    store_reg( R_EAX, 0 );
nkeynes@359
   950
:}
nkeynes@374
   951
MOV.L Rm, @Rn {:
nkeynes@361
   952
    load_reg( R_EAX, Rm );
nkeynes@361
   953
    load_reg( R_ECX, Rn );
nkeynes@374
   954
    check_walign32(R_ECX);
nkeynes@361
   955
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   956
:}
nkeynes@361
   957
MOV.L Rm, @-Rn {:  
nkeynes@361
   958
    load_reg( R_EAX, Rm );
nkeynes@361
   959
    load_reg( R_ECX, Rn );
nkeynes@374
   960
    check_walign32( R_ECX );
nkeynes@361
   961
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   962
    store_reg( R_ECX, Rn );
nkeynes@361
   963
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   964
:}
nkeynes@361
   965
MOV.L Rm, @(R0, Rn) {:  
nkeynes@361
   966
    load_reg( R_EAX, 0 );
nkeynes@361
   967
    load_reg( R_ECX, Rn );
nkeynes@361
   968
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
   969
    check_walign32( R_ECX );
nkeynes@361
   970
    load_reg( R_EAX, Rm );
nkeynes@361
   971
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   972
:}
nkeynes@361
   973
MOV.L R0, @(disp, GBR) {:  
nkeynes@361
   974
    load_spreg( R_ECX, R_GBR );
nkeynes@361
   975
    load_reg( R_EAX, 0 );
nkeynes@361
   976
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   977
    check_walign32( R_ECX );
nkeynes@361
   978
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   979
:}
nkeynes@361
   980
MOV.L Rm, @(disp, Rn) {:  
nkeynes@361
   981
    load_reg( R_ECX, Rn );
nkeynes@361
   982
    load_reg( R_EAX, Rm );
nkeynes@361
   983
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
   984
    check_walign32( R_ECX );
nkeynes@361
   985
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
   986
:}
nkeynes@361
   987
MOV.L @Rm, Rn {:  
nkeynes@361
   988
    load_reg( R_ECX, Rm );
nkeynes@374
   989
    check_ralign32( R_ECX );
nkeynes@361
   990
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   991
    store_reg( R_EAX, Rn );
nkeynes@361
   992
:}
nkeynes@361
   993
MOV.L @Rm+, Rn {:  
nkeynes@361
   994
    load_reg( R_EAX, Rm );
nkeynes@382
   995
    check_ralign32( R_EAX );
nkeynes@361
   996
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   997
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
   998
    store_reg( R_EAX, Rm );
nkeynes@361
   999
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1000
    store_reg( R_EAX, Rn );
nkeynes@361
  1001
:}
nkeynes@361
  1002
MOV.L @(R0, Rm), Rn {:  
nkeynes@361
  1003
    load_reg( R_EAX, 0 );
nkeynes@361
  1004
    load_reg( R_ECX, Rm );
nkeynes@361
  1005
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1006
    check_ralign32( R_ECX );
nkeynes@361
  1007
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1008
    store_reg( R_EAX, Rn );
nkeynes@361
  1009
:}
nkeynes@361
  1010
MOV.L @(disp, GBR), R0 {:
nkeynes@361
  1011
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1012
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1013
    check_ralign32( R_ECX );
nkeynes@361
  1014
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1015
    store_reg( R_EAX, 0 );
nkeynes@361
  1016
:}
nkeynes@361
  1017
MOV.L @(disp, PC), Rn {:  
nkeynes@374
  1018
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1019
	SLOTILLEGAL();
nkeynes@374
  1020
    } else {
nkeynes@374
  1021
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1022
	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@382
  1023
	store_reg( R_EAX, Rn );
nkeynes@374
  1024
    }
nkeynes@361
  1025
:}
nkeynes@361
  1026
MOV.L @(disp, Rm), Rn {:  
nkeynes@361
  1027
    load_reg( R_ECX, Rm );
nkeynes@361
  1028
    ADD_imm8s_r32( disp, R_ECX );
nkeynes@374
  1029
    check_ralign32( R_ECX );
nkeynes@361
  1030
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1031
    store_reg( R_EAX, Rn );
nkeynes@361
  1032
:}
nkeynes@361
  1033
MOV.W Rm, @Rn {:  
nkeynes@361
  1034
    load_reg( R_ECX, Rn );
nkeynes@374
  1035
    check_walign16( R_ECX );
nkeynes@382
  1036
    load_reg( R_EAX, Rm );
nkeynes@382
  1037
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1038
:}
nkeynes@361
  1039
MOV.W Rm, @-Rn {:  
nkeynes@361
  1040
    load_reg( R_ECX, Rn );
nkeynes@374
  1041
    check_walign16( R_ECX );
nkeynes@361
  1042
    load_reg( R_EAX, Rm );
nkeynes@361
  1043
    ADD_imm8s_r32( -2, R_ECX );
nkeynes@382
  1044
    store_reg( R_ECX, Rn );
nkeynes@361
  1045
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1046
:}
nkeynes@361
  1047
MOV.W Rm, @(R0, Rn) {:  
nkeynes@361
  1048
    load_reg( R_EAX, 0 );
nkeynes@361
  1049
    load_reg( R_ECX, Rn );
nkeynes@361
  1050
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1051
    check_walign16( R_ECX );
nkeynes@361
  1052
    load_reg( R_EAX, Rm );
nkeynes@361
  1053
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1054
:}
nkeynes@361
  1055
MOV.W R0, @(disp, GBR) {:  
nkeynes@361
  1056
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1057
    load_reg( R_EAX, 0 );
nkeynes@361
  1058
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1059
    check_walign16( R_ECX );
nkeynes@361
  1060
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1061
:}
nkeynes@361
  1062
MOV.W R0, @(disp, Rn) {:  
nkeynes@361
  1063
    load_reg( R_ECX, Rn );
nkeynes@361
  1064
    load_reg( R_EAX, 0 );
nkeynes@361
  1065
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1066
    check_walign16( R_ECX );
nkeynes@361
  1067
    MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@361
  1068
:}
nkeynes@361
  1069
MOV.W @Rm, Rn {:  
nkeynes@361
  1070
    load_reg( R_ECX, Rm );
nkeynes@374
  1071
    check_ralign16( R_ECX );
nkeynes@361
  1072
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1073
    store_reg( R_EAX, Rn );
nkeynes@361
  1074
:}
nkeynes@361
  1075
MOV.W @Rm+, Rn {:  
nkeynes@361
  1076
    load_reg( R_EAX, Rm );
nkeynes@374
  1077
    check_ralign16( R_EAX );
nkeynes@361
  1078
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1079
    ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1080
    store_reg( R_EAX, Rm );
nkeynes@361
  1081
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1082
    store_reg( R_EAX, Rn );
nkeynes@361
  1083
:}
nkeynes@361
  1084
MOV.W @(R0, Rm), Rn {:  
nkeynes@361
  1085
    load_reg( R_EAX, 0 );
nkeynes@361
  1086
    load_reg( R_ECX, Rm );
nkeynes@361
  1087
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1088
    check_ralign16( R_ECX );
nkeynes@361
  1089
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1090
    store_reg( R_EAX, Rn );
nkeynes@361
  1091
:}
nkeynes@361
  1092
MOV.W @(disp, GBR), R0 {:  
nkeynes@361
  1093
    load_spreg( R_ECX, R_GBR );
nkeynes@361
  1094
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1095
    check_ralign16( R_ECX );
nkeynes@361
  1096
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1097
    store_reg( R_EAX, 0 );
nkeynes@361
  1098
:}
nkeynes@361
  1099
MOV.W @(disp, PC), Rn {:  
nkeynes@374
  1100
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1101
	SLOTILLEGAL();
nkeynes@374
  1102
    } else {
nkeynes@374
  1103
	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374
  1104
	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374
  1105
	store_reg( R_EAX, Rn );
nkeynes@374
  1106
    }
nkeynes@361
  1107
:}
nkeynes@361
  1108
MOV.W @(disp, Rm), R0 {:  
nkeynes@361
  1109
    load_reg( R_ECX, Rm );
nkeynes@361
  1110
    ADD_imm32_r32( disp, R_ECX );
nkeynes@374
  1111
    check_ralign16( R_ECX );
nkeynes@361
  1112
    MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1113
    store_reg( R_EAX, 0 );
nkeynes@361
  1114
:}
nkeynes@361
  1115
MOVA @(disp, PC), R0 {:  
nkeynes@374
  1116
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1117
	SLOTILLEGAL();
nkeynes@374
  1118
    } else {
nkeynes@374
  1119
	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374
  1120
	store_reg( R_ECX, 0 );
nkeynes@374
  1121
    }
nkeynes@361
  1122
:}
nkeynes@361
  1123
MOVCA.L R0, @Rn {:  
nkeynes@361
  1124
    load_reg( R_EAX, 0 );
nkeynes@361
  1125
    load_reg( R_ECX, Rn );
nkeynes@374
  1126
    check_walign32( R_ECX );
nkeynes@361
  1127
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@361
  1128
:}
nkeynes@359
  1129
nkeynes@359
  1130
/* Control transfer instructions */
nkeynes@374
  1131
BF disp {:
nkeynes@374
  1132
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1133
	SLOTILLEGAL();
nkeynes@374
  1134
    } else {
nkeynes@374
  1135
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1136
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1137
	JNE_rel8( 5, nottaken );
nkeynes@374
  1138
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1139
	JMP_TARGET(nottaken);
nkeynes@374
  1140
	INC_r32(R_ESI);
nkeynes@374
  1141
	return 1;
nkeynes@374
  1142
    }
nkeynes@374
  1143
:}
nkeynes@374
  1144
BF/S disp {:
nkeynes@374
  1145
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1146
	SLOTILLEGAL();
nkeynes@374
  1147
    } else {
nkeynes@374
  1148
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1149
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1150
	JNE_rel8( 5, nottaken );
nkeynes@374
  1151
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1152
	JMP_TARGET(nottaken);
nkeynes@374
  1153
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1154
	INC_r32(R_ESI);
nkeynes@374
  1155
	return 0;
nkeynes@374
  1156
    }
nkeynes@374
  1157
:}
nkeynes@374
  1158
BRA disp {:  
nkeynes@374
  1159
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1160
	SLOTILLEGAL();
nkeynes@374
  1161
    } else {
nkeynes@374
  1162
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1163
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1164
	INC_r32(R_ESI);
nkeynes@374
  1165
	return 0;
nkeynes@374
  1166
    }
nkeynes@374
  1167
:}
nkeynes@374
  1168
BRAF Rn {:  
nkeynes@374
  1169
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1170
	SLOTILLEGAL();
nkeynes@374
  1171
    } else {
nkeynes@374
  1172
	load_reg( R_EDI, Rn );
nkeynes@382
  1173
	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374
  1174
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1175
	INC_r32(R_ESI);
nkeynes@374
  1176
	return 0;
nkeynes@374
  1177
    }
nkeynes@374
  1178
:}
nkeynes@374
  1179
BSR disp {:  
nkeynes@374
  1180
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1181
	SLOTILLEGAL();
nkeynes@374
  1182
    } else {
nkeynes@374
  1183
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1184
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1185
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374
  1186
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1187
	INC_r32(R_ESI);
nkeynes@374
  1188
	return 0;
nkeynes@374
  1189
    }
nkeynes@374
  1190
:}
nkeynes@374
  1191
BSRF Rn {:  
nkeynes@374
  1192
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1193
	SLOTILLEGAL();
nkeynes@374
  1194
    } else {
nkeynes@374
  1195
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1196
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1197
	load_reg( R_EDI, Rn );
nkeynes@374
  1198
	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374
  1199
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1200
	INC_r32(R_ESI);
nkeynes@374
  1201
	return 0;
nkeynes@374
  1202
    }
nkeynes@374
  1203
:}
nkeynes@374
  1204
BT disp {:
nkeynes@374
  1205
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1206
	SLOTILLEGAL();
nkeynes@374
  1207
    } else {
nkeynes@374
  1208
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1209
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1210
	JE_rel8( 5, nottaken );
nkeynes@374
  1211
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1212
	JMP_TARGET(nottaken);
nkeynes@374
  1213
	INC_r32(R_ESI);
nkeynes@374
  1214
	return 1;
nkeynes@374
  1215
    }
nkeynes@374
  1216
:}
nkeynes@374
  1217
BT/S disp {:
nkeynes@374
  1218
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1219
	SLOTILLEGAL();
nkeynes@374
  1220
    } else {
nkeynes@374
  1221
	load_imm32( R_EDI, pc + 2 );
nkeynes@374
  1222
	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380
  1223
	JE_rel8( 5, nottaken );
nkeynes@374
  1224
	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380
  1225
	JMP_TARGET(nottaken);
nkeynes@374
  1226
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1227
	INC_r32(R_ESI);
nkeynes@374
  1228
	return 0;
nkeynes@374
  1229
    }
nkeynes@374
  1230
:}
nkeynes@374
  1231
JMP @Rn {:  
nkeynes@374
  1232
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1233
	SLOTILLEGAL();
nkeynes@374
  1234
    } else {
nkeynes@374
  1235
	load_reg( R_EDI, Rn );
nkeynes@374
  1236
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1237
	INC_r32(R_ESI);
nkeynes@374
  1238
	return 0;
nkeynes@374
  1239
    }
nkeynes@374
  1240
:}
nkeynes@374
  1241
JSR @Rn {:  
nkeynes@374
  1242
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1243
	SLOTILLEGAL();
nkeynes@374
  1244
    } else {
nkeynes@374
  1245
	load_imm32( R_EAX, pc + 4 );
nkeynes@374
  1246
	store_spreg( R_EAX, R_PR );
nkeynes@374
  1247
	load_reg( R_EDI, Rn );
nkeynes@374
  1248
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1249
	INC_r32(R_ESI);
nkeynes@374
  1250
	return 0;
nkeynes@374
  1251
    }
nkeynes@374
  1252
:}
nkeynes@374
  1253
RTE {:  
nkeynes@374
  1254
    check_priv();
nkeynes@374
  1255
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1256
	SLOTILLEGAL();
nkeynes@374
  1257
    } else {
nkeynes@374
  1258
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1259
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1260
	call_func1( sh4_write_sr, R_EAX );
nkeynes@374
  1261
	sh4_x86.in_delay_slot = TRUE;
nkeynes@377
  1262
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1263
	sh4_x86.fpuen_checked = FALSE;
nkeynes@374
  1264
	INC_r32(R_ESI);
nkeynes@374
  1265
	return 0;
nkeynes@374
  1266
    }
nkeynes@374
  1267
:}
nkeynes@374
  1268
RTS {:  
nkeynes@374
  1269
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1270
	SLOTILLEGAL();
nkeynes@374
  1271
    } else {
nkeynes@374
  1272
	load_spreg( R_EDI, R_PR );
nkeynes@374
  1273
	sh4_x86.in_delay_slot = TRUE;
nkeynes@374
  1274
	INC_r32(R_ESI);
nkeynes@374
  1275
	return 0;
nkeynes@374
  1276
    }
nkeynes@374
  1277
:}
nkeynes@374
  1278
TRAPA #imm {:  
nkeynes@374
  1279
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1280
	SLOTILLEGAL();
nkeynes@374
  1281
    } else {
nkeynes@374
  1282
	// TODO: Write TRA 
nkeynes@374
  1283
	RAISE_EXCEPTION(EXC_TRAP);
nkeynes@374
  1284
    }
nkeynes@374
  1285
:}
nkeynes@374
  1286
UNDEF {:  
nkeynes@374
  1287
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1288
	SLOTILLEGAL();
nkeynes@374
  1289
    } else {
nkeynes@374
  1290
	RAISE_EXCEPTION(EXC_ILLEGAL);
nkeynes@382
  1291
	return 1;
nkeynes@374
  1292
    }
nkeynes@368
  1293
:}
nkeynes@374
  1294
nkeynes@374
  1295
CLRMAC {:  
nkeynes@374
  1296
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1297
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1298
    store_spreg( R_EAX, R_MACH );
nkeynes@368
  1299
:}
nkeynes@374
  1300
CLRS {:
nkeynes@374
  1301
    CLC();
nkeynes@374
  1302
    SETC_sh4r(R_S);
nkeynes@368
  1303
:}
nkeynes@374
  1304
CLRT {:  
nkeynes@374
  1305
    CLC();
nkeynes@374
  1306
    SETC_t();
nkeynes@359
  1307
:}
nkeynes@374
  1308
SETS {:  
nkeynes@374
  1309
    STC();
nkeynes@374
  1310
    SETC_sh4r(R_S);
nkeynes@359
  1311
:}
nkeynes@374
  1312
SETT {:  
nkeynes@374
  1313
    STC();
nkeynes@374
  1314
    SETC_t();
nkeynes@374
  1315
:}
nkeynes@359
  1316
nkeynes@375
  1317
/* Floating point moves */
nkeynes@375
  1318
FMOV FRm, FRn {:  
nkeynes@375
  1319
    /* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375
  1320
     * 1. 32-bit fr-to-fr (PR=0)
nkeynes@375
  1321
     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375
  1322
     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375
  1323
     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375
  1324
     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375
  1325
     */
nkeynes@377
  1326
    check_fpuen();
nkeynes@375
  1327
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1328
    load_fr_bank( R_EDX );
nkeynes@375
  1329
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1330
    JNE_rel8(8, doublesize);
nkeynes@375
  1331
    load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375
  1332
    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1333
    if( FRm&1 ) {
nkeynes@380
  1334
	JMP_rel8(22, end);
nkeynes@380
  1335
	JMP_TARGET(doublesize);
nkeynes@375
  1336
	load_xf_bank( R_ECX ); 
nkeynes@375
  1337
	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375
  1338
	if( FRn&1 ) {
nkeynes@375
  1339
	    load_fr( R_ECX, R_EDX, FRm );
nkeynes@375
  1340
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1341
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@375
  1342
	} else /* FRn&1 == 0 */ {
nkeynes@375
  1343
	    load_fr( R_ECX, R_ECX, FRm );
nkeynes@375
  1344
	    store_fr( R_EDX, R_EAX, FRn-1 );
nkeynes@375
  1345
	    store_fr( R_EDX, R_ECX, FRn );
nkeynes@375
  1346
	}
nkeynes@380
  1347
	JMP_TARGET(end);
nkeynes@375
  1348
    } else /* FRm&1 == 0 */ {
nkeynes@375
  1349
	if( FRn&1 ) {
nkeynes@380
  1350
	    JMP_rel8(22, end);
nkeynes@375
  1351
	    load_xf_bank( R_ECX );
nkeynes@375
  1352
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1353
	    load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375
  1354
	    store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375
  1355
	    store_fr( R_ECX, R_EDX, FRn );
nkeynes@380
  1356
	    JMP_TARGET(end);
nkeynes@375
  1357
	} else /* FRn&1 == 0 */ {
nkeynes@380
  1358
	    JMP_rel8(12, end);
nkeynes@375
  1359
	    load_fr( R_EDX, R_EAX, FRm );
nkeynes@375
  1360
	    load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375
  1361
	    store_fr( R_EDX, R_EAX, FRn );
nkeynes@375
  1362
	    store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380
  1363
	    JMP_TARGET(end);
nkeynes@375
  1364
	}
nkeynes@375
  1365
    }
nkeynes@375
  1366
:}
nkeynes@375
  1367
FMOV FRm, @Rn {:  
nkeynes@377
  1368
    check_fpuen();
nkeynes@375
  1369
    load_reg( R_EDX, Rn );
nkeynes@375
  1370
    check_walign32( R_EDX );
nkeynes@375
  1371
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1372
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1373
    JNE_rel8(20, doublesize);
nkeynes@377
  1374
    load_fr_bank( R_ECX );
nkeynes@375
  1375
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@375
  1376
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375
  1377
    if( FRm&1 ) {
nkeynes@380
  1378
	JMP_rel8( 46, end );
nkeynes@380
  1379
	JMP_TARGET(doublesize);
nkeynes@375
  1380
	load_xf_bank( R_ECX );
nkeynes@380
  1381
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1382
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1383
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1384
	JMP_TARGET(end);
nkeynes@375
  1385
    } else {
nkeynes@380
  1386
	JMP_rel8( 39, end );
nkeynes@380
  1387
	JMP_TARGET(doublesize);
nkeynes@377
  1388
	load_fr_bank( R_ECX );
nkeynes@380
  1389
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1390
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1391
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1392
	JMP_TARGET(end);
nkeynes@375
  1393
    }
nkeynes@375
  1394
:}
nkeynes@375
  1395
FMOV @Rm, FRn {:  
nkeynes@377
  1396
    check_fpuen();
nkeynes@375
  1397
    load_reg( R_EDX, Rm );
nkeynes@375
  1398
    check_ralign32( R_EDX );
nkeynes@375
  1399
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1400
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1401
    JNE_rel8(19, doublesize);
nkeynes@375
  1402
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1403
    load_fr_bank( R_ECX );
nkeynes@375
  1404
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@375
  1405
    if( FRn&1 ) {
nkeynes@380
  1406
	JMP_rel8(46, end);
nkeynes@380
  1407
	JMP_TARGET(doublesize);
nkeynes@375
  1408
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375
  1409
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375
  1410
	load_xf_bank( R_ECX );
nkeynes@380
  1411
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1412
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1413
	JMP_TARGET(end);
nkeynes@375
  1414
    } else {
nkeynes@380
  1415
	JMP_rel8(36, end);
nkeynes@380
  1416
	JMP_TARGET(doublesize);
nkeynes@375
  1417
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1418
	load_fr_bank( R_ECX );
nkeynes@380
  1419
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1420
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1421
	JMP_TARGET(end);
nkeynes@375
  1422
    }
nkeynes@375
  1423
:}
nkeynes@377
  1424
FMOV FRm, @-Rn {:  
nkeynes@377
  1425
    check_fpuen();
nkeynes@377
  1426
    load_reg( R_EDX, Rn );
nkeynes@377
  1427
    check_walign32( R_EDX );
nkeynes@377
  1428
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1429
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@382
  1430
    JNE_rel8(26, doublesize);
nkeynes@377
  1431
    load_fr_bank( R_ECX );
nkeynes@377
  1432
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1433
    ADD_imm8s_r32(-4,R_EDX);
nkeynes@377
  1434
    store_reg( R_EDX, Rn );
nkeynes@377
  1435
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1436
    if( FRm&1 ) {
nkeynes@382
  1437
	JMP_rel8( 52, end );
nkeynes@380
  1438
	JMP_TARGET(doublesize);
nkeynes@377
  1439
	load_xf_bank( R_ECX );
nkeynes@380
  1440
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1441
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1442
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1443
	store_reg( R_EDX, Rn );
nkeynes@380
  1444
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1445
	JMP_TARGET(end);
nkeynes@377
  1446
    } else {
nkeynes@382
  1447
	JMP_rel8( 45, end );
nkeynes@380
  1448
	JMP_TARGET(doublesize);
nkeynes@377
  1449
	load_fr_bank( R_ECX );
nkeynes@380
  1450
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1451
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1452
	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380
  1453
	store_reg( R_EDX, Rn );
nkeynes@380
  1454
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1455
	JMP_TARGET(end);
nkeynes@377
  1456
    }
nkeynes@377
  1457
:}
nkeynes@377
  1458
FMOV @Rm+, FRn {:  
nkeynes@377
  1459
    check_fpuen();
nkeynes@377
  1460
    load_reg( R_EDX, Rm );
nkeynes@377
  1461
    check_ralign32( R_EDX );
nkeynes@377
  1462
    MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377
  1463
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1464
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1465
    JNE_rel8(25, doublesize);
nkeynes@377
  1466
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@377
  1467
    store_reg( R_EAX, Rm );
nkeynes@377
  1468
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1469
    load_fr_bank( R_ECX );
nkeynes@377
  1470
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1471
    if( FRn&1 ) {
nkeynes@380
  1472
	JMP_rel8(52, end);
nkeynes@380
  1473
	JMP_TARGET(doublesize);
nkeynes@377
  1474
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1475
	store_reg(R_EAX, Rm);
nkeynes@377
  1476
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1477
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1478
	load_xf_bank( R_ECX );
nkeynes@380
  1479
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1480
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1481
	JMP_TARGET(end);
nkeynes@377
  1482
    } else {
nkeynes@380
  1483
	JMP_rel8(42, end);
nkeynes@377
  1484
	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377
  1485
	store_reg(R_EAX, Rm);
nkeynes@377
  1486
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1487
	load_fr_bank( R_ECX );
nkeynes@380
  1488
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1489
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1490
	JMP_TARGET(end);
nkeynes@377
  1491
    }
nkeynes@377
  1492
:}
nkeynes@377
  1493
FMOV FRm, @(R0, Rn) {:  
nkeynes@377
  1494
    check_fpuen();
nkeynes@377
  1495
    load_reg( R_EDX, Rn );
nkeynes@377
  1496
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1497
    check_walign32( R_EDX );
nkeynes@377
  1498
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1499
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1500
    JNE_rel8(20, doublesize);
nkeynes@377
  1501
    load_fr_bank( R_ECX );
nkeynes@377
  1502
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1503
    MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377
  1504
    if( FRm&1 ) {
nkeynes@380
  1505
	JMP_rel8( 46, end );
nkeynes@380
  1506
	JMP_TARGET(doublesize);
nkeynes@377
  1507
	load_xf_bank( R_ECX );
nkeynes@380
  1508
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1509
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1510
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1511
	JMP_TARGET(end);
nkeynes@377
  1512
    } else {
nkeynes@380
  1513
	JMP_rel8( 39, end );
nkeynes@380
  1514
	JMP_TARGET(doublesize);
nkeynes@377
  1515
	load_fr_bank( R_ECX );
nkeynes@380
  1516
	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380
  1517
	load_fr( R_ECX, R_ECX, FRm|0x01 );
nkeynes@380
  1518
	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380
  1519
	JMP_TARGET(end);
nkeynes@377
  1520
    }
nkeynes@377
  1521
:}
nkeynes@377
  1522
FMOV @(R0, Rm), FRn {:  
nkeynes@377
  1523
    check_fpuen();
nkeynes@377
  1524
    load_reg( R_EDX, Rm );
nkeynes@377
  1525
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377
  1526
    check_ralign32( R_EDX );
nkeynes@377
  1527
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1528
    TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380
  1529
    JNE_rel8(19, doublesize);
nkeynes@377
  1530
    MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377
  1531
    load_fr_bank( R_ECX );
nkeynes@377
  1532
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1533
    if( FRn&1 ) {
nkeynes@380
  1534
	JMP_rel8(46, end);
nkeynes@380
  1535
	JMP_TARGET(doublesize);
nkeynes@377
  1536
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1537
	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377
  1538
	load_xf_bank( R_ECX );
nkeynes@380
  1539
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1540
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1541
	JMP_TARGET(end);
nkeynes@377
  1542
    } else {
nkeynes@380
  1543
	JMP_rel8(36, end);
nkeynes@380
  1544
	JMP_TARGET(doublesize);
nkeynes@377
  1545
	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377
  1546
	load_fr_bank( R_ECX );
nkeynes@380
  1547
	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380
  1548
	store_fr( R_ECX, R_EDX, FRn|0x01 );
nkeynes@380
  1549
	JMP_TARGET(end);
nkeynes@377
  1550
    }
nkeynes@377
  1551
:}
nkeynes@377
  1552
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@377
  1553
    check_fpuen();
nkeynes@377
  1554
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1555
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1556
    JNE_rel8(8, end);
nkeynes@377
  1557
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377
  1558
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1559
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1560
    JMP_TARGET(end);
nkeynes@377
  1561
:}
nkeynes@377
  1562
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@377
  1563
    check_fpuen();
nkeynes@377
  1564
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1565
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1566
    JNE_rel8(11, end);
nkeynes@377
  1567
    load_imm32(R_EAX, 0x3F800000);
nkeynes@377
  1568
    load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377
  1569
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@380
  1570
    JMP_TARGET(end);
nkeynes@377
  1571
:}
nkeynes@377
  1572
nkeynes@377
  1573
FLOAT FPUL, FRn {:  
nkeynes@377
  1574
    check_fpuen();
nkeynes@377
  1575
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1576
    load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377
  1577
    FILD_sh4r(R_FPUL);
nkeynes@377
  1578
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1579
    JNE_rel8(5, doubleprec);
nkeynes@377
  1580
    pop_fr( R_EDX, FRn );
nkeynes@380
  1581
    JMP_rel8(3, end);
nkeynes@380
  1582
    JMP_TARGET(doubleprec);
nkeynes@377
  1583
    pop_dr( R_EDX, FRn );
nkeynes@380
  1584
    JMP_TARGET(end);
nkeynes@377
  1585
:}
nkeynes@377
  1586
FTRC FRm, FPUL {:  
nkeynes@377
  1587
    check_fpuen();
nkeynes@377
  1588
    // TODO
nkeynes@377
  1589
:}
nkeynes@377
  1590
FLDS FRm, FPUL {:  
nkeynes@377
  1591
    check_fpuen();
nkeynes@377
  1592
    load_fr_bank( R_ECX );
nkeynes@377
  1593
    load_fr( R_ECX, R_EAX, FRm );
nkeynes@377
  1594
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  1595
:}
nkeynes@377
  1596
FSTS FPUL, FRn {:  
nkeynes@377
  1597
    check_fpuen();
nkeynes@377
  1598
    load_fr_bank( R_ECX );
nkeynes@377
  1599
    load_spreg( R_EAX, R_FPUL );
nkeynes@377
  1600
    store_fr( R_ECX, R_EAX, FRn );
nkeynes@377
  1601
:}
nkeynes@377
  1602
FCNVDS FRm, FPUL {:  
nkeynes@377
  1603
    check_fpuen();
nkeynes@377
  1604
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1605
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1606
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1607
    load_fr_bank( R_ECX );
nkeynes@377
  1608
    push_dr( R_ECX, FRm );
nkeynes@377
  1609
    pop_fpul();
nkeynes@380
  1610
    JMP_TARGET(end);
nkeynes@377
  1611
:}
nkeynes@377
  1612
FCNVSD FPUL, FRn {:  
nkeynes@377
  1613
    check_fpuen();
nkeynes@377
  1614
    check_fpuen();
nkeynes@377
  1615
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1616
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1617
    JE_rel8(9, end); // only when PR=1
nkeynes@377
  1618
    load_fr_bank( R_ECX );
nkeynes@377
  1619
    push_fpul();
nkeynes@377
  1620
    pop_dr( R_ECX, FRn );
nkeynes@380
  1621
    JMP_TARGET(end);
nkeynes@377
  1622
:}
nkeynes@375
  1623
nkeynes@359
  1624
/* Floating point instructions */
nkeynes@374
  1625
FABS FRn {:  
nkeynes@377
  1626
    check_fpuen();
nkeynes@374
  1627
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1628
    load_fr_bank( R_EDX );
nkeynes@374
  1629
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1630
    JNE_rel8(10, doubleprec);
nkeynes@374
  1631
    push_fr(R_EDX, FRn); // 3
nkeynes@374
  1632
    FABS_st0(); // 2
nkeynes@374
  1633
    pop_fr( R_EDX, FRn); //3
nkeynes@380
  1634
    JMP_rel8(8,end); // 2
nkeynes@380
  1635
    JMP_TARGET(doubleprec);
nkeynes@374
  1636
    push_dr(R_EDX, FRn);
nkeynes@374
  1637
    FABS_st0();
nkeynes@374
  1638
    pop_dr(R_EDX, FRn);
nkeynes@380
  1639
    JMP_TARGET(end);
nkeynes@374
  1640
:}
nkeynes@377
  1641
FADD FRm, FRn {:  
nkeynes@377
  1642
    check_fpuen();
nkeynes@375
  1643
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1644
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1645
    load_fr_bank( R_EDX );
nkeynes@380
  1646
    JNE_rel8(13,doubleprec);
nkeynes@377
  1647
    push_fr(R_EDX, FRm);
nkeynes@377
  1648
    push_fr(R_EDX, FRn);
nkeynes@377
  1649
    FADDP_st(1);
nkeynes@377
  1650
    pop_fr(R_EDX, FRn);
nkeynes@380
  1651
    JMP_rel8(11,end);
nkeynes@380
  1652
    JMP_TARGET(doubleprec);
nkeynes@377
  1653
    push_dr(R_EDX, FRm);
nkeynes@377
  1654
    push_dr(R_EDX, FRn);
nkeynes@377
  1655
    FADDP_st(1);
nkeynes@377
  1656
    pop_dr(R_EDX, FRn);
nkeynes@380
  1657
    JMP_TARGET(end);
nkeynes@375
  1658
:}
nkeynes@377
  1659
FDIV FRm, FRn {:  
nkeynes@377
  1660
    check_fpuen();
nkeynes@375
  1661
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1662
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1663
    load_fr_bank( R_EDX );
nkeynes@380
  1664
    JNE_rel8(13, doubleprec);
nkeynes@377
  1665
    push_fr(R_EDX, FRn);
nkeynes@377
  1666
    push_fr(R_EDX, FRm);
nkeynes@377
  1667
    FDIVP_st(1);
nkeynes@377
  1668
    pop_fr(R_EDX, FRn);
nkeynes@380
  1669
    JMP_rel8(11, end);
nkeynes@380
  1670
    JMP_TARGET(doubleprec);
nkeynes@377
  1671
    push_dr(R_EDX, FRn);
nkeynes@377
  1672
    push_dr(R_EDX, FRm);
nkeynes@377
  1673
    FDIVP_st(1);
nkeynes@377
  1674
    pop_dr(R_EDX, FRn);
nkeynes@380
  1675
    JMP_TARGET(end);
nkeynes@375
  1676
:}
nkeynes@375
  1677
FMAC FR0, FRm, FRn {:  
nkeynes@377
  1678
    check_fpuen();
nkeynes@375
  1679
    load_spreg( R_ECX, R_FPSCR );
nkeynes@375
  1680
    load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@375
  1681
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380
  1682
    JNE_rel8(18, doubleprec);
nkeynes@375
  1683
    push_fr( R_EDX, 0 );
nkeynes@375
  1684
    push_fr( R_EDX, FRm );
nkeynes@375
  1685
    FMULP_st(1);
nkeynes@375
  1686
    push_fr( R_EDX, FRn );
nkeynes@375
  1687
    FADDP_st(1);
nkeynes@375
  1688
    pop_fr( R_EDX, FRn );
nkeynes@380
  1689
    JMP_rel8(16, end);
nkeynes@380
  1690
    JMP_TARGET(doubleprec);
nkeynes@375
  1691
    push_dr( R_EDX, 0 );
nkeynes@375
  1692
    push_dr( R_EDX, FRm );
nkeynes@375
  1693
    FMULP_st(1);
nkeynes@375
  1694
    push_dr( R_EDX, FRn );
nkeynes@375
  1695
    FADDP_st(1);
nkeynes@375
  1696
    pop_dr( R_EDX, FRn );
nkeynes@380
  1697
    JMP_TARGET(end);
nkeynes@375
  1698
:}
nkeynes@375
  1699
nkeynes@377
  1700
FMUL FRm, FRn {:  
nkeynes@377
  1701
    check_fpuen();
nkeynes@377
  1702
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1703
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1704
    load_fr_bank( R_EDX );
nkeynes@380
  1705
    JNE_rel8(13, doubleprec);
nkeynes@377
  1706
    push_fr(R_EDX, FRm);
nkeynes@377
  1707
    push_fr(R_EDX, FRn);
nkeynes@377
  1708
    FMULP_st(1);
nkeynes@377
  1709
    pop_fr(R_EDX, FRn);
nkeynes@380
  1710
    JMP_rel8(11, end);
nkeynes@380
  1711
    JMP_TARGET(doubleprec);
nkeynes@377
  1712
    push_dr(R_EDX, FRm);
nkeynes@377
  1713
    push_dr(R_EDX, FRn);
nkeynes@377
  1714
    FMULP_st(1);
nkeynes@377
  1715
    pop_dr(R_EDX, FRn);
nkeynes@380
  1716
    JMP_TARGET(end);
nkeynes@377
  1717
:}
nkeynes@377
  1718
FNEG FRn {:  
nkeynes@377
  1719
    check_fpuen();
nkeynes@377
  1720
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1721
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1722
    load_fr_bank( R_EDX );
nkeynes@380
  1723
    JNE_rel8(10, doubleprec);
nkeynes@377
  1724
    push_fr(R_EDX, FRn);
nkeynes@377
  1725
    FCHS_st0();
nkeynes@377
  1726
    pop_fr(R_EDX, FRn);
nkeynes@380
  1727
    JMP_rel8(8, end);
nkeynes@380
  1728
    JMP_TARGET(doubleprec);
nkeynes@377
  1729
    push_dr(R_EDX, FRn);
nkeynes@377
  1730
    FCHS_st0();
nkeynes@377
  1731
    pop_dr(R_EDX, FRn);
nkeynes@380
  1732
    JMP_TARGET(end);
nkeynes@377
  1733
:}
nkeynes@377
  1734
FSRRA FRn {:  
nkeynes@377
  1735
    check_fpuen();
nkeynes@377
  1736
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1737
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1738
    load_fr_bank( R_EDX );
nkeynes@380
  1739
    JNE_rel8(12, end); // PR=0 only
nkeynes@377
  1740
    FLD1_st0();
nkeynes@377
  1741
    push_fr(R_EDX, FRn);
nkeynes@377
  1742
    FSQRT_st0();
nkeynes@377
  1743
    FDIVP_st(1);
nkeynes@377
  1744
    pop_fr(R_EDX, FRn);
nkeynes@380
  1745
    JMP_TARGET(end);
nkeynes@377
  1746
:}
nkeynes@377
  1747
FSQRT FRn {:  
nkeynes@377
  1748
    check_fpuen();
nkeynes@377
  1749
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1750
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1751
    load_fr_bank( R_EDX );
nkeynes@380
  1752
    JNE_rel8(10, doubleprec);
nkeynes@377
  1753
    push_fr(R_EDX, FRn);
nkeynes@377
  1754
    FSQRT_st0();
nkeynes@377
  1755
    pop_fr(R_EDX, FRn);
nkeynes@380
  1756
    JMP_rel8(8, end);
nkeynes@380
  1757
    JMP_TARGET(doubleprec);
nkeynes@377
  1758
    push_dr(R_EDX, FRn);
nkeynes@377
  1759
    FSQRT_st0();
nkeynes@377
  1760
    pop_dr(R_EDX, FRn);
nkeynes@380
  1761
    JMP_TARGET(end);
nkeynes@377
  1762
:}
nkeynes@377
  1763
FSUB FRm, FRn {:  
nkeynes@377
  1764
    check_fpuen();
nkeynes@377
  1765
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1766
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1767
    load_fr_bank( R_EDX );
nkeynes@380
  1768
    JNE_rel8(13, doubleprec);
nkeynes@377
  1769
    push_fr(R_EDX, FRn);
nkeynes@377
  1770
    push_fr(R_EDX, FRm);
nkeynes@377
  1771
    FMULP_st(1);
nkeynes@377
  1772
    pop_fr(R_EDX, FRn);
nkeynes@380
  1773
    JMP_rel8(11, end);
nkeynes@380
  1774
    JMP_TARGET(doubleprec);
nkeynes@377
  1775
    push_dr(R_EDX, FRn);
nkeynes@377
  1776
    push_dr(R_EDX, FRm);
nkeynes@377
  1777
    FMULP_st(1);
nkeynes@377
  1778
    pop_dr(R_EDX, FRn);
nkeynes@380
  1779
    JMP_TARGET(end);
nkeynes@377
  1780
:}
nkeynes@377
  1781
nkeynes@377
  1782
FCMP/EQ FRm, FRn {:  
nkeynes@377
  1783
    check_fpuen();
nkeynes@377
  1784
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1785
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1786
    load_fr_bank( R_EDX );
nkeynes@380
  1787
    JNE_rel8(8, doubleprec);
nkeynes@377
  1788
    push_fr(R_EDX, FRm);
nkeynes@377
  1789
    push_fr(R_EDX, FRn);
nkeynes@380
  1790
    JMP_rel8(6, end);
nkeynes@380
  1791
    JMP_TARGET(doubleprec);
nkeynes@377
  1792
    push_dr(R_EDX, FRm);
nkeynes@377
  1793
    push_dr(R_EDX, FRn);
nkeynes@382
  1794
    JMP_TARGET(end);
nkeynes@377
  1795
    FCOMIP_st(1);
nkeynes@377
  1796
    SETE_t();
nkeynes@377
  1797
    FPOP_st();
nkeynes@377
  1798
:}
nkeynes@377
  1799
FCMP/GT FRm, FRn {:  
nkeynes@377
  1800
    check_fpuen();
nkeynes@377
  1801
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1802
    TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377
  1803
    load_fr_bank( R_EDX );
nkeynes@380
  1804
    JNE_rel8(8, doubleprec);
nkeynes@377
  1805
    push_fr(R_EDX, FRm);
nkeynes@377
  1806
    push_fr(R_EDX, FRn);
nkeynes@380
  1807
    JMP_rel8(6, end);
nkeynes@380
  1808
    JMP_TARGET(doubleprec);
nkeynes@377
  1809
    push_dr(R_EDX, FRm);
nkeynes@377
  1810
    push_dr(R_EDX, FRn);
nkeynes@380
  1811
    JMP_TARGET(end);
nkeynes@377
  1812
    FCOMIP_st(1);
nkeynes@377
  1813
    SETA_t();
nkeynes@377
  1814
    FPOP_st();
nkeynes@377
  1815
:}
nkeynes@377
  1816
nkeynes@377
  1817
FSCA FPUL, FRn {:  
nkeynes@377
  1818
    check_fpuen();
nkeynes@377
  1819
:}
nkeynes@377
  1820
FIPR FVm, FVn {:  
nkeynes@377
  1821
    check_fpuen();
nkeynes@377
  1822
:}
nkeynes@377
  1823
FTRV XMTRX, FVn {:  
nkeynes@377
  1824
    check_fpuen();
nkeynes@377
  1825
:}
nkeynes@377
  1826
nkeynes@377
  1827
FRCHG {:  
nkeynes@377
  1828
    check_fpuen();
nkeynes@377
  1829
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1830
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  1831
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1832
    
nkeynes@377
  1833
:}
nkeynes@377
  1834
FSCHG {:  
nkeynes@377
  1835
    check_fpuen();
nkeynes@377
  1836
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1837
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  1838
    store_spreg( R_ECX, R_FPSCR );
nkeynes@377
  1839
:}
nkeynes@359
  1840
nkeynes@359
  1841
/* Processor control instructions */
nkeynes@368
  1842
LDC Rm, SR {:
nkeynes@368
  1843
    load_reg( R_EAX, Rm );
nkeynes@374
  1844
    call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1845
    sh4_x86.priv_checked = FALSE;
nkeynes@377
  1846
    sh4_x86.fpuen_checked = FALSE;
nkeynes@368
  1847
:}
nkeynes@359
  1848
LDC Rm, GBR {: 
nkeynes@359
  1849
    load_reg( R_EAX, Rm );
nkeynes@359
  1850
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1851
:}
nkeynes@359
  1852
LDC Rm, VBR {:  
nkeynes@359
  1853
    load_reg( R_EAX, Rm );
nkeynes@359
  1854
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1855
:}
nkeynes@359
  1856
LDC Rm, SSR {:  
nkeynes@359
  1857
    load_reg( R_EAX, Rm );
nkeynes@359
  1858
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1859
:}
nkeynes@359
  1860
LDC Rm, SGR {:  
nkeynes@359
  1861
    load_reg( R_EAX, Rm );
nkeynes@359
  1862
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1863
:}
nkeynes@359
  1864
LDC Rm, SPC {:  
nkeynes@359
  1865
    load_reg( R_EAX, Rm );
nkeynes@359
  1866
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1867
:}
nkeynes@359
  1868
LDC Rm, DBR {:  
nkeynes@359
  1869
    load_reg( R_EAX, Rm );
nkeynes@359
  1870
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1871
:}
nkeynes@374
  1872
LDC Rm, Rn_BANK {:  
nkeynes@374
  1873
    load_reg( R_EAX, Rm );
nkeynes@374
  1874
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@374
  1875
:}
nkeynes@359
  1876
LDC.L @Rm+, GBR {:  
nkeynes@359
  1877
    load_reg( R_EAX, Rm );
nkeynes@359
  1878
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1879
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1880
    store_reg( R_EAX, Rm );
nkeynes@359
  1881
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1882
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  1883
:}
nkeynes@368
  1884
LDC.L @Rm+, SR {:
nkeynes@368
  1885
    load_reg( R_EAX, Rm );
nkeynes@368
  1886
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@368
  1887
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@368
  1888
    store_reg( R_EAX, Rm );
nkeynes@368
  1889
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1890
    call_func1( sh4_write_sr, R_EAX );
nkeynes@377
  1891
    sh4_x86.priv_checked = FALSE;
nkeynes@377
  1892
    sh4_x86.fpuen_checked = FALSE;
nkeynes@359
  1893
:}
nkeynes@359
  1894
LDC.L @Rm+, VBR {:  
nkeynes@359
  1895
    load_reg( R_EAX, Rm );
nkeynes@359
  1896
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1897
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1898
    store_reg( R_EAX, Rm );
nkeynes@359
  1899
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1900
    store_spreg( R_EAX, R_VBR );
nkeynes@359
  1901
:}
nkeynes@359
  1902
LDC.L @Rm+, SSR {:
nkeynes@359
  1903
    load_reg( R_EAX, Rm );
nkeynes@359
  1904
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1905
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1906
    store_reg( R_EAX, Rm );
nkeynes@359
  1907
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1908
    store_spreg( R_EAX, R_SSR );
nkeynes@359
  1909
:}
nkeynes@359
  1910
LDC.L @Rm+, SGR {:  
nkeynes@359
  1911
    load_reg( R_EAX, Rm );
nkeynes@359
  1912
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1913
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1914
    store_reg( R_EAX, Rm );
nkeynes@359
  1915
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1916
    store_spreg( R_EAX, R_SGR );
nkeynes@359
  1917
:}
nkeynes@359
  1918
LDC.L @Rm+, SPC {:  
nkeynes@359
  1919
    load_reg( R_EAX, Rm );
nkeynes@359
  1920
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1921
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1922
    store_reg( R_EAX, Rm );
nkeynes@359
  1923
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1924
    store_spreg( R_EAX, R_SPC );
nkeynes@359
  1925
:}
nkeynes@359
  1926
LDC.L @Rm+, DBR {:  
nkeynes@359
  1927
    load_reg( R_EAX, Rm );
nkeynes@359
  1928
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1929
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1930
    store_reg( R_EAX, Rm );
nkeynes@359
  1931
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1932
    store_spreg( R_EAX, R_DBR );
nkeynes@359
  1933
:}
nkeynes@359
  1934
LDC.L @Rm+, Rn_BANK {:  
nkeynes@374
  1935
    load_reg( R_EAX, Rm );
nkeynes@374
  1936
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374
  1937
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@374
  1938
    store_reg( R_EAX, Rm );
nkeynes@374
  1939
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374
  1940
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359
  1941
:}
nkeynes@359
  1942
LDS Rm, FPSCR {:  
nkeynes@359
  1943
    load_reg( R_EAX, Rm );
nkeynes@359
  1944
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1945
:}
nkeynes@359
  1946
LDS.L @Rm+, FPSCR {:  
nkeynes@359
  1947
    load_reg( R_EAX, Rm );
nkeynes@359
  1948
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1949
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1950
    store_reg( R_EAX, Rm );
nkeynes@359
  1951
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1952
    store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1953
:}
nkeynes@359
  1954
LDS Rm, FPUL {:  
nkeynes@359
  1955
    load_reg( R_EAX, Rm );
nkeynes@359
  1956
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1957
:}
nkeynes@359
  1958
LDS.L @Rm+, FPUL {:  
nkeynes@359
  1959
    load_reg( R_EAX, Rm );
nkeynes@359
  1960
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1961
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1962
    store_reg( R_EAX, Rm );
nkeynes@359
  1963
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1964
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1965
:}
nkeynes@359
  1966
LDS Rm, MACH {: 
nkeynes@359
  1967
    load_reg( R_EAX, Rm );
nkeynes@359
  1968
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1969
:}
nkeynes@359
  1970
LDS.L @Rm+, MACH {:  
nkeynes@359
  1971
    load_reg( R_EAX, Rm );
nkeynes@359
  1972
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1973
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1974
    store_reg( R_EAX, Rm );
nkeynes@359
  1975
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1976
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  1977
:}
nkeynes@359
  1978
LDS Rm, MACL {:  
nkeynes@359
  1979
    load_reg( R_EAX, Rm );
nkeynes@359
  1980
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1981
:}
nkeynes@359
  1982
LDS.L @Rm+, MACL {:  
nkeynes@359
  1983
    load_reg( R_EAX, Rm );
nkeynes@359
  1984
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1985
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1986
    store_reg( R_EAX, Rm );
nkeynes@359
  1987
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1988
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  1989
:}
nkeynes@359
  1990
LDS Rm, PR {:  
nkeynes@359
  1991
    load_reg( R_EAX, Rm );
nkeynes@359
  1992
    store_spreg( R_EAX, R_PR );
nkeynes@359
  1993
:}
nkeynes@359
  1994
LDS.L @Rm+, PR {:  
nkeynes@359
  1995
    load_reg( R_EAX, Rm );
nkeynes@359
  1996
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1997
    ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1998
    store_reg( R_EAX, Rm );
nkeynes@359
  1999
    MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  2000
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2001
:}
nkeynes@359
  2002
LDTLB {:  :}
nkeynes@359
  2003
OCBI @Rn {:  :}
nkeynes@359
  2004
OCBP @Rn {:  :}
nkeynes@359
  2005
OCBWB @Rn {:  :}
nkeynes@374
  2006
PREF @Rn {:
nkeynes@374
  2007
    load_reg( R_EAX, Rn );
nkeynes@374
  2008
    PUSH_r32( R_EAX );
nkeynes@374
  2009
    AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374
  2010
    CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380
  2011
    JNE_rel8(7, end);
nkeynes@374
  2012
    call_func0( sh4_flush_store_queue );
nkeynes@380
  2013
    JMP_TARGET(end);
nkeynes@377
  2014
    ADD_imm8s_r32( 4, R_ESP );
nkeynes@374
  2015
:}
nkeynes@374
  2016
 SLEEP {: /* TODO */ :}
nkeynes@368
  2017
 STC SR, Rn {:
nkeynes@374
  2018
     call_func0(sh4_read_sr);
nkeynes@368
  2019
     store_reg( R_EAX, Rn );
nkeynes@359
  2020
:}
nkeynes@359
  2021
STC GBR, Rn {:  
nkeynes@359
  2022
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2023
    store_reg( R_EAX, Rn );
nkeynes@359
  2024
:}
nkeynes@359
  2025
STC VBR, Rn {:  
nkeynes@359
  2026
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2027
    store_reg( R_EAX, Rn );
nkeynes@359
  2028
:}
nkeynes@359
  2029
STC SSR, Rn {:  
nkeynes@359
  2030
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2031
    store_reg( R_EAX, Rn );
nkeynes@359
  2032
:}
nkeynes@359
  2033
STC SPC, Rn {:  
nkeynes@359
  2034
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2035
    store_reg( R_EAX, Rn );
nkeynes@359
  2036
:}
nkeynes@359
  2037
STC SGR, Rn {:  
nkeynes@359
  2038
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2039
    store_reg( R_EAX, Rn );
nkeynes@359
  2040
:}
nkeynes@359
  2041
STC DBR, Rn {:  
nkeynes@359
  2042
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2043
    store_reg( R_EAX, Rn );
nkeynes@359
  2044
:}
nkeynes@374
  2045
STC Rm_BANK, Rn {:
nkeynes@374
  2046
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2047
    store_reg( R_EAX, Rn );
nkeynes@359
  2048
:}
nkeynes@374
  2049
STC.L SR, @-Rn {:
nkeynes@368
  2050
    load_reg( R_ECX, Rn );
nkeynes@382
  2051
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@368
  2052
    store_reg( R_ECX, Rn );
nkeynes@374
  2053
    call_func0( sh4_read_sr );
nkeynes@368
  2054
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2055
:}
nkeynes@359
  2056
STC.L VBR, @-Rn {:  
nkeynes@359
  2057
    load_reg( R_ECX, Rn );
nkeynes@382
  2058
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2059
    store_reg( R_ECX, Rn );
nkeynes@359
  2060
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2061
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2062
:}
nkeynes@359
  2063
STC.L SSR, @-Rn {:  
nkeynes@359
  2064
    load_reg( R_ECX, Rn );
nkeynes@382
  2065
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2066
    store_reg( R_ECX, Rn );
nkeynes@359
  2067
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2068
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2069
:}
nkeynes@359
  2070
STC.L SPC, @-Rn {:  
nkeynes@359
  2071
    load_reg( R_ECX, Rn );
nkeynes@382
  2072
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2073
    store_reg( R_ECX, Rn );
nkeynes@359
  2074
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2075
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2076
:}
nkeynes@359
  2077
STC.L SGR, @-Rn {:  
nkeynes@359
  2078
    load_reg( R_ECX, Rn );
nkeynes@382
  2079
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2080
    store_reg( R_ECX, Rn );
nkeynes@359
  2081
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2082
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2083
:}
nkeynes@359
  2084
STC.L DBR, @-Rn {:  
nkeynes@359
  2085
    load_reg( R_ECX, Rn );
nkeynes@382
  2086
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2087
    store_reg( R_ECX, Rn );
nkeynes@359
  2088
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2089
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2090
:}
nkeynes@374
  2091
STC.L Rm_BANK, @-Rn {:  
nkeynes@374
  2092
    load_reg( R_ECX, Rn );
nkeynes@382
  2093
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@374
  2094
    store_reg( R_ECX, Rn );
nkeynes@374
  2095
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2096
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@374
  2097
:}
nkeynes@359
  2098
STC.L GBR, @-Rn {:  
nkeynes@359
  2099
    load_reg( R_ECX, Rn );
nkeynes@382
  2100
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2101
    store_reg( R_ECX, Rn );
nkeynes@359
  2102
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2103
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2104
:}
nkeynes@359
  2105
STS FPSCR, Rn {:  
nkeynes@359
  2106
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2107
    store_reg( R_EAX, Rn );
nkeynes@359
  2108
:}
nkeynes@359
  2109
STS.L FPSCR, @-Rn {:  
nkeynes@359
  2110
    load_reg( R_ECX, Rn );
nkeynes@382
  2111
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2112
    store_reg( R_ECX, Rn );
nkeynes@359
  2113
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2114
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2115
:}
nkeynes@359
  2116
STS FPUL, Rn {:  
nkeynes@359
  2117
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2118
    store_reg( R_EAX, Rn );
nkeynes@359
  2119
:}
nkeynes@359
  2120
STS.L FPUL, @-Rn {:  
nkeynes@359
  2121
    load_reg( R_ECX, Rn );
nkeynes@382
  2122
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2123
    store_reg( R_ECX, Rn );
nkeynes@359
  2124
    load_spreg( R_EAX, R_FPUL );
nkeynes@359
  2125
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2126
:}
nkeynes@359
  2127
STS MACH, Rn {:  
nkeynes@359
  2128
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2129
    store_reg( R_EAX, Rn );
nkeynes@359
  2130
:}
nkeynes@359
  2131
STS.L MACH, @-Rn {:  
nkeynes@359
  2132
    load_reg( R_ECX, Rn );
nkeynes@382
  2133
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2134
    store_reg( R_ECX, Rn );
nkeynes@359
  2135
    load_spreg( R_EAX, R_MACH );
nkeynes@359
  2136
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2137
:}
nkeynes@359
  2138
STS MACL, Rn {:  
nkeynes@359
  2139
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2140
    store_reg( R_EAX, Rn );
nkeynes@359
  2141
:}
nkeynes@359
  2142
STS.L MACL, @-Rn {:  
nkeynes@359
  2143
    load_reg( R_ECX, Rn );
nkeynes@382
  2144
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2145
    store_reg( R_ECX, Rn );
nkeynes@359
  2146
    load_spreg( R_EAX, R_MACL );
nkeynes@359
  2147
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2148
:}
nkeynes@359
  2149
STS PR, Rn {:  
nkeynes@359
  2150
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2151
    store_reg( R_EAX, Rn );
nkeynes@359
  2152
:}
nkeynes@359
  2153
STS.L PR, @-Rn {:  
nkeynes@359
  2154
    load_reg( R_ECX, Rn );
nkeynes@382
  2155
    ADD_imm8s_r32( -4, R_ECX );
nkeynes@359
  2156
    store_reg( R_ECX, Rn );
nkeynes@359
  2157
    load_spreg( R_EAX, R_PR );
nkeynes@359
  2158
    MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  2159
:}
nkeynes@359
  2160
nkeynes@359
  2161
NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
nkeynes@359
  2162
%%
nkeynes@368
  2163
    INC_r32(R_ESI);
nkeynes@374
  2164
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  2165
	sh4_x86.in_delay_slot = FALSE;
nkeynes@374
  2166
	return 1;
nkeynes@374
  2167
    }
nkeynes@359
  2168
    return 0;
nkeynes@359
  2169
}
.