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lxdream.org :: lxdream/src/sh4/mmu.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 929:fd8cb0c82f5f
prev927:17b6b9e245d8
next931:430048ea8b71
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * MMU implementation
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE sh4_module
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#include <stdio.h>
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#include <assert.h>
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "mem.h"
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#ifdef HAVE_FRAME_ADDRESS
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#define RETURN_VIA(exc) do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
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#else
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#define RETURN_VIA(exc) return MMU_VMA_ERROR
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#endif
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#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
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/* The MMU (practically unique in the system) is allowed to raise exceptions
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 * directly, with a return code indicating that one was raised and the caller
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 * had better behave appropriately.
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 */
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#define RAISE_TLB_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_tlb_exception(code);
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#define RAISE_MEM_ERROR(code, vpn) \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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    sh4_raise_exception(code);
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#define RAISE_OTHER_ERROR(code) \
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    sh4_raise_exception(code);
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/**
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 * Abort with a non-MMU address error. Caused by user-mode code attempting
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 * to access privileged regions, or alignment faults.
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 */
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#define MMU_READ_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_READ)
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#define MMU_WRITE_ADDR_ERROR() RAISE_OTHER_ERROR(EXC_DATA_ADDR_WRITE)
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#define MMU_TLB_READ_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_READ, vpn)
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#define MMU_TLB_WRITE_MISS_ERROR(vpn) RAISE_TLB_ERROR(EXC_TLB_MISS_WRITE, vpn)
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#define MMU_TLB_INITIAL_WRITE_ERROR(vpn) RAISE_MEM_ERROR(EXC_INIT_PAGE_WRITE, vpn)
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#define MMU_TLB_READ_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_READ, vpn)
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#define MMU_TLB_WRITE_PROT_ERROR(vpn) RAISE_MEM_ERROR(EXC_TLB_PROT_WRITE, vpn)
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#define MMU_TLB_MULTI_HIT_ERROR(vpn) sh4_raise_reset(EXC_TLB_MULTI_HIT); \
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    MMIO_WRITE(MMU, TEA, vpn); \
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    MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)));
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#define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
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#define OCRAM_END   (0x20000000>>LXDREAM_PAGE_BITS)
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#define ITLB_ENTRY_COUNT 4
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#define UTLB_ENTRY_COUNT 64
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/* Entry address */
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#define TLB_VALID     0x00000100
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#define TLB_USERMODE  0x00000040
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#define TLB_WRITABLE  0x00000020
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#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
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#define TLB_SIZE_MASK 0x00000090
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#define TLB_SIZE_1K   0x00000000
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#define TLB_SIZE_4K   0x00000010
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#define TLB_SIZE_64K  0x00000080
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#define TLB_SIZE_1M   0x00000090
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#define TLB_CACHEABLE 0x00000008
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#define TLB_DIRTY     0x00000004
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#define TLB_SHARE     0x00000002
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#define TLB_WRITETHRU 0x00000001
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#define MASK_1K  0xFFFFFC00
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#define MASK_4K  0xFFFFF000
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#define MASK_64K 0xFFFF0000
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#define MASK_1M  0xFFF00000
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struct itlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t asid; // Process ID
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    uint32_t mask;
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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};
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struct utlb_entry {
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    sh4addr_t vpn; // Virtual Page Number
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    uint32_t mask; // Page size mask
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    uint32_t asid; // Process ID
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    sh4addr_t ppn; // Physical Page Number
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    uint32_t flags;
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    uint32_t pcmcia; // extra pcmcia data - not used
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};
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struct utlb_sort_entry {
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    sh4addr_t key; // Masked VPN + ASID
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    uint32_t mask; // Mask + 0x00FF
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    int entryNo;
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};
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static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
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static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
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static uint32_t mmu_urc;
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static uint32_t mmu_urb;
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static uint32_t mmu_lrui;
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static uint32_t mmu_asid; // current asid
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static struct utlb_sort_entry mmu_utlb_sorted[UTLB_ENTRY_COUNT];
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static uint32_t mmu_utlb_entries; // Number of entries in mmu_utlb_sorted. 
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static sh4ptr_t cache = NULL;
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static void mmu_invalidate_tlb();
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static void mmu_utlb_sorted_reset();
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static void mmu_utlb_sorted_reload(); 
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static uint32_t get_mask_for_flags( uint32_t flags )
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{
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    switch( flags & TLB_SIZE_MASK ) {
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    case TLB_SIZE_1K: return MASK_1K;
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    case TLB_SIZE_4K: return MASK_4K;
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    case TLB_SIZE_64K: return MASK_64K;
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    case TLB_SIZE_1M: return MASK_1M;
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    default: return 0; /* Unreachable */
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    }
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}
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MMIO_REGION_READ_FN( MMU, reg )
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{
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    reg &= 0xFFF;
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    switch( reg ) {
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    case MMUCR:
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        return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
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    default:
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        return MMIO_READ( MMU, reg );
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    }
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}
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MMIO_REGION_WRITE_FN( MMU, reg, val )
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{
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    uint32_t tmp;
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    reg &= 0xFFF;
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    switch(reg) {
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    case SH4VER:
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        return;
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    case PTEH:
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        val &= 0xFFFFFCFF;
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        if( (val & 0xFF) != mmu_asid ) {
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            mmu_asid = val&0xFF;
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            sh4_icache.page_vma = -1; // invalidate icache as asid has changed
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        }
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        break;
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    case PTEL:
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        val &= 0x1FFFFDFF;
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        break;
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    case PTEA:
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        val &= 0x0000000F;
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        break;
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    case TRA:
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    	val &= 0x000003FC;
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    	break;
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    case EXPEVT:
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    case INTEVT:
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    	val &= 0x00000FFF;
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    	break;
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    case MMUCR:
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        if( val & MMUCR_TI ) {
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            mmu_invalidate_tlb();
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        }
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        mmu_urc = (val >> 10) & 0x3F;
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        mmu_urb = (val >> 18) & 0x3F;
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        mmu_lrui = (val >> 26) & 0x3F;
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        val &= 0x00000301;
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        tmp = MMIO_READ( MMU, MMUCR );
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        if( (val ^ tmp) & (MMUCR_AT|MMUCR_SV) ) {
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            // AT flag has changed state - flush the xlt cache as all bets
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            // are off now. We also need to force an immediate exit from the
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            // current block
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            MMIO_WRITE( MMU, MMUCR, val );
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            sh4_flush_icache();
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        }
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        break;
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    case CCR:
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        mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
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        val &= 0x81A7;
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        break;
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    case MMUUNK1:
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    	/* Note that if the high bit is set, this appears to reset the machine.
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    	 * Not emulating this behaviour yet until we know why...
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    	 */
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    	val &= 0x00010007;
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    	break;
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    case QACR0:
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    case QACR1:
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    	val &= 0x0000001C;
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    	break;
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    case PMCR1:
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        PMM_write_control(0, val);
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        val &= 0x0000C13F;
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        break;
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    case PMCR2:
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        PMM_write_control(1, val);
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        val &= 0x0000C13F;
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        break;
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    default:
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        break;
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    }
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    MMIO_WRITE( MMU, reg, val );
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}
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void MMU_init()
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{
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    cache = mem_alloc_pages(2);
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}
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void MMU_reset()
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{
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    mmio_region_MMU_write( CCR, 0 );
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    mmio_region_MMU_write( MMUCR, 0 );
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    mmu_utlb_sorted_reload();
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}
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void MMU_save_state( FILE *f )
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{
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    fwrite( cache, 4096, 2, f );
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    fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
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    fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
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    fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
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    fwrite( &mmu_urb, sizeof(mmu_urb), 1, f );
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    fwrite( &mmu_lrui, sizeof(mmu_lrui), 1, f );
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    fwrite( &mmu_asid, sizeof(mmu_asid), 1, f );
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}
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int MMU_load_state( FILE *f )
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{
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    /* Setup the cache mode according to the saved register value
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     * (mem_load runs before this point to load all MMIO data)
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     */
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    mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
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    if( fread( cache, 4096, 2, f ) != 2 ) {
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        return 1;
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    }
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    if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urc), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_urc, sizeof(mmu_urb), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_lrui, sizeof(mmu_lrui), 1, f ) != 1 ) {
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        return 1;
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    }
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    if( fread( &mmu_asid, sizeof(mmu_asid), 1, f ) != 1 ) {
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        return 1;
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   279
    }
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    mmu_utlb_sorted_reload();
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   281
    return 0;
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   282
}
nkeynes@550
   283
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   284
void mmu_set_cache_mode( int mode )
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   285
{
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   286
    uint32_t i;
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   287
    switch( mode ) {
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   288
    case MEM_OC_INDEX0: /* OIX=0 */
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   289
        for( i=OCRAM_START; i<OCRAM_END; i++ )
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   290
            page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
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   291
        break;
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   292
    case MEM_OC_INDEX1: /* OIX=1 */
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   293
        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
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   295
        break;
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   296
    default: /* disabled */
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   297
        for( i=OCRAM_START; i<OCRAM_END; i++ )
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            page_map[i] = NULL;
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   299
        break;
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   300
    }
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   301
}
nkeynes@550
   302
nkeynes@915
   303
/******************* Sorted TLB data structure ****************/
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   304
/*
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   305
 * mmu_utlb_sorted maintains a list of all active (valid) entries,
nkeynes@915
   306
 * sorted by masked VPN and then ASID. Multi-hit entries are resolved 
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   307
 * ahead of time, and have -1 recorded as the corresponding PPN.
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 * 
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   309
 * FIXME: Multi-hit detection doesn't pick up cases where two pages 
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   310
 * overlap due to different sizes (and don't share the same base
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   311
 * address). 
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   312
 */ 
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   313
static void mmu_utlb_sorted_reset() 
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   314
{
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   315
    mmu_utlb_entries = 0;
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   316
}
nkeynes@915
   317
nkeynes@915
   318
/**
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   319
 * Find an entry in the sorted table (VPN+ASID check). 
nkeynes@915
   320
 */
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   321
static inline int mmu_utlb_sorted_find( sh4addr_t vma )
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   322
{
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   323
    int low = 0;
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   324
    int high = mmu_utlb_entries;
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   325
    uint32_t lookup = (vma & 0xFFFFFC00) + mmu_asid;
nkeynes@915
   326
nkeynes@915
   327
    mmu_urc++;
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   328
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
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   329
        mmu_urc = 0;
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   330
    }
nkeynes@915
   331
nkeynes@915
   332
    while( low != high ) {
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   333
        int posn = (high+low)>>1;
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   334
        int masked = lookup & mmu_utlb_sorted[posn].mask;
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   335
        if( mmu_utlb_sorted[posn].key < masked ) {
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   336
            low = posn+1;
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   337
        } else if( mmu_utlb_sorted[posn].key > masked ) {
nkeynes@915
   338
            high = posn;
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   339
        } else {
nkeynes@915
   340
            return mmu_utlb_sorted[posn].entryNo;
nkeynes@915
   341
        }
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   342
    }
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   343
    return -1;
nkeynes@915
   344
nkeynes@915
   345
}
nkeynes@915
   346
nkeynes@915
   347
static void mmu_utlb_insert_entry( int entry )
nkeynes@915
   348
{
nkeynes@915
   349
    int low = 0;
nkeynes@915
   350
    int high = mmu_utlb_entries;
nkeynes@915
   351
    uint32_t key = (mmu_utlb[entry].vpn & mmu_utlb[entry].mask) + mmu_utlb[entry].asid;
nkeynes@915
   352
nkeynes@915
   353
    assert( mmu_utlb_entries < UTLB_ENTRY_COUNT );
nkeynes@915
   354
    /* Find the insertion point */
nkeynes@915
   355
    while( low != high ) {
nkeynes@915
   356
        int posn = (high+low)>>1;
nkeynes@915
   357
        if( mmu_utlb_sorted[posn].key < key ) {
nkeynes@915
   358
            low = posn+1;
nkeynes@915
   359
        } else if( mmu_utlb_sorted[posn].key > key ) {
nkeynes@915
   360
            high = posn;
nkeynes@915
   361
        } else {
nkeynes@915
   362
            /* Exact match - multi-hit */
nkeynes@915
   363
            mmu_utlb_sorted[posn].entryNo = -2;
nkeynes@915
   364
            return;
nkeynes@915
   365
        }
nkeynes@915
   366
    } /* 0 2 4 6 */
nkeynes@915
   367
    memmove( &mmu_utlb_sorted[low+1], &mmu_utlb_sorted[low], 
nkeynes@915
   368
             (mmu_utlb_entries - low) * sizeof(struct utlb_sort_entry) );
nkeynes@915
   369
    mmu_utlb_sorted[low].key = key;
nkeynes@915
   370
    mmu_utlb_sorted[low].mask = mmu_utlb[entry].mask | 0x000000FF;
nkeynes@915
   371
    mmu_utlb_sorted[low].entryNo = entry;
nkeynes@915
   372
    mmu_utlb_entries++;
nkeynes@915
   373
}
nkeynes@915
   374
nkeynes@915
   375
static void mmu_utlb_remove_entry( int entry )
nkeynes@915
   376
{
nkeynes@915
   377
    int low = 0;
nkeynes@915
   378
    int high = mmu_utlb_entries;
nkeynes@915
   379
    uint32_t key = (mmu_utlb[entry].vpn & mmu_utlb[entry].mask) + mmu_utlb[entry].asid;
nkeynes@915
   380
    while( low != high ) {
nkeynes@915
   381
        int posn = (high+low)>>1;
nkeynes@915
   382
        if( mmu_utlb_sorted[posn].key < key ) {
nkeynes@915
   383
            low = posn+1;
nkeynes@915
   384
        } else if( mmu_utlb_sorted[posn].key > key ) {
nkeynes@915
   385
            high = posn;
nkeynes@915
   386
        } else {
nkeynes@915
   387
            if( mmu_utlb_sorted[posn].entryNo == -2 ) {
nkeynes@915
   388
                /* Multiple-entry recorded - rebuild the whole table minus entry */
nkeynes@915
   389
                int i;
nkeynes@915
   390
                mmu_utlb_entries = 0;
nkeynes@915
   391
                for( i=0; i< UTLB_ENTRY_COUNT; i++ ) {
nkeynes@915
   392
                    if( i != entry && (mmu_utlb[i].flags & TLB_VALID)  ) {
nkeynes@915
   393
                        mmu_utlb_insert_entry(i);
nkeynes@915
   394
                    }
nkeynes@915
   395
                }
nkeynes@915
   396
            } else {
nkeynes@915
   397
                mmu_utlb_entries--;
nkeynes@915
   398
                memmove( &mmu_utlb_sorted[posn], &mmu_utlb_sorted[posn+1],
nkeynes@915
   399
                         (mmu_utlb_entries - posn)*sizeof(struct utlb_sort_entry) );
nkeynes@915
   400
            }
nkeynes@915
   401
            return;
nkeynes@915
   402
        }
nkeynes@915
   403
    }
nkeynes@915
   404
    assert( 0 && "UTLB key not found!" );
nkeynes@915
   405
}
nkeynes@915
   406
nkeynes@915
   407
static void mmu_utlb_sorted_reload()
nkeynes@915
   408
{
nkeynes@915
   409
    int i;
nkeynes@915
   410
    mmu_utlb_entries = 0;
nkeynes@915
   411
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@915
   412
        if( mmu_utlb[i].flags & TLB_VALID ) 
nkeynes@915
   413
            mmu_utlb_insert_entry( i );
nkeynes@915
   414
    }
nkeynes@915
   415
}
nkeynes@915
   416
nkeynes@550
   417
/* TLB maintanence */
nkeynes@550
   418
nkeynes@550
   419
/**
nkeynes@550
   420
 * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
nkeynes@550
   421
 * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
nkeynes@550
   422
 */
nkeynes@550
   423
void MMU_ldtlb()
nkeynes@550
   424
{
nkeynes@915
   425
    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
nkeynes@915
   426
        mmu_utlb_remove_entry( mmu_urc );
nkeynes@550
   427
    mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
nkeynes@550
   428
    mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
nkeynes@550
   429
    mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
nkeynes@550
   430
    mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
nkeynes@550
   431
    mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
nkeynes@586
   432
    mmu_utlb[mmu_urc].mask = get_mask_for_flags(mmu_utlb[mmu_urc].flags);
nkeynes@915
   433
    if( mmu_utlb[mmu_urc].ppn >= 0x1C000000 )
nkeynes@915
   434
        mmu_utlb[mmu_urc].ppn |= 0xE0000000;
nkeynes@915
   435
    if( mmu_utlb[mmu_urc].flags & TLB_VALID )
nkeynes@915
   436
        mmu_utlb_insert_entry( mmu_urc );
nkeynes@550
   437
}
nkeynes@550
   438
nkeynes@550
   439
static void mmu_invalidate_tlb()
nkeynes@550
   440
{
nkeynes@550
   441
    int i;
nkeynes@550
   442
    for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   443
        mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550
   444
    }
nkeynes@550
   445
    for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   446
        mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550
   447
    }
nkeynes@915
   448
    mmu_utlb_entries = 0;
nkeynes@550
   449
}
nkeynes@550
   450
nkeynes@550
   451
#define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@550
   452
nkeynes@929
   453
int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@550
   454
{
nkeynes@550
   455
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   456
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@550
   457
}
nkeynes@929
   458
int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr )
nkeynes@550
   459
{
nkeynes@550
   460
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@915
   461
    return (ent->ppn & 0x1FFFFC00) | ent->flags;
nkeynes@550
   462
}
nkeynes@550
   463
nkeynes@929
   464
void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   465
{
nkeynes@550
   466
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   467
    ent->vpn = val & 0xFFFFFC00;
nkeynes@550
   468
    ent->asid = val & 0x000000FF;
nkeynes@550
   469
    ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@550
   470
}
nkeynes@550
   471
nkeynes@929
   472
void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   473
{
nkeynes@550
   474
    struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550
   475
    ent->ppn = val & 0x1FFFFC00;
nkeynes@550
   476
    ent->flags = val & 0x00001DA;
nkeynes@586
   477
    ent->mask = get_mask_for_flags(val);
nkeynes@915
   478
    if( ent->ppn >= 0x1C000000 )
nkeynes@915
   479
        ent->ppn |= 0xE0000000;
nkeynes@550
   480
}
nkeynes@550
   481
nkeynes@550
   482
#define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@550
   483
#define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@550
   484
#define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@550
   485
nkeynes@929
   486
int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@550
   487
{
nkeynes@550
   488
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   489
    return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@736
   490
    ((ent->flags & TLB_DIRTY)<<7);
nkeynes@550
   491
}
nkeynes@929
   492
int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr )
nkeynes@550
   493
{
nkeynes@550
   494
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   495
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   496
        return ent->pcmcia;
nkeynes@550
   497
    } else {
nkeynes@915
   498
        return (ent->ppn&0x1FFFFC00) | ent->flags;
nkeynes@550
   499
    }
nkeynes@550
   500
}
nkeynes@550
   501
nkeynes@586
   502
/**
nkeynes@586
   503
 * Find a UTLB entry for the associative TLB write - same as the normal
nkeynes@586
   504
 * lookup but ignores the valid bit.
nkeynes@586
   505
 */
nkeynes@669
   506
static inline int mmu_utlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   507
{
nkeynes@586
   508
    int result = -1;
nkeynes@586
   509
    unsigned int i;
nkeynes@586
   510
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   511
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   512
                ((mmu_utlb[i].flags & TLB_SHARE) || asid == mmu_utlb[i].asid) &&
nkeynes@736
   513
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   514
            if( result != -1 ) {
nkeynes@736
   515
                fprintf( stderr, "TLB Multi hit: %d %d\n", result, i );
nkeynes@736
   516
                return -2;
nkeynes@736
   517
            }
nkeynes@736
   518
            result = i;
nkeynes@736
   519
        }
nkeynes@586
   520
    }
nkeynes@586
   521
    return result;
nkeynes@586
   522
}
nkeynes@586
   523
nkeynes@586
   524
/**
nkeynes@586
   525
 * Find a ITLB entry for the associative TLB write - same as the normal
nkeynes@586
   526
 * lookup but ignores the valid bit.
nkeynes@586
   527
 */
nkeynes@669
   528
static inline int mmu_itlb_lookup_assoc( uint32_t vpn, uint32_t asid )
nkeynes@586
   529
{
nkeynes@586
   530
    int result = -1;
nkeynes@586
   531
    unsigned int i;
nkeynes@586
   532
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   533
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   534
                ((mmu_itlb[i].flags & TLB_SHARE) || asid == mmu_itlb[i].asid) &&
nkeynes@736
   535
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   536
            if( result != -1 ) {
nkeynes@736
   537
                return -2;
nkeynes@736
   538
            }
nkeynes@736
   539
            result = i;
nkeynes@736
   540
        }
nkeynes@586
   541
    }
nkeynes@586
   542
    return result;
nkeynes@586
   543
}
nkeynes@586
   544
nkeynes@929
   545
void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   546
{
nkeynes@550
   547
    if( UTLB_ASSOC(addr) ) {
nkeynes@736
   548
        int utlb = mmu_utlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   549
        if( utlb >= 0 ) {
nkeynes@736
   550
            struct utlb_entry *ent = &mmu_utlb[utlb];
nkeynes@915
   551
            uint32_t old_flags = ent->flags;
nkeynes@736
   552
            ent->flags = ent->flags & ~(TLB_DIRTY|TLB_VALID);
nkeynes@736
   553
            ent->flags |= (val & TLB_VALID);
nkeynes@736
   554
            ent->flags |= ((val & 0x200)>>7);
nkeynes@915
   555
            if( (old_flags & TLB_VALID) && !(ent->flags&TLB_VALID) ) {
nkeynes@915
   556
                mmu_utlb_remove_entry( utlb );
nkeynes@915
   557
            } else if( !(old_flags & TLB_VALID) && (ent->flags&TLB_VALID) ) {
nkeynes@915
   558
                mmu_utlb_insert_entry( utlb );
nkeynes@915
   559
            }
nkeynes@736
   560
        }
nkeynes@586
   561
nkeynes@736
   562
        int itlb = mmu_itlb_lookup_assoc( val, mmu_asid );
nkeynes@736
   563
        if( itlb >= 0 ) {
nkeynes@736
   564
            struct itlb_entry *ent = &mmu_itlb[itlb];
nkeynes@736
   565
            ent->flags = (ent->flags & (~TLB_VALID)) | (val & TLB_VALID);
nkeynes@736
   566
        }
nkeynes@586
   567
nkeynes@736
   568
        if( itlb == -2 || utlb == -2 ) {
nkeynes@736
   569
            MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
   570
            return;
nkeynes@736
   571
        }
nkeynes@550
   572
    } else {
nkeynes@736
   573
        struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@915
   574
        if( ent->flags & TLB_VALID ) 
nkeynes@915
   575
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@736
   576
        ent->vpn = (val & 0xFFFFFC00);
nkeynes@736
   577
        ent->asid = (val & 0xFF);
nkeynes@736
   578
        ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@736
   579
        ent->flags |= (val & TLB_VALID);
nkeynes@736
   580
        ent->flags |= ((val & 0x200)>>7);
nkeynes@915
   581
        if( ent->flags & TLB_VALID ) 
nkeynes@915
   582
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@550
   583
    }
nkeynes@550
   584
}
nkeynes@550
   585
nkeynes@929
   586
void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   587
{
nkeynes@550
   588
    struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550
   589
    if( UTLB_DATA2(addr) ) {
nkeynes@736
   590
        ent->pcmcia = val & 0x0000000F;
nkeynes@550
   591
    } else {
nkeynes@915
   592
        if( ent->flags & TLB_VALID ) 
nkeynes@915
   593
            mmu_utlb_remove_entry( UTLB_ENTRY(addr) );
nkeynes@736
   594
        ent->ppn = (val & 0x1FFFFC00);
nkeynes@736
   595
        ent->flags = (val & 0x000001FF);
nkeynes@736
   596
        ent->mask = get_mask_for_flags(val);
nkeynes@915
   597
        if( mmu_utlb[mmu_urc].ppn >= 0x1C000000 )
nkeynes@915
   598
            mmu_utlb[mmu_urc].ppn |= 0xE0000000;
nkeynes@915
   599
        if( ent->flags & TLB_VALID ) 
nkeynes@915
   600
            mmu_utlb_insert_entry( UTLB_ENTRY(addr) );
nkeynes@550
   601
    }
nkeynes@550
   602
}
nkeynes@550
   603
nkeynes@550
   604
/* Cache access - not implemented */
nkeynes@550
   605
nkeynes@929
   606
int32_t FASTCALL mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550
   607
{
nkeynes@550
   608
    return 0; // not implemented
nkeynes@550
   609
}
nkeynes@929
   610
int32_t FASTCALL mmu_icache_data_read( sh4addr_t addr )
nkeynes@550
   611
{
nkeynes@550
   612
    return 0; // not implemented
nkeynes@550
   613
}
nkeynes@929
   614
int32_t FASTCALL mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550
   615
{
nkeynes@550
   616
    return 0; // not implemented
nkeynes@550
   617
}
nkeynes@929
   618
int32_t FASTCALL mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550
   619
{
nkeynes@550
   620
    return 0; // not implemented
nkeynes@550
   621
}
nkeynes@550
   622
nkeynes@929
   623
void FASTCALL mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   624
{
nkeynes@550
   625
}
nkeynes@550
   626
nkeynes@929
   627
void FASTCALL mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   628
{
nkeynes@550
   629
}
nkeynes@550
   630
nkeynes@929
   631
void FASTCALL mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   632
{
nkeynes@550
   633
}
nkeynes@550
   634
nkeynes@929
   635
void FASTCALL mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550
   636
{
nkeynes@550
   637
}
nkeynes@586
   638
nkeynes@586
   639
/******************************************************************************/
nkeynes@586
   640
/*                        MMU TLB address translation                         */
nkeynes@586
   641
/******************************************************************************/
nkeynes@586
   642
nkeynes@586
   643
/**
nkeynes@826
   644
 * The translations are excessively complicated, but unfortunately it's a
nkeynes@586
   645
 * complicated system. TODO: make this not be painfully slow.
nkeynes@586
   646
 */
nkeynes@586
   647
nkeynes@586
   648
/**
nkeynes@586
   649
 * Perform the actual utlb lookup w/ asid matching.
nkeynes@586
   650
 * Possible utcomes are:
nkeynes@586
   651
 *   0..63 Single match - good, return entry found
nkeynes@586
   652
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   653
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   654
 * @param vpn virtual address to resolve
nkeynes@586
   655
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   656
 */
nkeynes@586
   657
static inline int mmu_utlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   658
{
nkeynes@586
   659
    int result = -1;
nkeynes@586
   660
    unsigned int i;
nkeynes@586
   661
nkeynes@586
   662
    mmu_urc++;
nkeynes@586
   663
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   664
        mmu_urc = 0;
nkeynes@586
   665
    }
nkeynes@586
   666
nkeynes@586
   667
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   668
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@826
   669
                ((mmu_utlb[i].flags & TLB_SHARE) || mmu_asid == mmu_utlb[i].asid) &&
nkeynes@736
   670
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   671
            if( result != -1 ) {
nkeynes@736
   672
                return -2;
nkeynes@736
   673
            }
nkeynes@736
   674
            result = i;
nkeynes@736
   675
        }
nkeynes@586
   676
    }
nkeynes@586
   677
    return result;
nkeynes@586
   678
}
nkeynes@586
   679
nkeynes@586
   680
/**
nkeynes@586
   681
 * Perform the actual utlb lookup matching on vpn only
nkeynes@586
   682
 * Possible utcomes are:
nkeynes@586
   683
 *   0..63 Single match - good, return entry found
nkeynes@586
   684
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   685
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   686
 * @param vpn virtual address to resolve
nkeynes@586
   687
 * @return the resultant UTLB entry, or an error.
nkeynes@586
   688
 */
nkeynes@586
   689
static inline int mmu_utlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   690
{
nkeynes@586
   691
    int result = -1;
nkeynes@586
   692
    unsigned int i;
nkeynes@586
   693
nkeynes@586
   694
    mmu_urc++;
nkeynes@586
   695
    if( mmu_urc == mmu_urb || mmu_urc == 0x40 ) {
nkeynes@736
   696
        mmu_urc = 0;
nkeynes@586
   697
    }
nkeynes@586
   698
nkeynes@586
   699
    for( i = 0; i < UTLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   700
        if( (mmu_utlb[i].flags & TLB_VALID) &&
nkeynes@736
   701
                ((mmu_utlb[i].vpn ^ vpn) & mmu_utlb[i].mask) == 0 ) {
nkeynes@736
   702
            if( result != -1 ) {
nkeynes@736
   703
                return -2;
nkeynes@736
   704
            }
nkeynes@736
   705
            result = i;
nkeynes@736
   706
        }
nkeynes@586
   707
    }
nkeynes@586
   708
nkeynes@586
   709
    return result;
nkeynes@586
   710
}
nkeynes@586
   711
nkeynes@586
   712
/**
nkeynes@586
   713
 * Update the ITLB by replacing the LRU entry with the specified UTLB entry.
nkeynes@586
   714
 * @return the number (0-3) of the replaced entry.
nkeynes@586
   715
 */
nkeynes@586
   716
static int inline mmu_itlb_update_from_utlb( int entryNo )
nkeynes@586
   717
{
nkeynes@586
   718
    int replace;
nkeynes@586
   719
    /* Determine entry to replace based on lrui */
nkeynes@586
   720
    if( (mmu_lrui & 0x38) == 0x38 ) {
nkeynes@736
   721
        replace = 0;
nkeynes@736
   722
        mmu_lrui = mmu_lrui & 0x07;
nkeynes@586
   723
    } else if( (mmu_lrui & 0x26) == 0x06 ) {
nkeynes@736
   724
        replace = 1;
nkeynes@736
   725
        mmu_lrui = (mmu_lrui & 0x19) | 0x20;
nkeynes@586
   726
    } else if( (mmu_lrui & 0x15) == 0x01 ) {
nkeynes@736
   727
        replace = 2;
nkeynes@736
   728
        mmu_lrui = (mmu_lrui & 0x3E) | 0x14;
nkeynes@586
   729
    } else { // Note - gets invalid entries too
nkeynes@736
   730
        replace = 3;
nkeynes@736
   731
        mmu_lrui = (mmu_lrui | 0x0B);
nkeynes@826
   732
    }
nkeynes@586
   733
nkeynes@586
   734
    mmu_itlb[replace].vpn = mmu_utlb[entryNo].vpn;
nkeynes@586
   735
    mmu_itlb[replace].mask = mmu_utlb[entryNo].mask;
nkeynes@586
   736
    mmu_itlb[replace].ppn = mmu_utlb[entryNo].ppn;
nkeynes@586
   737
    mmu_itlb[replace].asid = mmu_utlb[entryNo].asid;
nkeynes@586
   738
    mmu_itlb[replace].flags = mmu_utlb[entryNo].flags & 0x01DA;
nkeynes@586
   739
    return replace;
nkeynes@586
   740
}
nkeynes@586
   741
nkeynes@586
   742
/**
nkeynes@586
   743
 * Perform the actual itlb lookup w/ asid protection
nkeynes@586
   744
 * Possible utcomes are:
nkeynes@586
   745
 *   0..63 Single match - good, return entry found
nkeynes@586
   746
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   747
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   748
 * @param vpn virtual address to resolve
nkeynes@586
   749
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   750
 */
nkeynes@586
   751
static inline int mmu_itlb_lookup_vpn_asid( uint32_t vpn )
nkeynes@586
   752
{
nkeynes@586
   753
    int result = -1;
nkeynes@586
   754
    unsigned int i;
nkeynes@586
   755
nkeynes@586
   756
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   757
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@826
   758
                ((mmu_itlb[i].flags & TLB_SHARE) || mmu_asid == mmu_itlb[i].asid) &&
nkeynes@736
   759
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   760
            if( result != -1 ) {
nkeynes@736
   761
                return -2;
nkeynes@736
   762
            }
nkeynes@736
   763
            result = i;
nkeynes@736
   764
        }
nkeynes@586
   765
    }
nkeynes@586
   766
nkeynes@586
   767
    if( result == -1 ) {
nkeynes@915
   768
        int utlbEntry = mmu_utlb_sorted_find( vpn );
nkeynes@736
   769
        if( utlbEntry < 0 ) {
nkeynes@736
   770
            return utlbEntry;
nkeynes@736
   771
        } else {
nkeynes@736
   772
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   773
        }
nkeynes@586
   774
    }
nkeynes@586
   775
nkeynes@586
   776
    switch( result ) {
nkeynes@586
   777
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   778
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   779
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   780
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   781
    }
nkeynes@736
   782
nkeynes@586
   783
    return result;
nkeynes@586
   784
}
nkeynes@586
   785
nkeynes@586
   786
/**
nkeynes@586
   787
 * Perform the actual itlb lookup on vpn only
nkeynes@586
   788
 * Possible utcomes are:
nkeynes@586
   789
 *   0..63 Single match - good, return entry found
nkeynes@586
   790
 *   -1 No match - raise a tlb data miss exception
nkeynes@586
   791
 *   -2 Multiple matches - raise a multi-hit exception (reset)
nkeynes@586
   792
 * @param vpn virtual address to resolve
nkeynes@586
   793
 * @return the resultant ITLB entry, or an error.
nkeynes@586
   794
 */
nkeynes@586
   795
static inline int mmu_itlb_lookup_vpn( uint32_t vpn )
nkeynes@586
   796
{
nkeynes@586
   797
    int result = -1;
nkeynes@586
   798
    unsigned int i;
nkeynes@586
   799
nkeynes@586
   800
    for( i = 0; i < ITLB_ENTRY_COUNT; i++ ) {
nkeynes@736
   801
        if( (mmu_itlb[i].flags & TLB_VALID) &&
nkeynes@736
   802
                ((mmu_itlb[i].vpn ^ vpn) & mmu_itlb[i].mask) == 0 ) {
nkeynes@736
   803
            if( result != -1 ) {
nkeynes@736
   804
                return -2;
nkeynes@736
   805
            }
nkeynes@736
   806
            result = i;
nkeynes@736
   807
        }
nkeynes@586
   808
    }
nkeynes@586
   809
nkeynes@586
   810
    if( result == -1 ) {
nkeynes@736
   811
        int utlbEntry = mmu_utlb_lookup_vpn( vpn );
nkeynes@736
   812
        if( utlbEntry < 0 ) {
nkeynes@736
   813
            return utlbEntry;
nkeynes@736
   814
        } else {
nkeynes@736
   815
            return mmu_itlb_update_from_utlb( utlbEntry );
nkeynes@736
   816
        }
nkeynes@586
   817
    }
nkeynes@586
   818
nkeynes@586
   819
    switch( result ) {
nkeynes@586
   820
    case 0: mmu_lrui = (mmu_lrui & 0x07); break;
nkeynes@586
   821
    case 1: mmu_lrui = (mmu_lrui & 0x19) | 0x20; break;
nkeynes@586
   822
    case 2: mmu_lrui = (mmu_lrui & 0x3E) | 0x14; break;
nkeynes@586
   823
    case 3: mmu_lrui = (mmu_lrui | 0x0B); break;
nkeynes@586
   824
    }
nkeynes@736
   825
nkeynes@586
   826
    return result;
nkeynes@586
   827
}
nkeynes@927
   828
nkeynes@927
   829
#ifdef HAVE_FRAME_ADDRESS
nkeynes@927
   830
sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr, void *exc )
nkeynes@927
   831
#else
nkeynes@905
   832
sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr )
nkeynes@927
   833
#endif
nkeynes@586
   834
{
nkeynes@586
   835
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   836
    if( addr & 0x80000000 ) {
nkeynes@736
   837
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   838
            if( addr >= 0xE0000000 ) {
nkeynes@736
   839
                return addr; /* P4 - passthrough */
nkeynes@736
   840
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   841
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   842
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   843
            }
nkeynes@736
   844
        } else {
nkeynes@736
   845
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   846
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   847
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   848
                return addr;
nkeynes@736
   849
            }
nkeynes@736
   850
            MMU_READ_ADDR_ERROR();
nkeynes@927
   851
            RETURN_VIA(exc);
nkeynes@736
   852
        }
nkeynes@586
   853
    }
nkeynes@736
   854
nkeynes@586
   855
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   856
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   857
    }
nkeynes@586
   858
nkeynes@586
   859
    /* If we get this far, translation is required */
nkeynes@586
   860
    int entryNo;
nkeynes@586
   861
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@915
   862
        entryNo = mmu_utlb_sorted_find( addr );
nkeynes@586
   863
    } else {
nkeynes@736
   864
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   865
    }
nkeynes@586
   866
nkeynes@586
   867
    switch(entryNo) {
nkeynes@586
   868
    case -1:
nkeynes@736
   869
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@927
   870
    RETURN_VIA(exc);
nkeynes@586
   871
    case -2:
nkeynes@736
   872
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@927
   873
    RETURN_VIA(exc);
nkeynes@586
   874
    default:
nkeynes@736
   875
        if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
nkeynes@736
   876
                !IS_SH4_PRIVMODE() ) {
nkeynes@736
   877
            /* protection violation */
nkeynes@736
   878
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@927
   879
            RETURN_VIA(exc);
nkeynes@736
   880
        }
nkeynes@586
   881
nkeynes@736
   882
        /* finally generate the target address */
nkeynes@915
   883
        return (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
nkeynes@810
   884
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@586
   885
    }
nkeynes@586
   886
}
nkeynes@586
   887
nkeynes@927
   888
#ifdef HAVE_FRAME_ADDRESS
nkeynes@927
   889
sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr, void *exc )
nkeynes@927
   890
#else
nkeynes@905
   891
sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr )
nkeynes@927
   892
#endif
nkeynes@586
   893
{
nkeynes@586
   894
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
   895
    if( addr & 0x80000000 ) {
nkeynes@736
   896
        if( IS_SH4_PRIVMODE() ) {
nkeynes@736
   897
            if( addr >= 0xE0000000 ) {
nkeynes@736
   898
                return addr; /* P4 - passthrough */
nkeynes@736
   899
            } else if( addr < 0xC0000000 ) {
nkeynes@736
   900
                /* P1, P2 regions are pass-through (no translation) */
nkeynes@736
   901
                return VMA_TO_EXT_ADDR(addr);
nkeynes@736
   902
            }
nkeynes@736
   903
        } else {
nkeynes@736
   904
            if( addr >= 0xE0000000 && addr < 0xE4000000 &&
nkeynes@736
   905
                    ((mmucr&MMUCR_SQMD) == 0) ) {
nkeynes@736
   906
                /* Conditional user-mode access to the store-queue (no translation) */
nkeynes@736
   907
                return addr;
nkeynes@736
   908
            }
nkeynes@736
   909
            MMU_WRITE_ADDR_ERROR();
nkeynes@927
   910
            RETURN_VIA(exc);
nkeynes@736
   911
        }
nkeynes@586
   912
    }
nkeynes@736
   913
nkeynes@586
   914
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
   915
        return VMA_TO_EXT_ADDR(addr);
nkeynes@586
   916
    }
nkeynes@586
   917
nkeynes@586
   918
    /* If we get this far, translation is required */
nkeynes@586
   919
    int entryNo;
nkeynes@586
   920
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@915
   921
        entryNo = mmu_utlb_sorted_find( addr );
nkeynes@586
   922
    } else {
nkeynes@736
   923
        entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@586
   924
    }
nkeynes@586
   925
nkeynes@586
   926
    switch(entryNo) {
nkeynes@586
   927
    case -1:
nkeynes@736
   928
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@927
   929
    RETURN_VIA(exc);
nkeynes@586
   930
    case -2:
nkeynes@736
   931
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@927
   932
    RETURN_VIA(exc);
nkeynes@586
   933
    default:
nkeynes@736
   934
        if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@736
   935
                : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@736
   936
            /* protection violation */
nkeynes@736
   937
            MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@927
   938
            RETURN_VIA(exc);
nkeynes@736
   939
        }
nkeynes@586
   940
nkeynes@736
   941
        if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@736
   942
            MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@927
   943
            RETURN_VIA(exc);
nkeynes@736
   944
        }
nkeynes@586
   945
nkeynes@736
   946
        /* finally generate the target address */
nkeynes@826
   947
        sh4addr_t pma = (mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
nkeynes@810
   948
        	(addr & (~mmu_utlb[entryNo].mask));
nkeynes@810
   949
        return pma;
nkeynes@586
   950
    }
nkeynes@586
   951
}
nkeynes@586
   952
nkeynes@586
   953
/**
nkeynes@586
   954
 * Update the icache for an untranslated address
nkeynes@586
   955
 */
nkeynes@905
   956
static inline void mmu_update_icache_phys( sh4addr_t addr )
nkeynes@586
   957
{
nkeynes@586
   958
    if( (addr & 0x1C000000) == 0x0C000000 ) {
nkeynes@736
   959
        /* Main ram */
nkeynes@736
   960
        sh4_icache.page_vma = addr & 0xFF000000;
nkeynes@736
   961
        sh4_icache.page_ppa = 0x0C000000;
nkeynes@736
   962
        sh4_icache.mask = 0xFF000000;
nkeynes@736
   963
        sh4_icache.page = sh4_main_ram;
nkeynes@586
   964
    } else if( (addr & 0x1FE00000) == 0 ) {
nkeynes@736
   965
        /* BIOS ROM */
nkeynes@736
   966
        sh4_icache.page_vma = addr & 0xFFE00000;
nkeynes@736
   967
        sh4_icache.page_ppa = 0;
nkeynes@736
   968
        sh4_icache.mask = 0xFFE00000;
nkeynes@736
   969
        sh4_icache.page = mem_get_region(0);
nkeynes@586
   970
    } else {
nkeynes@736
   971
        /* not supported */
nkeynes@736
   972
        sh4_icache.page_vma = -1;
nkeynes@586
   973
    }
nkeynes@586
   974
}
nkeynes@586
   975
nkeynes@586
   976
/**
nkeynes@586
   977
 * Update the sh4_icache structure to describe the page(s) containing the
nkeynes@586
   978
 * given vma. If the address does not reference a RAM/ROM region, the icache
nkeynes@586
   979
 * will be invalidated instead.
nkeynes@586
   980
 * If AT is on, this method will raise TLB exceptions normally
nkeynes@586
   981
 * (hence this method should only be used immediately prior to execution of
nkeynes@586
   982
 * code), and otherwise will set the icache according to the matching TLB entry.
nkeynes@586
   983
 * If AT is off, this method will set the entire referenced RAM/ROM region in
nkeynes@586
   984
 * the icache.
nkeynes@586
   985
 * @return TRUE if the update completed (successfully or otherwise), FALSE
nkeynes@586
   986
 * if an exception was raised.
nkeynes@586
   987
 */
nkeynes@905
   988
gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
nkeynes@586
   989
{
nkeynes@586
   990
    int entryNo;
nkeynes@586
   991
    if( IS_SH4_PRIVMODE()  ) {
nkeynes@736
   992
        if( addr & 0x80000000 ) {
nkeynes@736
   993
            if( addr < 0xC0000000 ) {
nkeynes@736
   994
                /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
   995
                mmu_update_icache_phys(addr);
nkeynes@736
   996
                return TRUE;
nkeynes@736
   997
            } else if( addr >= 0xE0000000 && addr < 0xFFFFFF00 ) {
nkeynes@736
   998
                MMU_READ_ADDR_ERROR();
nkeynes@736
   999
                return FALSE;
nkeynes@736
  1000
            }
nkeynes@736
  1001
        }
nkeynes@586
  1002
nkeynes@736
  1003
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1004
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1005
            mmu_update_icache_phys(addr);
nkeynes@736
  1006
            return TRUE;
nkeynes@736
  1007
        }
nkeynes@736
  1008
nkeynes@826
  1009
        if( (mmucr & MMUCR_SV) == 0 )
nkeynes@807
  1010
        	entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1011
        else
nkeynes@807
  1012
        	entryNo = mmu_itlb_lookup_vpn( addr );
nkeynes@586
  1013
    } else {
nkeynes@736
  1014
        if( addr & 0x80000000 ) {
nkeynes@736
  1015
            MMU_READ_ADDR_ERROR();
nkeynes@736
  1016
            return FALSE;
nkeynes@736
  1017
        }
nkeynes@586
  1018
nkeynes@736
  1019
        uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@736
  1020
        if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1021
            mmu_update_icache_phys(addr);
nkeynes@736
  1022
            return TRUE;
nkeynes@736
  1023
        }
nkeynes@736
  1024
nkeynes@807
  1025
        entryNo = mmu_itlb_lookup_vpn_asid( addr );
nkeynes@807
  1026
nkeynes@736
  1027
        if( entryNo != -1 && (mmu_itlb[entryNo].flags & TLB_USERMODE) == 0 ) {
nkeynes@736
  1028
            MMU_TLB_READ_PROT_ERROR(addr);
nkeynes@736
  1029
            return FALSE;
nkeynes@736
  1030
        }
nkeynes@586
  1031
    }
nkeynes@586
  1032
nkeynes@586
  1033
    switch(entryNo) {
nkeynes@586
  1034
    case -1:
nkeynes@736
  1035
    MMU_TLB_READ_MISS_ERROR(addr);
nkeynes@736
  1036
    return FALSE;
nkeynes@586
  1037
    case -2:
nkeynes@736
  1038
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@736
  1039
    return FALSE;
nkeynes@586
  1040
    default:
nkeynes@736
  1041
        sh4_icache.page_ppa = mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask;
nkeynes@736
  1042
        sh4_icache.page = mem_get_region( sh4_icache.page_ppa );
nkeynes@736
  1043
        if( sh4_icache.page == NULL ) {
nkeynes@736
  1044
            sh4_icache.page_vma = -1;
nkeynes@736
  1045
        } else {
nkeynes@736
  1046
            sh4_icache.page_vma = mmu_itlb[entryNo].vpn & mmu_itlb[entryNo].mask;
nkeynes@736
  1047
            sh4_icache.mask = mmu_itlb[entryNo].mask;
nkeynes@736
  1048
        }
nkeynes@736
  1049
        return TRUE;
nkeynes@586
  1050
    }
nkeynes@586
  1051
}
nkeynes@586
  1052
nkeynes@597
  1053
/**
nkeynes@826
  1054
 * Translate address for disassembly purposes (ie performs an instruction
nkeynes@597
  1055
 * lookup) - does not raise exceptions or modify any state, and ignores
nkeynes@597
  1056
 * protection bits. Returns the translated address, or MMU_VMA_ERROR
nkeynes@826
  1057
 * on translation failure.
nkeynes@597
  1058
 */
nkeynes@905
  1059
sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
nkeynes@597
  1060
{
nkeynes@597
  1061
    if( vma & 0x80000000 ) {
nkeynes@736
  1062
        if( vma < 0xC0000000 ) {
nkeynes@736
  1063
            /* P1, P2 and P4 regions are pass-through (no translation) */
nkeynes@736
  1064
            return VMA_TO_EXT_ADDR(vma);
nkeynes@736
  1065
        } else if( vma >= 0xE0000000 && vma < 0xFFFFFF00 ) {
nkeynes@736
  1066
            /* Not translatable */
nkeynes@736
  1067
            return MMU_VMA_ERROR;
nkeynes@736
  1068
        }
nkeynes@597
  1069
    }
nkeynes@597
  1070
nkeynes@597
  1071
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@597
  1072
    if( (mmucr & MMUCR_AT) == 0 ) {
nkeynes@736
  1073
        return VMA_TO_EXT_ADDR(vma);
nkeynes@597
  1074
    }
nkeynes@736
  1075
nkeynes@597
  1076
    int entryNo = mmu_itlb_lookup_vpn( vma );
nkeynes@597
  1077
    if( entryNo == -2 ) {
nkeynes@736
  1078
        entryNo = mmu_itlb_lookup_vpn_asid( vma );
nkeynes@597
  1079
    }
nkeynes@597
  1080
    if( entryNo < 0 ) {
nkeynes@736
  1081
        return MMU_VMA_ERROR;
nkeynes@597
  1082
    } else {
nkeynes@826
  1083
        return (mmu_itlb[entryNo].ppn & mmu_itlb[entryNo].mask) |
nkeynes@826
  1084
        (vma & (~mmu_itlb[entryNo].mask));
nkeynes@597
  1085
    }
nkeynes@597
  1086
}
nkeynes@597
  1087
nkeynes@911
  1088
void FASTCALL sh4_flush_store_queue( sh4addr_t addr )
nkeynes@911
  1089
{
nkeynes@911
  1090
    int queue = (addr&0x20)>>2;
nkeynes@911
  1091
    uint32_t hi = MMIO_READ( MMU, QACR0 + (queue>>1)) << 24;
nkeynes@911
  1092
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@911
  1093
    sh4addr_t target = (addr&0x03FFFFE0) | hi;
nkeynes@911
  1094
    mem_copy_to_sh4( target, src, 32 );
nkeynes@911
  1095
} 
nkeynes@911
  1096
nkeynes@911
  1097
gboolean FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr )
nkeynes@586
  1098
{
nkeynes@586
  1099
    uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@586
  1100
    int queue = (addr&0x20)>>2;
nkeynes@586
  1101
    sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
nkeynes@586
  1102
    sh4addr_t target;
nkeynes@586
  1103
    /* Store queue operation */
nkeynes@736
  1104
nkeynes@911
  1105
    int entryNo;
nkeynes@911
  1106
    if( ((mmucr & MMUCR_SV) == 0) || !IS_SH4_PRIVMODE() ) {
nkeynes@911
  1107
    	entryNo = mmu_utlb_lookup_vpn_asid( addr );
nkeynes@911
  1108
    } else {
nkeynes@911
  1109
    	entryNo = mmu_utlb_lookup_vpn( addr );
nkeynes@911
  1110
    }
nkeynes@911
  1111
    switch(entryNo) {
nkeynes@911
  1112
    case -1:
nkeynes@911
  1113
    MMU_TLB_WRITE_MISS_ERROR(addr);
nkeynes@911
  1114
    return FALSE;
nkeynes@911
  1115
    case -2:
nkeynes@911
  1116
    MMU_TLB_MULTI_HIT_ERROR(addr);
nkeynes@911
  1117
    return FALSE;
nkeynes@911
  1118
    default:
nkeynes@911
  1119
    	if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
nkeynes@911
  1120
    			: ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
nkeynes@911
  1121
    		/* protection violation */
nkeynes@911
  1122
    		MMU_TLB_WRITE_PROT_ERROR(addr);
nkeynes@911
  1123
    		return FALSE;
nkeynes@911
  1124
    	}
nkeynes@736
  1125
nkeynes@911
  1126
    	if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
nkeynes@911
  1127
    		MMU_TLB_INITIAL_WRITE_ERROR(addr);
nkeynes@911
  1128
    		return FALSE;
nkeynes@911
  1129
    	}
nkeynes@911
  1130
nkeynes@911
  1131
    	/* finally generate the target address */
nkeynes@911
  1132
    	target = ((mmu_utlb[entryNo].ppn & mmu_utlb[entryNo].mask) |
nkeynes@911
  1133
    			(addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
nkeynes@586
  1134
    }
nkeynes@911
  1135
nkeynes@586
  1136
    mem_copy_to_sh4( target, src, 32 );
nkeynes@586
  1137
    return TRUE;
nkeynes@586
  1138
}
nkeynes@586
  1139
.