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lxdream.org :: lxdream/src/sh4/pmm.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/pmm.c
changeset 929:fd8cb0c82f5f
prev841:808d64b05073
next975:007bf7eb944f
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
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/**
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 * $Id: pmm.c 833 2008-08-18 12:18:10Z nkeynes $
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 * 
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 * PMM (performance counter) module
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include "sh4/sh4mmio.h"
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#include "sh4/sh4core.h"
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#include "clock.h"
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/*
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 * Performance counter list from Paul Mundt's OProfile patch
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 * Currently only 0x23 is actually supported, since it doesn't require any
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 * actual instrumentation
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 * 
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 *     0x01            Operand read access
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 *     0x02            Operand write access
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 *     0x03            UTLB miss
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 *     0x04            Operand cache read miss
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 *     0x05            Operand cache write miss
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 *     0x06            Instruction fetch (w/ cache)
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 *     0x07            Instruction TLB miss
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 *     0x08            Instruction cache miss
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 *     0x09            All operand accesses
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 *     0x0a            All instruction accesses
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 *     0x0b            OC RAM operand access
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 *     0x0d            On-chip I/O space access
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 *     0x0e            Operand access (r/w)
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 *     0x0f            Operand cache miss (r/w)
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 *     0x10            Branch instruction
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 *     0x11            Branch taken
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 *     0x12            BSR/BSRF/JSR
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 *     0x13            Instruction execution
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 *     0x14            Instruction execution in parallel
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 *     0x15            FPU Instruction execution
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 *     0x16            Interrupt
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 *     0x17            NMI
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 *     0x18            trapa instruction execution
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 *     0x19            UBCA match
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 *     0x1a            UBCB match
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 *     0x21            Instruction cache fill
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 *     0x22            Operand cache fill
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 *     0x23            Elapsed time
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 *     0x24            Pipeline freeze by I-cache miss
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 *     0x25            Pipeline freeze by D-cache miss
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 *     0x27            Pipeline freeze by branch instruction
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 *     0x28            Pipeline freeze by CPU register
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 *     0x29            Pipeline freeze by FPU
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 */
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struct PMM_counter_struct {
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    uint64_t count;
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    uint32_t mode; /* if running only, otherwise 0 */
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    uint32_t runfor;
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};
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static struct PMM_counter_struct PMM_counter[2] = {{0,0},{0,0}};
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void PMM_reset(void)
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{
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    PMM_counter[0].count = 0;
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    PMM_counter[0].mode = 0;
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    PMM_counter[0].runfor = 0;
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    PMM_counter[1].count = 0;
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    PMM_counter[1].mode = 0;
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    PMM_counter[1].runfor = 0;
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}
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void PMM_save_state( FILE *f ) {
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    fwrite( &PMM_counter, sizeof(PMM_counter), 1, f );
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}
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int PMM_load_state( FILE *f ) 
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{
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    fread( &PMM_counter, sizeof(PMM_counter), 1, f );
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    return 0;
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}
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void PMM_count( int ctr, uint32_t runfor )
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{
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    uint32_t delta = runfor - PMM_counter[ctr].runfor;
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    switch( PMM_counter[ctr].mode ) {
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    case 0x23:
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        PMM_counter[ctr].count += (delta / (1000/SH4_BASE_RATE)); 
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        break;
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    default:
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        break;
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    }
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    PMM_counter[ctr].runfor = runfor;
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}
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uint32_t PMM_run_slice( uint32_t nanosecs )
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{
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    PMM_count( 0, nanosecs );
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    PMM_count( 1, nanosecs );
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    PMM_counter[0].runfor = 0;
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    PMM_counter[1].runfor = 0;
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    return nanosecs;
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}
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void PMM_write_control( int ctr, uint32_t val )
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{
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    int is_running = ((val & PMCR_RUNNING) == PMCR_RUNNING);
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    PMM_count(ctr, sh4r.slice_cycle);
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    if( PMM_counter[ctr].mode == 0 && (val & PMCR_PMCLR) != 0 ) {
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        PMM_counter[ctr].count = 0;
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    }
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    if( is_running ) {
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        int mode = val & 0x3F;
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        if( mode != PMM_counter[ctr].mode ) {
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            /* Instrumentation setup goes here */
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            PMM_counter[ctr].mode = mode;
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        }
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    } else if( PMM_counter[ctr].mode != 0 ) {
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        /* Instrumentation removal goes here */
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        PMM_counter[ctr].mode = 0;
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    }
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}
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MMIO_REGION_READ_FN( PMM, reg )
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{   
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    switch( reg & 0x1F ) {
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    case 0: return 0; /* not a register */
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    case PMCTR1H: 
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        PMM_count(0, sh4r.slice_cycle);
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        return ((uint32_t)(PMM_counter[0].count >> 32)) & 0x0000FFFF;
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    case PMCTR1L: 
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        PMM_count(0, sh4r.slice_cycle);
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        return (uint32_t)PMM_counter[0].count;
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    case PMCTR2H: 
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        PMM_count(1, sh4r.slice_cycle);
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        return ((uint32_t)(PMM_counter[1].count >> 32)) & 0x0000FFFF;
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    default: 
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        PMM_count(1, sh4r.slice_cycle);
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        return (uint32_t)PMM_counter[1].count;
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    }
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}
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MMIO_REGION_WRITE_FN( PMM, reg, val )
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{
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    /* Read-only */
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}
.