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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 929:fd8cb0c82f5f
prev927:17b6b9e245d8
next930:07e5b11419db
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#include <stddef.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#ifdef HAVE_FRAME_ADDRESS
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) {  call_func1_exc(mmu_vma_to_phys_read, addr_reg, pc); MEM_RESULT(addr_reg); }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1_exc(mmu_vma_to_phys_write, addr_reg, pc); MEM_RESULT(addr_reg); }
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#else
nkeynes@927
   313
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@586
   314
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@927
   315
#endif
nkeynes@368
   316
nkeynes@590
   317
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   318
nkeynes@539
   319
/****** Import appropriate calling conventions ******/
nkeynes@675
   320
#if SIZEOF_VOID_P == 8
nkeynes@539
   321
#include "sh4/ia64abi.h"
nkeynes@675
   322
#else /* 32-bit system */
nkeynes@539
   323
#include "sh4/ia32abi.h"
nkeynes@539
   324
#endif
nkeynes@539
   325
nkeynes@929
   326
#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@929
   327
nkeynes@929
   328
/**
nkeynes@929
   329
 * Given an address in addr_reg and a cache entry, test if the cache is valid
nkeynes@929
   330
 * and decode otherwise.
nkeynes@929
   331
 * At conclusion of this:
nkeynes@929
   332
 *    R_EBX will contain the address
nkeynes@929
   333
 *    R_ECX will contain the memory region vtable
nkeynes@929
   334
 *    R_EAX, R_EDX (and any other volatiles) are clobbered
nkeynes@929
   335
 */
nkeynes@929
   336
static inline void MEM_DECODE_ADDRESS( int addr_reg, int rm )
nkeynes@929
   337
{
nkeynes@929
   338
    MOV_r32_r32( addr_reg, R_EBX );
nkeynes@929
   339
    AND_sh4r_r32( REG_OFFSET(pointer_cache[rm].page_mask), addr_reg );
nkeynes@929
   340
    CMP_sh4r_r32( REG_OFFSET(pointer_cache[rm].page_vma), addr_reg );
nkeynes@929
   341
    EXPJE_rel8(uptodate);
nkeynes@929
   342
    store_spreg( addr_reg, REG_OFFSET(pointer_cache[rm].page_vma) ); 
nkeynes@929
   343
    call_func1( sh7750_decode_address, addr_reg );
nkeynes@929
   344
    store_spreg( R_EAX, REG_OFFSET(pointer_cache[rm].page_fn) );
nkeynes@929
   345
    JMP_TARGET(uptodate);
nkeynes@929
   346
    load_spreg( R_ECX, REG_OFFSET(pointer_cache[rm].page_fn) );
nkeynes@929
   347
}
nkeynes@929
   348
nkeynes@929
   349
static inline void MEM_READ_LONG_CACHED( int addr_reg, int value_reg, int rm )
nkeynes@929
   350
{
nkeynes@929
   351
    MEM_DECODE_ADDRESS( addr_reg, rm );
nkeynes@929
   352
    call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
nkeynes@929
   353
    MEM_RESULT(value_reg);
nkeynes@929
   354
}
nkeynes@929
   355
nkeynes@929
   356
static inline void MEM_READ_WORD_CACHED( int addr_reg, int value_reg, int rm )
nkeynes@929
   357
{
nkeynes@929
   358
    MEM_DECODE_ADDRESS( addr_reg, rm );
nkeynes@929
   359
    call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_word), R_EBX );
nkeynes@929
   360
    MEM_RESULT(value_reg);
nkeynes@929
   361
}
nkeynes@929
   362
nkeynes@929
   363
static inline void MEM_READ_BYTE_CACHED( int addr_reg, int value_reg, int rm )
nkeynes@929
   364
{
nkeynes@929
   365
    MEM_DECODE_ADDRESS( addr_reg, rm );
nkeynes@929
   366
    call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_byte), R_EBX );
nkeynes@929
   367
    MEM_RESULT(value_reg);    
nkeynes@929
   368
}
nkeynes@929
   369
nkeynes@929
   370
static inline void MEM_WRITE_LONG_CACHED_SP( int addr_reg, int ebpdisp, int rn )
nkeynes@929
   371
{
nkeynes@929
   372
    MEM_DECODE_ADDRESS( addr_reg, rn );
nkeynes@929
   373
    MOV_sh4r_r32( ebpdisp, R_EDX );
nkeynes@929
   374
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
nkeynes@929
   375
} 
nkeynes@929
   376
nkeynes@929
   377
#define MEM_WRITE_LONG_CACHED( addr_reg, value_rm, rn ) MEM_WRITE_LONG_CACHED_SP( addr_reg, REG_OFFSET(r[value_rm]), rn )
nkeynes@929
   378
nkeynes@929
   379
static inline void MEM_WRITE_WORD_CACHED( int addr_reg, int value_rm, int rn )
nkeynes@929
   380
{
nkeynes@929
   381
    MEM_DECODE_ADDRESS( addr_reg, rn );
nkeynes@929
   382
    MOVZX_sh4r16_r32( REG_OFFSET(r[value_rm]), R_EDX );
nkeynes@929
   383
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_word), R_EBX, R_EDX );
nkeynes@929
   384
}
nkeynes@929
   385
nkeynes@929
   386
static inline void MEM_WRITE_BYTE_CACHED( int addr_reg, int value_rm, int rn )
nkeynes@929
   387
{
nkeynes@929
   388
    MEM_DECODE_ADDRESS( addr_reg, rn );
nkeynes@929
   389
    MOVZX_sh4r8_r32( REG_OFFSET(r[value_rm]), R_EDX );
nkeynes@929
   390
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_byte), R_EBX, R_EDX );
nkeynes@929
   391
}
nkeynes@929
   392
nkeynes@929
   393
static inline void MEM_WRITE_BYTE_UNCHECKED( int addr_reg, int value_reg, int rn )
nkeynes@929
   394
{
nkeynes@929
   395
    load_spreg( R_ECX, REG_OFFSET(pointer_cache[rn].page_fn) );
nkeynes@929
   396
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_byte), addr_reg, R_EDX );
nkeynes@929
   397
}    
nkeynes@929
   398
nkeynes@929
   399
static inline void MEM_WRITE_FLOAT_CACHED( int addr_reg, int value_frm, int rn )
nkeynes@929
   400
{
nkeynes@929
   401
    MEM_DECODE_ADDRESS( addr_reg, rn );
nkeynes@929
   402
    load_fr( R_EDX, value_frm );
nkeynes@929
   403
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
nkeynes@929
   404
} 
nkeynes@929
   405
nkeynes@929
   406
static inline void MEM_READ_DOUBLE_CACHED( int addr_reg, int value_reg1, int value_reg2, int rm )
nkeynes@929
   407
{
nkeynes@929
   408
    MEM_DECODE_ADDRESS( addr_reg, rm );
nkeynes@929
   409
    call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
nkeynes@929
   410
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@929
   411
    load_spreg( R_ECX, REG_OFFSET(pointer_cache[rm].page_fn) );
nkeynes@929
   412
    LEA_r32disp8_r32( R_EBX, 4, R_EBX );
nkeynes@929
   413
    call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
nkeynes@929
   414
    MEM_RESULT(value_reg2);
nkeynes@929
   415
    MOV_esp8_r32( 0, value_reg1 );
nkeynes@929
   416
}
nkeynes@929
   417
nkeynes@929
   418
static inline void MEM_WRITE_DOUBLE_CACHED( int addr_reg, int value_frm, int rn )
nkeynes@929
   419
{
nkeynes@929
   420
    MEM_DECODE_ADDRESS( addr_reg, rn );
nkeynes@929
   421
    load_dr0( R_EDX, value_frm );
nkeynes@929
   422
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
nkeynes@929
   423
    LEA_r32disp8_r32( R_EBX, 4, R_EBX );
nkeynes@929
   424
    load_spreg( R_ECX, REG_OFFSET(pointer_cache[rn].page_fn) );
nkeynes@929
   425
    load_dr1( R_EDX, value_frm );
nkeynes@929
   426
    call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
nkeynes@929
   427
}
nkeynes@929
   428
nkeynes@929
   429
nkeynes@929
   430
nkeynes@901
   431
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   432
{
nkeynes@927
   433
    enter_block();
nkeynes@901
   434
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   435
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   436
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   437
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   438
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   439
    sh4_x86.block_start_pc = pc;
nkeynes@901
   440
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   442
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   443
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   444
}
nkeynes@901
   445
nkeynes@901
   446
nkeynes@593
   447
uint32_t sh4_translate_end_block_size()
nkeynes@593
   448
{
nkeynes@596
   449
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   450
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   451
    } else {
nkeynes@901
   452
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   453
    }
nkeynes@593
   454
}
nkeynes@593
   455
nkeynes@593
   456
nkeynes@590
   457
/**
nkeynes@590
   458
 * Embed a breakpoint into the generated code
nkeynes@590
   459
 */
nkeynes@586
   460
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   461
{
nkeynes@591
   462
    load_imm32( R_EAX, pc );
nkeynes@591
   463
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   464
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   465
}
nkeynes@590
   466
nkeynes@601
   467
nkeynes@601
   468
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   469
nkeynes@590
   470
/**
nkeynes@590
   471
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   472
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   473
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   474
 *
nkeynes@601
   475
 * Performs:
nkeynes@601
   476
 *   Set PC = endpc
nkeynes@601
   477
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   478
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   479
 *   Call sh4_execute_instruction
nkeynes@601
   480
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   481
 */
nkeynes@601
   482
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   483
{
nkeynes@590
   484
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   485
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   486
    
nkeynes@601
   487
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   488
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   489
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   490
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   491
nkeynes@590
   492
    call_func0( sh4_execute_instruction );    
nkeynes@601
   493
    load_spreg( R_EAX, R_PC );
nkeynes@590
   494
    if( sh4_x86.tlb_on ) {
nkeynes@590
   495
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   496
    } else {
nkeynes@590
   497
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   498
    }
nkeynes@926
   499
    exit_block();
nkeynes@590
   500
} 
nkeynes@539
   501
nkeynes@359
   502
/**
nkeynes@359
   503
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   504
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   505
 * 
nkeynes@586
   506
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   507
 *
nkeynes@359
   508
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   509
 * (eg a branch or 
nkeynes@359
   510
 */
nkeynes@590
   511
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   512
{
nkeynes@388
   513
    uint32_t ir;
nkeynes@586
   514
    /* Read instruction from icache */
nkeynes@586
   515
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   516
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   517
    
nkeynes@586
   518
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   519
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   520
    }
nkeynes@359
   521
%%
nkeynes@359
   522
/* ALU operations */
nkeynes@359
   523
ADD Rm, Rn {:
nkeynes@671
   524
    COUNT_INST(I_ADD);
nkeynes@359
   525
    load_reg( R_EAX, Rm );
nkeynes@359
   526
    load_reg( R_ECX, Rn );
nkeynes@359
   527
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   528
    store_reg( R_ECX, Rn );
nkeynes@417
   529
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   530
:}
nkeynes@359
   531
ADD #imm, Rn {:  
nkeynes@671
   532
    COUNT_INST(I_ADDI);
nkeynes@359
   533
    load_reg( R_EAX, Rn );
nkeynes@359
   534
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   535
    store_reg( R_EAX, Rn );
nkeynes@417
   536
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   537
:}
nkeynes@359
   538
ADDC Rm, Rn {:
nkeynes@671
   539
    COUNT_INST(I_ADDC);
nkeynes@417
   540
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   541
        LDC_t();
nkeynes@417
   542
    }
nkeynes@359
   543
    load_reg( R_EAX, Rm );
nkeynes@359
   544
    load_reg( R_ECX, Rn );
nkeynes@359
   545
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   546
    store_reg( R_ECX, Rn );
nkeynes@359
   547
    SETC_t();
nkeynes@417
   548
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   549
:}
nkeynes@359
   550
ADDV Rm, Rn {:
nkeynes@671
   551
    COUNT_INST(I_ADDV);
nkeynes@359
   552
    load_reg( R_EAX, Rm );
nkeynes@359
   553
    load_reg( R_ECX, Rn );
nkeynes@359
   554
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   555
    store_reg( R_ECX, Rn );
nkeynes@359
   556
    SETO_t();
nkeynes@417
   557
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   558
:}
nkeynes@359
   559
AND Rm, Rn {:
nkeynes@671
   560
    COUNT_INST(I_AND);
nkeynes@359
   561
    load_reg( R_EAX, Rm );
nkeynes@359
   562
    load_reg( R_ECX, Rn );
nkeynes@359
   563
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   564
    store_reg( R_ECX, Rn );
nkeynes@417
   565
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   566
:}
nkeynes@359
   567
AND #imm, R0 {:  
nkeynes@671
   568
    COUNT_INST(I_ANDI);
nkeynes@359
   569
    load_reg( R_EAX, 0 );
nkeynes@359
   570
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   571
    store_reg( R_EAX, 0 );
nkeynes@417
   572
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   573
:}
nkeynes@359
   574
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   575
    COUNT_INST(I_ANDB);
nkeynes@359
   576
    load_reg( R_EAX, 0 );
nkeynes@359
   577
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   578
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   579
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
   580
    MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
nkeynes@905
   581
    AND_imm32_r32(imm, R_EDX );
nkeynes@929
   582
    MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
nkeynes@417
   583
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   584
:}
nkeynes@359
   585
CMP/EQ Rm, Rn {:  
nkeynes@671
   586
    COUNT_INST(I_CMPEQ);
nkeynes@359
   587
    load_reg( R_EAX, Rm );
nkeynes@359
   588
    load_reg( R_ECX, Rn );
nkeynes@359
   589
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   590
    SETE_t();
nkeynes@417
   591
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   592
:}
nkeynes@359
   593
CMP/EQ #imm, R0 {:  
nkeynes@671
   594
    COUNT_INST(I_CMPEQI);
nkeynes@359
   595
    load_reg( R_EAX, 0 );
nkeynes@359
   596
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   597
    SETE_t();
nkeynes@417
   598
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   599
:}
nkeynes@359
   600
CMP/GE Rm, Rn {:  
nkeynes@671
   601
    COUNT_INST(I_CMPGE);
nkeynes@359
   602
    load_reg( R_EAX, Rm );
nkeynes@359
   603
    load_reg( R_ECX, Rn );
nkeynes@359
   604
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   605
    SETGE_t();
nkeynes@417
   606
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   607
:}
nkeynes@359
   608
CMP/GT Rm, Rn {: 
nkeynes@671
   609
    COUNT_INST(I_CMPGT);
nkeynes@359
   610
    load_reg( R_EAX, Rm );
nkeynes@359
   611
    load_reg( R_ECX, Rn );
nkeynes@359
   612
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   613
    SETG_t();
nkeynes@417
   614
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   615
:}
nkeynes@359
   616
CMP/HI Rm, Rn {:  
nkeynes@671
   617
    COUNT_INST(I_CMPHI);
nkeynes@359
   618
    load_reg( R_EAX, Rm );
nkeynes@359
   619
    load_reg( R_ECX, Rn );
nkeynes@359
   620
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   621
    SETA_t();
nkeynes@417
   622
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   623
:}
nkeynes@359
   624
CMP/HS Rm, Rn {: 
nkeynes@671
   625
    COUNT_INST(I_CMPHS);
nkeynes@359
   626
    load_reg( R_EAX, Rm );
nkeynes@359
   627
    load_reg( R_ECX, Rn );
nkeynes@359
   628
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   629
    SETAE_t();
nkeynes@417
   630
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   631
 :}
nkeynes@359
   632
CMP/PL Rn {: 
nkeynes@671
   633
    COUNT_INST(I_CMPPL);
nkeynes@359
   634
    load_reg( R_EAX, Rn );
nkeynes@359
   635
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   636
    SETG_t();
nkeynes@417
   637
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   638
:}
nkeynes@359
   639
CMP/PZ Rn {:  
nkeynes@671
   640
    COUNT_INST(I_CMPPZ);
nkeynes@359
   641
    load_reg( R_EAX, Rn );
nkeynes@359
   642
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   643
    SETGE_t();
nkeynes@417
   644
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   645
:}
nkeynes@361
   646
CMP/STR Rm, Rn {:  
nkeynes@671
   647
    COUNT_INST(I_CMPSTR);
nkeynes@368
   648
    load_reg( R_EAX, Rm );
nkeynes@368
   649
    load_reg( R_ECX, Rn );
nkeynes@368
   650
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   651
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   652
    JE_rel8(target1);
nkeynes@669
   653
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   654
    JE_rel8(target2);
nkeynes@669
   655
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   656
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   657
    JE_rel8(target3);
nkeynes@669
   658
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   659
    JMP_TARGET(target1);
nkeynes@380
   660
    JMP_TARGET(target2);
nkeynes@380
   661
    JMP_TARGET(target3);
nkeynes@368
   662
    SETE_t();
nkeynes@417
   663
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   664
:}
nkeynes@361
   665
DIV0S Rm, Rn {:
nkeynes@671
   666
    COUNT_INST(I_DIV0S);
nkeynes@361
   667
    load_reg( R_EAX, Rm );
nkeynes@386
   668
    load_reg( R_ECX, Rn );
nkeynes@361
   669
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   670
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   671
    store_spreg( R_EAX, R_M );
nkeynes@361
   672
    store_spreg( R_ECX, R_Q );
nkeynes@361
   673
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   674
    SETNE_t();
nkeynes@417
   675
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   676
:}
nkeynes@361
   677
DIV0U {:  
nkeynes@671
   678
    COUNT_INST(I_DIV0U);
nkeynes@361
   679
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   680
    store_spreg( R_EAX, R_Q );
nkeynes@361
   681
    store_spreg( R_EAX, R_M );
nkeynes@361
   682
    store_spreg( R_EAX, R_T );
nkeynes@417
   683
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   684
:}
nkeynes@386
   685
DIV1 Rm, Rn {:
nkeynes@671
   686
    COUNT_INST(I_DIV1);
nkeynes@386
   687
    load_spreg( R_ECX, R_M );
nkeynes@386
   688
    load_reg( R_EAX, Rn );
nkeynes@417
   689
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   690
	LDC_t();
nkeynes@417
   691
    }
nkeynes@386
   692
    RCL1_r32( R_EAX );
nkeynes@386
   693
    SETC_r8( R_DL ); // Q'
nkeynes@386
   694
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   695
    JE_rel8(mqequal);
nkeynes@386
   696
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   697
    JMP_rel8(end);
nkeynes@380
   698
    JMP_TARGET(mqequal);
nkeynes@386
   699
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   700
    JMP_TARGET(end);
nkeynes@386
   701
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   702
    SETC_r8(R_AL); // tmp1
nkeynes@386
   703
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   704
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   705
    store_spreg( R_ECX, R_Q );
nkeynes@386
   706
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   707
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   708
    store_spreg( R_EAX, R_T );
nkeynes@417
   709
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   710
:}
nkeynes@361
   711
DMULS.L Rm, Rn {:  
nkeynes@671
   712
    COUNT_INST(I_DMULS);
nkeynes@361
   713
    load_reg( R_EAX, Rm );
nkeynes@361
   714
    load_reg( R_ECX, Rn );
nkeynes@361
   715
    IMUL_r32(R_ECX);
nkeynes@361
   716
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   717
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   718
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   719
:}
nkeynes@361
   720
DMULU.L Rm, Rn {:  
nkeynes@671
   721
    COUNT_INST(I_DMULU);
nkeynes@361
   722
    load_reg( R_EAX, Rm );
nkeynes@361
   723
    load_reg( R_ECX, Rn );
nkeynes@361
   724
    MUL_r32(R_ECX);
nkeynes@361
   725
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   726
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   727
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   728
:}
nkeynes@359
   729
DT Rn {:  
nkeynes@671
   730
    COUNT_INST(I_DT);
nkeynes@359
   731
    load_reg( R_EAX, Rn );
nkeynes@382
   732
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   733
    store_reg( R_EAX, Rn );
nkeynes@359
   734
    SETE_t();
nkeynes@417
   735
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   736
:}
nkeynes@359
   737
EXTS.B Rm, Rn {:  
nkeynes@671
   738
    COUNT_INST(I_EXTSB);
nkeynes@359
   739
    load_reg( R_EAX, Rm );
nkeynes@359
   740
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   741
    store_reg( R_EAX, Rn );
nkeynes@359
   742
:}
nkeynes@361
   743
EXTS.W Rm, Rn {:  
nkeynes@671
   744
    COUNT_INST(I_EXTSW);
nkeynes@361
   745
    load_reg( R_EAX, Rm );
nkeynes@361
   746
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   747
    store_reg( R_EAX, Rn );
nkeynes@361
   748
:}
nkeynes@361
   749
EXTU.B Rm, Rn {:  
nkeynes@671
   750
    COUNT_INST(I_EXTUB);
nkeynes@361
   751
    load_reg( R_EAX, Rm );
nkeynes@361
   752
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   753
    store_reg( R_EAX, Rn );
nkeynes@361
   754
:}
nkeynes@361
   755
EXTU.W Rm, Rn {:  
nkeynes@671
   756
    COUNT_INST(I_EXTUW);
nkeynes@361
   757
    load_reg( R_EAX, Rm );
nkeynes@361
   758
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   759
    store_reg( R_EAX, Rn );
nkeynes@361
   760
:}
nkeynes@586
   761
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   762
    COUNT_INST(I_MACL);
nkeynes@586
   763
    if( Rm == Rn ) {
nkeynes@586
   764
	load_reg( R_EAX, Rm );
nkeynes@586
   765
	check_ralign32( R_EAX );
nkeynes@586
   766
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   767
	MOV_r32_esp8(R_EAX, 0);
nkeynes@586
   768
	load_reg( R_EAX, Rn );
nkeynes@586
   769
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@926
   770
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   771
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   772
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   773
	// adding a page-boundary check to skip the second translation
nkeynes@586
   774
    } else {
nkeynes@586
   775
	load_reg( R_EAX, Rm );
nkeynes@586
   776
	check_ralign32( R_EAX );
nkeynes@586
   777
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   778
	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   779
	load_reg( R_EAX, Rn );
nkeynes@926
   780
	check_ralign32( R_EAX );
nkeynes@926
   781
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   782
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   783
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   784
    }
nkeynes@586
   785
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@929
   786
    MOV_r32_r32( R_EAX, R_EBX );
nkeynes@926
   787
    MOV_esp8_r32( 0, R_EAX );
nkeynes@926
   788
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@929
   789
    MOV_r32_r32( R_EBX, R_ECX );
nkeynes@586
   790
nkeynes@386
   791
    IMUL_r32( R_ECX );
nkeynes@386
   792
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   793
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   794
nkeynes@386
   795
    load_spreg( R_ECX, R_S );
nkeynes@386
   796
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   797
    JE_rel8( nosat );
nkeynes@386
   798
    call_func0( signsat48 );
nkeynes@386
   799
    JMP_TARGET( nosat );
nkeynes@417
   800
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   801
:}
nkeynes@386
   802
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   803
    COUNT_INST(I_MACW);
nkeynes@586
   804
    if( Rm == Rn ) {
nkeynes@586
   805
	load_reg( R_EAX, Rm );
nkeynes@586
   806
	check_ralign16( R_EAX );
nkeynes@586
   807
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   808
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@586
   809
	load_reg( R_EAX, Rn );
nkeynes@586
   810
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@926
   811
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   812
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   813
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   814
	// adding a page-boundary check to skip the second translation
nkeynes@586
   815
    } else {
nkeynes@586
   816
	load_reg( R_EAX, Rm );
nkeynes@586
   817
	check_ralign16( R_EAX );
nkeynes@586
   818
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   819
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   820
	load_reg( R_EAX, Rn );
nkeynes@926
   821
	check_ralign16( R_EAX );
nkeynes@926
   822
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   823
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   824
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   825
    }
nkeynes@586
   826
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@929
   827
    MOV_r32_r32( R_EAX, R_EBX );
nkeynes@926
   828
    MOV_esp8_r32( 0, R_EAX );
nkeynes@926
   829
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@929
   830
    MOV_r32_r32( R_EBX, R_ECX );
nkeynes@926
   831
nkeynes@386
   832
    IMUL_r32( R_ECX );
nkeynes@386
   833
    load_spreg( R_ECX, R_S );
nkeynes@386
   834
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   835
    JE_rel8( nosat );
nkeynes@386
   836
nkeynes@386
   837
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   838
    JNO_rel8( end );            // 2
nkeynes@386
   839
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   840
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   841
    JS_rel8( positive );        // 2
nkeynes@386
   842
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   843
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   844
    JMP_rel8(end2);           // 2
nkeynes@386
   845
nkeynes@386
   846
    JMP_TARGET(positive);
nkeynes@386
   847
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   848
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   849
    JMP_rel8(end3);            // 2
nkeynes@386
   850
nkeynes@386
   851
    JMP_TARGET(nosat);
nkeynes@386
   852
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   853
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   854
    JMP_TARGET(end);
nkeynes@386
   855
    JMP_TARGET(end2);
nkeynes@386
   856
    JMP_TARGET(end3);
nkeynes@417
   857
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   858
:}
nkeynes@359
   859
MOVT Rn {:  
nkeynes@671
   860
    COUNT_INST(I_MOVT);
nkeynes@359
   861
    load_spreg( R_EAX, R_T );
nkeynes@359
   862
    store_reg( R_EAX, Rn );
nkeynes@359
   863
:}
nkeynes@361
   864
MUL.L Rm, Rn {:  
nkeynes@671
   865
    COUNT_INST(I_MULL);
nkeynes@361
   866
    load_reg( R_EAX, Rm );
nkeynes@361
   867
    load_reg( R_ECX, Rn );
nkeynes@361
   868
    MUL_r32( R_ECX );
nkeynes@361
   869
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   870
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   871
:}
nkeynes@374
   872
MULS.W Rm, Rn {:
nkeynes@671
   873
    COUNT_INST(I_MULSW);
nkeynes@374
   874
    load_reg16s( R_EAX, Rm );
nkeynes@374
   875
    load_reg16s( R_ECX, Rn );
nkeynes@374
   876
    MUL_r32( R_ECX );
nkeynes@374
   877
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   878
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   879
:}
nkeynes@374
   880
MULU.W Rm, Rn {:  
nkeynes@671
   881
    COUNT_INST(I_MULUW);
nkeynes@374
   882
    load_reg16u( R_EAX, Rm );
nkeynes@374
   883
    load_reg16u( R_ECX, Rn );
nkeynes@374
   884
    MUL_r32( R_ECX );
nkeynes@374
   885
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   886
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   887
:}
nkeynes@359
   888
NEG Rm, Rn {:
nkeynes@671
   889
    COUNT_INST(I_NEG);
nkeynes@359
   890
    load_reg( R_EAX, Rm );
nkeynes@359
   891
    NEG_r32( R_EAX );
nkeynes@359
   892
    store_reg( R_EAX, Rn );
nkeynes@417
   893
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   894
:}
nkeynes@359
   895
NEGC Rm, Rn {:  
nkeynes@671
   896
    COUNT_INST(I_NEGC);
nkeynes@359
   897
    load_reg( R_EAX, Rm );
nkeynes@359
   898
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   899
    LDC_t();
nkeynes@359
   900
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   901
    store_reg( R_ECX, Rn );
nkeynes@359
   902
    SETC_t();
nkeynes@417
   903
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   904
:}
nkeynes@359
   905
NOT Rm, Rn {:  
nkeynes@671
   906
    COUNT_INST(I_NOT);
nkeynes@359
   907
    load_reg( R_EAX, Rm );
nkeynes@359
   908
    NOT_r32( R_EAX );
nkeynes@359
   909
    store_reg( R_EAX, Rn );
nkeynes@417
   910
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   911
:}
nkeynes@359
   912
OR Rm, Rn {:  
nkeynes@671
   913
    COUNT_INST(I_OR);
nkeynes@359
   914
    load_reg( R_EAX, Rm );
nkeynes@359
   915
    load_reg( R_ECX, Rn );
nkeynes@359
   916
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   917
    store_reg( R_ECX, Rn );
nkeynes@417
   918
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   919
:}
nkeynes@359
   920
OR #imm, R0 {:
nkeynes@671
   921
    COUNT_INST(I_ORI);
nkeynes@359
   922
    load_reg( R_EAX, 0 );
nkeynes@359
   923
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   924
    store_reg( R_EAX, 0 );
nkeynes@417
   925
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   926
:}
nkeynes@374
   927
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   928
    COUNT_INST(I_ORB);
nkeynes@374
   929
    load_reg( R_EAX, 0 );
nkeynes@374
   930
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   931
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   932
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
   933
    MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
nkeynes@905
   934
    OR_imm32_r32(imm, R_EDX );
nkeynes@929
   935
    MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
nkeynes@417
   936
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   937
:}
nkeynes@359
   938
ROTCL Rn {:
nkeynes@671
   939
    COUNT_INST(I_ROTCL);
nkeynes@359
   940
    load_reg( R_EAX, Rn );
nkeynes@417
   941
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   942
	LDC_t();
nkeynes@417
   943
    }
nkeynes@359
   944
    RCL1_r32( R_EAX );
nkeynes@359
   945
    store_reg( R_EAX, Rn );
nkeynes@359
   946
    SETC_t();
nkeynes@417
   947
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   948
:}
nkeynes@359
   949
ROTCR Rn {:  
nkeynes@671
   950
    COUNT_INST(I_ROTCR);
nkeynes@359
   951
    load_reg( R_EAX, Rn );
nkeynes@417
   952
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   953
	LDC_t();
nkeynes@417
   954
    }
nkeynes@359
   955
    RCR1_r32( R_EAX );
nkeynes@359
   956
    store_reg( R_EAX, Rn );
nkeynes@359
   957
    SETC_t();
nkeynes@417
   958
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   959
:}
nkeynes@359
   960
ROTL Rn {:  
nkeynes@671
   961
    COUNT_INST(I_ROTL);
nkeynes@359
   962
    load_reg( R_EAX, Rn );
nkeynes@359
   963
    ROL1_r32( R_EAX );
nkeynes@359
   964
    store_reg( R_EAX, Rn );
nkeynes@359
   965
    SETC_t();
nkeynes@417
   966
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   967
:}
nkeynes@359
   968
ROTR Rn {:  
nkeynes@671
   969
    COUNT_INST(I_ROTR);
nkeynes@359
   970
    load_reg( R_EAX, Rn );
nkeynes@359
   971
    ROR1_r32( R_EAX );
nkeynes@359
   972
    store_reg( R_EAX, Rn );
nkeynes@359
   973
    SETC_t();
nkeynes@417
   974
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   975
:}
nkeynes@359
   976
SHAD Rm, Rn {:
nkeynes@671
   977
    COUNT_INST(I_SHAD);
nkeynes@359
   978
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   979
    load_reg( R_EAX, Rn );
nkeynes@361
   980
    load_reg( R_ECX, Rm );
nkeynes@361
   981
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   982
    JGE_rel8(doshl);
nkeynes@361
   983
                    
nkeynes@361
   984
    NEG_r32( R_ECX );      // 2
nkeynes@361
   985
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   986
    JE_rel8(emptysar);     // 2
nkeynes@361
   987
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   988
    JMP_rel8(end);          // 2
nkeynes@386
   989
nkeynes@386
   990
    JMP_TARGET(emptysar);
nkeynes@386
   991
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   992
    JMP_rel8(end2);
nkeynes@382
   993
nkeynes@380
   994
    JMP_TARGET(doshl);
nkeynes@361
   995
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   996
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   997
    JMP_TARGET(end);
nkeynes@386
   998
    JMP_TARGET(end2);
nkeynes@361
   999
    store_reg( R_EAX, Rn );
nkeynes@417
  1000
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1001
:}
nkeynes@359
  1002
SHLD Rm, Rn {:  
nkeynes@671
  1003
    COUNT_INST(I_SHLD);
nkeynes@368
  1004
    load_reg( R_EAX, Rn );
nkeynes@368
  1005
    load_reg( R_ECX, Rm );
nkeynes@382
  1006
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
  1007
    JGE_rel8(doshl);
nkeynes@368
  1008
nkeynes@382
  1009
    NEG_r32( R_ECX );      // 2
nkeynes@382
  1010
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
  1011
    JE_rel8(emptyshr );
nkeynes@382
  1012
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
  1013
    JMP_rel8(end);          // 2
nkeynes@386
  1014
nkeynes@386
  1015
    JMP_TARGET(emptyshr);
nkeynes@386
  1016
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
  1017
    JMP_rel8(end2);
nkeynes@382
  1018
nkeynes@382
  1019
    JMP_TARGET(doshl);
nkeynes@382
  1020
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
  1021
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
  1022
    JMP_TARGET(end);
nkeynes@386
  1023
    JMP_TARGET(end2);
nkeynes@368
  1024
    store_reg( R_EAX, Rn );
nkeynes@417
  1025
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1026
:}
nkeynes@359
  1027
SHAL Rn {: 
nkeynes@671
  1028
    COUNT_INST(I_SHAL);
nkeynes@359
  1029
    load_reg( R_EAX, Rn );
nkeynes@359
  1030
    SHL1_r32( R_EAX );
nkeynes@397
  1031
    SETC_t();
nkeynes@359
  1032
    store_reg( R_EAX, Rn );
nkeynes@417
  1033
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1034
:}
nkeynes@359
  1035
SHAR Rn {:  
nkeynes@671
  1036
    COUNT_INST(I_SHAR);
nkeynes@359
  1037
    load_reg( R_EAX, Rn );
nkeynes@359
  1038
    SAR1_r32( R_EAX );
nkeynes@397
  1039
    SETC_t();
nkeynes@359
  1040
    store_reg( R_EAX, Rn );
nkeynes@417
  1041
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1042
:}
nkeynes@359
  1043
SHLL Rn {:  
nkeynes@671
  1044
    COUNT_INST(I_SHLL);
nkeynes@359
  1045
    load_reg( R_EAX, Rn );
nkeynes@359
  1046
    SHL1_r32( R_EAX );
nkeynes@397
  1047
    SETC_t();
nkeynes@359
  1048
    store_reg( R_EAX, Rn );
nkeynes@417
  1049
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1050
:}
nkeynes@359
  1051
SHLL2 Rn {:
nkeynes@671
  1052
    COUNT_INST(I_SHLL);
nkeynes@359
  1053
    load_reg( R_EAX, Rn );
nkeynes@359
  1054
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1055
    store_reg( R_EAX, Rn );
nkeynes@417
  1056
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1057
:}
nkeynes@359
  1058
SHLL8 Rn {:  
nkeynes@671
  1059
    COUNT_INST(I_SHLL);
nkeynes@359
  1060
    load_reg( R_EAX, Rn );
nkeynes@359
  1061
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1062
    store_reg( R_EAX, Rn );
nkeynes@417
  1063
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1064
:}
nkeynes@359
  1065
SHLL16 Rn {:  
nkeynes@671
  1066
    COUNT_INST(I_SHLL);
nkeynes@359
  1067
    load_reg( R_EAX, Rn );
nkeynes@359
  1068
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1069
    store_reg( R_EAX, Rn );
nkeynes@417
  1070
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1071
:}
nkeynes@359
  1072
SHLR Rn {:  
nkeynes@671
  1073
    COUNT_INST(I_SHLR);
nkeynes@359
  1074
    load_reg( R_EAX, Rn );
nkeynes@359
  1075
    SHR1_r32( R_EAX );
nkeynes@397
  1076
    SETC_t();
nkeynes@359
  1077
    store_reg( R_EAX, Rn );
nkeynes@417
  1078
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1079
:}
nkeynes@359
  1080
SHLR2 Rn {:  
nkeynes@671
  1081
    COUNT_INST(I_SHLR);
nkeynes@359
  1082
    load_reg( R_EAX, Rn );
nkeynes@359
  1083
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1084
    store_reg( R_EAX, Rn );
nkeynes@417
  1085
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1086
:}
nkeynes@359
  1087
SHLR8 Rn {:  
nkeynes@671
  1088
    COUNT_INST(I_SHLR);
nkeynes@359
  1089
    load_reg( R_EAX, Rn );
nkeynes@359
  1090
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1091
    store_reg( R_EAX, Rn );
nkeynes@417
  1092
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1093
:}
nkeynes@359
  1094
SHLR16 Rn {:  
nkeynes@671
  1095
    COUNT_INST(I_SHLR);
nkeynes@359
  1096
    load_reg( R_EAX, Rn );
nkeynes@359
  1097
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1098
    store_reg( R_EAX, Rn );
nkeynes@417
  1099
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1100
:}
nkeynes@359
  1101
SUB Rm, Rn {:  
nkeynes@671
  1102
    COUNT_INST(I_SUB);
nkeynes@359
  1103
    load_reg( R_EAX, Rm );
nkeynes@359
  1104
    load_reg( R_ECX, Rn );
nkeynes@359
  1105
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1106
    store_reg( R_ECX, Rn );
nkeynes@417
  1107
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1108
:}
nkeynes@359
  1109
SUBC Rm, Rn {:  
nkeynes@671
  1110
    COUNT_INST(I_SUBC);
nkeynes@359
  1111
    load_reg( R_EAX, Rm );
nkeynes@359
  1112
    load_reg( R_ECX, Rn );
nkeynes@417
  1113
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1114
	LDC_t();
nkeynes@417
  1115
    }
nkeynes@359
  1116
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1117
    store_reg( R_ECX, Rn );
nkeynes@394
  1118
    SETC_t();
nkeynes@417
  1119
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1120
:}
nkeynes@359
  1121
SUBV Rm, Rn {:  
nkeynes@671
  1122
    COUNT_INST(I_SUBV);
nkeynes@359
  1123
    load_reg( R_EAX, Rm );
nkeynes@359
  1124
    load_reg( R_ECX, Rn );
nkeynes@359
  1125
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1126
    store_reg( R_ECX, Rn );
nkeynes@359
  1127
    SETO_t();
nkeynes@417
  1128
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1129
:}
nkeynes@359
  1130
SWAP.B Rm, Rn {:  
nkeynes@671
  1131
    COUNT_INST(I_SWAPB);
nkeynes@359
  1132
    load_reg( R_EAX, Rm );
nkeynes@601
  1133
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1134
    store_reg( R_EAX, Rn );
nkeynes@359
  1135
:}
nkeynes@359
  1136
SWAP.W Rm, Rn {:  
nkeynes@671
  1137
    COUNT_INST(I_SWAPB);
nkeynes@359
  1138
    load_reg( R_EAX, Rm );
nkeynes@359
  1139
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1140
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1141
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1142
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1143
    store_reg( R_ECX, Rn );
nkeynes@417
  1144
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1145
:}
nkeynes@361
  1146
TAS.B @Rn {:  
nkeynes@671
  1147
    COUNT_INST(I_TASB);
nkeynes@586
  1148
    load_reg( R_EAX, Rn );
nkeynes@586
  1149
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1150
    MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
nkeynes@905
  1151
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1152
    SETE_t();
nkeynes@905
  1153
    OR_imm8_r8( 0x80, R_DL );
nkeynes@929
  1154
    MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
nkeynes@417
  1155
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1156
:}
nkeynes@361
  1157
TST Rm, Rn {:  
nkeynes@671
  1158
    COUNT_INST(I_TST);
nkeynes@361
  1159
    load_reg( R_EAX, Rm );
nkeynes@361
  1160
    load_reg( R_ECX, Rn );
nkeynes@361
  1161
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1162
    SETE_t();
nkeynes@417
  1163
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1164
:}
nkeynes@368
  1165
TST #imm, R0 {:  
nkeynes@671
  1166
    COUNT_INST(I_TSTI);
nkeynes@368
  1167
    load_reg( R_EAX, 0 );
nkeynes@368
  1168
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1169
    SETE_t();
nkeynes@417
  1170
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1171
:}
nkeynes@368
  1172
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1173
    COUNT_INST(I_TSTB);
nkeynes@368
  1174
    load_reg( R_EAX, 0);
nkeynes@368
  1175
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1176
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1177
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1178
    MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 16 );
nkeynes@394
  1179
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1180
    SETE_t();
nkeynes@417
  1181
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1182
:}
nkeynes@359
  1183
XOR Rm, Rn {:  
nkeynes@671
  1184
    COUNT_INST(I_XOR);
nkeynes@359
  1185
    load_reg( R_EAX, Rm );
nkeynes@359
  1186
    load_reg( R_ECX, Rn );
nkeynes@359
  1187
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1188
    store_reg( R_ECX, Rn );
nkeynes@417
  1189
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1190
:}
nkeynes@359
  1191
XOR #imm, R0 {:  
nkeynes@671
  1192
    COUNT_INST(I_XORI);
nkeynes@359
  1193
    load_reg( R_EAX, 0 );
nkeynes@359
  1194
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1195
    store_reg( R_EAX, 0 );
nkeynes@417
  1196
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1197
:}
nkeynes@359
  1198
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1199
    COUNT_INST(I_XORB);
nkeynes@359
  1200
    load_reg( R_EAX, 0 );
nkeynes@359
  1201
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1202
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1203
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1204
    MEM_READ_BYTE_CACHED(R_EAX, R_EDX, 16);
nkeynes@905
  1205
    XOR_imm32_r32( imm, R_EDX );
nkeynes@929
  1206
    MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
nkeynes@417
  1207
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1208
:}
nkeynes@361
  1209
XTRCT Rm, Rn {:
nkeynes@671
  1210
    COUNT_INST(I_XTRCT);
nkeynes@361
  1211
    load_reg( R_EAX, Rm );
nkeynes@394
  1212
    load_reg( R_ECX, Rn );
nkeynes@394
  1213
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1214
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1215
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1216
    store_reg( R_ECX, Rn );
nkeynes@417
  1217
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1218
:}
nkeynes@359
  1219
nkeynes@359
  1220
/* Data move instructions */
nkeynes@359
  1221
MOV Rm, Rn {:  
nkeynes@671
  1222
    COUNT_INST(I_MOV);
nkeynes@359
  1223
    load_reg( R_EAX, Rm );
nkeynes@359
  1224
    store_reg( R_EAX, Rn );
nkeynes@359
  1225
:}
nkeynes@359
  1226
MOV #imm, Rn {:  
nkeynes@671
  1227
    COUNT_INST(I_MOVI);
nkeynes@359
  1228
    load_imm32( R_EAX, imm );
nkeynes@359
  1229
    store_reg( R_EAX, Rn );
nkeynes@359
  1230
:}
nkeynes@359
  1231
MOV.B Rm, @Rn {:  
nkeynes@671
  1232
    COUNT_INST(I_MOVB);
nkeynes@586
  1233
    load_reg( R_EAX, Rn );
nkeynes@586
  1234
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1235
    MEM_WRITE_BYTE_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1236
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1237
:}
nkeynes@359
  1238
MOV.B Rm, @-Rn {:  
nkeynes@671
  1239
    COUNT_INST(I_MOVB);
nkeynes@586
  1240
    load_reg( R_EAX, Rn );
nkeynes@586
  1241
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1242
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1243
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@929
  1244
    MEM_WRITE_BYTE_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1245
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1246
:}
nkeynes@359
  1247
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1248
    COUNT_INST(I_MOVB);
nkeynes@359
  1249
    load_reg( R_EAX, 0 );
nkeynes@359
  1250
    load_reg( R_ECX, Rn );
nkeynes@586
  1251
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1252
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1253
    MEM_WRITE_BYTE_CACHED( R_EAX, Rm, 0 );
nkeynes@417
  1254
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1255
:}
nkeynes@359
  1256
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1257
    COUNT_INST(I_MOVB);
nkeynes@586
  1258
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1259
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1260
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1261
    MEM_WRITE_BYTE_CACHED( R_EAX, 0, 16 );
nkeynes@417
  1262
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1263
:}
nkeynes@359
  1264
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1265
    COUNT_INST(I_MOVB);
nkeynes@586
  1266
    load_reg( R_EAX, Rn );
nkeynes@586
  1267
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1268
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1269
    MEM_WRITE_BYTE_CACHED( R_EAX, 0, Rn );
nkeynes@417
  1270
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1271
:}
nkeynes@359
  1272
MOV.B @Rm, Rn {:  
nkeynes@671
  1273
    COUNT_INST(I_MOVB);
nkeynes@586
  1274
    load_reg( R_EAX, Rm );
nkeynes@586
  1275
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1276
    MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
nkeynes@386
  1277
    store_reg( R_EAX, Rn );
nkeynes@417
  1278
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1279
:}
nkeynes@359
  1280
MOV.B @Rm+, Rn {:  
nkeynes@671
  1281
    COUNT_INST(I_MOVB);
nkeynes@586
  1282
    load_reg( R_EAX, Rm );
nkeynes@586
  1283
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1284
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@929
  1285
    MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  1286
    store_reg( R_EAX, Rn );
nkeynes@417
  1287
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1288
:}
nkeynes@359
  1289
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1290
    COUNT_INST(I_MOVB);
nkeynes@359
  1291
    load_reg( R_EAX, 0 );
nkeynes@359
  1292
    load_reg( R_ECX, Rm );
nkeynes@586
  1293
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1294
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@929
  1295
    MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 0 );
nkeynes@359
  1296
    store_reg( R_EAX, Rn );
nkeynes@417
  1297
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1298
:}
nkeynes@359
  1299
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1300
    COUNT_INST(I_MOVB);
nkeynes@586
  1301
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1302
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1303
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1304
    MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 16 );
nkeynes@359
  1305
    store_reg( R_EAX, 0 );
nkeynes@417
  1306
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1307
:}
nkeynes@359
  1308
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1309
    COUNT_INST(I_MOVB);
nkeynes@586
  1310
    load_reg( R_EAX, Rm );
nkeynes@586
  1311
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1312
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1313
    MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  1314
    store_reg( R_EAX, 0 );
nkeynes@417
  1315
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1316
:}
nkeynes@374
  1317
MOV.L Rm, @Rn {:
nkeynes@671
  1318
    COUNT_INST(I_MOVL);
nkeynes@586
  1319
    load_reg( R_EAX, Rn );
nkeynes@586
  1320
    check_walign32(R_EAX);
nkeynes@586
  1321
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1322
    MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1323
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1324
:}
nkeynes@361
  1325
MOV.L Rm, @-Rn {:  
nkeynes@671
  1326
    COUNT_INST(I_MOVL);
nkeynes@586
  1327
    load_reg( R_EAX, Rn );
nkeynes@586
  1328
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1329
    check_walign32( R_EAX );
nkeynes@586
  1330
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1331
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@929
  1332
    MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1333
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1334
:}
nkeynes@361
  1335
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1336
    COUNT_INST(I_MOVL);
nkeynes@361
  1337
    load_reg( R_EAX, 0 );
nkeynes@361
  1338
    load_reg( R_ECX, Rn );
nkeynes@586
  1339
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1340
    check_walign32( R_EAX );
nkeynes@586
  1341
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1342
    MEM_WRITE_LONG_CACHED( R_EAX, Rm, 0 );
nkeynes@417
  1343
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1344
:}
nkeynes@361
  1345
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1346
    COUNT_INST(I_MOVL);
nkeynes@586
  1347
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1348
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1349
    check_walign32( R_EAX );
nkeynes@586
  1350
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1351
    MEM_WRITE_LONG_CACHED( R_EAX, 0, 16 );
nkeynes@417
  1352
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1353
:}
nkeynes@361
  1354
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1355
    COUNT_INST(I_MOVL);
nkeynes@586
  1356
    load_reg( R_EAX, Rn );
nkeynes@586
  1357
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1358
    check_walign32( R_EAX );
nkeynes@586
  1359
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1360
    MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1361
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1362
:}
nkeynes@361
  1363
MOV.L @Rm, Rn {:  
nkeynes@671
  1364
    COUNT_INST(I_MOVL);
nkeynes@586
  1365
    load_reg( R_EAX, Rm );
nkeynes@586
  1366
    check_ralign32( R_EAX );
nkeynes@586
  1367
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1368
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@361
  1369
    store_reg( R_EAX, Rn );
nkeynes@417
  1370
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1371
:}
nkeynes@361
  1372
MOV.L @Rm+, Rn {:  
nkeynes@671
  1373
    COUNT_INST(I_MOVL);
nkeynes@361
  1374
    load_reg( R_EAX, Rm );
nkeynes@382
  1375
    check_ralign32( R_EAX );
nkeynes@586
  1376
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1377
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  1378
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@361
  1379
    store_reg( R_EAX, Rn );
nkeynes@417
  1380
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1381
:}
nkeynes@361
  1382
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1383
    COUNT_INST(I_MOVL);
nkeynes@361
  1384
    load_reg( R_EAX, 0 );
nkeynes@361
  1385
    load_reg( R_ECX, Rm );
nkeynes@586
  1386
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1387
    check_ralign32( R_EAX );
nkeynes@586
  1388
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1389
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, 0 );
nkeynes@361
  1390
    store_reg( R_EAX, Rn );
nkeynes@417
  1391
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1392
:}
nkeynes@361
  1393
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1394
    COUNT_INST(I_MOVL);
nkeynes@586
  1395
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1396
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1397
    check_ralign32( R_EAX );
nkeynes@586
  1398
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1399
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, 16 );
nkeynes@361
  1400
    store_reg( R_EAX, 0 );
nkeynes@417
  1401
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1402
:}
nkeynes@361
  1403
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1404
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1405
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1406
	SLOTILLEGAL();
nkeynes@374
  1407
    } else {
nkeynes@388
  1408
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1409
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1410
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1411
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1412
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1413
nkeynes@586
  1414
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1415
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1416
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1417
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1418
	    // behaviour though.
nkeynes@586
  1419
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1420
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1421
	} else {
nkeynes@586
  1422
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1423
	    // different virtual address than the translation was done with,
nkeynes@586
  1424
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1425
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1426
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1427
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1428
	    MEM_READ_LONG_CACHED( R_EAX, R_EAX, 16 );
nkeynes@586
  1429
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1430
	}
nkeynes@382
  1431
	store_reg( R_EAX, Rn );
nkeynes@374
  1432
    }
nkeynes@361
  1433
:}
nkeynes@361
  1434
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1435
    COUNT_INST(I_MOVL);
nkeynes@586
  1436
    load_reg( R_EAX, Rm );
nkeynes@586
  1437
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1438
    check_ralign32( R_EAX );
nkeynes@586
  1439
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1440
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@361
  1441
    store_reg( R_EAX, Rn );
nkeynes@417
  1442
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1443
:}
nkeynes@361
  1444
MOV.W Rm, @Rn {:  
nkeynes@671
  1445
    COUNT_INST(I_MOVW);
nkeynes@586
  1446
    load_reg( R_EAX, Rn );
nkeynes@586
  1447
    check_walign16( R_EAX );
nkeynes@586
  1448
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@929
  1449
    MEM_WRITE_WORD_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1450
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1451
:}
nkeynes@361
  1452
MOV.W Rm, @-Rn {:  
nkeynes@671
  1453
    COUNT_INST(I_MOVW);
nkeynes@586
  1454
    load_reg( R_EAX, Rn );
nkeynes@586
  1455
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1456
    check_walign16( R_EAX );
nkeynes@586
  1457
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1458
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@929
  1459
    MEM_WRITE_WORD_CACHED( R_EAX, Rm, Rn );
nkeynes@417
  1460
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1461
:}
nkeynes@361
  1462
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1463
    COUNT_INST(I_MOVW);
nkeynes@361
  1464
    load_reg( R_EAX, 0 );
nkeynes@361
  1465
    load_reg( R_ECX, Rn );
nkeynes@586
  1466
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1467
    check_walign16( R_EAX );
nkeynes@586
  1468
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1469
    MEM_WRITE_WORD_CACHED( R_EAX, Rm, 0 );
nkeynes@417
  1470
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1471
:}
nkeynes@361
  1472
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1473
    COUNT_INST(I_MOVW);
nkeynes@586
  1474
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1475
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1476
    check_walign16( R_EAX );
nkeynes@586
  1477
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1478
    MEM_WRITE_WORD_CACHED( R_EAX, 0, 16 );
nkeynes@417
  1479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1480
:}
nkeynes@361
  1481
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1482
    COUNT_INST(I_MOVW);
nkeynes@586
  1483
    load_reg( R_EAX, Rn );
nkeynes@586
  1484
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1485
    check_walign16( R_EAX );
nkeynes@586
  1486
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1487
    MEM_WRITE_WORD_CACHED( R_EAX, 0, Rn );
nkeynes@417
  1488
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1489
:}
nkeynes@361
  1490
MOV.W @Rm, Rn {:  
nkeynes@671
  1491
    COUNT_INST(I_MOVW);
nkeynes@586
  1492
    load_reg( R_EAX, Rm );
nkeynes@586
  1493
    check_ralign16( R_EAX );
nkeynes@586
  1494
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1495
    MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
nkeynes@361
  1496
    store_reg( R_EAX, Rn );
nkeynes@417
  1497
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1498
:}
nkeynes@361
  1499
MOV.W @Rm+, Rn {:  
nkeynes@671
  1500
    COUNT_INST(I_MOVW);
nkeynes@361
  1501
    load_reg( R_EAX, Rm );
nkeynes@374
  1502
    check_ralign16( R_EAX );
nkeynes@586
  1503
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1504
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@929
  1505
    MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
nkeynes@361
  1506
    store_reg( R_EAX, Rn );
nkeynes@417
  1507
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1508
:}
nkeynes@361
  1509
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1510
    COUNT_INST(I_MOVW);
nkeynes@361
  1511
    load_reg( R_EAX, 0 );
nkeynes@361
  1512
    load_reg( R_ECX, Rm );
nkeynes@586
  1513
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1514
    check_ralign16( R_EAX );
nkeynes@586
  1515
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1516
    MEM_READ_WORD_CACHED( R_EAX, R_EAX, 0 );
nkeynes@361
  1517
    store_reg( R_EAX, Rn );
nkeynes@417
  1518
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1519
:}
nkeynes@361
  1520
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1521
    COUNT_INST(I_MOVW);
nkeynes@586
  1522
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1523
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1524
    check_ralign16( R_EAX );
nkeynes@586
  1525
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1526
    MEM_READ_WORD_CACHED( R_EAX, R_EAX, 16 );
nkeynes@361
  1527
    store_reg( R_EAX, 0 );
nkeynes@417
  1528
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1529
:}
nkeynes@361
  1530
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1531
    COUNT_INST(I_MOVW);
nkeynes@374
  1532
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1533
	SLOTILLEGAL();
nkeynes@374
  1534
    } else {
nkeynes@586
  1535
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1536
	uint32_t target = pc + disp + 4;
nkeynes@586
  1537
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1538
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1539
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1540
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1541
	} else {
nkeynes@586
  1542
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1543
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1544
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1545
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1546
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1547
	}
nkeynes@374
  1548
	store_reg( R_EAX, Rn );
nkeynes@374
  1549
    }
nkeynes@361
  1550
:}
nkeynes@361
  1551
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1552
    COUNT_INST(I_MOVW);
nkeynes@586
  1553
    load_reg( R_EAX, Rm );
nkeynes@586
  1554
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1555
    check_ralign16( R_EAX );
nkeynes@586
  1556
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1557
    MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
nkeynes@361
  1558
    store_reg( R_EAX, 0 );
nkeynes@417
  1559
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1560
:}
nkeynes@361
  1561
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1562
    COUNT_INST(I_MOVA);
nkeynes@374
  1563
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1564
	SLOTILLEGAL();
nkeynes@374
  1565
    } else {
nkeynes@586
  1566
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1567
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1568
	store_reg( R_ECX, 0 );
nkeynes@586
  1569
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1570
    }
nkeynes@361
  1571
:}
nkeynes@361
  1572
MOVCA.L R0, @Rn {:  
nkeynes@671
  1573
    COUNT_INST(I_MOVCA);
nkeynes@586
  1574
    load_reg( R_EAX, Rn );
nkeynes@586
  1575
    check_walign32( R_EAX );
nkeynes@586
  1576
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1577
    MEM_WRITE_LONG_CACHED( R_EAX, 0, Rn );
nkeynes@417
  1578
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1579
:}
nkeynes@359
  1580
nkeynes@359
  1581
/* Control transfer instructions */
nkeynes@374
  1582
BF disp {:
nkeynes@671
  1583
    COUNT_INST(I_BF);
nkeynes@374
  1584
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1585
	SLOTILLEGAL();
nkeynes@374
  1586
    } else {
nkeynes@586
  1587
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1588
	JT_rel8( nottaken );
nkeynes@586
  1589
	exit_block_rel(target, pc+2 );
nkeynes@380
  1590
	JMP_TARGET(nottaken);
nkeynes@408
  1591
	return 2;
nkeynes@374
  1592
    }
nkeynes@374
  1593
:}
nkeynes@374
  1594
BF/S disp {:
nkeynes@671
  1595
    COUNT_INST(I_BFS);
nkeynes@374
  1596
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1597
	SLOTILLEGAL();
nkeynes@374
  1598
    } else {
nkeynes@590
  1599
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1600
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1601
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1602
	    JT_rel8(nottaken);
nkeynes@601
  1603
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1604
	    JMP_TARGET(nottaken);
nkeynes@601
  1605
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1606
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1607
	    exit_block_emu(pc+2);
nkeynes@601
  1608
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1609
	    return 2;
nkeynes@601
  1610
	} else {
nkeynes@601
  1611
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1612
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1613
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1614
	    }
nkeynes@601
  1615
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1616
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1617
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1618
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1619
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1620
	    
nkeynes@601
  1621
	    // not taken
nkeynes@601
  1622
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1623
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1624
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1625
	    return 4;
nkeynes@417
  1626
	}
nkeynes@374
  1627
    }
nkeynes@374
  1628
:}
nkeynes@374
  1629
BRA disp {:  
nkeynes@671
  1630
    COUNT_INST(I_BRA);
nkeynes@374
  1631
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1632
	SLOTILLEGAL();
nkeynes@374
  1633
    } else {
nkeynes@590
  1634
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1635
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1636
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1637
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1638
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1639
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1640
	    exit_block_emu(pc+2);
nkeynes@601
  1641
	    return 2;
nkeynes@601
  1642
	} else {
nkeynes@601
  1643
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1644
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1645
	    return 4;
nkeynes@601
  1646
	}
nkeynes@374
  1647
    }
nkeynes@374
  1648
:}
nkeynes@374
  1649
BRAF Rn {:  
nkeynes@671
  1650
    COUNT_INST(I_BRAF);
nkeynes@374
  1651
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1652
	SLOTILLEGAL();
nkeynes@374
  1653
    } else {
nkeynes@590
  1654
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1655
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1656
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1657
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1658
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1659
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1660
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1661
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1662
	    exit_block_emu(pc+2);
nkeynes@601
  1663
	    return 2;
nkeynes@601
  1664
	} else {
nkeynes@601
  1665
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1666
	    exit_block_newpcset(pc+2);
nkeynes@601
  1667
	    return 4;
nkeynes@601
  1668
	}
nkeynes@374
  1669
    }
nkeynes@374
  1670
:}
nkeynes@374
  1671
BSR disp {:  
nkeynes@671
  1672
    COUNT_INST(I_BSR);
nkeynes@374
  1673
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1674
	SLOTILLEGAL();
nkeynes@374
  1675
    } else {
nkeynes@590
  1676
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1677
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1678
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1679
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1680
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1681
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1682
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1683
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1684
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1685
	    exit_block_emu(pc+2);
nkeynes@601
  1686
	    return 2;
nkeynes@601
  1687
	} else {
nkeynes@601
  1688
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1689
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1690
	    return 4;
nkeynes@601
  1691
	}
nkeynes@374
  1692
    }
nkeynes@374
  1693
:}
nkeynes@374
  1694
BSRF Rn {:  
nkeynes@671
  1695
    COUNT_INST(I_BSRF);
nkeynes@374
  1696
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1697
	SLOTILLEGAL();
nkeynes@374
  1698
    } else {
nkeynes@590
  1699
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1700
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1701
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1702
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1703
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1704
nkeynes@601
  1705
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1706
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1707
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1708
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1709
	    exit_block_emu(pc+2);
nkeynes@601
  1710
	    return 2;
nkeynes@601
  1711
	} else {
nkeynes@601
  1712
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1713
	    exit_block_newpcset(pc+2);
nkeynes@601
  1714
	    return 4;
nkeynes@601
  1715
	}
nkeynes@374
  1716
    }
nkeynes@374
  1717
:}
nkeynes@374
  1718
BT disp {:
nkeynes@671
  1719
    COUNT_INST(I_BT);
nkeynes@374
  1720
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1721
	SLOTILLEGAL();
nkeynes@374
  1722
    } else {
nkeynes@586
  1723
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1724
	JF_rel8( nottaken );
nkeynes@586
  1725
	exit_block_rel(target, pc+2 );
nkeynes@380
  1726
	JMP_TARGET(nottaken);
nkeynes@408
  1727
	return 2;
nkeynes@374
  1728
    }
nkeynes@374
  1729
:}
nkeynes@374
  1730
BT/S disp {:
nkeynes@671
  1731
    COUNT_INST(I_BTS);
nkeynes@374
  1732
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1733
	SLOTILLEGAL();
nkeynes@374
  1734
    } else {
nkeynes@590
  1735
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1736
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1737
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1738
	    JF_rel8(nottaken);
nkeynes@601
  1739
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1740
	    JMP_TARGET(nottaken);
nkeynes@601
  1741
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1742
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1743
	    exit_block_emu(pc+2);
nkeynes@601
  1744
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1745
	    return 2;
nkeynes@601
  1746
	} else {
nkeynes@601
  1747
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1748
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1749
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1750
	    }
nkeynes@601
  1751
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1752
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1753
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1754
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1755
	    // not taken
nkeynes@601
  1756
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1757
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1758
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1759
	    return 4;
nkeynes@417
  1760
	}
nkeynes@374
  1761
    }
nkeynes@374
  1762
:}
nkeynes@374
  1763
JMP @Rn {:  
nkeynes@671
  1764
    COUNT_INST(I_JMP);
nkeynes@374
  1765
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1766
	SLOTILLEGAL();
nkeynes@374
  1767
    } else {
nkeynes@408
  1768
	load_reg( R_ECX, Rn );
nkeynes@590
  1769
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1770
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1771
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1772
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1773
	    exit_block_emu(pc+2);
nkeynes@601
  1774
	    return 2;
nkeynes@601
  1775
	} else {
nkeynes@601
  1776
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1777
	    exit_block_newpcset(pc+2);
nkeynes@601
  1778
	    return 4;
nkeynes@601
  1779
	}
nkeynes@374
  1780
    }
nkeynes@374
  1781
:}
nkeynes@374
  1782
JSR @Rn {:  
nkeynes@671
  1783
    COUNT_INST(I_JSR);
nkeynes@374
  1784
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1785
	SLOTILLEGAL();
nkeynes@374
  1786
    } else {
nkeynes@590
  1787
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1788
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1789
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1790
	load_reg( R_ECX, Rn );
nkeynes@590
  1791
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1792
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1793
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1794
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1795
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1796
	    exit_block_emu(pc+2);
nkeynes@601
  1797
	    return 2;
nkeynes@601
  1798
	} else {
nkeynes@601
  1799
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1800
	    exit_block_newpcset(pc+2);
nkeynes@601
  1801
	    return 4;
nkeynes@601
  1802
	}
nkeynes@374
  1803
    }
nkeynes@374
  1804
:}
nkeynes@374
  1805
RTE {:  
nkeynes@671
  1806
    COUNT_INST(I_RTE);
nkeynes@374
  1807
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1808
	SLOTILLEGAL();
nkeynes@374
  1809
    } else {
nkeynes@408
  1810
	check_priv();
nkeynes@408
  1811
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1812
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1813
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1814
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1815
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1816
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1817
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1818
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1819
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1820
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1821
	    exit_block_emu(pc+2);
nkeynes@601
  1822
	    return 2;
nkeynes@601
  1823
	} else {
nkeynes@601
  1824
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1825
	    exit_block_newpcset(pc+2);
nkeynes@601
  1826
	    return 4;
nkeynes@601
  1827
	}
nkeynes@374
  1828
    }
nkeynes@374
  1829
:}
nkeynes@374
  1830
RTS {:  
nkeynes@671
  1831
    COUNT_INST(I_RTS);
nkeynes@374
  1832
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1833
	SLOTILLEGAL();
nkeynes@374
  1834
    } else {
nkeynes@408
  1835
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1836
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1837
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1838
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1839
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1840
	    exit_block_emu(pc+2);
nkeynes@601
  1841
	    return 2;
nkeynes@601
  1842
	} else {
nkeynes@601
  1843
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1844
	    exit_block_newpcset(pc+2);
nkeynes@601
  1845
	    return 4;
nkeynes@601
  1846
	}
nkeynes@374
  1847
    }
nkeynes@374
  1848
:}
nkeynes@374
  1849
TRAPA #imm {:  
nkeynes@671
  1850
    COUNT_INST(I_TRAPA);
nkeynes@374
  1851
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1852
	SLOTILLEGAL();
nkeynes@374
  1853
    } else {
nkeynes@590
  1854
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1855
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1856
	load_imm32( R_EAX, imm );
nkeynes@527
  1857
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1858
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1859
	exit_block_pcset(pc);
nkeynes@409
  1860
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1861
	return 2;
nkeynes@374
  1862
    }
nkeynes@374
  1863
:}
nkeynes@374
  1864
UNDEF {:  
nkeynes@671
  1865
    COUNT_INST(I_UNDEF);
nkeynes@374
  1866
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1867
	SLOTILLEGAL();
nkeynes@374
  1868
    } else {
nkeynes@586
  1869
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1870
	return 2;
nkeynes@374
  1871
    }
nkeynes@368
  1872
:}
nkeynes@374
  1873
nkeynes@374
  1874
CLRMAC {:  
nkeynes@671
  1875
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1876
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1877
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1878
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1879
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1880
:}
nkeynes@374
  1881
CLRS {:
nkeynes@671
  1882
    COUNT_INST(I_CLRS);
nkeynes@374
  1883
    CLC();
nkeynes@374
  1884
    SETC_sh4r(R_S);
nkeynes@872
  1885
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1886
:}
nkeynes@374
  1887
CLRT {:  
nkeynes@671
  1888
    COUNT_INST(I_CLRT);
nkeynes@374
  1889
    CLC();
nkeynes@374
  1890
    SETC_t();
nkeynes@417
  1891
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1892
:}
nkeynes@374
  1893
SETS {:  
nkeynes@671
  1894
    COUNT_INST(I_SETS);
nkeynes@374
  1895
    STC();
nkeynes@374
  1896
    SETC_sh4r(R_S);
nkeynes@872
  1897
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1898
:}
nkeynes@374
  1899
SETT {:  
nkeynes@671
  1900
    COUNT_INST(I_SETT);
nkeynes@374
  1901
    STC();
nkeynes@374
  1902
    SETC_t();
nkeynes@417
  1903
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1904
:}
nkeynes@359
  1905
nkeynes@375
  1906
/* Floating point moves */
nkeynes@375
  1907
FMOV FRm, FRn {:  
nkeynes@671
  1908
    COUNT_INST(I_FMOV1);
nkeynes@377
  1909
    check_fpuen();
nkeynes@901
  1910
    if( sh4_x86.double_size ) {
nkeynes@901
  1911
        load_dr0( R_EAX, FRm );
nkeynes@901
  1912
        load_dr1( R_ECX, FRm );
nkeynes@901
  1913
        store_dr0( R_EAX, FRn );
nkeynes@901
  1914
        store_dr1( R_ECX, FRn );
nkeynes@901
  1915
    } else {
nkeynes@901
  1916
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1917
        store_fr( R_EAX, FRn );
nkeynes@901
  1918
    }
nkeynes@375
  1919
:}
nkeynes@416
  1920
FMOV FRm, @Rn {: 
nkeynes@671
  1921
    COUNT_INST(I_FMOV2);
nkeynes@586
  1922
    check_fpuen();
nkeynes@586
  1923
    load_reg( R_EAX, Rn );
nkeynes@901
  1924
    if( sh4_x86.double_size ) {
nkeynes@901
  1925
        check_walign64( R_EAX );
nkeynes@901
  1926
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1927
        MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, Rn );
nkeynes@901
  1928
    } else {
nkeynes@901
  1929
        check_walign32( R_EAX );
nkeynes@901
  1930
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  1931
        MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, Rn );
nkeynes@901
  1932
    }
nkeynes@417
  1933
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1934
:}
nkeynes@375
  1935
FMOV @Rm, FRn {:  
nkeynes@671
  1936
    COUNT_INST(I_FMOV5);
nkeynes@586
  1937
    check_fpuen();
nkeynes@586
  1938
    load_reg( R_EAX, Rm );
nkeynes@901
  1939
    if( sh4_x86.double_size ) {
nkeynes@901
  1940
        check_ralign64( R_EAX );
nkeynes@901
  1941
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1942
        MEM_READ_DOUBLE_CACHED( R_EAX, R_EDX, R_EAX, Rm );
nkeynes@905
  1943
        store_dr0( R_EDX, FRn );
nkeynes@901
  1944
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1945
    } else {
nkeynes@901
  1946
        check_ralign32( R_EAX );
nkeynes@901
  1947
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  1948
        MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@901
  1949
        store_fr( R_EAX, FRn );
nkeynes@901
  1950
    }
nkeynes@417
  1951
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1952
:}
nkeynes@377
  1953
FMOV FRm, @-Rn {:  
nkeynes@671
  1954
    COUNT_INST(I_FMOV3);
nkeynes@586
  1955
    check_fpuen();
nkeynes@586
  1956
    load_reg( R_EAX, Rn );
nkeynes@901
  1957
    if( sh4_x86.double_size ) {
nkeynes@901
  1958
        check_walign64( R_EAX );
nkeynes@929
  1959
        LEA_r32disp8_r32( R_EAX, -8, R_EAX );
nkeynes@901
  1960
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1961
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@929
  1962
        MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, Rn );
nkeynes@901
  1963
    } else {
nkeynes@901
  1964
        check_walign32( R_EAX );
nkeynes@929
  1965
        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@901
  1966
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@901
  1967
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@929
  1968
        MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, Rn );
nkeynes@901
  1969
    }
nkeynes@417
  1970
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1971
:}
nkeynes@416
  1972
FMOV @Rm+, FRn {:
nkeynes@671
  1973
    COUNT_INST(I_FMOV6);
nkeynes@586
  1974
    check_fpuen();
nkeynes@586
  1975
    load_reg( R_EAX, Rm );
nkeynes@901
  1976
    if( sh4_x86.double_size ) {
nkeynes@901
  1977
        check_ralign64( R_EAX );
nkeynes@901
  1978
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1979
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@929
  1980
        MEM_READ_DOUBLE_CACHED( R_EAX, R_EDX, R_EAX, Rm );
nkeynes@905
  1981
        store_dr0( R_EDX, FRn );
nkeynes@901
  1982
        store_dr1( R_EAX, FRn );
nkeynes@901
  1983
    } else {
nkeynes@901
  1984
        check_ralign32( R_EAX );
nkeynes@901
  1985
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1986
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  1987
        MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@901
  1988
        store_fr( R_EAX, FRn );
nkeynes@901
  1989
    }
nkeynes@417
  1990
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1991
:}
nkeynes@377
  1992
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1993
    COUNT_INST(I_FMOV4);
nkeynes@586
  1994
    check_fpuen();
nkeynes@586
  1995
    load_reg( R_EAX, Rn );
nkeynes@586
  1996
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1997
    if( sh4_x86.double_size ) {
nkeynes@901
  1998
        check_walign64( R_EAX );
nkeynes@901
  1999
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  2000
        MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, 0 );
nkeynes@901
  2001
    } else {
nkeynes@901
  2002
        check_walign32( R_EAX );
nkeynes@901
  2003
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  2004
        MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, 0 );
nkeynes@901
  2005
    }
nkeynes@417
  2006
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2007
:}
nkeynes@377
  2008
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  2009
    COUNT_INST(I_FMOV7);
nkeynes@586
  2010
    check_fpuen();
nkeynes@586
  2011
    load_reg( R_EAX, Rm );
nkeynes@586
  2012
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  2013
    if( sh4_x86.double_size ) {
nkeynes@901
  2014
        check_ralign64( R_EAX );
nkeynes@901
  2015
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  2016
        MEM_READ_DOUBLE_CACHED( R_EAX, R_ECX, R_EAX, 0 );
nkeynes@901
  2017
        store_dr0( R_ECX, FRn );
nkeynes@901
  2018
        store_dr1( R_EAX, FRn );
nkeynes@901
  2019
    } else {
nkeynes@901
  2020
        check_ralign32( R_EAX );
nkeynes@901
  2021
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@929
  2022
        MEM_READ_LONG_CACHED( R_EAX, R_EAX, 0 );
nkeynes@901
  2023
        store_fr( R_EAX, FRn );
nkeynes@901
  2024
    }
nkeynes@417
  2025
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2026
:}
nkeynes@377
  2027
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  2028
    COUNT_INST(I_FLDI0);
nkeynes@377
  2029
    check_fpuen();
nkeynes@901
  2030
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2031
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  2032
        store_fr( R_EAX, FRn );
nkeynes@901
  2033
    }
nkeynes@417
  2034
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2035
:}
nkeynes@377
  2036
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  2037
    COUNT_INST(I_FLDI1);
nkeynes@377
  2038
    check_fpuen();
nkeynes@901
  2039
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2040
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  2041
        store_fr( R_EAX, FRn );
nkeynes@901
  2042
    }
nkeynes@377
  2043
:}
nkeynes@377
  2044
nkeynes@377
  2045
FLOAT FPUL, FRn {:  
nkeynes@671
  2046
    COUNT_INST(I_FLOAT);
nkeynes@377
  2047
    check_fpuen();
nkeynes@377
  2048
    FILD_sh4r(R_FPUL);
nkeynes@901
  2049
    if( sh4_x86.double_prec ) {
nkeynes@901
  2050
        pop_dr( FRn );
nkeynes@901
  2051
    } else {
nkeynes@901
  2052
        pop_fr( FRn );
nkeynes@901
  2053
    }
nkeynes@377
  2054
:}
nkeynes@377
  2055
FTRC FRm, FPUL {:  
nkeynes@671
  2056
    COUNT_INST(I_FTRC);
nkeynes@377
  2057
    check_fpuen();
nkeynes@901
  2058
    if( sh4_x86.double_prec ) {
nkeynes@901
  2059
        push_dr( FRm );
nkeynes@901
  2060
    } else {
nkeynes@901
  2061
        push_fr( FRm );
nkeynes@901
  2062
    }
nkeynes@789
  2063
    load_ptr( R_ECX, &max_int );
nkeynes@388
  2064
    FILD_r32ind( R_ECX );
nkeynes@388
  2065
    FCOMIP_st(1);
nkeynes@669
  2066
    JNA_rel8( sat );
nkeynes@789
  2067
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  2068
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  2069
    FCOMIP_st(1);                   // 2
nkeynes@669
  2070
    JAE_rel8( sat2 );            // 2
nkeynes@789
  2071
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  2072
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2073
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2074
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2075
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2076
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2077
    JMP_rel8(end);             // 2
nkeynes@388
  2078
nkeynes@388
  2079
    JMP_TARGET(sat);
nkeynes@388
  2080
    JMP_TARGET(sat2);
nkeynes@388
  2081
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2082
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2083
    FPOP_st();
nkeynes@388
  2084
    JMP_TARGET(end);
nkeynes@417
  2085
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2086
:}
nkeynes@377
  2087
FLDS FRm, FPUL {:  
nkeynes@671
  2088
    COUNT_INST(I_FLDS);
nkeynes@377
  2089
    check_fpuen();
nkeynes@669
  2090
    load_fr( R_EAX, FRm );
nkeynes@377
  2091
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2092
:}
nkeynes@377
  2093
FSTS FPUL, FRn {:  
nkeynes@671
  2094
    COUNT_INST(I_FSTS);
nkeynes@377
  2095
    check_fpuen();
nkeynes@377
  2096
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2097
    store_fr( R_EAX, FRn );
nkeynes@377
  2098
:}
nkeynes@377
  2099
FCNVDS FRm, FPUL {:  
nkeynes@671
  2100
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2101
    check_fpuen();
nkeynes@901
  2102
    if( sh4_x86.double_prec ) {
nkeynes@901
  2103
        push_dr( FRm );
nkeynes@901
  2104
        pop_fpul();
nkeynes@901
  2105
    }
nkeynes@377
  2106
:}
nkeynes@377
  2107
FCNVSD FPUL, FRn {:  
nkeynes@671
  2108
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2109
    check_fpuen();
nkeynes@901
  2110
    if( sh4_x86.double_prec ) {
nkeynes@901
  2111
        push_fpul();
nkeynes@901
  2112
        pop_dr( FRn );
nkeynes@901
  2113
    }
nkeynes@377
  2114
:}
nkeynes@375
  2115
nkeynes@359
  2116
/* Floating point instructions */
nkeynes@374
  2117
FABS FRn {:  
nkeynes@671
  2118
    COUNT_INST(I_FABS);
nkeynes@377
  2119
    check_fpuen();
nkeynes@901
  2120
    if( sh4_x86.double_prec ) {
nkeynes@901
  2121
        push_dr(FRn);
nkeynes@901
  2122
        FABS_st0();
nkeynes@901
  2123
        pop_dr(FRn);
nkeynes@901
  2124
    } else {
nkeynes@901
  2125
        push_fr(FRn);
nkeynes@901
  2126
        FABS_st0();
nkeynes@901
  2127
        pop_fr(FRn);
nkeynes@901
  2128
    }
nkeynes@374
  2129
:}
nkeynes@377
  2130
FADD FRm, FRn {:  
nkeynes@671
  2131
    COUNT_INST(I_FADD);
nkeynes@377
  2132
    check_fpuen();
nkeynes@901
  2133
    if( sh4_x86.double_prec ) {
nkeynes@901
  2134
        push_dr(FRm);
nkeynes@901
  2135
        push_dr(FRn);
nkeynes@901
  2136
        FADDP_st(1);
nkeynes@901
  2137
        pop_dr(FRn);
nkeynes@901
  2138
    } else {
nkeynes@901
  2139
        push_fr(FRm);
nkeynes@901
  2140
        push_fr(FRn);
nkeynes@901
  2141
        FADDP_st(1);
nkeynes@901
  2142
        pop_fr(FRn);
nkeynes@901
  2143
    }
nkeynes@375
  2144
:}
nkeynes@377
  2145
FDIV FRm, FRn {:  
nkeynes@671
  2146
    COUNT_INST(I_FDIV);
nkeynes@377
  2147
    check_fpuen();
nkeynes@901
  2148
    if( sh4_x86.double_prec ) {
nkeynes@901
  2149
        push_dr(FRn);
nkeynes@901
  2150
        push_dr(FRm);
nkeynes@901
  2151
        FDIVP_st(1);
nkeynes@901
  2152
        pop_dr(FRn);
nkeynes@901
  2153
    } else {
nkeynes@901
  2154
        push_fr(FRn);
nkeynes@901
  2155
        push_fr(FRm);
nkeynes@901
  2156
        FDIVP_st(1);
nkeynes@901
  2157
        pop_fr(FRn);
nkeynes@901
  2158
    }
nkeynes@375
  2159
:}
nkeynes@375
  2160
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2161
    COUNT_INST(I_FMAC);
nkeynes@377
  2162
    check_fpuen();
nkeynes@901
  2163
    if( sh4_x86.double_prec ) {
nkeynes@901
  2164
        push_dr( 0 );
nkeynes@901
  2165
        push_dr( FRm );
nkeynes@901
  2166
        FMULP_st(1);
nkeynes@901
  2167
        push_dr( FRn );
nkeynes@901
  2168
        FADDP_st(1);
nkeynes@901
  2169
        pop_dr( FRn );
nkeynes@901
  2170
    } else {
nkeynes@901
  2171
        push_fr( 0 );
nkeynes@901
  2172
        push_fr( FRm );
nkeynes@901
  2173
        FMULP_st(1);
nkeynes@901
  2174
        push_fr( FRn );
nkeynes@901
  2175
        FADDP_st(1);
nkeynes@901
  2176
        pop_fr( FRn );
nkeynes@901
  2177
    }
nkeynes@375
  2178
:}
nkeynes@375
  2179
nkeynes@377
  2180
FMUL FRm, FRn {:  
nkeynes@671
  2181
    COUNT_INST(I_FMUL);
nkeynes@377
  2182
    check_fpuen();
nkeynes@901
  2183
    if( sh4_x86.double_prec ) {
nkeynes@901
  2184
        push_dr(FRm);
nkeynes@901
  2185
        push_dr(FRn);
nkeynes@901
  2186
        FMULP_st(1);
nkeynes@901
  2187
        pop_dr(FRn);
nkeynes@901
  2188
    } else {
nkeynes@901
  2189
        push_fr(FRm);
nkeynes@901
  2190
        push_fr(FRn);
nkeynes@901
  2191
        FMULP_st(1);
nkeynes@901
  2192
        pop_fr(FRn);
nkeynes@901
  2193
    }
nkeynes@377
  2194
:}
nkeynes@377
  2195
FNEG FRn {:  
nkeynes@671
  2196
    COUNT_INST(I_FNEG);
nkeynes@377
  2197
    check_fpuen();
nkeynes@901
  2198
    if( sh4_x86.double_prec ) {
nkeynes@901
  2199
        push_dr(FRn);
nkeynes@901
  2200
        FCHS_st0();
nkeynes@901
  2201
        pop_dr(FRn);
nkeynes@901
  2202
    } else {
nkeynes@901
  2203
        push_fr(FRn);
nkeynes@901
  2204
        FCHS_st0();
nkeynes@901
  2205
        pop_fr(FRn);
nkeynes@901
  2206
    }
nkeynes@377
  2207
:}
nkeynes@377
  2208
FSRRA FRn {:  
nkeynes@671
  2209
    COUNT_INST(I_FSRRA);
nkeynes@377
  2210
    check_fpuen();
nkeynes@901
  2211
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2212
        FLD1_st0();
nkeynes@901
  2213
        push_fr(FRn);
nkeynes@901
  2214
        FSQRT_st0();
nkeynes@901
  2215
        FDIVP_st(1);
nkeynes@901
  2216
        pop_fr(FRn);
nkeynes@901
  2217
    }
nkeynes@377
  2218
:}
nkeynes@377
  2219
FSQRT FRn {:  
nkeynes@671
  2220
    COUNT_INST(I_FSQRT);
nkeynes@377
  2221
    check_fpuen();
nkeynes@901
  2222
    if( sh4_x86.double_prec ) {
nkeynes@901
  2223
        push_dr(FRn);
nkeynes@901
  2224
        FSQRT_st0();
nkeynes@901
  2225
        pop_dr(FRn);
nkeynes@901
  2226
    } else {
nkeynes@901
  2227
        push_fr(FRn);
nkeynes@901
  2228
        FSQRT_st0();
nkeynes@901
  2229
        pop_fr(FRn);
nkeynes@901
  2230
    }
nkeynes@377
  2231
:}
nkeynes@377
  2232
FSUB FRm, FRn {:  
nkeynes@671
  2233
    COUNT_INST(I_FSUB);
nkeynes@377
  2234
    check_fpuen();
nkeynes@901
  2235
    if( sh4_x86.double_prec ) {
nkeynes@901
  2236
        push_dr(FRn);
nkeynes@901
  2237
        push_dr(FRm);
nkeynes@901
  2238
        FSUBP_st(1);
nkeynes@901
  2239
        pop_dr(FRn);
nkeynes@901
  2240
    } else {
nkeynes@901
  2241
        push_fr(FRn);
nkeynes@901
  2242
        push_fr(FRm);
nkeynes@901
  2243
        FSUBP_st(1);
nkeynes@901
  2244
        pop_fr(FRn);
nkeynes@901
  2245
    }
nkeynes@377
  2246
:}
nkeynes@377
  2247
nkeynes@377
  2248
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2249
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2250
    check_fpuen();
nkeynes@901
  2251
    if( sh4_x86.double_prec ) {
nkeynes@901
  2252
        push_dr(FRm);
nkeynes@901
  2253
        push_dr(FRn);
nkeynes@901
  2254
    } else {
nkeynes@901
  2255
        push_fr(FRm);
nkeynes@901
  2256
        push_fr(FRn);
nkeynes@901
  2257
    }
nkeynes@377
  2258
    FCOMIP_st(1);
nkeynes@377
  2259
    SETE_t();
nkeynes@377
  2260
    FPOP_st();
nkeynes@901
  2261
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2262
:}
nkeynes@377
  2263
FCMP/GT FRm, FRn {:  
nkeynes@671
  2264
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2265
    check_fpuen();
nkeynes@901
  2266
    if( sh4_x86.double_prec ) {
nkeynes@901
  2267
        push_dr(FRm);
nkeynes@901
  2268
        push_dr(FRn);
nkeynes@901
  2269
    } else {
nkeynes@901
  2270
        push_fr(FRm);
nkeynes@901
  2271
        push_fr(FRn);
nkeynes@901
  2272
    }
nkeynes@377
  2273
    FCOMIP_st(1);
nkeynes@377
  2274
    SETA_t();
nkeynes@377
  2275
    FPOP_st();
nkeynes@901
  2276
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2277
:}
nkeynes@377
  2278
nkeynes@377
  2279
FSCA FPUL, FRn {:  
nkeynes@671
  2280
    COUNT_INST(I_FSCA);
nkeynes@377
  2281
    check_fpuen();
nkeynes@901
  2282
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2283
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2284
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2285
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2286
    }
nkeynes@417
  2287
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2288
:}
nkeynes@377
  2289
FIPR FVm, FVn {:  
nkeynes@671
  2290
    COUNT_INST(I_FIPR);
nkeynes@377
  2291
    check_fpuen();
nkeynes@901
  2292
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2293
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2294
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2295
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2296
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2297
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2298
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2299
        } else {
nkeynes@904
  2300
            push_fr( FVm<<2 );
nkeynes@903
  2301
            push_fr( FVn<<2 );
nkeynes@903
  2302
            FMULP_st(1);
nkeynes@903
  2303
            push_fr( (FVm<<2)+1);
nkeynes@903
  2304
            push_fr( (FVn<<2)+1);
nkeynes@903
  2305
            FMULP_st(1);
nkeynes@903
  2306
            FADDP_st(1);
nkeynes@903
  2307
            push_fr( (FVm<<2)+2);
nkeynes@903
  2308
            push_fr( (FVn<<2)+2);
nkeynes@903
  2309
            FMULP_st(1);
nkeynes@903
  2310
            FADDP_st(1);
nkeynes@903
  2311
            push_fr( (FVm<<2)+3);
nkeynes@903
  2312
            push_fr( (FVn<<2)+3);
nkeynes@903
  2313
            FMULP_st(1);
nkeynes@903
  2314
            FADDP_st(1);
nkeynes@903
  2315
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2316
        }
nkeynes@901
  2317
    }
nkeynes@377
  2318
:}
nkeynes@377
  2319
FTRV XMTRX, FVn {:  
nkeynes@671
  2320
    COUNT_INST(I_FTRV);
nkeynes@377
  2321
    check_fpuen();
nkeynes@901
  2322
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2323
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2324
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2325
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2326
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2327
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2328
nkeynes@903
  2329
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2330
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2331
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2332
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2333
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2334
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2335
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2336
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2337
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2338
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2339
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2340
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2341
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2342
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2343
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2344
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2345
        } else {
nkeynes@903
  2346
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2347
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2348
        }
nkeynes@901
  2349
    }
nkeynes@417
  2350
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2351
:}
nkeynes@377
  2352
nkeynes@377
  2353
FRCHG {:  
nkeynes@671
  2354
    COUNT_INST(I_FRCHG);
nkeynes@377
  2355
    check_fpuen();
nkeynes@377
  2356
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2357
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2358
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2359
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2360
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2361
:}
nkeynes@377
  2362
FSCHG {:  
nkeynes@671
  2363
    COUNT_INST(I_FSCHG);
nkeynes@377
  2364
    check_fpuen();
nkeynes@377
  2365
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2366
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2367
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2369
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2370
:}
nkeynes@359
  2371
nkeynes@359
  2372
/* Processor control instructions */
nkeynes@368
  2373
LDC Rm, SR {:
nkeynes@671
  2374
    COUNT_INST(I_LDCSR);
nkeynes@386
  2375
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2376
	SLOTILLEGAL();
nkeynes@386
  2377
    } else {
nkeynes@386
  2378
	check_priv();
nkeynes@386
  2379
	load_reg( R_EAX, Rm );
nkeynes@386
  2380
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2381
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2382
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2383
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2384
    }
nkeynes@368
  2385
:}
nkeynes@359
  2386
LDC Rm, GBR {: 
nkeynes@671
  2387
    COUNT_INST(I_LDC);
nkeynes@359
  2388
    load_reg( R_EAX, Rm );
nkeynes@359
  2389
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2390
:}
nkeynes@359
  2391
LDC Rm, VBR {:  
nkeynes@671
  2392
    COUNT_INST(I_LDC);
nkeynes@386
  2393
    check_priv();
nkeynes@359
  2394
    load_reg( R_EAX, Rm );
nkeynes@359
  2395
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2396
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2397
:}
nkeynes@359
  2398
LDC Rm, SSR {:  
nkeynes@671
  2399
    COUNT_INST(I_LDC);
nkeynes@386
  2400
    check_priv();
nkeynes@359
  2401
    load_reg( R_EAX, Rm );
nkeynes@359
  2402
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2403
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2404
:}
nkeynes@359
  2405
LDC Rm, SGR {:  
nkeynes@671
  2406
    COUNT_INST(I_LDC);
nkeynes@386
  2407
    check_priv();
nkeynes@359
  2408
    load_reg( R_EAX, Rm );
nkeynes@359
  2409
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2410
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2411
:}
nkeynes@359
  2412
LDC Rm, SPC {:  
nkeynes@671
  2413
    COUNT_INST(I_LDC);
nkeynes@386
  2414
    check_priv();
nkeynes@359
  2415
    load_reg( R_EAX, Rm );
nkeynes@359
  2416
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2417
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2418
:}
nkeynes@359
  2419
LDC Rm, DBR {:  
nkeynes@671
  2420
    COUNT_INST(I_LDC);
nkeynes@386
  2421
    check_priv();
nkeynes@359
  2422
    load_reg( R_EAX, Rm );
nkeynes@359
  2423
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2425
:}
nkeynes@374
  2426
LDC Rm, Rn_BANK {:  
nkeynes@671
  2427
    COUNT_INST(I_LDC);
nkeynes@386
  2428
    check_priv();
nkeynes@374
  2429
    load_reg( R_EAX, Rm );
nkeynes@374
  2430
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2431
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2432
:}
nkeynes@359
  2433
LDC.L @Rm+, GBR {:  
nkeynes@671
  2434
    COUNT_INST(I_LDCM);
nkeynes@359
  2435
    load_reg( R_EAX, Rm );
nkeynes@395
  2436
    check_ralign32( R_EAX );
nkeynes@586
  2437
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2438
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2439
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2440
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2441
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2442
:}
nkeynes@368
  2443
LDC.L @Rm+, SR {:
nkeynes@671
  2444
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2445
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2446
	SLOTILLEGAL();
nkeynes@386
  2447
    } else {
nkeynes@586
  2448
	check_priv();
nkeynes@386
  2449
	load_reg( R_EAX, Rm );
nkeynes@395
  2450
	check_ralign32( R_EAX );
nkeynes@586
  2451
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2452
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2453
	MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@386
  2454
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2455
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2456
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2457
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2458
    }
nkeynes@359
  2459
:}
nkeynes@359
  2460
LDC.L @Rm+, VBR {:  
nkeynes@671
  2461
    COUNT_INST(I_LDCM);
nkeynes@586
  2462
    check_priv();
nkeynes@359
  2463
    load_reg( R_EAX, Rm );
nkeynes@395
  2464
    check_ralign32( R_EAX );
nkeynes@586
  2465
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2466
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2467
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2468
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2469
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2470
:}
nkeynes@359
  2471
LDC.L @Rm+, SSR {:
nkeynes@671
  2472
    COUNT_INST(I_LDCM);
nkeynes@586
  2473
    check_priv();
nkeynes@359
  2474
    load_reg( R_EAX, Rm );
nkeynes@416
  2475
    check_ralign32( R_EAX );
nkeynes@586
  2476
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2477
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2478
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2479
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2480
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2481
:}
nkeynes@359
  2482
LDC.L @Rm+, SGR {:  
nkeynes@671
  2483
    COUNT_INST(I_LDCM);
nkeynes@586
  2484
    check_priv();
nkeynes@359
  2485
    load_reg( R_EAX, Rm );
nkeynes@395
  2486
    check_ralign32( R_EAX );
nkeynes@586
  2487
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2488
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2489
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2490
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2491
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2492
:}
nkeynes@359
  2493
LDC.L @Rm+, SPC {:  
nkeynes@671
  2494
    COUNT_INST(I_LDCM);
nkeynes@586
  2495
    check_priv();
nkeynes@359
  2496
    load_reg( R_EAX, Rm );
nkeynes@395
  2497
    check_ralign32( R_EAX );
nkeynes@586
  2498
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2499
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2500
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2501
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2502
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2503
:}
nkeynes@359
  2504
LDC.L @Rm+, DBR {:  
nkeynes@671
  2505
    COUNT_INST(I_LDCM);
nkeynes@586
  2506
    check_priv();
nkeynes@359
  2507
    load_reg( R_EAX, Rm );
nkeynes@395
  2508
    check_ralign32( R_EAX );
nkeynes@586
  2509
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2510
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2511
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2512
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2513
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2514
:}
nkeynes@359
  2515
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2516
    COUNT_INST(I_LDCM);
nkeynes@586
  2517
    check_priv();
nkeynes@374
  2518
    load_reg( R_EAX, Rm );
nkeynes@395
  2519
    check_ralign32( R_EAX );
nkeynes@586
  2520
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2521
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2522
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@374
  2523
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2524
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2525
:}
nkeynes@626
  2526
LDS Rm, FPSCR {:
nkeynes@673
  2527
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2528
    check_fpuen();
nkeynes@359
  2529
    load_reg( R_EAX, Rm );
nkeynes@669
  2530
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2531
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2532
    return 2;
nkeynes@359
  2533
:}
nkeynes@359
  2534
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2535
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2536
    check_fpuen();
nkeynes@359
  2537
    load_reg( R_EAX, Rm );
nkeynes@395
  2538
    check_ralign32( R_EAX );
nkeynes@586
  2539
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2540
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2541
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@669
  2542
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2543
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2544
    return 2;
nkeynes@359
  2545
:}
nkeynes@359
  2546
LDS Rm, FPUL {:  
nkeynes@671
  2547
    COUNT_INST(I_LDS);
nkeynes@626
  2548
    check_fpuen();
nkeynes@359
  2549
    load_reg( R_EAX, Rm );
nkeynes@359
  2550
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2551
:}
nkeynes@359
  2552
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2553
    COUNT_INST(I_LDSM);
nkeynes@626
  2554
    check_fpuen();
nkeynes@359
  2555
    load_reg( R_EAX, Rm );
nkeynes@395
  2556
    check_ralign32( R_EAX );
nkeynes@586
  2557
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2558
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2559
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2560
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2561
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2562
:}
nkeynes@359
  2563
LDS Rm, MACH {: 
nkeynes@671
  2564
    COUNT_INST(I_LDS);
nkeynes@359
  2565
    load_reg( R_EAX, Rm );
nkeynes@359
  2566
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2567
:}
nkeynes@359
  2568
LDS.L @Rm+, MACH {:  
nkeynes@671
  2569
    COUNT_INST(I_LDSM);
nkeynes@359
  2570
    load_reg( R_EAX, Rm );
nkeynes@395
  2571
    check_ralign32( R_EAX );
nkeynes@586
  2572
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2573
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2574
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2575
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2576
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2577
:}
nkeynes@359
  2578
LDS Rm, MACL {:  
nkeynes@671
  2579
    COUNT_INST(I_LDS);
nkeynes@359
  2580
    load_reg( R_EAX, Rm );
nkeynes@359
  2581
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2582
:}
nkeynes@359
  2583
LDS.L @Rm+, MACL {:  
nkeynes@671
  2584
    COUNT_INST(I_LDSM);
nkeynes@359
  2585
    load_reg( R_EAX, Rm );
nkeynes@395
  2586
    check_ralign32( R_EAX );
nkeynes@586
  2587
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2588
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2589
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2590
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2592
:}
nkeynes@359
  2593
LDS Rm, PR {:  
nkeynes@671
  2594
    COUNT_INST(I_LDS);
nkeynes@359
  2595
    load_reg( R_EAX, Rm );
nkeynes@359
  2596
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2597
:}
nkeynes@359
  2598
LDS.L @Rm+, PR {:  
nkeynes@671
  2599
    COUNT_INST(I_LDSM);
nkeynes@359
  2600
    load_reg( R_EAX, Rm );
nkeynes@395
  2601
    check_ralign32( R_EAX );
nkeynes@586
  2602
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2603
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@929
  2604
    MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
nkeynes@359
  2605
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2606
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2607
:}
nkeynes@550
  2608
LDTLB {:  
nkeynes@671
  2609
    COUNT_INST(I_LDTLB);
nkeynes@553
  2610
    call_func0( MMU_ldtlb );
nkeynes@875
  2611
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2612
:}
nkeynes@671
  2613
OCBI @Rn {:
nkeynes@671
  2614
    COUNT_INST(I_OCBI);
nkeynes@671
  2615
:}
nkeynes@671
  2616
OCBP @Rn {:
nkeynes@671
  2617
    COUNT_INST(I_OCBP);
nkeynes@671
  2618
:}
nkeynes@671
  2619
OCBWB @Rn {:
nkeynes@671
  2620
    COUNT_INST(I_OCBWB);
nkeynes@671
  2621
:}
nkeynes@374
  2622
PREF @Rn {:
nkeynes@671
  2623
    COUNT_INST(I_PREF);
nkeynes@374
  2624
    load_reg( R_EAX, Rn );
nkeynes@532
  2625
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2626
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2627
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2628
    JNE_rel8(end);
nkeynes@911
  2629
    if( sh4_x86.tlb_on ) {
nkeynes@911
  2630
    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
nkeynes@911
  2631
        TEST_r32_r32( R_EAX, R_EAX );
nkeynes@911
  2632
        JE_exc(-1);
nkeynes@911
  2633
    } else {
nkeynes@911
  2634
    	call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@911
  2635
   	}
nkeynes@380
  2636
    JMP_TARGET(end);
nkeynes@417
  2637
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2638
:}
nkeynes@388
  2639
SLEEP {: 
nkeynes@671
  2640
    COUNT_INST(I_SLEEP);
nkeynes@388
  2641
    check_priv();
nkeynes@388
  2642
    call_func0( sh4_sleep );
nkeynes@417
  2643
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2644
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2645
    return 2;
nkeynes@388
  2646
:}
nkeynes@386
  2647
STC SR, Rn {:
nkeynes@671
  2648
    COUNT_INST(I_STCSR);
nkeynes@386
  2649
    check_priv();
nkeynes@386
  2650
    call_func0(sh4_read_sr);
nkeynes@386
  2651
    store_reg( R_EAX, Rn );
nkeynes@417
  2652
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2653
:}
nkeynes@359
  2654
STC GBR, Rn {:  
nkeynes@671
  2655
    COUNT_INST(I_STC);
nkeynes@359
  2656
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2657
    store_reg( R_EAX, Rn );
nkeynes@359
  2658
:}
nkeynes@359
  2659
STC VBR, Rn {:  
nkeynes@671
  2660
    COUNT_INST(I_STC);
nkeynes@386
  2661
    check_priv();
nkeynes@359
  2662
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2663
    store_reg( R_EAX, Rn );
nkeynes@417
  2664
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2665
:}
nkeynes@359
  2666
STC SSR, Rn {:  
nkeynes@671
  2667
    COUNT_INST(I_STC);
nkeynes@386
  2668
    check_priv();
nkeynes@359
  2669
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2670
    store_reg( R_EAX, Rn );
nkeynes@417
  2671
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2672
:}
nkeynes@359
  2673
STC SPC, Rn {:  
nkeynes@671
  2674
    COUNT_INST(I_STC);
nkeynes@386
  2675
    check_priv();
nkeynes@359
  2676
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2677
    store_reg( R_EAX, Rn );
nkeynes@417
  2678
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2679
:}
nkeynes@359
  2680
STC SGR, Rn {:  
nkeynes@671
  2681
    COUNT_INST(I_STC);
nkeynes@386
  2682
    check_priv();
nkeynes@359
  2683
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2684
    store_reg( R_EAX, Rn );
nkeynes@417
  2685
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2686
:}
nkeynes@359
  2687
STC DBR, Rn {:  
nkeynes@671
  2688
    COUNT_INST(I_STC);
nkeynes@386
  2689
    check_priv();
nkeynes@359
  2690
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2691
    store_reg( R_EAX, Rn );
nkeynes@417
  2692
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2693
:}
nkeynes@374
  2694
STC Rm_BANK, Rn {:
nkeynes@671
  2695
    COUNT_INST(I_STC);
nkeynes@386
  2696
    check_priv();
nkeynes@374
  2697
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2698
    store_reg( R_EAX, Rn );
nkeynes@417
  2699
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2700
:}
nkeynes@374
  2701
STC.L SR, @-Rn {:
nkeynes@671
  2702
    COUNT_INST(I_STCSRM);
nkeynes@586
  2703
    check_priv();
nkeynes@586
  2704
    load_reg( R_EAX, Rn );
nkeynes@586
  2705
    check_walign32( R_EAX );
nkeynes@586
  2706
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2707
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@929
  2708
    MOV_r32_r32( R_EAX, R_EBX );
nkeynes@395
  2709
    call_func0( sh4_read_sr );
nkeynes@926
  2710
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@586
  2711
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@929
  2712
    MEM_WRITE_LONG( R_EBX, R_EDX );
nkeynes@417
  2713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2714
:}
nkeynes@359
  2715
STC.L VBR, @-Rn {:  
nkeynes@671
  2716
    COUNT_INST(I_STCM);
nkeynes@586
  2717
    check_priv();
nkeynes@586
  2718
    load_reg( R_EAX, Rn );
nkeynes@586
  2719
    check_walign32( R_EAX );
nkeynes@586
  2720
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2721
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2722
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@929
  2723
    MEM_WRITE_LONG_CACHED_SP( R_EAX, R_VBR, Rn );
nkeynes@417
  2724
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2725
:}
nkeynes@359
  2726
STC.L SSR, @-Rn {:  
nkeynes@671
  2727
    COUNT_INST(I_STCM);
nkeynes@586
  2728
    check_priv();
nkeynes@586
  2729
    load_reg( R_EAX, Rn );
nkeynes@586
  2730
    check_walign32( R_EAX );
nkeynes@586
  2731
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2732
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2733