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lxdream.org :: lxdream/src/sh4/timer.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/timer.c
changeset 929:fd8cb0c82f5f
prev859:b941c703ccd6
next975:007bf7eb944f
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
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nkeynes@23
     1
/**
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 * $Id$
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 * 
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 * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
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 * keep things simple (they intertwine a bit).
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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    18
 */
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#include <assert.h>
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#include "lxdream.h"
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#include "mem.h"
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#include "clock.h"
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#include "eventq.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/intc.h"
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/********************************* CPG *************************************/
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/* This is the base clock from which all other clocks are derived. 
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 * Note: The real clock runs at 33Mhz, which is multiplied by the PLL to
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 * run the instruction clock at 200Mhz. For sake of simplicity/precision,
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 * we instead use 200Mhz as the base rate and divide everything down instead.
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 **/
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uint32_t sh4_input_freq = SH4_BASE_RATE;
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uint32_t sh4_cpu_multiplier = 2000; /* = 0.5 * frequency */
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    38
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uint32_t sh4_cpu_freq = SH4_BASE_RATE;
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uint32_t sh4_bus_freq = SH4_BASE_RATE / 2;
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uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 4;
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uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
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uint32_t sh4_bus_period = 2* 1000 / SH4_BASE_RATE;
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uint32_t sh4_peripheral_period = 4 * 2000 / SH4_BASE_RATE;
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    46
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MMIO_REGION_READ_FN( CPG, reg )
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{
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    return MMIO_READ( CPG, reg&0xFFF );
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}
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/* CPU + bus dividers (note officially only the first 6 values are valid) */
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int ifc_divider[8] = { 1, 2, 3, 4, 5, 8, 8, 8 };
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/* Peripheral clock dividers (only first 5 are officially valid) */
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int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
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MMIO_REGION_WRITE_FN( CPG, reg, val )
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{
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    uint32_t div;
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    uint32_t primary_clock = sh4_input_freq;
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    reg &= 0xFFF;
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    switch( reg ) {
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    case FRQCR: /* Frequency control */
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        if( (val & FRQCR_PLL1EN) == 0 )
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            primary_clock /= 6;
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        div = ifc_divider[(val >> 6) & 0x07];
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        sh4_cpu_freq = primary_clock / div;
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        sh4_cpu_period = sh4_cpu_multiplier * div / sh4_input_freq;
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        div = ifc_divider[(val >> 3) & 0x07];
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        sh4_bus_freq = primary_clock / div;
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        sh4_bus_period = 1000 * div / sh4_input_freq;
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        div = pfc_divider[val & 0x07];
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        sh4_peripheral_freq = primary_clock / div;
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        sh4_peripheral_period = 1000 * div / sh4_input_freq;
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        /* Update everything that depends on the peripheral frequency */
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        SCIF_update_line_speed();
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        break;
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    case WTCSR: /* Watchdog timer */
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        break;
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    }
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    MMIO_WRITE( CPG, reg, val );
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}
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/**
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 * We don't really know what the default reset value is as it's determined
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 * by the mode select pins. This is the standard value that the BIOS sets,
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 * however, so it works for now.
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 */
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void CPG_reset( )
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{
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    mmio_region_CPG_write( FRQCR, 0x0E0A );
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}
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    95
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/********************************** RTC *************************************/
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uint32_t rtc_output_period;
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MMIO_REGION_READ_FN( RTC, reg )
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{
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    return MMIO_READ( RTC, reg &0xFFF );
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}
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MMIO_REGION_WRITE_FN( RTC, reg, val )
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{
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    MMIO_WRITE( RTC, reg &0xFFF, val );
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}
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/********************************** TMU *************************************/
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#define TMU_IS_RUNNING(timer)  (MMIO_READ(TMU,TSTR) & (1<<timer))
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uint32_t TMU_count( int timer, uint32_t nanosecs );
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void TMU_event_callback( int eventid )
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{
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    TMU_count( eventid - EVENT_TMU0, sh4r.slice_cycle );
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}
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void TMU_init(void)
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{
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    register_event_callback( EVENT_TMU0, TMU_event_callback );
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    register_event_callback( EVENT_TMU1, TMU_event_callback );
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    register_event_callback( EVENT_TMU2, TMU_event_callback );
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}    
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#define TCR_ICPF 0x0200
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#define TCR_UNF  0x0100
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#define TCR_UNIE 0x0020
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#define TCR_IRQ_ACTIVE (TCR_UNF|TCR_UNIE)
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struct TMU_timer {
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    uint32_t timer_period;
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    uint32_t timer_remainder; /* left-over cycles from last count */
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    uint32_t timer_run; /* cycles already run from this slice */
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};
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static struct TMU_timer TMU_timers[3];
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void TMU_set_timer_control( int timer,  int tcr )
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{
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    uint32_t period = 1;
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    uint32_t oldtcr = MMIO_READ( TMU, TCR0 + (12*timer) );
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   147
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    if( (oldtcr & TCR_UNF) == 0 ) {
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        tcr = tcr & (~TCR_UNF);
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    } else {
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        if( ((oldtcr & TCR_UNIE) == 0) && 
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                (tcr & TCR_IRQ_ACTIVE) == TCR_IRQ_ACTIVE ) {
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            intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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        } else if( (oldtcr & TCR_UNIE) != 0 && 
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                (tcr & TCR_IRQ_ACTIVE) != TCR_IRQ_ACTIVE ) {
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            intc_clear_interrupt( INT_TMU_TUNI0 + timer );
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        }
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    }
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    switch( tcr & 0x07 ) {
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    case 0:
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        period = sh4_peripheral_period << 2 ;
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        break;
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    case 1: 
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        period = sh4_peripheral_period << 4;
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        break;
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    case 2:
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        period = sh4_peripheral_period << 6;
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        break;
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    case 3: 
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        period = sh4_peripheral_period << 8;
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        break;
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    case 4:
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        period = sh4_peripheral_period << 10;
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        break;
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    case 5:
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        /* Illegal value. */
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        ERROR( "TMU %d period set to illegal value (5)", timer );
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        period = sh4_peripheral_period << 12; /* for something to do */
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        break;
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    case 6:
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        period = rtc_output_period;
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        break;
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    case 7:
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        /* External clock... Hrm? */
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        period = sh4_peripheral_period; /* I dunno... */
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        break;
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    }
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    TMU_timers[timer].timer_period = period;
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    MMIO_WRITE( TMU, TCR0 + (12*timer), tcr );
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}
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void TMU_schedule_timer( int timer )
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{
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    uint64_t duration = (uint64_t)((uint32_t)(MMIO_READ( TMU, TCNT0 + 12*timer )+1)) * 
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    (uint64_t)TMU_timers[timer].timer_period - TMU_timers[timer].timer_remainder;
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    event_schedule_long( EVENT_TMU0+timer, (uint32_t)(duration / 1000000000), 
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                         (uint32_t)(duration % 1000000000) );
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}
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void TMU_start( int timer )
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{
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    TMU_timers[timer].timer_run = sh4r.slice_cycle;
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    TMU_timers[timer].timer_remainder = 0;
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    TMU_schedule_timer( timer );
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}
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/**
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 * Stop the given timer. Run it up to the current time and leave it there.
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 */
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void TMU_stop( int timer )
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{
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    TMU_count( timer, sh4r.slice_cycle );
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    event_cancel( EVENT_TMU0+timer );
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}
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/**
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 * Count the specified timer for a given number of nanoseconds.
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 */
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uint32_t TMU_count( int timer, uint32_t nanosecs ) 
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{
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    uint32_t run_ns = nanosecs + TMU_timers[timer].timer_remainder -
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    TMU_timers[timer].timer_run;
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    TMU_timers[timer].timer_remainder = 
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        run_ns % TMU_timers[timer].timer_period;
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    TMU_timers[timer].timer_run = nanosecs;
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    uint32_t count = run_ns / TMU_timers[timer].timer_period;
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    uint32_t value = MMIO_READ( TMU, TCNT0 + 12*timer );
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    uint32_t reset = MMIO_READ( TMU, TCOR0 + 12*timer );
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    if( count > value ) {
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        uint32_t tcr = MMIO_READ( TMU, TCR0 + 12*timer );
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        tcr |= TCR_UNF;
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        count -= value;
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        value = reset - (count % reset) + 1;
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        MMIO_WRITE( TMU, TCR0 + 12*timer, tcr );
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        if( tcr & TCR_UNIE ) 
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            intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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        MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
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        TMU_schedule_timer(timer);
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   241
    } else {
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        value -= count;
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   243
        MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
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    }
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    return value;
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}
nkeynes@23
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nkeynes@929
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MMIO_REGION_READ_FN( TMU, reg )
nkeynes@929
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{
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   250
    reg &= 0xFFF;
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    switch( reg ) {
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    case TCNT0:
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   253
        TMU_count( 0, sh4r.slice_cycle );
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        break;
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   255
    case TCNT1:
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        TMU_count( 1, sh4r.slice_cycle );
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        break;
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   258
    case TCNT2:
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   259
        TMU_count( 2, sh4r.slice_cycle );
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        break;
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   261
    }
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    return MMIO_READ( TMU, reg );
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   263
}
nkeynes@929
   264
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   265
MMIO_REGION_WRITE_FN( TMU, reg, val )
nkeynes@23
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{
nkeynes@53
   267
    uint32_t oldval;
nkeynes@53
   268
    int i;
nkeynes@929
   269
    reg &= 0xFFF;
nkeynes@23
   270
    switch( reg ) {
nkeynes@53
   271
    case TSTR:
nkeynes@736
   272
        oldval = MMIO_READ( TMU, TSTR );
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   273
        for( i=0; i<3; i++ ) {
nkeynes@736
   274
            uint32_t tmp = 1<<i;
nkeynes@736
   275
            if( (oldval & tmp) != 0 && (val&tmp) == 0  )
nkeynes@736
   276
                TMU_stop(i);
nkeynes@736
   277
            else if( (oldval&tmp) == 0 && (val&tmp) != 0 )
nkeynes@736
   278
                TMU_start(i);
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   279
        }
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   280
        break;
nkeynes@53
   281
    case TCR0:
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   282
        TMU_set_timer_control( 0, val );
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   283
        return;
nkeynes@53
   284
    case TCR1:
nkeynes@736
   285
        TMU_set_timer_control( 1, val );
nkeynes@736
   286
        return;
nkeynes@53
   287
    case TCR2:
nkeynes@736
   288
        TMU_set_timer_control( 2, val );
nkeynes@736
   289
        return;
nkeynes@619
   290
    case TCNT0:
nkeynes@736
   291
        MMIO_WRITE( TMU, reg, val );
nkeynes@736
   292
        if( TMU_IS_RUNNING(0) ) { // reschedule
nkeynes@736
   293
            TMU_timers[0].timer_run = sh4r.slice_cycle;
nkeynes@736
   294
            TMU_schedule_timer( 0 );
nkeynes@736
   295
        }
nkeynes@736
   296
        return;
nkeynes@619
   297
    case TCNT1:
nkeynes@736
   298
        MMIO_WRITE( TMU, reg, val );
nkeynes@736
   299
        if( TMU_IS_RUNNING(1) ) { // reschedule
nkeynes@736
   300
            TMU_timers[1].timer_run = sh4r.slice_cycle;
nkeynes@736
   301
            TMU_schedule_timer( 1 );
nkeynes@736
   302
        }
nkeynes@736
   303
        return;
nkeynes@619
   304
    case TCNT2:
nkeynes@736
   305
        MMIO_WRITE( TMU, reg, val );
nkeynes@736
   306
        if( TMU_IS_RUNNING(2) ) { // reschedule
nkeynes@736
   307
            TMU_timers[2].timer_run = sh4r.slice_cycle;
nkeynes@736
   308
            TMU_schedule_timer( 2 );
nkeynes@736
   309
        }
nkeynes@736
   310
        return;
nkeynes@23
   311
    }
nkeynes@23
   312
    MMIO_WRITE( TMU, reg, val );
nkeynes@23
   313
}
nkeynes@23
   314
nkeynes@619
   315
void TMU_count_all( uint32_t nanosecs )
nkeynes@23
   316
{
nkeynes@23
   317
    int tcr = MMIO_READ( TMU, TSTR );
nkeynes@23
   318
    if( tcr & 0x01 ) {
nkeynes@736
   319
        TMU_count( 0, nanosecs );
nkeynes@23
   320
    }
nkeynes@23
   321
    if( tcr & 0x02 ) {
nkeynes@736
   322
        TMU_count( 1, nanosecs );
nkeynes@23
   323
    }
nkeynes@23
   324
    if( tcr & 0x04 ) {
nkeynes@736
   325
        TMU_count( 2, nanosecs );
nkeynes@23
   326
    }
nkeynes@23
   327
}
nkeynes@53
   328
nkeynes@619
   329
void TMU_run_slice( uint32_t nanosecs )
nkeynes@619
   330
{
nkeynes@619
   331
    TMU_count_all( nanosecs );
nkeynes@619
   332
    TMU_timers[0].timer_run = 0;
nkeynes@619
   333
    TMU_timers[1].timer_run = 0;
nkeynes@619
   334
    TMU_timers[2].timer_run = 0;
nkeynes@619
   335
}
nkeynes@619
   336
nkeynes@53
   337
void TMU_update_clocks()
nkeynes@53
   338
{
nkeynes@115
   339
    TMU_set_timer_control( 0, MMIO_READ( TMU, TCR0 ) );
nkeynes@115
   340
    TMU_set_timer_control( 1, MMIO_READ( TMU, TCR1 ) );
nkeynes@115
   341
    TMU_set_timer_control( 2, MMIO_READ( TMU, TCR2 ) );
nkeynes@53
   342
}
nkeynes@53
   343
nkeynes@53
   344
void TMU_reset( )
nkeynes@53
   345
{
nkeynes@53
   346
    TMU_timers[0].timer_remainder = 0;
nkeynes@53
   347
    TMU_timers[0].timer_run = 0;
nkeynes@53
   348
    TMU_timers[1].timer_remainder = 0;
nkeynes@53
   349
    TMU_timers[1].timer_run = 0;
nkeynes@53
   350
    TMU_timers[2].timer_remainder = 0;
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   351
    TMU_timers[2].timer_run = 0;
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    TMU_update_clocks();
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   353
}
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   354
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void TMU_save_state( FILE *f ) {
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    fwrite( &TMU_timers, sizeof(TMU_timers), 1, f );
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   357
}
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   358
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   359
int TMU_load_state( FILE *f ) 
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   360
{
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   361
    fread( &TMU_timers, sizeof(TMU_timers), 1, f );
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    return 0;
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   363
}
.