nkeynes@23 | 1 | /**
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nkeynes@561 | 2 | * $Id$
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nkeynes@23 | 3 | *
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nkeynes@23 | 4 | * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
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nkeynes@23 | 5 | * keep things simple (they intertwine a bit).
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nkeynes@23 | 6 | *
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nkeynes@23 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@23 | 8 | *
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nkeynes@23 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@23 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@23 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@23 | 12 | * (at your option) any later version.
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nkeynes@23 | 13 | *
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nkeynes@23 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@23 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@23 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@23 | 17 | * GNU General Public License for more details.
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nkeynes@23 | 18 | */
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nkeynes@23 | 19 |
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nkeynes@619 | 20 | #include <assert.h>
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nkeynes@619 | 21 | #include "lxdream.h"
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nkeynes@23 | 22 | #include "mem.h"
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nkeynes@23 | 23 | #include "clock.h"
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nkeynes@619 | 24 | #include "eventq.h"
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nkeynes@619 | 25 | #include "sh4/sh4core.h"
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nkeynes@619 | 26 | #include "sh4/sh4mmio.h"
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nkeynes@619 | 27 | #include "sh4/intc.h"
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nkeynes@23 | 28 |
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nkeynes@23 | 29 | /********************************* CPG *************************************/
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nkeynes@859 | 30 | /* This is the base clock from which all other clocks are derived.
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nkeynes@859 | 31 | * Note: The real clock runs at 33Mhz, which is multiplied by the PLL to
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nkeynes@859 | 32 | * run the instruction clock at 200Mhz. For sake of simplicity/precision,
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nkeynes@859 | 33 | * we instead use 200Mhz as the base rate and divide everything down instead.
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nkeynes@859 | 34 | **/
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nkeynes@53 | 35 | uint32_t sh4_input_freq = SH4_BASE_RATE;
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nkeynes@53 | 36 |
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nkeynes@414 | 37 | uint32_t sh4_cpu_multiplier = 2000; /* = 0.5 * frequency */
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nkeynes@414 | 38 |
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nkeynes@53 | 39 | uint32_t sh4_cpu_freq = SH4_BASE_RATE;
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nkeynes@859 | 40 | uint32_t sh4_bus_freq = SH4_BASE_RATE / 2;
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nkeynes@859 | 41 | uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 4;
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nkeynes@53 | 42 |
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nkeynes@53 | 43 | uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
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nkeynes@859 | 44 | uint32_t sh4_bus_period = 2* 1000 / SH4_BASE_RATE;
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nkeynes@859 | 45 | uint32_t sh4_peripheral_period = 4 * 2000 / SH4_BASE_RATE;
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nkeynes@23 | 46 |
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nkeynes@929 | 47 | MMIO_REGION_READ_FN( CPG, reg )
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nkeynes@23 | 48 | {
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nkeynes@929 | 49 | return MMIO_READ( CPG, reg&0xFFF );
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nkeynes@23 | 50 | }
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nkeynes@23 | 51 |
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nkeynes@53 | 52 | /* CPU + bus dividers (note officially only the first 6 values are valid) */
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nkeynes@53 | 53 | int ifc_divider[8] = { 1, 2, 3, 4, 5, 8, 8, 8 };
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nkeynes@53 | 54 | /* Peripheral clock dividers (only first 5 are officially valid) */
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nkeynes@53 | 55 | int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
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nkeynes@53 | 56 |
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nkeynes@929 | 57 | MMIO_REGION_WRITE_FN( CPG, reg, val )
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nkeynes@23 | 58 | {
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nkeynes@53 | 59 | uint32_t div;
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nkeynes@859 | 60 | uint32_t primary_clock = sh4_input_freq;
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nkeynes@929 | 61 | reg &= 0xFFF;
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nkeynes@53 | 62 | switch( reg ) {
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nkeynes@53 | 63 | case FRQCR: /* Frequency control */
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nkeynes@859 | 64 | if( (val & FRQCR_PLL1EN) == 0 )
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nkeynes@859 | 65 | primary_clock /= 6;
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nkeynes@736 | 66 | div = ifc_divider[(val >> 6) & 0x07];
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nkeynes@859 | 67 | sh4_cpu_freq = primary_clock / div;
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nkeynes@736 | 68 | sh4_cpu_period = sh4_cpu_multiplier * div / sh4_input_freq;
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nkeynes@736 | 69 | div = ifc_divider[(val >> 3) & 0x07];
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nkeynes@859 | 70 | sh4_bus_freq = primary_clock / div;
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nkeynes@736 | 71 | sh4_bus_period = 1000 * div / sh4_input_freq;
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nkeynes@736 | 72 | div = pfc_divider[val & 0x07];
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nkeynes@859 | 73 | sh4_peripheral_freq = primary_clock / div;
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nkeynes@736 | 74 | sh4_peripheral_period = 1000 * div / sh4_input_freq;
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nkeynes@53 | 75 |
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nkeynes@736 | 76 | /* Update everything that depends on the peripheral frequency */
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nkeynes@736 | 77 | SCIF_update_line_speed();
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nkeynes@736 | 78 | break;
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nkeynes@53 | 79 | case WTCSR: /* Watchdog timer */
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nkeynes@736 | 80 | break;
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nkeynes@53 | 81 | }
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nkeynes@736 | 82 |
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nkeynes@23 | 83 | MMIO_WRITE( CPG, reg, val );
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nkeynes@23 | 84 | }
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nkeynes@23 | 85 |
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nkeynes@260 | 86 | /**
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nkeynes@260 | 87 | * We don't really know what the default reset value is as it's determined
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nkeynes@260 | 88 | * by the mode select pins. This is the standard value that the BIOS sets,
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nkeynes@260 | 89 | * however, so it works for now.
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nkeynes@260 | 90 | */
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nkeynes@260 | 91 | void CPG_reset( )
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nkeynes@260 | 92 | {
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nkeynes@260 | 93 | mmio_region_CPG_write( FRQCR, 0x0E0A );
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nkeynes@260 | 94 | }
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nkeynes@260 | 95 |
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nkeynes@260 | 96 |
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nkeynes@23 | 97 | /********************************** RTC *************************************/
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nkeynes@23 | 98 |
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nkeynes@53 | 99 | uint32_t rtc_output_period;
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nkeynes@53 | 100 |
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nkeynes@929 | 101 | MMIO_REGION_READ_FN( RTC, reg )
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nkeynes@23 | 102 | {
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nkeynes@929 | 103 | return MMIO_READ( RTC, reg &0xFFF );
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nkeynes@23 | 104 | }
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nkeynes@23 | 105 |
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nkeynes@929 | 106 | MMIO_REGION_WRITE_FN( RTC, reg, val )
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nkeynes@23 | 107 | {
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nkeynes@929 | 108 | MMIO_WRITE( RTC, reg &0xFFF, val );
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nkeynes@23 | 109 | }
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nkeynes@23 | 110 |
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nkeynes@23 | 111 | /********************************** TMU *************************************/
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nkeynes@23 | 112 |
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nkeynes@619 | 113 | #define TMU_IS_RUNNING(timer) (MMIO_READ(TMU,TSTR) & (1<<timer))
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nkeynes@619 | 114 |
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nkeynes@260 | 115 | uint32_t TMU_count( int timer, uint32_t nanosecs );
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nkeynes@260 | 116 |
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nkeynes@619 | 117 | void TMU_event_callback( int eventid )
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nkeynes@619 | 118 | {
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nkeynes@619 | 119 | TMU_count( eventid - EVENT_TMU0, sh4r.slice_cycle );
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nkeynes@619 | 120 | }
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nkeynes@619 | 121 |
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nkeynes@619 | 122 | void TMU_init(void)
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nkeynes@619 | 123 | {
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nkeynes@619 | 124 | register_event_callback( EVENT_TMU0, TMU_event_callback );
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nkeynes@619 | 125 | register_event_callback( EVENT_TMU1, TMU_event_callback );
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nkeynes@619 | 126 | register_event_callback( EVENT_TMU2, TMU_event_callback );
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nkeynes@619 | 127 | }
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nkeynes@260 | 128 |
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nkeynes@53 | 129 | #define TCR_ICPF 0x0200
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nkeynes@53 | 130 | #define TCR_UNF 0x0100
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nkeynes@53 | 131 | #define TCR_UNIE 0x0020
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nkeynes@53 | 132 |
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nkeynes@115 | 133 | #define TCR_IRQ_ACTIVE (TCR_UNF|TCR_UNIE)
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nkeynes@115 | 134 |
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nkeynes@53 | 135 | struct TMU_timer {
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nkeynes@53 | 136 | uint32_t timer_period;
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nkeynes@53 | 137 | uint32_t timer_remainder; /* left-over cycles from last count */
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nkeynes@53 | 138 | uint32_t timer_run; /* cycles already run from this slice */
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nkeynes@53 | 139 | };
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nkeynes@53 | 140 |
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nkeynes@619 | 141 | static struct TMU_timer TMU_timers[3];
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nkeynes@23 | 142 |
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nkeynes@115 | 143 | void TMU_set_timer_control( int timer, int tcr )
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nkeynes@53 | 144 | {
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nkeynes@53 | 145 | uint32_t period = 1;
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nkeynes@115 | 146 | uint32_t oldtcr = MMIO_READ( TMU, TCR0 + (12*timer) );
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nkeynes@115 | 147 |
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nkeynes@115 | 148 | if( (oldtcr & TCR_UNF) == 0 ) {
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nkeynes@736 | 149 | tcr = tcr & (~TCR_UNF);
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nkeynes@115 | 150 | } else {
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nkeynes@736 | 151 | if( ((oldtcr & TCR_UNIE) == 0) &&
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nkeynes@736 | 152 | (tcr & TCR_IRQ_ACTIVE) == TCR_IRQ_ACTIVE ) {
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nkeynes@736 | 153 | intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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nkeynes@736 | 154 | } else if( (oldtcr & TCR_UNIE) != 0 &&
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nkeynes@736 | 155 | (tcr & TCR_IRQ_ACTIVE) != TCR_IRQ_ACTIVE ) {
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nkeynes@736 | 156 | intc_clear_interrupt( INT_TMU_TUNI0 + timer );
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nkeynes@736 | 157 | }
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nkeynes@115 | 158 | }
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nkeynes@115 | 159 |
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nkeynes@53 | 160 | switch( tcr & 0x07 ) {
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nkeynes@53 | 161 | case 0:
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nkeynes@736 | 162 | period = sh4_peripheral_period << 2 ;
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nkeynes@736 | 163 | break;
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nkeynes@53 | 164 | case 1:
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nkeynes@736 | 165 | period = sh4_peripheral_period << 4;
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nkeynes@736 | 166 | break;
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nkeynes@53 | 167 | case 2:
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nkeynes@736 | 168 | period = sh4_peripheral_period << 6;
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nkeynes@736 | 169 | break;
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nkeynes@53 | 170 | case 3:
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nkeynes@736 | 171 | period = sh4_peripheral_period << 8;
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nkeynes@736 | 172 | break;
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nkeynes@53 | 173 | case 4:
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nkeynes@736 | 174 | period = sh4_peripheral_period << 10;
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nkeynes@736 | 175 | break;
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nkeynes@53 | 176 | case 5:
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nkeynes@736 | 177 | /* Illegal value. */
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nkeynes@736 | 178 | ERROR( "TMU %d period set to illegal value (5)", timer );
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nkeynes@736 | 179 | period = sh4_peripheral_period << 12; /* for something to do */
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nkeynes@736 | 180 | break;
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nkeynes@53 | 181 | case 6:
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nkeynes@736 | 182 | period = rtc_output_period;
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nkeynes@736 | 183 | break;
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nkeynes@53 | 184 | case 7:
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nkeynes@736 | 185 | /* External clock... Hrm? */
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nkeynes@736 | 186 | period = sh4_peripheral_period; /* I dunno... */
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nkeynes@736 | 187 | break;
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nkeynes@53 | 188 | }
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nkeynes@53 | 189 | TMU_timers[timer].timer_period = period;
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nkeynes@115 | 190 |
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nkeynes@115 | 191 | MMIO_WRITE( TMU, TCR0 + (12*timer), tcr );
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nkeynes@53 | 192 | }
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nkeynes@23 | 193 |
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nkeynes@619 | 194 | void TMU_schedule_timer( int timer )
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nkeynes@619 | 195 | {
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nkeynes@619 | 196 | uint64_t duration = (uint64_t)((uint32_t)(MMIO_READ( TMU, TCNT0 + 12*timer )+1)) *
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nkeynes@736 | 197 | (uint64_t)TMU_timers[timer].timer_period - TMU_timers[timer].timer_remainder;
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nkeynes@619 | 198 | event_schedule_long( EVENT_TMU0+timer, (uint32_t)(duration / 1000000000),
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nkeynes@736 | 199 | (uint32_t)(duration % 1000000000) );
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nkeynes@619 | 200 | }
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nkeynes@619 | 201 |
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nkeynes@53 | 202 | void TMU_start( int timer )
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nkeynes@23 | 203 | {
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nkeynes@260 | 204 | TMU_timers[timer].timer_run = sh4r.slice_cycle;
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nkeynes@53 | 205 | TMU_timers[timer].timer_remainder = 0;
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nkeynes@619 | 206 | TMU_schedule_timer( timer );
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nkeynes@53 | 207 | }
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nkeynes@53 | 208 |
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nkeynes@264 | 209 | /**
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nkeynes@264 | 210 | * Stop the given timer. Run it up to the current time and leave it there.
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nkeynes@264 | 211 | */
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nkeynes@53 | 212 | void TMU_stop( int timer )
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nkeynes@53 | 213 | {
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nkeynes@264 | 214 | TMU_count( timer, sh4r.slice_cycle );
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nkeynes@619 | 215 | event_cancel( EVENT_TMU0+timer );
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nkeynes@53 | 216 | }
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nkeynes@53 | 217 |
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nkeynes@53 | 218 | /**
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nkeynes@53 | 219 | * Count the specified timer for a given number of nanoseconds.
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nkeynes@53 | 220 | */
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nkeynes@53 | 221 | uint32_t TMU_count( int timer, uint32_t nanosecs )
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nkeynes@53 | 222 | {
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nkeynes@619 | 223 | uint32_t run_ns = nanosecs + TMU_timers[timer].timer_remainder -
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nkeynes@736 | 224 | TMU_timers[timer].timer_run;
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nkeynes@53 | 225 | TMU_timers[timer].timer_remainder =
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nkeynes@736 | 226 | run_ns % TMU_timers[timer].timer_period;
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nkeynes@619 | 227 | TMU_timers[timer].timer_run = nanosecs;
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nkeynes@619 | 228 | uint32_t count = run_ns / TMU_timers[timer].timer_period;
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nkeynes@53 | 229 | uint32_t value = MMIO_READ( TMU, TCNT0 + 12*timer );
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nkeynes@53 | 230 | uint32_t reset = MMIO_READ( TMU, TCOR0 + 12*timer );
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nkeynes@53 | 231 | if( count > value ) {
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nkeynes@736 | 232 | uint32_t tcr = MMIO_READ( TMU, TCR0 + 12*timer );
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nkeynes@736 | 233 | tcr |= TCR_UNF;
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nkeynes@736 | 234 | count -= value;
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nkeynes@619 | 235 | value = reset - (count % reset) + 1;
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nkeynes@736 | 236 | MMIO_WRITE( TMU, TCR0 + 12*timer, tcr );
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nkeynes@736 | 237 | if( tcr & TCR_UNIE )
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nkeynes@736 | 238 | intc_raise_interrupt( INT_TMU_TUNI0 + timer );
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nkeynes@736 | 239 | MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
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nkeynes@736 | 240 | TMU_schedule_timer(timer);
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nkeynes@53 | 241 | } else {
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nkeynes@736 | 242 | value -= count;
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nkeynes@736 | 243 | MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
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nkeynes@23 | 244 | }
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nkeynes@53 | 245 | return value;
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nkeynes@23 | 246 | }
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nkeynes@23 | 247 |
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nkeynes@929 | 248 | MMIO_REGION_READ_FN( TMU, reg )
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nkeynes@929 | 249 | {
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nkeynes@929 | 250 | reg &= 0xFFF;
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nkeynes@929 | 251 | switch( reg ) {
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nkeynes@929 | 252 | case TCNT0:
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nkeynes@929 | 253 | TMU_count( 0, sh4r.slice_cycle );
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nkeynes@929 | 254 | break;
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nkeynes@929 | 255 | case TCNT1:
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nkeynes@929 | 256 | TMU_count( 1, sh4r.slice_cycle );
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nkeynes@929 | 257 | break;
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nkeynes@929 | 258 | case TCNT2:
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nkeynes@929 | 259 | TMU_count( 2, sh4r.slice_cycle );
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nkeynes@929 | 260 | break;
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nkeynes@929 | 261 | }
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nkeynes@929 | 262 | return MMIO_READ( TMU, reg );
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nkeynes@929 | 263 | }
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nkeynes@929 | 264 |
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nkeynes@929 | 265 | MMIO_REGION_WRITE_FN( TMU, reg, val )
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nkeynes@23 | 266 | {
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nkeynes@53 | 267 | uint32_t oldval;
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nkeynes@53 | 268 | int i;
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nkeynes@929 | 269 | reg &= 0xFFF;
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nkeynes@23 | 270 | switch( reg ) {
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nkeynes@53 | 271 | case TSTR:
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nkeynes@736 | 272 | oldval = MMIO_READ( TMU, TSTR );
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nkeynes@736 | 273 | for( i=0; i<3; i++ ) {
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nkeynes@736 | 274 | uint32_t tmp = 1<<i;
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nkeynes@736 | 275 | if( (oldval & tmp) != 0 && (val&tmp) == 0 )
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nkeynes@736 | 276 | TMU_stop(i);
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nkeynes@736 | 277 | else if( (oldval&tmp) == 0 && (val&tmp) != 0 )
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nkeynes@736 | 278 | TMU_start(i);
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nkeynes@736 | 279 | }
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nkeynes@736 | 280 | break;
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nkeynes@53 | 281 | case TCR0:
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nkeynes@736 | 282 | TMU_set_timer_control( 0, val );
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nkeynes@736 | 283 | return;
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nkeynes@53 | 284 | case TCR1:
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nkeynes@736 | 285 | TMU_set_timer_control( 1, val );
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nkeynes@736 | 286 | return;
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nkeynes@53 | 287 | case TCR2:
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nkeynes@736 | 288 | TMU_set_timer_control( 2, val );
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nkeynes@736 | 289 | return;
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nkeynes@619 | 290 | case TCNT0:
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nkeynes@736 | 291 | MMIO_WRITE( TMU, reg, val );
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nkeynes@736 | 292 | if( TMU_IS_RUNNING(0) ) { // reschedule
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nkeynes@736 | 293 | TMU_timers[0].timer_run = sh4r.slice_cycle;
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nkeynes@736 | 294 | TMU_schedule_timer( 0 );
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nkeynes@736 | 295 | }
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nkeynes@736 | 296 | return;
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nkeynes@619 | 297 | case TCNT1:
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nkeynes@736 | 298 | MMIO_WRITE( TMU, reg, val );
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nkeynes@736 | 299 | if( TMU_IS_RUNNING(1) ) { // reschedule
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nkeynes@736 | 300 | TMU_timers[1].timer_run = sh4r.slice_cycle;
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nkeynes@736 | 301 | TMU_schedule_timer( 1 );
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nkeynes@736 | 302 | }
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nkeynes@736 | 303 | return;
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nkeynes@619 | 304 | case TCNT2:
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nkeynes@736 | 305 | MMIO_WRITE( TMU, reg, val );
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nkeynes@736 | 306 | if( TMU_IS_RUNNING(2) ) { // reschedule
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nkeynes@736 | 307 | TMU_timers[2].timer_run = sh4r.slice_cycle;
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nkeynes@736 | 308 | TMU_schedule_timer( 2 );
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nkeynes@736 | 309 | }
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nkeynes@736 | 310 | return;
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nkeynes@23 | 311 | }
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nkeynes@23 | 312 | MMIO_WRITE( TMU, reg, val );
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nkeynes@23 | 313 | }
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nkeynes@23 | 314 |
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nkeynes@619 | 315 | void TMU_count_all( uint32_t nanosecs )
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nkeynes@23 | 316 | {
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nkeynes@23 | 317 | int tcr = MMIO_READ( TMU, TSTR );
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nkeynes@23 | 318 | if( tcr & 0x01 ) {
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nkeynes@736 | 319 | TMU_count( 0, nanosecs );
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nkeynes@23 | 320 | }
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nkeynes@23 | 321 | if( tcr & 0x02 ) {
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nkeynes@736 | 322 | TMU_count( 1, nanosecs );
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nkeynes@23 | 323 | }
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nkeynes@23 | 324 | if( tcr & 0x04 ) {
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nkeynes@736 | 325 | TMU_count( 2, nanosecs );
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nkeynes@23 | 326 | }
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nkeynes@23 | 327 | }
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nkeynes@53 | 328 |
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nkeynes@619 | 329 | void TMU_run_slice( uint32_t nanosecs )
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nkeynes@619 | 330 | {
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nkeynes@619 | 331 | TMU_count_all( nanosecs );
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nkeynes@619 | 332 | TMU_timers[0].timer_run = 0;
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nkeynes@619 | 333 | TMU_timers[1].timer_run = 0;
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nkeynes@619 | 334 | TMU_timers[2].timer_run = 0;
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nkeynes@619 | 335 | }
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nkeynes@619 | 336 |
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nkeynes@53 | 337 | void TMU_update_clocks()
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nkeynes@53 | 338 | {
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nkeynes@115 | 339 | TMU_set_timer_control( 0, MMIO_READ( TMU, TCR0 ) );
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nkeynes@115 | 340 | TMU_set_timer_control( 1, MMIO_READ( TMU, TCR1 ) );
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nkeynes@115 | 341 | TMU_set_timer_control( 2, MMIO_READ( TMU, TCR2 ) );
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nkeynes@53 | 342 | }
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nkeynes@53 | 343 |
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nkeynes@53 | 344 | void TMU_reset( )
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nkeynes@53 | 345 | {
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nkeynes@53 | 346 | TMU_timers[0].timer_remainder = 0;
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nkeynes@53 | 347 | TMU_timers[0].timer_run = 0;
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nkeynes@53 | 348 | TMU_timers[1].timer_remainder = 0;
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nkeynes@53 | 349 | TMU_timers[1].timer_run = 0;
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nkeynes@53 | 350 | TMU_timers[2].timer_remainder = 0;
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nkeynes@53 | 351 | TMU_timers[2].timer_run = 0;
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nkeynes@53 | 352 | TMU_update_clocks();
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nkeynes@53 | 353 | }
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nkeynes@53 | 354 |
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nkeynes@53 | 355 | void TMU_save_state( FILE *f ) {
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nkeynes@53 | 356 | fwrite( &TMU_timers, sizeof(TMU_timers), 1, f );
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nkeynes@53 | 357 | }
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nkeynes@53 | 358 |
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nkeynes@53 | 359 | int TMU_load_state( FILE *f )
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nkeynes@53 | 360 | {
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nkeynes@53 | 361 | fread( &TMU_timers, sizeof(TMU_timers), 1, f );
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nkeynes@53 | 362 | return 0;
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nkeynes@53 | 363 | }
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