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lxdream.org :: lxdream/src/sh4/sh4.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 559:06714bc64271
prev526:ba3da45b5754
next561:533f6b478071
author nkeynes
date Tue Jan 01 04:58:57 2008 +0000 (12 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Commit first pass at full TLB support - still needs a lot more work
file annotate diff log raw
1.1 --- a/src/sh4/sh4.c Sat Nov 17 06:04:19 2007 +0000
1.2 +++ b/src/sh4/sh4.c Tue Jan 01 04:58:57 2008 +0000
1.3 @@ -30,10 +30,6 @@
1.4 #include "clock.h"
1.5 #include "syscall.h"
1.6
1.7 -#define EXV_EXCEPTION 0x100 /* General exception vector */
1.8 -#define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
1.9 -#define EXV_INTERRUPT 0x600 /* External interrupt vector */
1.10 -
1.11 void sh4_init( void );
1.12 void sh4_xlat_init( void );
1.13 void sh4_reset( void );
1.14 @@ -254,6 +250,21 @@
1.15 RAISE( code, EXV_EXCEPTION );
1.16 }
1.17
1.18 +/**
1.19 + * Raise a CPU reset exception with the specified exception code.
1.20 + */
1.21 +gboolean sh4_raise_reset( int code )
1.22 +{
1.23 + // FIXME: reset modules as per "manual reset"
1.24 + sh4_reset();
1.25 + MMIO_WRITE(MMU,EXPEVT,code);
1.26 + sh4r.vbr = 0;
1.27 + sh4r.pc = 0xA0000000;
1.28 + sh4r.new_pc = sh4r.pc + 2;
1.29 + sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
1.30 + &(~SR_FD) );
1.31 +}
1.32 +
1.33 gboolean sh4_raise_trap( int trap )
1.34 {
1.35 MMIO_WRITE( MMU, TRA, trap<<2 );
.