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lxdream.org :: lxdream/src/sh4/sh4x86.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 930:07e5b11419db
prev929:fd8cb0c82f5f
next936:f394309c399a
author nkeynes
date Mon Dec 22 09:51:11 2008 +0000 (11 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Remove pointer cache and add full address-space map. Much better
file annotate diff log raw
1.1 --- a/src/sh4/sh4x86.in Sat Dec 20 03:01:40 2008 +0000
1.2 +++ b/src/sh4/sh4x86.in Mon Dec 22 09:51:11 2008 +0000
1.3 @@ -20,7 +20,6 @@
1.4
1.5 #include <assert.h>
1.6 #include <math.h>
1.7 -#include <stddef.h>
1.8
1.9 #ifndef NDEBUG
1.10 #define DEBUG_JUMPS 1
1.11 @@ -289,13 +288,14 @@
1.12 JNE_exc(EXC_DATA_ADDR_WRITE);
1.13
1.14 #define UNDEF(ir)
1.15 +#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
1.16 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
1.17 -#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
1.18 -#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
1.19 -#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
1.20 -#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
1.21 -#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
1.22 -#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
1.23 +#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); call_func1_r32disp8(R_ECX, MEM_REGION_PTR(read_byte), addr_reg ); MEM_RESULT(value_reg)
1.24 +#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); call_func1_r32disp8(R_ECX, MEM_REGION_PTR(read_word), addr_reg ); MEM_RESULT(value_reg)
1.25 +#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); call_func1_r32disp8(R_ECX, MEM_REGION_PTR(read_long), addr_reg ); MEM_RESULT(value_reg)
1.26 +#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); call_func2_r32disp8(R_ECX, MEM_REGION_PTR(write_byte), addr_reg, value_reg)
1.27 +#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); call_func2_r32disp8(R_ECX, MEM_REGION_PTR(write_word), addr_reg, value_reg)
1.28 +#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); call_func2_r32disp8(R_ECX, MEM_REGION_PTR(write_long), addr_reg, value_reg)
1.29
1.30 #ifdef HAVE_FRAME_ADDRESS
1.31 /**
1.32 @@ -323,111 +323,6 @@
1.33 #include "sh4/ia32abi.h"
1.34 #endif
1.35
1.36 -#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
1.37 -
1.38 -/**
1.39 - * Given an address in addr_reg and a cache entry, test if the cache is valid
1.40 - * and decode otherwise.
1.41 - * At conclusion of this:
1.42 - * R_EBX will contain the address
1.43 - * R_ECX will contain the memory region vtable
1.44 - * R_EAX, R_EDX (and any other volatiles) are clobbered
1.45 - */
1.46 -static inline void MEM_DECODE_ADDRESS( int addr_reg, int rm )
1.47 -{
1.48 - MOV_r32_r32( addr_reg, R_EBX );
1.49 - AND_sh4r_r32( REG_OFFSET(pointer_cache[rm].page_mask), addr_reg );
1.50 - CMP_sh4r_r32( REG_OFFSET(pointer_cache[rm].page_vma), addr_reg );
1.51 - EXPJE_rel8(uptodate);
1.52 - store_spreg( addr_reg, REG_OFFSET(pointer_cache[rm].page_vma) );
1.53 - call_func1( sh7750_decode_address, addr_reg );
1.54 - store_spreg( R_EAX, REG_OFFSET(pointer_cache[rm].page_fn) );
1.55 - JMP_TARGET(uptodate);
1.56 - load_spreg( R_ECX, REG_OFFSET(pointer_cache[rm].page_fn) );
1.57 -}
1.58 -
1.59 -static inline void MEM_READ_LONG_CACHED( int addr_reg, int value_reg, int rm )
1.60 -{
1.61 - MEM_DECODE_ADDRESS( addr_reg, rm );
1.62 - call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
1.63 - MEM_RESULT(value_reg);
1.64 -}
1.65 -
1.66 -static inline void MEM_READ_WORD_CACHED( int addr_reg, int value_reg, int rm )
1.67 -{
1.68 - MEM_DECODE_ADDRESS( addr_reg, rm );
1.69 - call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_word), R_EBX );
1.70 - MEM_RESULT(value_reg);
1.71 -}
1.72 -
1.73 -static inline void MEM_READ_BYTE_CACHED( int addr_reg, int value_reg, int rm )
1.74 -{
1.75 - MEM_DECODE_ADDRESS( addr_reg, rm );
1.76 - call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_byte), R_EBX );
1.77 - MEM_RESULT(value_reg);
1.78 -}
1.79 -
1.80 -static inline void MEM_WRITE_LONG_CACHED_SP( int addr_reg, int ebpdisp, int rn )
1.81 -{
1.82 - MEM_DECODE_ADDRESS( addr_reg, rn );
1.83 - MOV_sh4r_r32( ebpdisp, R_EDX );
1.84 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.85 -}
1.86 -
1.87 -#define MEM_WRITE_LONG_CACHED( addr_reg, value_rm, rn ) MEM_WRITE_LONG_CACHED_SP( addr_reg, REG_OFFSET(r[value_rm]), rn )
1.88 -
1.89 -static inline void MEM_WRITE_WORD_CACHED( int addr_reg, int value_rm, int rn )
1.90 -{
1.91 - MEM_DECODE_ADDRESS( addr_reg, rn );
1.92 - MOVZX_sh4r16_r32( REG_OFFSET(r[value_rm]), R_EDX );
1.93 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_word), R_EBX, R_EDX );
1.94 -}
1.95 -
1.96 -static inline void MEM_WRITE_BYTE_CACHED( int addr_reg, int value_rm, int rn )
1.97 -{
1.98 - MEM_DECODE_ADDRESS( addr_reg, rn );
1.99 - MOVZX_sh4r8_r32( REG_OFFSET(r[value_rm]), R_EDX );
1.100 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_byte), R_EBX, R_EDX );
1.101 -}
1.102 -
1.103 -static inline void MEM_WRITE_BYTE_UNCHECKED( int addr_reg, int value_reg, int rn )
1.104 -{
1.105 - load_spreg( R_ECX, REG_OFFSET(pointer_cache[rn].page_fn) );
1.106 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_byte), addr_reg, R_EDX );
1.107 -}
1.108 -
1.109 -static inline void MEM_WRITE_FLOAT_CACHED( int addr_reg, int value_frm, int rn )
1.110 -{
1.111 - MEM_DECODE_ADDRESS( addr_reg, rn );
1.112 - load_fr( R_EDX, value_frm );
1.113 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.114 -}
1.115 -
1.116 -static inline void MEM_READ_DOUBLE_CACHED( int addr_reg, int value_reg1, int value_reg2, int rm )
1.117 -{
1.118 - MEM_DECODE_ADDRESS( addr_reg, rm );
1.119 - call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
1.120 - MOV_r32_esp8( R_EAX, 0 );
1.121 - load_spreg( R_ECX, REG_OFFSET(pointer_cache[rm].page_fn) );
1.122 - LEA_r32disp8_r32( R_EBX, 4, R_EBX );
1.123 - call_func1_r32ind( R_ECX, MEM_REGION_PTR(read_long), R_EBX );
1.124 - MEM_RESULT(value_reg2);
1.125 - MOV_esp8_r32( 0, value_reg1 );
1.126 -}
1.127 -
1.128 -static inline void MEM_WRITE_DOUBLE_CACHED( int addr_reg, int value_frm, int rn )
1.129 -{
1.130 - MEM_DECODE_ADDRESS( addr_reg, rn );
1.131 - load_dr0( R_EDX, value_frm );
1.132 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.133 - LEA_r32disp8_r32( R_EBX, 4, R_EBX );
1.134 - load_spreg( R_ECX, REG_OFFSET(pointer_cache[rn].page_fn) );
1.135 - load_dr1( R_EDX, value_frm );
1.136 - call_func2_r32ind( R_ECX, MEM_REGION_PTR(write_long), R_EBX, R_EDX );
1.137 -}
1.138 -
1.139 -
1.140 -
1.141 void sh4_translate_begin_block( sh4addr_t pc )
1.142 {
1.143 enter_block();
1.144 @@ -577,9 +472,11 @@
1.145 load_spreg( R_ECX, R_GBR );
1.146 ADD_r32_r32( R_ECX, R_EAX );
1.147 MMU_TRANSLATE_WRITE( R_EAX );
1.148 - MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
1.149 + MOV_r32_esp8(R_EAX, 0);
1.150 + MEM_READ_BYTE( R_EAX, R_EDX );
1.151 + MOV_esp8_r32(0, R_EAX);
1.152 AND_imm32_r32(imm, R_EDX );
1.153 - MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.154 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.155 sh4_x86.tstate = TSTATE_NONE;
1.156 :}
1.157 CMP/EQ Rm, Rn {:
1.158 @@ -783,10 +680,10 @@
1.159 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.160 }
1.161 MEM_READ_LONG( R_EAX, R_EAX );
1.162 - MOV_r32_r32( R_EAX, R_EBX );
1.163 + MOV_r32_esp8( R_EAX, 4 );
1.164 MOV_esp8_r32( 0, R_EAX );
1.165 MEM_READ_LONG( R_EAX, R_EAX );
1.166 - MOV_r32_r32( R_EBX, R_ECX );
1.167 + MOV_esp8_r32( 4, R_ECX );
1.168
1.169 IMUL_r32( R_ECX );
1.170 ADD_r32_sh4r( R_EAX, R_MACL );
1.171 @@ -824,10 +721,10 @@
1.172 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
1.173 }
1.174 MEM_READ_WORD( R_EAX, R_EAX );
1.175 - MOV_r32_r32( R_EAX, R_EBX );
1.176 + MOV_r32_esp8( R_EAX, 4 );
1.177 MOV_esp8_r32( 0, R_EAX );
1.178 MEM_READ_WORD( R_EAX, R_EAX );
1.179 - MOV_r32_r32( R_EBX, R_ECX );
1.180 + MOV_esp8_r32( 4, R_ECX );
1.181
1.182 IMUL_r32( R_ECX );
1.183 load_spreg( R_ECX, R_S );
1.184 @@ -930,9 +827,11 @@
1.185 load_spreg( R_ECX, R_GBR );
1.186 ADD_r32_r32( R_ECX, R_EAX );
1.187 MMU_TRANSLATE_WRITE( R_EAX );
1.188 - MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
1.189 + MOV_r32_esp8( R_EAX, 0 );
1.190 + MEM_READ_BYTE( R_EAX, R_EDX );
1.191 + MOV_esp8_r32( 0, R_EAX );
1.192 OR_imm32_r32(imm, R_EDX );
1.193 - MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.194 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.195 sh4_x86.tstate = TSTATE_NONE;
1.196 :}
1.197 ROTCL Rn {:
1.198 @@ -1147,11 +1046,13 @@
1.199 COUNT_INST(I_TASB);
1.200 load_reg( R_EAX, Rn );
1.201 MMU_TRANSLATE_WRITE( R_EAX );
1.202 - MEM_READ_BYTE_CACHED( R_EAX, R_EDX, 16 );
1.203 + MOV_r32_esp8( R_EAX, 0 );
1.204 + MEM_READ_BYTE( R_EAX, R_EDX );
1.205 TEST_r8_r8( R_DL, R_DL );
1.206 SETE_t();
1.207 OR_imm8_r8( 0x80, R_DL );
1.208 - MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.209 + MOV_esp8_r32( 0, R_EAX );
1.210 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.211 sh4_x86.tstate = TSTATE_NONE;
1.212 :}
1.213 TST Rm, Rn {:
1.214 @@ -1175,7 +1076,7 @@
1.215 load_reg( R_ECX, R_GBR);
1.216 ADD_r32_r32( R_ECX, R_EAX );
1.217 MMU_TRANSLATE_READ( R_EAX );
1.218 - MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 16 );
1.219 + MEM_READ_BYTE( R_EAX, R_EAX );
1.220 TEST_imm8_r8( imm, R_AL );
1.221 SETE_t();
1.222 sh4_x86.tstate = TSTATE_E;
1.223 @@ -1201,9 +1102,11 @@
1.224 load_spreg( R_ECX, R_GBR );
1.225 ADD_r32_r32( R_ECX, R_EAX );
1.226 MMU_TRANSLATE_WRITE( R_EAX );
1.227 - MEM_READ_BYTE_CACHED(R_EAX, R_EDX, 16);
1.228 + MOV_r32_esp8( R_EAX, 0 );
1.229 + MEM_READ_BYTE(R_EAX, R_EDX);
1.230 + MOV_esp8_r32( 0, R_EAX );
1.231 XOR_imm32_r32( imm, R_EDX );
1.232 - MEM_WRITE_BYTE_UNCHECKED( R_EBX, R_EDX, 16 );
1.233 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.234 sh4_x86.tstate = TSTATE_NONE;
1.235 :}
1.236 XTRCT Rm, Rn {:
1.237 @@ -1232,7 +1135,8 @@
1.238 COUNT_INST(I_MOVB);
1.239 load_reg( R_EAX, Rn );
1.240 MMU_TRANSLATE_WRITE( R_EAX );
1.241 - MEM_WRITE_BYTE_CACHED( R_EAX, Rm, Rn );
1.242 + load_reg( R_EDX, Rm );
1.243 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.244 sh4_x86.tstate = TSTATE_NONE;
1.245 :}
1.246 MOV.B Rm, @-Rn {:
1.247 @@ -1240,8 +1144,9 @@
1.248 load_reg( R_EAX, Rn );
1.249 ADD_imm8s_r32( -1, R_EAX );
1.250 MMU_TRANSLATE_WRITE( R_EAX );
1.251 + load_reg( R_EDX, Rm );
1.252 ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
1.253 - MEM_WRITE_BYTE_CACHED( R_EAX, Rm, Rn );
1.254 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.255 sh4_x86.tstate = TSTATE_NONE;
1.256 :}
1.257 MOV.B Rm, @(R0, Rn) {:
1.258 @@ -1250,7 +1155,8 @@
1.259 load_reg( R_ECX, Rn );
1.260 ADD_r32_r32( R_ECX, R_EAX );
1.261 MMU_TRANSLATE_WRITE( R_EAX );
1.262 - MEM_WRITE_BYTE_CACHED( R_EAX, Rm, 0 );
1.263 + load_reg( R_EDX, Rm );
1.264 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.265 sh4_x86.tstate = TSTATE_NONE;
1.266 :}
1.267 MOV.B R0, @(disp, GBR) {:
1.268 @@ -1258,7 +1164,8 @@
1.269 load_spreg( R_EAX, R_GBR );
1.270 ADD_imm32_r32( disp, R_EAX );
1.271 MMU_TRANSLATE_WRITE( R_EAX );
1.272 - MEM_WRITE_BYTE_CACHED( R_EAX, 0, 16 );
1.273 + load_reg( R_EDX, 0 );
1.274 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.275 sh4_x86.tstate = TSTATE_NONE;
1.276 :}
1.277 MOV.B R0, @(disp, Rn) {:
1.278 @@ -1266,14 +1173,15 @@
1.279 load_reg( R_EAX, Rn );
1.280 ADD_imm32_r32( disp, R_EAX );
1.281 MMU_TRANSLATE_WRITE( R_EAX );
1.282 - MEM_WRITE_BYTE_CACHED( R_EAX, 0, Rn );
1.283 + load_reg( R_EDX, 0 );
1.284 + MEM_WRITE_BYTE( R_EAX, R_EDX );
1.285 sh4_x86.tstate = TSTATE_NONE;
1.286 :}
1.287 MOV.B @Rm, Rn {:
1.288 COUNT_INST(I_MOVB);
1.289 load_reg( R_EAX, Rm );
1.290 MMU_TRANSLATE_READ( R_EAX );
1.291 - MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
1.292 + MEM_READ_BYTE( R_EAX, R_EAX );
1.293 store_reg( R_EAX, Rn );
1.294 sh4_x86.tstate = TSTATE_NONE;
1.295 :}
1.296 @@ -1282,7 +1190,7 @@
1.297 load_reg( R_EAX, Rm );
1.298 MMU_TRANSLATE_READ( R_EAX );
1.299 ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
1.300 - MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
1.301 + MEM_READ_BYTE( R_EAX, R_EAX );
1.302 store_reg( R_EAX, Rn );
1.303 sh4_x86.tstate = TSTATE_NONE;
1.304 :}
1.305 @@ -1292,7 +1200,7 @@
1.306 load_reg( R_ECX, Rm );
1.307 ADD_r32_r32( R_ECX, R_EAX );
1.308 MMU_TRANSLATE_READ( R_EAX )
1.309 - MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 0 );
1.310 + MEM_READ_BYTE( R_EAX, R_EAX );
1.311 store_reg( R_EAX, Rn );
1.312 sh4_x86.tstate = TSTATE_NONE;
1.313 :}
1.314 @@ -1301,7 +1209,7 @@
1.315 load_spreg( R_EAX, R_GBR );
1.316 ADD_imm32_r32( disp, R_EAX );
1.317 MMU_TRANSLATE_READ( R_EAX );
1.318 - MEM_READ_BYTE_CACHED( R_EAX, R_EAX, 16 );
1.319 + MEM_READ_BYTE( R_EAX, R_EAX );
1.320 store_reg( R_EAX, 0 );
1.321 sh4_x86.tstate = TSTATE_NONE;
1.322 :}
1.323 @@ -1310,7 +1218,7 @@
1.324 load_reg( R_EAX, Rm );
1.325 ADD_imm32_r32( disp, R_EAX );
1.326 MMU_TRANSLATE_READ( R_EAX );
1.327 - MEM_READ_BYTE_CACHED( R_EAX, R_EAX, Rm );
1.328 + MEM_READ_BYTE( R_EAX, R_EAX );
1.329 store_reg( R_EAX, 0 );
1.330 sh4_x86.tstate = TSTATE_NONE;
1.331 :}
1.332 @@ -1318,8 +1226,19 @@
1.333 COUNT_INST(I_MOVL);
1.334 load_reg( R_EAX, Rn );
1.335 check_walign32(R_EAX);
1.336 + MOV_r32_r32( R_EAX, R_ECX );
1.337 + AND_imm32_r32( 0xFC000000, R_ECX );
1.338 + CMP_imm32_r32( 0xE0000000, R_ECX );
1.339 + JNE_rel8( notsq );
1.340 + AND_imm8s_r32( 0x3C, R_EAX );
1.341 + load_reg( R_EDX, Rm );
1.342 + MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
1.343 + JMP_rel8(end);
1.344 + JMP_TARGET(notsq);
1.345 MMU_TRANSLATE_WRITE( R_EAX );
1.346 - MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
1.347 + load_reg( R_EDX, Rm );
1.348 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.349 + JMP_TARGET(end);
1.350 sh4_x86.tstate = TSTATE_NONE;
1.351 :}
1.352 MOV.L Rm, @-Rn {:
1.353 @@ -1328,8 +1247,9 @@
1.354 ADD_imm8s_r32( -4, R_EAX );
1.355 check_walign32( R_EAX );
1.356 MMU_TRANSLATE_WRITE( R_EAX );
1.357 + load_reg( R_EDX, Rm );
1.358 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.359 - MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
1.360 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.361 sh4_x86.tstate = TSTATE_NONE;
1.362 :}
1.363 MOV.L Rm, @(R0, Rn) {:
1.364 @@ -1339,7 +1259,8 @@
1.365 ADD_r32_r32( R_ECX, R_EAX );
1.366 check_walign32( R_EAX );
1.367 MMU_TRANSLATE_WRITE( R_EAX );
1.368 - MEM_WRITE_LONG_CACHED( R_EAX, Rm, 0 );
1.369 + load_reg( R_EDX, Rm );
1.370 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.371 sh4_x86.tstate = TSTATE_NONE;
1.372 :}
1.373 MOV.L R0, @(disp, GBR) {:
1.374 @@ -1348,7 +1269,8 @@
1.375 ADD_imm32_r32( disp, R_EAX );
1.376 check_walign32( R_EAX );
1.377 MMU_TRANSLATE_WRITE( R_EAX );
1.378 - MEM_WRITE_LONG_CACHED( R_EAX, 0, 16 );
1.379 + load_reg( R_EDX, 0 );
1.380 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.381 sh4_x86.tstate = TSTATE_NONE;
1.382 :}
1.383 MOV.L Rm, @(disp, Rn) {:
1.384 @@ -1356,8 +1278,19 @@
1.385 load_reg( R_EAX, Rn );
1.386 ADD_imm32_r32( disp, R_EAX );
1.387 check_walign32( R_EAX );
1.388 + MOV_r32_r32( R_EAX, R_ECX );
1.389 + AND_imm32_r32( 0xFC000000, R_ECX );
1.390 + CMP_imm32_r32( 0xE0000000, R_ECX );
1.391 + JNE_rel8( notsq );
1.392 + AND_imm8s_r32( 0x3C, R_EAX );
1.393 + load_reg( R_EDX, Rm );
1.394 + MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
1.395 + JMP_rel8(end);
1.396 + JMP_TARGET(notsq);
1.397 MMU_TRANSLATE_WRITE( R_EAX );
1.398 - MEM_WRITE_LONG_CACHED( R_EAX, Rm, Rn );
1.399 + load_reg( R_EDX, Rm );
1.400 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.401 + JMP_TARGET(end);
1.402 sh4_x86.tstate = TSTATE_NONE;
1.403 :}
1.404 MOV.L @Rm, Rn {:
1.405 @@ -1365,7 +1298,7 @@
1.406 load_reg( R_EAX, Rm );
1.407 check_ralign32( R_EAX );
1.408 MMU_TRANSLATE_READ( R_EAX );
1.409 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.410 + MEM_READ_LONG( R_EAX, R_EAX );
1.411 store_reg( R_EAX, Rn );
1.412 sh4_x86.tstate = TSTATE_NONE;
1.413 :}
1.414 @@ -1375,7 +1308,7 @@
1.415 check_ralign32( R_EAX );
1.416 MMU_TRANSLATE_READ( R_EAX );
1.417 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.418 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.419 + MEM_READ_LONG( R_EAX, R_EAX );
1.420 store_reg( R_EAX, Rn );
1.421 sh4_x86.tstate = TSTATE_NONE;
1.422 :}
1.423 @@ -1386,7 +1319,7 @@
1.424 ADD_r32_r32( R_ECX, R_EAX );
1.425 check_ralign32( R_EAX );
1.426 MMU_TRANSLATE_READ( R_EAX );
1.427 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, 0 );
1.428 + MEM_READ_LONG( R_EAX, R_EAX );
1.429 store_reg( R_EAX, Rn );
1.430 sh4_x86.tstate = TSTATE_NONE;
1.431 :}
1.432 @@ -1396,7 +1329,7 @@
1.433 ADD_imm32_r32( disp, R_EAX );
1.434 check_ralign32( R_EAX );
1.435 MMU_TRANSLATE_READ( R_EAX );
1.436 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, 16 );
1.437 + MEM_READ_LONG( R_EAX, R_EAX );
1.438 store_reg( R_EAX, 0 );
1.439 sh4_x86.tstate = TSTATE_NONE;
1.440 :}
1.441 @@ -1425,7 +1358,7 @@
1.442 load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
1.443 ADD_sh4r_r32( R_PC, R_EAX );
1.444 MMU_TRANSLATE_READ( R_EAX );
1.445 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, 16 );
1.446 + MEM_READ_LONG( R_EAX, R_EAX );
1.447 sh4_x86.tstate = TSTATE_NONE;
1.448 }
1.449 store_reg( R_EAX, Rn );
1.450 @@ -1437,7 +1370,7 @@
1.451 ADD_imm8s_r32( disp, R_EAX );
1.452 check_ralign32( R_EAX );
1.453 MMU_TRANSLATE_READ( R_EAX );
1.454 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.455 + MEM_READ_LONG( R_EAX, R_EAX );
1.456 store_reg( R_EAX, Rn );
1.457 sh4_x86.tstate = TSTATE_NONE;
1.458 :}
1.459 @@ -1446,7 +1379,8 @@
1.460 load_reg( R_EAX, Rn );
1.461 check_walign16( R_EAX );
1.462 MMU_TRANSLATE_WRITE( R_EAX )
1.463 - MEM_WRITE_WORD_CACHED( R_EAX, Rm, Rn );
1.464 + load_reg( R_EDX, Rm );
1.465 + MEM_WRITE_WORD( R_EAX, R_EDX );
1.466 sh4_x86.tstate = TSTATE_NONE;
1.467 :}
1.468 MOV.W Rm, @-Rn {:
1.469 @@ -1455,8 +1389,9 @@
1.470 ADD_imm8s_r32( -2, R_EAX );
1.471 check_walign16( R_EAX );
1.472 MMU_TRANSLATE_WRITE( R_EAX );
1.473 + load_reg( R_EDX, Rm );
1.474 ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
1.475 - MEM_WRITE_WORD_CACHED( R_EAX, Rm, Rn );
1.476 + MEM_WRITE_WORD( R_EAX, R_EDX );
1.477 sh4_x86.tstate = TSTATE_NONE;
1.478 :}
1.479 MOV.W Rm, @(R0, Rn) {:
1.480 @@ -1466,7 +1401,8 @@
1.481 ADD_r32_r32( R_ECX, R_EAX );
1.482 check_walign16( R_EAX );
1.483 MMU_TRANSLATE_WRITE( R_EAX );
1.484 - MEM_WRITE_WORD_CACHED( R_EAX, Rm, 0 );
1.485 + load_reg( R_EDX, Rm );
1.486 + MEM_WRITE_WORD( R_EAX, R_EDX );
1.487 sh4_x86.tstate = TSTATE_NONE;
1.488 :}
1.489 MOV.W R0, @(disp, GBR) {:
1.490 @@ -1475,7 +1411,8 @@
1.491 ADD_imm32_r32( disp, R_EAX );
1.492 check_walign16( R_EAX );
1.493 MMU_TRANSLATE_WRITE( R_EAX );
1.494 - MEM_WRITE_WORD_CACHED( R_EAX, 0, 16 );
1.495 + load_reg( R_EDX, 0 );
1.496 + MEM_WRITE_WORD( R_EAX, R_EDX );
1.497 sh4_x86.tstate = TSTATE_NONE;
1.498 :}
1.499 MOV.W R0, @(disp, Rn) {:
1.500 @@ -1484,7 +1421,8 @@
1.501 ADD_imm32_r32( disp, R_EAX );
1.502 check_walign16( R_EAX );
1.503 MMU_TRANSLATE_WRITE( R_EAX );
1.504 - MEM_WRITE_WORD_CACHED( R_EAX, 0, Rn );
1.505 + load_reg( R_EDX, 0 );
1.506 + MEM_WRITE_WORD( R_EAX, R_EDX );
1.507 sh4_x86.tstate = TSTATE_NONE;
1.508 :}
1.509 MOV.W @Rm, Rn {:
1.510 @@ -1492,7 +1430,7 @@
1.511 load_reg( R_EAX, Rm );
1.512 check_ralign16( R_EAX );
1.513 MMU_TRANSLATE_READ( R_EAX );
1.514 - MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
1.515 + MEM_READ_WORD( R_EAX, R_EAX );
1.516 store_reg( R_EAX, Rn );
1.517 sh4_x86.tstate = TSTATE_NONE;
1.518 :}
1.519 @@ -1502,7 +1440,7 @@
1.520 check_ralign16( R_EAX );
1.521 MMU_TRANSLATE_READ( R_EAX );
1.522 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
1.523 - MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
1.524 + MEM_READ_WORD( R_EAX, R_EAX );
1.525 store_reg( R_EAX, Rn );
1.526 sh4_x86.tstate = TSTATE_NONE;
1.527 :}
1.528 @@ -1513,7 +1451,7 @@
1.529 ADD_r32_r32( R_ECX, R_EAX );
1.530 check_ralign16( R_EAX );
1.531 MMU_TRANSLATE_READ( R_EAX );
1.532 - MEM_READ_WORD_CACHED( R_EAX, R_EAX, 0 );
1.533 + MEM_READ_WORD( R_EAX, R_EAX );
1.534 store_reg( R_EAX, Rn );
1.535 sh4_x86.tstate = TSTATE_NONE;
1.536 :}
1.537 @@ -1523,7 +1461,7 @@
1.538 ADD_imm32_r32( disp, R_EAX );
1.539 check_ralign16( R_EAX );
1.540 MMU_TRANSLATE_READ( R_EAX );
1.541 - MEM_READ_WORD_CACHED( R_EAX, R_EAX, 16 );
1.542 + MEM_READ_WORD( R_EAX, R_EAX );
1.543 store_reg( R_EAX, 0 );
1.544 sh4_x86.tstate = TSTATE_NONE;
1.545 :}
1.546 @@ -1554,7 +1492,7 @@
1.547 ADD_imm32_r32( disp, R_EAX );
1.548 check_ralign16( R_EAX );
1.549 MMU_TRANSLATE_READ( R_EAX );
1.550 - MEM_READ_WORD_CACHED( R_EAX, R_EAX, Rm );
1.551 + MEM_READ_WORD( R_EAX, R_EAX );
1.552 store_reg( R_EAX, 0 );
1.553 sh4_x86.tstate = TSTATE_NONE;
1.554 :}
1.555 @@ -1574,7 +1512,8 @@
1.556 load_reg( R_EAX, Rn );
1.557 check_walign32( R_EAX );
1.558 MMU_TRANSLATE_WRITE( R_EAX );
1.559 - MEM_WRITE_LONG_CACHED( R_EAX, 0, Rn );
1.560 + load_reg( R_EDX, 0 );
1.561 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.562 sh4_x86.tstate = TSTATE_NONE;
1.563 :}
1.564
1.565 @@ -1924,11 +1863,14 @@
1.566 if( sh4_x86.double_size ) {
1.567 check_walign64( R_EAX );
1.568 MMU_TRANSLATE_WRITE( R_EAX );
1.569 - MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, Rn );
1.570 + load_dr0( R_EDX, FRm );
1.571 + load_dr1( R_ECX, FRm );
1.572 + MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
1.573 } else {
1.574 check_walign32( R_EAX );
1.575 MMU_TRANSLATE_WRITE( R_EAX );
1.576 - MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, Rn );
1.577 + load_fr( R_EDX, FRm );
1.578 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.579 }
1.580 sh4_x86.tstate = TSTATE_NONE;
1.581 :}
1.582 @@ -1939,13 +1881,13 @@
1.583 if( sh4_x86.double_size ) {
1.584 check_ralign64( R_EAX );
1.585 MMU_TRANSLATE_READ( R_EAX );
1.586 - MEM_READ_DOUBLE_CACHED( R_EAX, R_EDX, R_EAX, Rm );
1.587 + MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
1.588 store_dr0( R_EDX, FRn );
1.589 store_dr1( R_EAX, FRn );
1.590 } else {
1.591 check_ralign32( R_EAX );
1.592 MMU_TRANSLATE_READ( R_EAX );
1.593 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.594 + MEM_READ_LONG( R_EAX, R_EAX );
1.595 store_fr( R_EAX, FRn );
1.596 }
1.597 sh4_x86.tstate = TSTATE_NONE;
1.598 @@ -1956,16 +1898,19 @@
1.599 load_reg( R_EAX, Rn );
1.600 if( sh4_x86.double_size ) {
1.601 check_walign64( R_EAX );
1.602 - LEA_r32disp8_r32( R_EAX, -8, R_EAX );
1.603 + ADD_imm8s_r32(-8,R_EAX);
1.604 MMU_TRANSLATE_WRITE( R_EAX );
1.605 + load_dr0( R_EDX, FRm );
1.606 + load_dr1( R_ECX, FRm );
1.607 ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
1.608 - MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, Rn );
1.609 + MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
1.610 } else {
1.611 check_walign32( R_EAX );
1.612 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );
1.613 + ADD_imm8s_r32( -4, R_EAX );
1.614 MMU_TRANSLATE_WRITE( R_EAX );
1.615 + load_fr( R_EDX, FRm );
1.616 ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
1.617 - MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, Rn );
1.618 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.619 }
1.620 sh4_x86.tstate = TSTATE_NONE;
1.621 :}
1.622 @@ -1977,14 +1922,14 @@
1.623 check_ralign64( R_EAX );
1.624 MMU_TRANSLATE_READ( R_EAX );
1.625 ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
1.626 - MEM_READ_DOUBLE_CACHED( R_EAX, R_EDX, R_EAX, Rm );
1.627 + MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
1.628 store_dr0( R_EDX, FRn );
1.629 store_dr1( R_EAX, FRn );
1.630 } else {
1.631 check_ralign32( R_EAX );
1.632 MMU_TRANSLATE_READ( R_EAX );
1.633 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.634 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.635 + MEM_READ_LONG( R_EAX, R_EAX );
1.636 store_fr( R_EAX, FRn );
1.637 }
1.638 sh4_x86.tstate = TSTATE_NONE;
1.639 @@ -1997,11 +1942,14 @@
1.640 if( sh4_x86.double_size ) {
1.641 check_walign64( R_EAX );
1.642 MMU_TRANSLATE_WRITE( R_EAX );
1.643 - MEM_WRITE_DOUBLE_CACHED( R_EAX, FRm, 0 );
1.644 + load_dr0( R_EDX, FRm );
1.645 + load_dr1( R_ECX, FRm );
1.646 + MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
1.647 } else {
1.648 check_walign32( R_EAX );
1.649 MMU_TRANSLATE_WRITE( R_EAX );
1.650 - MEM_WRITE_FLOAT_CACHED( R_EAX, FRm, 0 );
1.651 + load_fr( R_EDX, FRm );
1.652 + MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
1.653 }
1.654 sh4_x86.tstate = TSTATE_NONE;
1.655 :}
1.656 @@ -2013,13 +1961,13 @@
1.657 if( sh4_x86.double_size ) {
1.658 check_ralign64( R_EAX );
1.659 MMU_TRANSLATE_READ( R_EAX );
1.660 - MEM_READ_DOUBLE_CACHED( R_EAX, R_ECX, R_EAX, 0 );
1.661 + MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
1.662 store_dr0( R_ECX, FRn );
1.663 store_dr1( R_EAX, FRn );
1.664 } else {
1.665 check_ralign32( R_EAX );
1.666 MMU_TRANSLATE_READ( R_EAX );
1.667 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, 0 );
1.668 + MEM_READ_LONG( R_EAX, R_EAX );
1.669 store_fr( R_EAX, FRn );
1.670 }
1.671 sh4_x86.tstate = TSTATE_NONE;
1.672 @@ -2436,7 +2384,7 @@
1.673 check_ralign32( R_EAX );
1.674 MMU_TRANSLATE_READ( R_EAX );
1.675 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.676 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.677 + MEM_READ_LONG( R_EAX, R_EAX );
1.678 store_spreg( R_EAX, R_GBR );
1.679 sh4_x86.tstate = TSTATE_NONE;
1.680 :}
1.681 @@ -2450,7 +2398,7 @@
1.682 check_ralign32( R_EAX );
1.683 MMU_TRANSLATE_READ( R_EAX );
1.684 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.685 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.686 + MEM_READ_LONG( R_EAX, R_EAX );
1.687 call_func1( sh4_write_sr, R_EAX );
1.688 sh4_x86.priv_checked = FALSE;
1.689 sh4_x86.fpuen_checked = FALSE;
1.690 @@ -2464,7 +2412,7 @@
1.691 check_ralign32( R_EAX );
1.692 MMU_TRANSLATE_READ( R_EAX );
1.693 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.694 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.695 + MEM_READ_LONG( R_EAX, R_EAX );
1.696 store_spreg( R_EAX, R_VBR );
1.697 sh4_x86.tstate = TSTATE_NONE;
1.698 :}
1.699 @@ -2475,7 +2423,7 @@
1.700 check_ralign32( R_EAX );
1.701 MMU_TRANSLATE_READ( R_EAX );
1.702 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.703 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.704 + MEM_READ_LONG( R_EAX, R_EAX );
1.705 store_spreg( R_EAX, R_SSR );
1.706 sh4_x86.tstate = TSTATE_NONE;
1.707 :}
1.708 @@ -2486,7 +2434,7 @@
1.709 check_ralign32( R_EAX );
1.710 MMU_TRANSLATE_READ( R_EAX );
1.711 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.712 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.713 + MEM_READ_LONG( R_EAX, R_EAX );
1.714 store_spreg( R_EAX, R_SGR );
1.715 sh4_x86.tstate = TSTATE_NONE;
1.716 :}
1.717 @@ -2497,7 +2445,7 @@
1.718 check_ralign32( R_EAX );
1.719 MMU_TRANSLATE_READ( R_EAX );
1.720 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.721 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.722 + MEM_READ_LONG( R_EAX, R_EAX );
1.723 store_spreg( R_EAX, R_SPC );
1.724 sh4_x86.tstate = TSTATE_NONE;
1.725 :}
1.726 @@ -2508,7 +2456,7 @@
1.727 check_ralign32( R_EAX );
1.728 MMU_TRANSLATE_READ( R_EAX );
1.729 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.730 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.731 + MEM_READ_LONG( R_EAX, R_EAX );
1.732 store_spreg( R_EAX, R_DBR );
1.733 sh4_x86.tstate = TSTATE_NONE;
1.734 :}
1.735 @@ -2519,7 +2467,7 @@
1.736 check_ralign32( R_EAX );
1.737 MMU_TRANSLATE_READ( R_EAX );
1.738 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.739 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.740 + MEM_READ_LONG( R_EAX, R_EAX );
1.741 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
1.742 sh4_x86.tstate = TSTATE_NONE;
1.743 :}
1.744 @@ -2538,7 +2486,7 @@
1.745 check_ralign32( R_EAX );
1.746 MMU_TRANSLATE_READ( R_EAX );
1.747 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.748 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.749 + MEM_READ_LONG( R_EAX, R_EAX );
1.750 call_func1( sh4_write_fpscr, R_EAX );
1.751 sh4_x86.tstate = TSTATE_NONE;
1.752 return 2;
1.753 @@ -2556,7 +2504,7 @@
1.754 check_ralign32( R_EAX );
1.755 MMU_TRANSLATE_READ( R_EAX );
1.756 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.757 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.758 + MEM_READ_LONG( R_EAX, R_EAX );
1.759 store_spreg( R_EAX, R_FPUL );
1.760 sh4_x86.tstate = TSTATE_NONE;
1.761 :}
1.762 @@ -2571,7 +2519,7 @@
1.763 check_ralign32( R_EAX );
1.764 MMU_TRANSLATE_READ( R_EAX );
1.765 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.766 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.767 + MEM_READ_LONG( R_EAX, R_EAX );
1.768 store_spreg( R_EAX, R_MACH );
1.769 sh4_x86.tstate = TSTATE_NONE;
1.770 :}
1.771 @@ -2586,7 +2534,7 @@
1.772 check_ralign32( R_EAX );
1.773 MMU_TRANSLATE_READ( R_EAX );
1.774 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.775 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.776 + MEM_READ_LONG( R_EAX, R_EAX );
1.777 store_spreg( R_EAX, R_MACL );
1.778 sh4_x86.tstate = TSTATE_NONE;
1.779 :}
1.780 @@ -2601,7 +2549,7 @@
1.781 check_ralign32( R_EAX );
1.782 MMU_TRANSLATE_READ( R_EAX );
1.783 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
1.784 - MEM_READ_LONG_CACHED( R_EAX, R_EAX, Rm );
1.785 + MEM_READ_LONG( R_EAX, R_EAX );
1.786 store_spreg( R_EAX, R_PR );
1.787 sh4_x86.tstate = TSTATE_NONE;
1.788 :}
1.789 @@ -2705,11 +2653,12 @@
1.790 check_walign32( R_EAX );
1.791 ADD_imm8s_r32( -4, R_EAX );
1.792 MMU_TRANSLATE_WRITE( R_EAX );
1.793 - MOV_r32_r32( R_EAX, R_EBX );
1.794 + MOV_r32_esp8( R_EAX, 0 );
1.795 call_func0( sh4_read_sr );
1.796 MOV_r32_r32( R_EAX, R_EDX );
1.797 + MOV_esp8_r32( 0, R_EAX );
1.798 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.799 - MEM_WRITE_LONG( R_EBX, R_EDX );
1.800 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.801 sh4_x86.tstate = TSTATE_NONE;
1.802 :}
1.803 STC.L VBR, @-Rn {:
1.804 @@ -2719,8 +2668,9 @@
1.805 check_walign32( R_EAX );
1.806 ADD_imm8s_r32( -4, R_EAX );
1.807 MMU_TRANSLATE_WRITE( R_EAX );
1.808 + load_spreg( R_EDX, R_VBR );
1.809 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.810 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_VBR, Rn );
1.811 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.812 sh4_x86.tstate = TSTATE_NONE;
1.813 :}
1.814 STC.L SSR, @-Rn {:
1.815 @@ -2730,8 +2680,9 @@
1.816 check_walign32( R_EAX );
1.817 ADD_imm8s_r32( -4, R_EAX );
1.818 MMU_TRANSLATE_WRITE( R_EAX );
1.819 + load_spreg( R_EDX, R_SSR );
1.820 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.821 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_SSR, Rn );
1.822 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.823 sh4_x86.tstate = TSTATE_NONE;
1.824 :}
1.825 STC.L SPC, @-Rn {:
1.826 @@ -2741,8 +2692,9 @@
1.827 check_walign32( R_EAX );
1.828 ADD_imm8s_r32( -4, R_EAX );
1.829 MMU_TRANSLATE_WRITE( R_EAX );
1.830 + load_spreg( R_EDX, R_SPC );
1.831 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.832 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_SPC, Rn );
1.833 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.834 sh4_x86.tstate = TSTATE_NONE;
1.835 :}
1.836 STC.L SGR, @-Rn {:
1.837 @@ -2752,8 +2704,9 @@
1.838 check_walign32( R_EAX );
1.839 ADD_imm8s_r32( -4, R_EAX );
1.840 MMU_TRANSLATE_WRITE( R_EAX );
1.841 + load_spreg( R_EDX, R_SGR );
1.842 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.843 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_SGR, Rn );
1.844 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.845 sh4_x86.tstate = TSTATE_NONE;
1.846 :}
1.847 STC.L DBR, @-Rn {:
1.848 @@ -2763,8 +2716,9 @@
1.849 check_walign32( R_EAX );
1.850 ADD_imm8s_r32( -4, R_EAX );
1.851 MMU_TRANSLATE_WRITE( R_EAX );
1.852 + load_spreg( R_EDX, R_DBR );
1.853 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.854 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_DBR, Rn );
1.855 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.856 sh4_x86.tstate = TSTATE_NONE;
1.857 :}
1.858 STC.L Rm_BANK, @-Rn {:
1.859 @@ -2774,8 +2728,9 @@
1.860 check_walign32( R_EAX );
1.861 ADD_imm8s_r32( -4, R_EAX );
1.862 MMU_TRANSLATE_WRITE( R_EAX );
1.863 + load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
1.864 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.865 - MEM_WRITE_LONG_CACHED_SP( R_EAX, REG_OFFSET(r_bank[Rm_BANK]), Rn );
1.866 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.867 sh4_x86.tstate = TSTATE_NONE;
1.868 :}
1.869 STC.L GBR, @-Rn {:
1.870 @@ -2784,8 +2739,9 @@
1.871 check_walign32( R_EAX );
1.872 ADD_imm8s_r32( -4, R_EAX );
1.873 MMU_TRANSLATE_WRITE( R_EAX );
1.874 + load_spreg( R_EDX, R_GBR );
1.875 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.876 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_GBR, Rn );
1.877 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.878 sh4_x86.tstate = TSTATE_NONE;
1.879 :}
1.880 STS FPSCR, Rn {:
1.881 @@ -2801,8 +2757,9 @@
1.882 check_walign32( R_EAX );
1.883 ADD_imm8s_r32( -4, R_EAX );
1.884 MMU_TRANSLATE_WRITE( R_EAX );
1.885 + load_spreg( R_EDX, R_FPSCR );
1.886 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.887 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_FPSCR, Rn );
1.888 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.889 sh4_x86.tstate = TSTATE_NONE;
1.890 :}
1.891 STS FPUL, Rn {:
1.892 @@ -2818,8 +2775,9 @@
1.893 check_walign32( R_EAX );
1.894 ADD_imm8s_r32( -4, R_EAX );
1.895 MMU_TRANSLATE_WRITE( R_EAX );
1.896 + load_spreg( R_EDX, R_FPUL );
1.897 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.898 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_FPUL, Rn );
1.899 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.900 sh4_x86.tstate = TSTATE_NONE;
1.901 :}
1.902 STS MACH, Rn {:
1.903 @@ -2833,8 +2791,9 @@
1.904 check_walign32( R_EAX );
1.905 ADD_imm8s_r32( -4, R_EAX );
1.906 MMU_TRANSLATE_WRITE( R_EAX );
1.907 + load_spreg( R_EDX, R_MACH );
1.908 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.909 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_MACH, Rn );
1.910 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.911 sh4_x86.tstate = TSTATE_NONE;
1.912 :}
1.913 STS MACL, Rn {:
1.914 @@ -2848,8 +2807,9 @@
1.915 check_walign32( R_EAX );
1.916 ADD_imm8s_r32( -4, R_EAX );
1.917 MMU_TRANSLATE_WRITE( R_EAX );
1.918 + load_spreg( R_EDX, R_MACL );
1.919 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.920 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_MACL, Rn );
1.921 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.922 sh4_x86.tstate = TSTATE_NONE;
1.923 :}
1.924 STS PR, Rn {:
1.925 @@ -2863,8 +2823,9 @@
1.926 check_walign32( R_EAX );
1.927 ADD_imm8s_r32( -4, R_EAX );
1.928 MMU_TRANSLATE_WRITE( R_EAX );
1.929 + load_spreg( R_EDX, R_PR );
1.930 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
1.931 - MEM_WRITE_LONG_CACHED_SP( R_EAX, R_PR, Rn );
1.932 + MEM_WRITE_LONG( R_EAX, R_EDX );
1.933 sh4_x86.tstate = TSTATE_NONE;
1.934 :}
1.935
.