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lxdream.org :: lxdream/src/aica/armdasm.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/aica/armdasm.c
changeset 11:0a82ef380c45
prev7:976a16e92aab
next13:28aea89fb9c6
author nkeynes
date Sun Dec 11 12:00:09 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Moved arm material under aica/
Hooked arm disasm up
file annotate diff log raw
1.1 --- a/src/aica/armdasm.c Sun Dec 12 07:44:09 2004 +0000
1.2 +++ b/src/aica/armdasm.c Sun Dec 11 12:00:09 2005 +0000
1.3 @@ -6,6 +6,7 @@
1.4 */
1.5
1.6 #include "aica/armcore.h"
1.7 +#include "aica/armdasm.h"
1.8 #include <stdlib.h>
1.9
1.10 #define COND(ir) (ir>>28)
1.11 @@ -32,6 +33,30 @@
1.12 #define FSXC(ir) msrFieldMask[RN(ir)]
1.13 #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir))
1.14
1.15 +
1.16 +const struct reg_desc_struct arm_reg_map[] =
1.17 + { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]},
1.18 + {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]},
1.19 + {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]},
1.20 + {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]},
1.21 + {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]},
1.22 + {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]},
1.23 + {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]},
1.24 + {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]},
1.25 + {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr},
1.26 + {NULL, 0, NULL} };
1.27 +
1.28 +
1.29 +const struct cpu_desc_struct arm_cpu_desc = { "ARM7", arm_disasm_instruction, 4,
1.30 + (char *)&armr, sizeof(armr), arm_reg_map,
1.31 + &armr.r[15], &armr.icount };
1.32 +const struct cpu_desc_struct armt_cpu_desc = { "ARM7T", armt_disasm_instruction, 2,
1.33 + (char*)&armr, sizeof(armr), arm_reg_map,
1.34 + &armr.r[15], &armr.icount };
1.35 +
1.36 +
1.37 +
1.38 +
1.39 char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC",
1.40 "HI", "LS", "GE", "LT", "GT", "LE", " " /*AL*/, "NV" };
1.41
1.42 @@ -127,12 +152,15 @@
1.43 }
1.44 }
1.45
1.46 -int arm_disasm_instruction( uint32_t pc, char *buf, int len )
1.47 +uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
1.48 {
1.49 - char operand[32];
1.50 - uint32_t ir = arm_mem_read_long(pc);
1.51 - int i,j;
1.52 + char operand[32];
1.53 + uint32_t ir = arm_read_long(pc);
1.54 + int i,j;
1.55
1.56 + sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF,
1.57 + (ir>>16)&0xFF, (ir>>24) );
1.58 +
1.59 if( COND(ir) == 0x0F ) {
1.60 UNIMP(ir);
1.61 return pc+4;
1.62 @@ -421,3 +449,12 @@
1.63
1.64 return pc+4;
1.65 }
1.66 +
1.67 +
1.68 +uint32_t armt_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
1.69 +{
1.70 + uint32_t ir = arm_read_word(pc);
1.71 + sprintf( opcode, "%02X %02X", ir&0xFF, (ir>>8) );
1.72 + UNIMP(ir);
1.73 + return pc+2;
1.74 +}
.