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lxdream.org :: lxdream/src/sh4/sh4xir.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4xir.in
changeset 1012:0b8cc74ac83a
prev1011:fdd58619b760
author nkeynes
date Sun Apr 19 05:14:19 2009 +0000 (13 years ago)
branchxlat-refactor
permissions -rw-r--r--
last change Remove branch instructions and replace with direct modification of PC + EXIT
Add MIN/MAX instructions (for bound checks)
Implement x86_target_is_legal
Correct a few sh4 instructions
file annotate diff log raw
1.1 --- a/src/sh4/sh4xir.in Sun Apr 12 07:24:45 2009 +0000
1.2 +++ b/src/sh4/sh4xir.in Sun Apr 19 05:14:19 2009 +0000
1.3 @@ -139,7 +139,7 @@
1.4 XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );
1.5 }
1.6 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.7 - XOP1S( OP_BR, R_SPC )->next = NULL;
1.8 + XOP0( OP_EXIT )->next = NULL;
1.9 start->prev = NULL;
1.10 return start;
1.11 }
1.12 @@ -160,7 +160,7 @@
1.13 XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );
1.14 }
1.15 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.16 - XOP1S( OP_BR, R_SPC )->next = NULL;
1.17 + XOP0( OP_EXIT )->next = NULL;
1.18
1.19 ins->next = xbb->ir_ptr;
1.20 xbb->ir_ptr->prev = ins;
1.21 @@ -214,7 +214,7 @@
1.22 XOP2IS( OP_MOV, 1, R_DELAY_SLOT ); \
1.23 XOP0( OP_BARRIER ); \
1.24 XOPCALL0( sh4_execute_instruction ); \
1.25 - XOP1S( OP_BR, R_PC ); \
1.26 + XOP0( OP_EXIT ); \
1.27 } while(0)
1.28
1.29
1.30 @@ -644,8 +644,7 @@
1.31 // behaviour to confirm) Unlikely to be anyone depending on this
1.32 // behaviour though.
1.33 sh4ptr_t ptr = GET_ICACHE_PTR(target);
1.34 - XOP2PT( OP_LOADPTRL, ptr, REG_TMP0 );
1.35 - XOP2TS( OP_MOVSX16, REG_TMP0, R_R(Rn) );
1.36 + XOP2PT( OP_LOADPTRW, ptr, REG_TMP0 );
1.37 } else {
1.38 // Note: we use sh4r.pc for the calc as we could be running at a
1.39 // different virtual address than the translation was done with,
1.40 @@ -794,9 +793,15 @@
1.41 FTRC FRm, FPUL {:
1.42 CHECKFPUEN();
1.43 if( sh4_xir.double_prec ) {
1.44 - XOP2SS( OP_DTOI, R_DR(FRm), R_FPUL );
1.45 + XOP2SS( OP_MOVQ, R_DR(FRm), REG_TMPD0 );
1.46 + XOP2FS( OP_MAXD, (double)0x8000000000000000, REG_TMPD0 );
1.47 + XOP2FS( OP_MIND, (double)0x7FFFFFFFFFFFFFFF, REG_TMPD0 );
1.48 + XOP2SS( OP_DTOI, REG_TMPD0, R_FPUL );
1.49 } else {
1.50 - XOP2SS( OP_FTOI, R_FR(FRm), R_FPUL );
1.51 + XOP2SS( OP_MOV, R_FR(FRm), REG_TMPF0 );
1.52 + XOP2FS( OP_MAXF, (double)0x80000000, REG_TMPF0 );
1.53 + XOP2FS( OP_MINF, (double)0x7FFFFFFF, REG_TMPF0 );
1.54 + XOP2SS( OP_FTOI, REG_TMPF0, R_FPUL );
1.55 }
1.56 :}
1.57 FLDS FRm, FPUL {:
1.58 @@ -1181,7 +1186,9 @@
1.59 } else {
1.60 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.61 XOP2IS( OP_CMP, 0, R_T );
1.62 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
1.63 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );
1.64 + XOP2ISCC( OP_ADD, CC_NE, pc+2-xbb->pc_begin, R_PC );
1.65 + XOP0( OP_EXIT );
1.66 }
1.67 return 2;
1.68 :}
1.69 @@ -1191,8 +1198,11 @@
1.70 return 2;
1.71 } else {
1.72 if( UNTRANSLATABLE(pc+2 ) ) {
1.73 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.74 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );
1.75 XOP2IS( OP_CMP, 0, R_T );
1.76 - XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
1.77 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_NEW_PC );
1.78 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_NEW_PC );
1.79 EMU_DELAY_SLOT();
1.80 return 2;
1.81 } else {
1.82 @@ -1201,7 +1211,9 @@
1.83 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.84 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.85 XOP2IT( OP_CMP, 0, REG_TMP2 );
1.86 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
1.87 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );
1.88 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_PC );
1.89 + XOP0( OP_EXIT );
1.90 }
1.91 return 4;
1.92 }
1.93 @@ -1213,7 +1225,9 @@
1.94 } else {
1.95 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.96 XOP2IS( OP_CMP, 1, R_T );
1.97 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
1.98 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );
1.99 + XOP2ISCC( OP_ADD, CC_NE, pc+2-xbb->pc_begin, R_PC );
1.100 + XOP0( OP_EXIT );
1.101 }
1.102 return 2;
1.103 :}
1.104 @@ -1223,8 +1237,11 @@
1.105 return 2;
1.106 } else {
1.107 if( UNTRANSLATABLE(pc+2 ) ) {
1.108 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.109 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );
1.110 XOP2IS( OP_CMP, 1, R_T );
1.111 - XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );
1.112 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_NEW_PC );
1.113 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_NEW_PC );
1.114 EMU_DELAY_SLOT();
1.115 return 2;
1.116 } else {
1.117 @@ -1233,7 +1250,9 @@
1.118 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.119 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.120 XOP2IT( OP_CMP, 1, REG_TMP2 );
1.121 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );
1.122 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );
1.123 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_PC );
1.124 + XOP0( OP_EXIT );
1.125 }
1.126 return 4;
1.127 }
1.128 @@ -1253,7 +1272,8 @@
1.129 sh4_decode_instruction( xbb, pc+2, TRUE );
1.130 if( xbb->ir_ptr->prev == NULL || !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.131 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.132 - XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );
1.133 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_PC );
1.134 + XOP0( OP_EXIT );
1.135 }
1.136 return 4;
1.137 }
1.138 @@ -1264,9 +1284,9 @@
1.139 SLOTILLEGAL();
1.140 return 2;
1.141 } else {
1.142 - XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );
1.143 - XOP2ST( OP_ADD, R_PC, REG_TMP2 );
1.144 + XOP2ST( OP_MOV, R_PC, REG_TMP2 );
1.145 XOP2IT( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );
1.146 + XOP2ST( OP_ADD, R_R(Rn), REG_TMP2 );
1.147 if( UNTRANSLATABLE(pc+2) ) {
1.148 XOP2TS( OP_MOV, REG_TMP2, R_NEW_PC );
1.149 EMU_DELAY_SLOT();
1.150 @@ -1275,7 +1295,8 @@
1.151 sh4_decode_instruction( xbb, pc + 2, TRUE );
1.152 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.153 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.154 - XOP1T( OP_BR, REG_TMP2 );
1.155 + XOP2TS( OP_MOV, REG_TMP2, R_PC );
1.156 + XOP0( OP_EXIT );
1.157 }
1.158 return 4;
1.159 }
1.160 @@ -1297,7 +1318,8 @@
1.161 sh4_decode_instruction( xbb, pc+2, TRUE );
1.162 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.163 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.164 - XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );
1.165 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_PC );
1.166 + XOP0( OP_EXIT );
1.167 }
1.168 return 4;
1.169 }
1.170 @@ -1321,7 +1343,8 @@
1.171 sh4_decode_instruction( xbb, pc+2, TRUE );
1.172 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.173 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.174 - XOP1T( OP_BR, REG_TMP2 );
1.175 + XOP2TS( OP_ADD, REG_TMP2, R_PC );
1.176 + XOP0( OP_EXIT );
1.177 }
1.178 return 4;
1.179 }
1.180 @@ -1341,7 +1364,8 @@
1.181 sh4_decode_instruction( xbb, pc+2, TRUE );
1.182 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.183 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.184 - XOP1T( OP_BR, REG_TMP2 );
1.185 + XOP2TS( OP_MOV, REG_TMP2, R_PC );
1.186 + XOP0( OP_EXIT );
1.187 }
1.188 return 4;
1.189 }
1.190 @@ -1363,7 +1387,8 @@
1.191 sh4_decode_instruction( xbb, pc+2, TRUE );
1.192 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.193 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.194 - XOP1T( OP_BR, REG_TMP2 );
1.195 + XOP2TS( OP_MOV, REG_TMP2, R_PC );
1.196 + XOP0( OP_EXIT );
1.197 }
1.198 return 4;
1.199 }
1.200 @@ -1385,7 +1410,8 @@
1.201 sh4_decode_instruction( xbb, pc+2, TRUE );
1.202 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.203 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.204 - XOP1T( OP_BR, REG_TMP2 );
1.205 + XOP2TS( OP_MOV, REG_TMP2, R_PC );
1.206 + XOP0( OP_EXIT );
1.207 }
1.208 return 4;
1.209 }
1.210 @@ -1405,14 +1431,25 @@
1.211 sh4_decode_instruction( xbb, pc+2, TRUE );
1.212 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {
1.213 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.214 - XOP1T( OP_BR, REG_TMP2 );
1.215 + XOP2TS( OP_MOV, REG_TMP2, R_PC );
1.216 + XOP0( OP_EXIT );
1.217 }
1.218 return 4;
1.219 }
1.220 }
1.221 :}
1.222 -TRAPA #imm {: XOPCALL1I( sh4_raise_trap, imm ); return pc+2; :}
1.223 -SLEEP {: XOPCALL0( sh4_sleep ); return pc+2; :}
1.224 +TRAPA #imm {:
1.225 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );
1.226 + XOP2IS( OP_ADD, pc+4-xbb->pc_begin, R_PC );
1.227 + XOPCALL1I( sh4_raise_trap, imm );
1.228 + XOP0( OP_EXIT );
1.229 + return 2;
1.230 +:}
1.231 +SLEEP {:
1.232 + XOPCALL0( sh4_sleep );
1.233 + XOP0( OP_EXIT);
1.234 + return 2;
1.235 +:}
1.236 UNDEF {: UNDEF(ir); :}
1.237 NOP {: /* Do nothing */ :}
1.238
.