1.1 --- a/src/aica/armcore.c	Tue Jan 10 13:56:54 2006 +0000
     1.2 +++ b/src/aica/armcore.c	Thu Jan 12 11:30:19 2006 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: armcore.c,v 1.16 2006-01-10 13:56:54 nkeynes Exp $
     1.6 + * $Id: armcore.c,v 1.17 2006-01-12 11:30:19 nkeynes Exp $
     1.7   * 
     1.8   * ARM7TDMI CPU emulation core.
     1.9   *
    1.10 @@ -18,8 +18,9 @@
    1.11  
    1.12  #define MODULE aica_module
    1.13  #include "dream.h"
    1.14 +#include "mem.h"
    1.15  #include "aica/armcore.h"
    1.16 -#include "mem.h"
    1.17 +#include "aica/aica.h"
    1.18  
    1.19  #define STM_R15_OFFSET 12
    1.20  
    1.21 @@ -46,6 +47,7 @@
    1.22  uint32_t arm_cpu_freq = ARM_BASE_RATE;
    1.23  uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE;
    1.24  
    1.25 +#define CYCLES_PER_SAMPLE ((ARM_BASE_RATE * 1000000) / AICA_SAMPLE_RATE)
    1.26  
    1.27  static struct breakpoint_struct arm_breakpoints[MAX_BREAKPOINTS];
    1.28  static int arm_breakpoint_count = 0;
    1.29 @@ -85,35 +87,40 @@
    1.30      return 0;
    1.31  }
    1.32  
    1.33 -uint32_t arm_run_slice( uint32_t nanosecs )
    1.34 +#define IS_TIMER_ENABLED() (MMIO_READ( AICA2, AICA_TCR ) & 0x40)
    1.35 +
    1.36 +uint32_t arm_run_slice( uint32_t num_samples )
    1.37  {
    1.38 -    int i;
    1.39 -    uint32_t target = armr.icount + nanosecs / arm_cpu_period;
    1.40 -    uint32_t start = armr.icount;
    1.41 -    while( armr.icount < target ) {
    1.42 -	armr.icount++;
    1.43 -	if( !arm_execute_instruction() )
    1.44 +    int i,j,k;
    1.45 +    for( i=0; i<num_samples; i++ ) {
    1.46 +	for( j=0; j < CYCLES_PER_SAMPLE; j++ ) {
    1.47 +	    armr.icount++;
    1.48 +	    if( !arm_execute_instruction() )
    1.49 +		return i;
    1.50 +#ifdef ENABLE_DEBUG_MODE
    1.51 +	    for( k=0; k<arm_breakpoint_count; k++ ) {
    1.52 +		if( arm_breakpoints[k].address == armr.r[15] ) {
    1.53 +		    dreamcast_stop();
    1.54 +		    if( arm_breakpoints[k].type == BREAK_ONESHOT )
    1.55 +			arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
    1.56 +		    return i;
    1.57 +		}
    1.58 +	    }
    1.59 +#endif	
    1.60 +	}
    1.61 +
    1.62 +	if( IS_TIMER_ENABLED() ) {
    1.63 +	    uint8_t val = MMIO_READ( AICA2, AICA_TIMER );
    1.64 +	    val++;
    1.65 +	    if( val == 0 )
    1.66 +		aica_event( AICA_EVENT_TIMER );
    1.67 +	    MMIO_WRITE( AICA2, AICA_TIMER, val );
    1.68 +	}
    1.69 +	if( !dreamcast_is_running() )
    1.70  	    break;
    1.71 -#ifdef ENABLE_DEBUG_MODE
    1.72 -	for( i=0; i<arm_breakpoint_count; i++ ) {
    1.73 -	    if( arm_breakpoints[i].address == armr.r[15] ) {
    1.74 -		break;
    1.75 -	    }
    1.76 -	}
    1.77 -	if( i != arm_breakpoint_count ) {
    1.78 -	    dreamcast_stop();
    1.79 -	    if( arm_breakpoints[i].type == BREAK_ONESHOT )
    1.80 -		arm_clear_breakpoint( armr.r[15], BREAK_ONESHOT );
    1.81 -	    break;
    1.82 -	}
    1.83 -#endif	
    1.84      }
    1.85  
    1.86 -    if( target != armr.icount ) {
    1.87 -	/* Halted - compute time actually executed */
    1.88 -	nanosecs = (armr.icount - start) * arm_cpu_period;
    1.89 -    }
    1.90 -    return nanosecs;
    1.91 +    return i;
    1.92  }
    1.93  
    1.94  void arm_save_state( FILE *f )