1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/sh4/mmu.h	Wed Jan 14 00:16:44 2009 +0000
     1.3 @@ -0,0 +1,159 @@
     1.4 +/**
     1.5 + * $Id$
     1.6 + *
     1.7 + * MMU/TLB definitions.
     1.8 + *
     1.9 + * Copyright (c) 2005 Nathan Keynes.
    1.10 + *
    1.11 + * This program is free software; you can redistribute it and/or modify
    1.12 + * it under the terms of the GNU General Public License as published by
    1.13 + * the Free Software Foundation; either version 2 of the License, or
    1.14 + * (at your option) any later version.
    1.15 + *
    1.16 + * This program is distributed in the hope that it will be useful,
    1.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
    1.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    1.19 + * GNU General Public License for more details.
    1.20 + */
    1.21 +
    1.22 +
    1.23 +#ifndef lxdream_sh4_mmu_H
    1.24 +#define lxdream_sh4_mmu_H 1
    1.25 +
    1.26 +#include "lxdream.h"
    1.27 +
    1.28 +#ifdef __cplusplus
    1.29 +extern "C" {
    1.30 +#endif
    1.31 +
    1.32 +#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
    1.33 +
    1.34 +/************************** UTLB/ITLB Definitions ***************************/
    1.35 +/* mmucr register bits */
    1.36 +#define MMUCR_AT   0x00000001 /* Address Translation enabled */
    1.37 +#define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */
    1.38 +#define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
    1.39 +#define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
    1.40 +#define MMUCR_URC  0x0000FC00 /* UTLB access counter */
    1.41 +#define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */
    1.42 +#define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
    1.43 +#define MMUCR_MASK 0xFCFCFF05
    1.44 +#define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
    1.45 +    
    1.46 +#define IS_TLB_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
    1.47 +#define IS_SV_ENABLED() (MMIO_READ(MMU,MMUCR)&MMUCR_SV)
    1.48 +
    1.49 +#define ITLB_ENTRY_COUNT 4
    1.50 +#define UTLB_ENTRY_COUNT 64
    1.51 +
    1.52 +/* Entry address */
    1.53 +#define TLB_VALID     0x00000100
    1.54 +#define TLB_USERMODE  0x00000040
    1.55 +#define TLB_WRITABLE  0x00000020
    1.56 +#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
    1.57 +#define TLB_SIZE_MASK 0x00000090
    1.58 +#define TLB_SIZE_1K   0x00000000
    1.59 +#define TLB_SIZE_4K   0x00000010
    1.60 +#define TLB_SIZE_64K  0x00000080
    1.61 +#define TLB_SIZE_1M   0x00000090
    1.62 +#define TLB_CACHEABLE 0x00000008
    1.63 +#define TLB_DIRTY     0x00000004
    1.64 +#define TLB_SHARE     0x00000002
    1.65 +#define TLB_WRITETHRU 0x00000001
    1.66 +
    1.67 +#define MASK_1K  0xFFFFFC00
    1.68 +#define MASK_4K  0xFFFFF000
    1.69 +#define MASK_64K 0xFFFF0000
    1.70 +#define MASK_1M  0xFFF00000
    1.71 +
    1.72 +struct itlb_entry {
    1.73 +    sh4addr_t vpn; // Virtual Page Number
    1.74 +    uint32_t asid; // Process ID
    1.75 +    uint32_t mask;
    1.76 +    sh4addr_t ppn; // Physical Page Number
    1.77 +    uint32_t flags;
    1.78 +};
    1.79 +
    1.80 +struct utlb_entry {
    1.81 +    sh4addr_t vpn; // Virtual Page Number
    1.82 +    uint32_t mask; // Page size mask
    1.83 +    uint32_t asid; // Process ID
    1.84 +    sh4addr_t ppn; // Physical Page Number
    1.85 +    uint32_t flags;
    1.86 +    uint32_t pcmcia; // extra pcmcia data - not used in this implementation
    1.87 +};
    1.88 +
    1.89 +#define TLB_FUNC_SIZE 48
    1.90 +
    1.91 +struct utlb_page_entry {
    1.92 +    struct mem_region_fn fn;
    1.93 +    struct mem_region_fn *user_fn;
    1.94 +    mem_region_fn_t target;
    1.95 +    unsigned char code[TLB_FUNC_SIZE*9];
    1.96 +};
    1.97 +
    1.98 +struct utlb_1k_entry {
    1.99 +    struct mem_region_fn fn;
   1.100 +    struct mem_region_fn user_fn;
   1.101 +    struct mem_region_fn *subpages[4];
   1.102 +    struct mem_region_fn *user_subpages[4];
   1.103 +    unsigned char code[TLB_FUNC_SIZE*18];
   1.104 +};
   1.105 +
   1.106 +struct utlb_default_regions {
   1.107 +    mem_region_fn_t tlb_miss;
   1.108 +    mem_region_fn_t tlb_prot;
   1.109 +    mem_region_fn_t tlb_multihit;
   1.110 +};
   1.111 +
   1.112 +
   1.113 +void mmu_utlb_init_vtable( struct utlb_entry *ent, struct utlb_page_entry *page, gboolean writable ); 
   1.114 +void mmu_utlb_1k_init_vtable( struct utlb_1k_entry *ent ); 
   1.115 +void mmu_utlb_init_storequeue_vtable( struct utlb_entry *ent, struct utlb_page_entry *page );
   1.116 +
   1.117 +extern uint32_t mmu_urc;
   1.118 +extern uint32_t mmu_urb;
   1.119 +
   1.120 +/** Primary SH4 address space (privileged and user access)
   1.121 + * Page map (4KB) of the entire 32-bit address space
   1.122 + * Note: only callable from the SH4 cores as it depends on the caller setting
   1.123 + * up an appropriate exception environment. 
   1.124 + **/
   1.125 +extern struct mem_region_fn **sh4_address_space;
   1.126 +extern struct mem_region_fn **sh4_user_address_space;
   1.127 +
   1.128 +/************ Storequeue/cache functions ***********/
   1.129 +void FASTCALL ccn_storequeue_write_long( sh4addr_t addr, uint32_t val );
   1.130 +int32_t FASTCALL ccn_storequeue_read_long( sh4addr_t addr );
   1.131 +
   1.132 +/** Default storequeue prefetch when TLB is disabled */
   1.133 +void FASTCALL ccn_storequeue_prefetch( sh4addr_t addr ); 
   1.134 +
   1.135 +/** TLB-enabled variant of the storequeue prefetch */
   1.136 +void FASTCALL ccn_storequeue_prefetch_tlb( sh4addr_t addr );
   1.137 +
   1.138 +/** Non-storequeue prefetch */
   1.139 +void FASTCALL ccn_prefetch( sh4addr_t addr );
   1.140 +
   1.141 +/** Non-cached prefetch (ie, no-op) */
   1.142 +void FASTCALL ccn_uncached_prefetch( sh4addr_t addr );
   1.143 +
   1.144 +
   1.145 +extern struct mem_region_fn mem_region_address_error;
   1.146 +extern struct mem_region_fn mem_region_tlb_miss;
   1.147 +extern struct mem_region_fn mem_region_tlb_multihit;
   1.148 +extern struct mem_region_fn mem_region_tlb_protected;
   1.149 +
   1.150 +extern struct mem_region_fn p4_region_storequeue; 
   1.151 +extern struct mem_region_fn p4_region_storequeue_multihit; 
   1.152 +extern struct mem_region_fn p4_region_storequeue_miss; 
   1.153 +extern struct mem_region_fn p4_region_storequeue_protected; 
   1.154 +extern struct mem_region_fn p4_region_storequeue_sqmd; 
   1.155 +extern struct mem_region_fn p4_region_storequeue_sqmd_miss; 
   1.156 +extern struct mem_region_fn p4_region_storequeue_sqmd_multihit; 
   1.157 +extern struct mem_region_fn p4_region_storequeue_sqmd_protected; 
   1.158 +
   1.159 +#ifdef __cplusplus
   1.160 +}
   1.161 +#endif
   1.162 +#endif /* !lxdream_sh4_mmu_H */