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lxdream.org :: lxdream/src/asic.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 305:1191085c5988
prev302:96b5cc24309c
next325:5717ae5d4746
author nkeynes
date Thu Jan 18 11:14:01 2007 +0000 (14 years ago)
permissions -rw-r--r--
last change Rearrange asic cascade events
file annotate diff log raw
1.1 --- a/src/asic.c Wed Jan 17 21:27:20 2007 +0000
1.2 +++ b/src/asic.c Thu Jan 18 11:14:01 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.24 2007-01-17 21:27:20 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.25 2007-01-18 11:14:01 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -217,13 +217,27 @@
1.11 intc_raise_interrupt( INT_IRQ11 );
1.12 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
1.13 intc_raise_interrupt( INT_IRQ9 );
1.14 +
1.15 + if( event >= 64 ) { /* Third word */
1.16 + asic_event( EVENT_CASCADE2 );
1.17 + } else if( event >= 32 ) { /* Second word */
1.18 + asic_event( EVENT_CASCADE1 );
1.19 + }
1.20 }
1.21
1.22 void asic_clear_event( int event ) {
1.23 int offset = ((event&0x60)>>3);
1.24 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
1.25 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
1.26 -
1.27 + if( result == 0 ) {
1.28 + /* clear cascades if necessary */
1.29 + if( event >= 64 ) {
1.30 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
1.31 + } else if( event >= 32 ) {
1.32 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
1.33 + }
1.34 + }
1.35 +
1.36 asic_check_cleared_events();
1.37 }
1.38
1.39 @@ -297,12 +311,19 @@
1.40 {
1.41 switch( reg ) {
1.42 case PIRQ1:
1.43 - val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
1.44 - /* fallthrough */
1.45 + break; /* Treat this as read-only for the moment */
1.46 case PIRQ0:
1.47 + val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
1.48 + MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.49 + asic_check_cleared_events();
1.50 + break;
1.51 case PIRQ2:
1.52 - /* Clear any interrupts */
1.53 - MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.54 + /* Clear any events */
1.55 + val = MMIO_READ(ASIC, reg)&(~val);
1.56 + MMIO_WRITE( ASIC, reg, val );
1.57 + if( val == 0 ) { /* all clear - clear the cascade bit */
1.58 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
1.59 + }
1.60 asic_check_cleared_events();
1.61 break;
1.62 case SYSRESET:
.