1.1 --- a/src/sh4/sh4core.in	Sun Sep 16 07:01:07 2007 +0000
     1.2 +++ b/src/sh4/sh4core.in	Tue Sep 18 09:14:20 2007 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4core.in,v 1.6 2007-09-16 07:01:07 nkeynes Exp $
     1.6 + * $Id: sh4core.in,v 1.7 2007-09-18 09:14:20 nkeynes Exp $
     1.7   * 
     1.8   * SH4 emulation core, and parent module for all the SH4 peripheral
     1.9   * modules.
    1.10 @@ -42,8 +42,8 @@
    1.11  
    1.12  uint32_t sh4_run_slice( uint32_t );
    1.13  
    1.14 -static uint16_t *sh4_icache = NULL;
    1.15 -static uint32_t sh4_icache_addr = 0;
    1.16 +uint16_t *sh4_icache = NULL;
    1.17 +uint32_t sh4_icache_addr = 0;
    1.18  
    1.19  uint32_t sh4_run_slice( uint32_t nanosecs ) 
    1.20  {
    1.21 @@ -68,6 +68,7 @@
    1.22  		    sh4_accept_interrupt();
    1.23  		}
    1.24  	    }
    1.25 +	    //	    sh4_stats_add( sh4r.pc );
    1.26  	    if( !sh4_execute_instruction() ) {
    1.27  		break;
    1.28  	    }
    1.29 @@ -286,6 +287,12 @@
    1.30      RAISE( code, EXV_EXCEPTION );
    1.31  }
    1.32  
    1.33 +gboolean sh4_raise_trap( int trap )
    1.34 +{
    1.35 +    MMIO_WRITE( MMU, TRA, trap<<2 );
    1.36 +    return sh4_raise_exception( EXC_TRAP );
    1.37 +}
    1.38 +
    1.39  gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
    1.40      if( sh4r.in_delay_slot ) {
    1.41  	return sh4_raise_exception(slot_code);
    1.42 @@ -1204,14 +1211,19 @@
    1.43  FSCA FPUL, FRn {:
    1.44      CHECKFPUEN();
    1.45      if( !IS_FPU_DOUBLEPREC() ) {
    1.46 +	sh4_fsca( FPULi, &(DRF(FRn>>1)) );
    1.47 +	/*
    1.48          float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
    1.49          FR(FRn) = sinf(angle);
    1.50          FR((FRn)+1) = cosf(angle);
    1.51 +	*/
    1.52      }
    1.53  :}
    1.54  FTRV XMTRX, FVn {:
    1.55      CHECKFPUEN();
    1.56      if( !IS_FPU_DOUBLEPREC() ) {
    1.57 +	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
    1.58 +	/*
    1.59          tmp = FVn<<2;
    1.60  	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
    1.61          float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
    1.62 @@ -1223,6 +1235,7 @@
    1.63  	    xf[11]*fv[2] + xf[15]*fv[3];
    1.64          FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
    1.65  	    xf[10]*fv[2] + xf[14]*fv[3];
    1.66 +	*/
    1.67      }
    1.68  :}
    1.69  UNDEF {: