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lxdream.org :: lxdream/src/sh4/sh4core.in :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.in
changeset 974:16b079ed11bb
prev970:44d62d0850c8
next984:a01567058a47
author nkeynes
date Mon Jan 26 03:09:53 2009 +0000 (11 years ago)
permissions -rw-r--r--
last change Fix double-counting of instructions in delay slots in sh4_finalize_instruction
Fix spc value when taking an exception in mmu_update_icache in a delay slot
Fix under-counting of instructions in newpc delay slots in translated blocks
file annotate diff log raw
1.1 --- a/src/sh4/sh4core.in Thu Jan 22 00:50:09 2009 +0000
1.2 +++ b/src/sh4/sh4core.in Mon Jan 26 03:09:53 2009 +0000
1.3 @@ -256,21 +256,18 @@
1.4 sh4r.pc += 2;
1.5 sh4_finalize_instruction();
1.6 sh4r.pc += disp;
1.7 - sh4r.slice_cycle += sh4_cpu_period;
1.8 :}
1.9 BRAF Rn {:
1.10 sh4r.pc += 2;
1.11 tmp = sh4r.r[Rn];
1.12 sh4_finalize_instruction();
1.13 sh4r.pc += tmp;
1.14 - sh4r.slice_cycle += sh4_cpu_period;
1.15 :}
1.16 BSR disp {:
1.17 /* Note: PR is already set */
1.18 sh4r.pc += 2;
1.19 sh4_finalize_instruction();
1.20 sh4r.pc += disp;
1.21 - sh4r.slice_cycle += sh4_cpu_period;
1.22 :}
1.23 BSRF Rn {:
1.24 /* Note: PR is already set */
1.25 @@ -278,7 +275,6 @@
1.26 tmp = sh4r.r[Rn];
1.27 sh4_finalize_instruction();
1.28 sh4r.pc += tmp;
1.29 - sh4r.slice_cycle += sh4_cpu_period;
1.30 :}
1.31 BF/S disp {:
1.32 sh4r.pc += 2;
1.33 @@ -286,7 +282,6 @@
1.34 if( !sh4r.t ) {
1.35 sh4r.pc += disp;
1.36 }
1.37 - sh4r.slice_cycle += sh4_cpu_period;
1.38 :}
1.39 BT/S disp {:
1.40 sh4r.pc += 2;
1.41 @@ -294,7 +289,6 @@
1.42 if( sh4r.t ) {
1.43 sh4r.pc += disp;
1.44 }
1.45 - sh4r.slice_cycle += sh4_cpu_period;
1.46 :}
1.47 JMP @Rn {:
1.48 sh4r.pc += 2;
1.49 @@ -302,7 +296,7 @@
1.50 sh4_finalize_instruction();
1.51 sh4r.pc = tmp;
1.52 sh4r.new_pc = tmp + 2;
1.53 - sh4r.slice_cycle += 2*sh4_cpu_period;
1.54 + sh4r.slice_cycle += sh4_cpu_period;
1.55 return;
1.56 :}
1.57 JSR @Rn {:
1.58 @@ -312,7 +306,7 @@
1.59 sh4_finalize_instruction();
1.60 sh4r.pc = tmp;
1.61 sh4r.new_pc = tmp + 2;
1.62 - sh4r.slice_cycle += 2*sh4_cpu_period;
1.63 + sh4r.slice_cycle += sh4_cpu_period;
1.64 return;
1.65 :}
1.66 RTS {:
1.67 @@ -320,7 +314,7 @@
1.68 sh4_finalize_instruction();
1.69 sh4r.pc = sh4r.pr;
1.70 sh4r.new_pc = sh4r.pr + 2;
1.71 - sh4r.slice_cycle += 2*sh4_cpu_period;
1.72 + sh4r.slice_cycle += sh4_cpu_period;
1.73 return;
1.74 :}
1.75 RTE {:
1.76 @@ -329,7 +323,7 @@
1.77 sh4_finalize_instruction();
1.78 sh4r.pc = sh4r.spc;
1.79 sh4r.new_pc = sh4r.pr + 2;
1.80 - sh4r.slice_cycle += 2*sh4_cpu_period;
1.81 + sh4r.slice_cycle += sh4_cpu_period;
1.82 return;
1.83 :}
1.84 MOV.B Rm, @-Rn {: sh4r.r[Rn]--; :}
1.85 @@ -339,6 +333,7 @@
1.86 MOV.W @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 2; } :}
1.87 MOV.L @Rm+, Rn {: if( Rm != Rn ) { sh4r.r[Rm] += 4; } :}
1.88 %%
1.89 + sh4r.in_delay_slot = 0;
1.90 sh4r.pc += 2;
1.91 sh4r.new_pc = sh4r.pc+2;
1.92 sh4r.slice_cycle += sh4_cpu_period;
1.93 @@ -380,7 +375,11 @@
1.94
1.95 /* Read instruction */
1.96 if( !IS_IN_ICACHE(pc) ) {
1.97 + gboolean delay_slot = sh4r.in_delay_slot;
1.98 if( !mmu_update_icache(pc) ) {
1.99 + if( delay_slot ) {
1.100 + sh4r.spc -= 2;
1.101 + }
1.102 // Fault - look for the fault handler
1.103 if( !mmu_update_icache(sh4r.pc) ) {
1.104 // double fault - halt
.