1.1 --- a/src/sh4/sh4dasm.in	Thu Jan 15 03:54:21 2009 +0000
     1.2 +++ b/src/sh4/sh4dasm.in	Tue Mar 24 11:15:57 2009 +0000
     1.3 @@ -23,32 +23,6 @@
     1.4  
     1.5  #define UNIMP(ir) snprintf( buf, len, "???     " )
     1.6  
     1.7 -
     1.8 -const struct reg_desc_struct sh4_reg_map[] = 
     1.9 -  { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},
    1.10 -    {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},
    1.11 -    {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},
    1.12 -    {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},
    1.13 -    {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},
    1.14 -    {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},
    1.15 -    {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},
    1.16 -    {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},
    1.17 -    {"SR", REG_INT, &sh4r.sr}, {"GBR", REG_INT, &sh4r.gbr},
    1.18 -    {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},
    1.19 -    {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},
    1.20 -    {"VBR",REG_INT, &sh4r.vbr},
    1.21 -    {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
    1.22 -    {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
    1.23 -    {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},
    1.24 -    {NULL, 0, NULL} };
    1.25 -
    1.26 -
    1.27 -const struct cpu_desc_struct sh4_cpu_desc = 
    1.28 -    { "SH4", sh4_disasm_instruction, sh4_execute_instruction, sh4_has_page, 
    1.29 -      sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
    1.30 -      (char *)&sh4r, sizeof(sh4r), sh4_reg_map,
    1.31 -      &sh4r.pc };
    1.32 -
    1.33  uint32_t sh4_disasm_instruction( sh4vma_t pc, char *buf, int len, char *opcode )
    1.34  {
    1.35      sh4addr_t addr = mmu_vma_to_phys_disasm(pc);