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lxdream.org :: lxdream/src/sh4/mmu.c :: diff
lxdream 0.9.1
released Jun 29
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filename src/sh4/mmu.c
changeset 927:17b6b9e245d8
prev915:c989eb4c22d8
next929:fd8cb0c82f5f
next953:f4a156508ad1
author nkeynes
date Mon Dec 15 10:44:56 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Add return-address-modifying exception return code to mmu TLB lookups (a little bit faster)
file annotate diff log raw
1.1 --- a/src/sh4/mmu.c Fri Nov 07 06:39:12 2008 +0000
1.2 +++ b/src/sh4/mmu.c Mon Dec 15 10:44:56 2008 +0000
1.3 @@ -24,6 +24,12 @@
1.4 #include "sh4/sh4trans.h"
1.5 #include "mem.h"
1.6
1.7 +#ifdef HAVE_FRAME_ADDRESS
1.8 +#define RETURN_VIA(exc) do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
1.9 +#else
1.10 +#define RETURN_VIA(exc) return MMU_VMA_ERROR
1.11 +#endif
1.12 +
1.13 #define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
1.14
1.15 /* The MMU (practically unique in the system) is allowed to raise exceptions
1.16 @@ -817,8 +823,12 @@
1.17
1.18 return result;
1.19 }
1.20 -
1.21 +
1.22 +#ifdef HAVE_FRAME_ADDRESS
1.23 +sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr, void *exc )
1.24 +#else
1.25 sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr )
1.26 +#endif
1.27 {
1.28 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1.29 if( addr & 0x80000000 ) {
1.30 @@ -836,7 +846,7 @@
1.31 return addr;
1.32 }
1.33 MMU_READ_ADDR_ERROR();
1.34 - return MMU_VMA_ERROR;
1.35 + RETURN_VIA(exc);
1.36 }
1.37 }
1.38
1.39 @@ -855,16 +865,16 @@
1.40 switch(entryNo) {
1.41 case -1:
1.42 MMU_TLB_READ_MISS_ERROR(addr);
1.43 - return MMU_VMA_ERROR;
1.44 + RETURN_VIA(exc);
1.45 case -2:
1.46 MMU_TLB_MULTI_HIT_ERROR(addr);
1.47 - return MMU_VMA_ERROR;
1.48 + RETURN_VIA(exc);
1.49 default:
1.50 if( (mmu_utlb[entryNo].flags & TLB_USERMODE) == 0 &&
1.51 !IS_SH4_PRIVMODE() ) {
1.52 /* protection violation */
1.53 MMU_TLB_READ_PROT_ERROR(addr);
1.54 - return MMU_VMA_ERROR;
1.55 + RETURN_VIA(exc);
1.56 }
1.57
1.58 /* finally generate the target address */
1.59 @@ -873,7 +883,11 @@
1.60 }
1.61 }
1.62
1.63 +#ifdef HAVE_FRAME_ADDRESS
1.64 +sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr, void *exc )
1.65 +#else
1.66 sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr )
1.67 +#endif
1.68 {
1.69 uint32_t mmucr = MMIO_READ(MMU,MMUCR);
1.70 if( addr & 0x80000000 ) {
1.71 @@ -891,7 +905,7 @@
1.72 return addr;
1.73 }
1.74 MMU_WRITE_ADDR_ERROR();
1.75 - return MMU_VMA_ERROR;
1.76 + RETURN_VIA(exc);
1.77 }
1.78 }
1.79
1.80 @@ -910,21 +924,21 @@
1.81 switch(entryNo) {
1.82 case -1:
1.83 MMU_TLB_WRITE_MISS_ERROR(addr);
1.84 - return MMU_VMA_ERROR;
1.85 + RETURN_VIA(exc);
1.86 case -2:
1.87 MMU_TLB_MULTI_HIT_ERROR(addr);
1.88 - return MMU_VMA_ERROR;
1.89 + RETURN_VIA(exc);
1.90 default:
1.91 if( IS_SH4_PRIVMODE() ? ((mmu_utlb[entryNo].flags & TLB_WRITABLE) == 0)
1.92 : ((mmu_utlb[entryNo].flags & TLB_USERWRITABLE) != TLB_USERWRITABLE) ) {
1.93 /* protection violation */
1.94 MMU_TLB_WRITE_PROT_ERROR(addr);
1.95 - return MMU_VMA_ERROR;
1.96 + RETURN_VIA(exc);
1.97 }
1.98
1.99 if( (mmu_utlb[entryNo].flags & TLB_DIRTY) == 0 ) {
1.100 MMU_TLB_INITIAL_WRITE_ERROR(addr);
1.101 - return MMU_VMA_ERROR;
1.102 + RETURN_VIA(exc);
1.103 }
1.104
1.105 /* finally generate the target address */
.