1.1 --- a/src/sh4/sh4mem.c	Thu Oct 04 10:49:41 2007 +0000
     1.2 +++ b/src/sh4/sh4mem.c	Sun Oct 07 06:03:22 2007 +0000
     1.3 @@ -1,5 +1,5 @@
     1.4  /**
     1.5 - * $Id: sh4mem.c,v 1.26 2007-10-04 10:49:41 nkeynes Exp $
     1.6 + * $Id: sh4mem.c,v 1.27 2007-10-06 09:03:24 nkeynes Exp $
     1.7   * sh4mem.c is responsible for the SH4's access to memory (including memory
     1.8   * mapped I/O), using the page maps created in mem.c
     1.9   *
    1.10 @@ -23,10 +23,12 @@
    1.11  #include "dream.h"
    1.12  #include "mem.h"
    1.13  #include "mmio.h"
    1.14 -#include "sh4core.h"
    1.15 -#include "sh4mmio.h"
    1.16  #include "dreamcast.h"
    1.17 +#include "sh4/sh4core.h"
    1.18 +#include "sh4/sh4mmio.h"
    1.19 +#include "sh4/xltcache.h"
    1.20  #include "pvr2/pvr2.h"
    1.21 +#include "asic.h"
    1.22  
    1.23  #define OC_BASE 0x1C000000
    1.24  #define OC_TOP  0x20000000
    1.25 @@ -370,8 +372,6 @@
    1.26  }
    1.27  
    1.28  void mem_copy_to_sh4( uint32_t destaddr, char *src, size_t count ) {
    1.29 -    int region;
    1.30 -
    1.31      if( destaddr >= 0x10000000 && destaddr < 0x14000000 ) {
    1.32  	pvr2_dma_write( destaddr, src, count );
    1.33  	return;
    1.34 @@ -396,6 +396,6 @@
    1.35      int queue = (addr&0x20)>>2;
    1.36      char *src = (char *)&sh4r.store_queue[queue];
    1.37      uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
    1.38 -    uint32_t target = addr&0x03FFFFE0 | hi;
    1.39 +    uint32_t target = (addr&0x03FFFFE0) | hi;
    1.40      mem_copy_to_sh4( target, src, 32 );
    1.41  }