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filename src/sh4/sh4mmio.h
changeset 953:f4a156508ad1
prev859:b941c703ccd6
next1067:d3c00ffccfcd
author nkeynes
date Thu Jan 15 03:54:21 2009 +0000 (15 years ago)
permissions -rw-r--r--
last change Fix missing prototype for mmu_vma_to_phys_disasm
Fix missing return value in mmu_ext_page_remapped
file annotate diff log raw 
     1.1 --- a/src/sh4/sh4mmio.h	Fri Sep 26 10:29:10 2008 +0000

     1.2 +++ b/src/sh4/sh4mmio.h	Thu Jan 15 03:54:21 2009 +0000

     1.3 @@ -203,19 +203,6 @@

     1.4      MMIO_REGION( PMM )

     1.5  MMIO_REGION_LIST_END

     1.6  

     1.7 -/* mmucr register bits */

     1.8 -#define MMUCR_AT   0x00000001 /* Address Translation enabled */

     1.9 -#define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */

    1.10 -#define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */

    1.11 -#define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */

    1.12 -#define MMUCR_URC  0x0000FC00 /* UTLB access counter */

    1.13 -#define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */

    1.14 -#define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */

    1.15 -#define MMUCR_MASK 0xFCFCFF05

    1.16 -#define MMUCR_RMASK 0xFCFCFF01 /* Read mask */

    1.17 -

    1.18 -#define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)

    1.19 -

    1.20  /* ccr register bits */

    1.21  #define CCR_IIX    0x00008000 /* IC index enable */

    1.22  #define CCR_ICI    0x00000800 /* IC invalidation (always read as 0) */

    1.23 @@ -243,24 +230,6 @@

    1.24  void mmu_set_cache_mode( int );

    1.25  void mmu_ldtlb(void);

    1.26  

    1.27 -int32_t mmu_icache_addr_read( sh4addr_t addr );

    1.28 -int32_t mmu_icache_data_read( sh4addr_t addr );

    1.29 -int32_t mmu_itlb_addr_read( sh4addr_t addr );

    1.30 -int32_t mmu_itlb_data_read( sh4addr_t addr );

    1.31 -int32_t mmu_ocache_addr_read( sh4addr_t addr );

    1.32 -int32_t mmu_ocache_data_read( sh4addr_t addr );

    1.33 -int32_t mmu_utlb_addr_read( sh4addr_t addr );

    1.34 -int32_t mmu_utlb_data_read( sh4addr_t addr );

    1.35 -void mmu_icache_addr_write( sh4addr_t addr, uint32_t val );

    1.36 -void mmu_icache_data_write( sh4addr_t addr, uint32_t val );

    1.37 -void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val );

    1.38 -void mmu_itlb_data_write( sh4addr_t addr, uint32_t val );

    1.39 -void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val );

    1.40 -void mmu_ocache_data_write( sh4addr_t addr, uint32_t val );

    1.41 -void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val );

    1.42 -void mmu_utlb_data_write( sh4addr_t addr, uint32_t val );

    1.43 -

    1.44 -

    1.45  #ifdef __cplusplus

    1.46  }

    1.47  #endif
.